Am 29.08.22 um 21:30 schrieb Felix Kuehling:
Am 2022-08-29 um 14:59 schrieb Christian König:
Am 29.08.22 um 18:07 schrieb Felix Kuehling:
Am 2022-08-29 um 11:38 schrieb Christian König:
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a different location than was intended at alloca
On 8/29/2022 10:20 PM, Alex Deucher wrote:
On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
HDP flush is used early in the init sequence as part of memory controller
block initialization. Hence remapping of HDP registers needed for flush
needs to happen earlier.
This also fixes the Unsupp
From: Hawking Zhang
Add ip block support for gfx v11_0_3.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dri
From: Hawking Zhang
All gc v11_0_3 registers in gcvml2 range have different
register offset from the ones in gc v11_0_0. v11_0_3
imu_rlc_ram programming has to be separated from v11_0_0
implementation
Signed-off-by: Hawking Zhang
Signed-off-by: Yang Wang
Reviewed-by: Frank Min
Signed-off-by:
From: Hawking Zhang
Set AMDGPU_FAMILY_GC_11_0_0.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/
From: Hawking Zhang
Add ip block support for mes v11_0_3.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dri
From: Hawking Zhang
To support new gfx ip block
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amd
From: David Belanger
Added missing cases for GFX 11.0.3 code in a few switch statements.
Signed-off-by: David Belanger
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8
2 files change
From: Hawking Zhang
initialize some gfx config for gfx v11_0_3
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gp
From: Hawking Zhang
To support new mes ip block
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgp
From: Yang Wang
add gfxhub_v3_0_3 support
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 511 +
drivers/gpu
From: Hawking Zhang
initialize gmc sw config for v11_0_3
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/am
From: Hawking Zhang
Add ip block support for gmc v11_0_3.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dri
This set adds support for Graphics Memory Controller
v11.0.3. Patch 1 contains new register headers and is
too big for the mailing list.
Frank Min (1):
drm/amdgpu: add gc v11_0_3 ip headers
Hawking Zhang (2):
drm/amdgpu: initialize gmc sw config for v11_0_3
drm/amdgpu: add new ip block for
Applied. Thanks!
Alex
On Mon, Aug 29, 2022 at 8:29 AM wrote:
>
> From: Jinpeng Cui
>
> Return value from kfd_wait_on_events() and io_remap_pfn_range() directly
> instead of taking this in another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: Jinpeng Cui
> ---
> drivers/gp
Applied. Thanks!
Alex
On Mon, Aug 29, 2022 at 8:13 AM wrote:
>
> From: Jinpeng Cui
>
> Return value from expression directly instead of
> taking this in another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: Jinpeng Cui
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw
Am 2022-08-29 um 14:59 schrieb Christian König:
Am 29.08.22 um 18:07 schrieb Felix Kuehling:
Am 2022-08-29 um 11:38 schrieb Christian König:
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a different location than was intended at allocation
time,
for example when restoring fails
On 8/29/22 06:41, Hans de Goede wrote:
Hi,
On 8/26/22 00:21, Daniel Dadap wrote:
On 8/25/22 9:37 AM, Hans de Goede wrote:
On some new laptop designs a new Nvidia specific WMI interface is present
which gives info about panel brightness control and may allow controlling
the brightness through
Am 29.08.22 um 18:07 schrieb Felix Kuehling:
Am 2022-08-29 um 11:38 schrieb Christian König:
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a different location than was intended at allocation
time,
for example when restoring fails after an eviction or BOs get pinned in
system memo
On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
>
> HDP flush is used early in the init sequence as part of memory controller
> block initialization. Hence remapping of HDP registers needed for flush
> needs to happen earlier.
>
> This also fixes the Unsupported Request error reported through AE
On 2022-08-24 13:38, Felix Kuehling wrote:
> Do you mind squashing the two patches. It would make them easier to review
> because it makes it easier to see that the same functions are using both.
Will do.
Regards,
Daniel
Am 2022-08-29 um 11:38 schrieb Christian König:
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a different location than was intended at allocation time,
for example when restoring fails after an eviction or BOs get pinned in
system memory. On some GPUs the MTYPE for coherent mapping
On Friday, August 26th, 2022 at 10:19, Ville Syrjälä
wrote:
> On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> > This new kernel capability indicates whether async page-flips are
> > supported via the atomic uAPI. DRM clients can use it to check
> > for support before feeding DRM_MOD
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a different location than was intended at allocation time,
for example when restoring fails after an eviction or BOs get pinned in
system memory. On some GPUs the MTYPE for coherent mappings depends on
the actual memory location.
Use the
Am 2022-08-29 um 11:00 schrieb Alex Sierra:
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra
Acked-by: Alex Deucher
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 dele
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/dr
The debugger must be notified by any debugger subscribed exception
that comes from hardware interrupts.
Debugger notification must be scheduled as HW state may be unknown
when receiving an exception that could require an immediate process
eviction.
If a debugger session exits, any exceptions it s
Bump the minor version to declare debugging capability is now
available.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 -
include/uapi/linux/kfd_ioctl.h | 3 ++-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd
Allow the debugger to set wave behaviour on to either normally operate,
halt at launch, trap on every instruction, terminate immediately or
stall on allocation.
Signed-off-by: Jonathan Kim
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 18 ++
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturu
The debugger subscibes to nofication for requested exceptions on attach.
Allow the debugger to change its subsciption later on.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 36
drivers/gpu/dr
Unlike single process debug devices, multi-process debug devices allow
debug mode setting per-VMID (non-device-global).
Because the HWS manages PASID-VMID mapping, the new MAP_PROCESS API allows
the KFD to forward the required SPI debug register write requests.
To request a new debug mode setting
Allow the debugger to get a snapshot of a specified number of queues
containing various queue property information that is copied to the
debugger.
Since the debugger doesn't know how many queues exist at any given time,
allow the debugger to pass the requested number of snapshots as 0 to get
the a
Allow the debugger to a single query queue, device and process exception
in a FIFO manner.
The KFD should also return the GPU or Queue id of the exception.
The debugger also has the option of clearing exceptions after
being queried.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_
From: Jay Cornwall
Trap handler behavior will differ when a debugger is attached.
Make the debug trap flag available in the trap handler TMA.
Update it when the debug trap ioctl is invoked.
v3: Rebase for upstream
v2:
Add missing debug flag setup on APUs
Signed-off-by: Jay Cornwall
Reviewed-
Similar to queue snapshot, return an array of device information using
an entry_size check and return.
Unlike queue snapshots, the debugger needs to pass to correct number of
devices that exist. If it fails to do so, the KFD will return the
number of actual devices so that the debugger can make a
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting during GFXOFF. During GFXOFF, these registers
wi
Exception events can be generated from interrupts or queue activitity.
The raise event function will save exception status of a queue, device
or process then notify the debugger of the status change by writing to
a debugger polled file descriptor that the debugger provides during
debug attach.
Fo
Add a debug operation that allows the debugger to send an exception
directly to runtime through a payload address.
For memory violations, normal vmfault signals will be applied to
notify runtime instead after passing in the saved exception data
when a memory violation was raised to the debugger.
GFX9.4.2 now supports per-VMID debug mode controls registers
(SPI_GDBG_PER_VMID_CNTL).
Because the KFD lets the HWS handle PASID-VMID mapping, the KFD will
forward all debug mode setting register writes to the HWS scheduler
using a new MAP_PROCESS API, so instead of writing to registers, return
th
Expose debug capabilities in the KFD topology node's HSA capabilities and
debug properties flags.
Ensure correct capabilities are exposed based on firmware support.
Flag definitions can be referenced in uapi/linux/kfd_sysfs.h.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_topo
Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory
address per device.
Note that there exists only 4 watch points per devices to date, so have
the KFD keep track of what w
In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.
On queue suspend, the KFD will copy the context save header information
so that the debugger can correctly crawl the appropr
Allow the debugger to query additional info based on an exception code.
For device exceptions, it's currently only memory violation information.
For process exceptions, it's currently only runtime information.
Queue exception only report the queue exception status.
The debugger has the option of c
This operation coordinates the debugger with the target HSA runtime
process.
The main motive for this coordination is due to CP performance overhead
when enabling trap temporaries via SPI_GDBG_PER_VMID_CNTL.Trap_en.
This overhead is unacceptable for microbench performance in normal mode
for certai
This operation allows the debugger to override the enabled HW
exceptions on the device.
On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they are global, only address watch exceptions are all
The HWS schedule allows a grace period for wave completion prior to
preemption but the debugger requires good performance since it preempts
on every HW debug mode setting transaction request.
For good performance, allow immediate preemption by setting the grace
period to 0.
Note that setting the
Allow the debugger to set single memory and single ALU operations.
Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty instruction. Trap temporaries 0 & 1 save
the program count
Similar to GFX9 debug devices, set the hardware debug mode by draining
the SPI appropriately prior the mode setting request.
Because GFX10 has waves allocated by the work group boundaray and each
SE's SPI instances do not communicate, the SPI drain time is much longer.
This long drain time will be
The ROCm debugger will attach to a process to debug by PTRACE and will
expect the KFD to prepare a process for the target PID, whether the
target PID has opened the KFD device or not.
This patch is to explicity handle this requirement. Further HW mode
setting and runtime coordination requirements
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID from
the HWS dynamic VMID allocation via SET_RESOUC
Add missing debug trap registers references and initialize all debug
registers on boot by clearing the hardware exception overrides and the
wave allocation ID index.
For debug devices that only support single process debugging, enable
trap temporary setup by default.
Debug devices that support mu
On GFX9.4.1, the implicit wait count instruction on s_barrier is
disabled by default in the driver during normal operation for
performance requirements.
There is a hardware bug in GFX9.4.1 where if the implicit wait count
instruction after an s_barrier instruction is disabled, any wave that
hits a
Introduce the GPU debug operations interface.
For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
instruction set, provide the necessary interface to allow the debugger
to HW debug-mode set and query exceptions per HSA queue, process or
device.
The runtime_enable interface co
Implement the per-device calls to enable or disable HW debug mode for
GFX9 prior to GFX9.4.1.
GFX9.4.1 and onward will require their own enable/disable sequence as
follow on patches.
When hardware debug mode setting is requested, waves will inherit
these settings in the Shader Processor Input's (
Introduce the require KGD debug calls that will execute hardware debug
mode setting.
Signed-off-by: Jonathan Kim
---
.../gpu/drm/amd/include/kgd_kfd_interface.h | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
b/drivers/g
This series is to expose the required KFD IOCTLs targeted to enable
ROCm's extension of the GNU Debugger for HSA compute debugging.
The series is divided into the following sections:
Section 1 - Drawing out the interfaces and preparing the KFD for
enable/disable calls
[PATCH 01/29] drm/amdkfd:
On Mon, Aug 29, 2022 at 9:43 AM Zhen Ni wrote:
>
> Nomodeset kernel parameter is for all graphics cards. Amdgpu cannot
> be set separately in some scenarios, such as hybrid graphics(i + a).
> Add modeset module parameter for amdgpu to set kernel mode separately.
>
> Signed-off-by: Zhen Ni
amdgpu
Nomodeset kernel parameter is for all graphics cards. Amdgpu cannot
be set separately in some scenarios, such as hybrid graphics(i + a).
Add modeset module parameter for amdgpu to set kernel mode separately.
Signed-off-by: Zhen Ni
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 -
1
Allows submitting jobs as gang which needs to run on multiple engines at the
same time.
All members of the gang get the same implicit, explicit and VM dependencies. So
no gang member will start running until everything else is ready.
The last job is considered the gang leader (usually a submissio
Move setting the job resources into amdgpu_job.c
Signed-off-by: Christian König
Reviewed-by: Andrey Grodzovsky
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 17 +
drivers/gpu/drm/amd/a
Allows submitting jobs as gang which needs to run on multiple
engines at the same time.
Basic idea is that we have a global gang submit fence representing when the
gang leader is finally pushed to run on the hardware last.
Jobs submitted as gang are never re-submitted in case of a GPU reset since
Check if the entity is already limited, not if it's assigned to the
first instance.
v2: only a cleanup, not a fix
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 5 ++---
2 files changed, 4 insertions(+), 6 deletions(-)
I've finally fixed why the gang submit patches broke VCN3/4 video
decoding for AV1.
Please re-test.
Thanks,
Christian.
Similar to what we did for VCN3 use the job instead of the parser
entity. Cleanup the coding style quite a bit as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 46 +++
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/drive
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD preemption fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/dri
This reverts commit 250195ff744f260c169f5427422b6f39c58cb883.
The job should now be initialized when we reach the parser functions.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/dri
We should not have any different CS constrains based
on the execution environment.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdg
We already discussed that the call to drm_sched_entity_select_rq() needs
to move to drm_sched_job_arm() to be able to set a new scheduler list
between _init() and _arm(). This was just not applied for some reason.
Signed-off-by: Christian König
Reviewed-by: Andrey Grodzovsky
---
drivers/gpu/drm
This reverts commit 94f4c4965e5513ba624488f4b601d6b385635aec.
We found that the bo_list is missing a protection for its list entries.
Since that is fixed now this workaround can be removed again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++-
Sort the functions in the order they are called and cleanup the coding
style and function names to represent the data they process.
Check the size of the IB chunk, initialize resulting entity and scheduler
job much earlier as well.
v2: fix job initialisation order and use correct scheduler instan
Am 2022-08-28 um 11:28 schrieb Christian König:
Am 26.08.22 um 23:49 schrieb Felix Kuehling:
On 2022-08-26 11:47, Alex Sierra wrote:
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 fi
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2
From: Jinpeng Cui
Return value from expression directly instead of
taking this in another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: Jinpeng Cui
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 13 -
1 file changed, 8 insertions(+), 5
From: Jinpeng Cui
Return value from kfd_wait_on_events() and io_remap_pfn_range() directly
instead of taking this in another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: Jinpeng Cui
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 9 ++---
1 file changed, 2 insertions(+), 7 de
1. The indentation of statements in the same curly bracket should be
consistent.
2. Variable declarations in the same function should be aligned.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888
Link: https://bugzilla.openanolis.cn
Hi,
On 8/26/22 00:21, Daniel Dadap wrote:
> On 8/25/22 9:37 AM, Hans de Goede wrote:
>> On some new laptop designs a new Nvidia specific WMI interface is present
>> which gives info about panel brightness control and may allow controlling
>> the brightness through this interface when the embedded
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
On Sat, 27 Aug 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since we only use the parsed vrefresh range to determine
> if VRR should be supported we should only accept continuous
> frequency displays here.
>
> Cc: Manasi Navare
> Cc: Nicholas Kazlauskas
> Cc: Harry Wentland
> Cc: Leo L
On Sat, 27 Aug 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename info->monitor_range to info->vrr_range to actually
> reflect its usage.
>
> Cc: Manasi Navare
> Cc: Nicholas Kazlauskas
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Rodrigo Siqueira
> Cc: amd-gfx@lists.freedesktop.org
> Si
Make sure the register offsets used for HDP flush in VF is
initialized early so that it works fine during any early HDP flush
sequence. For that, move the offset initialization to *_remap_hdp.
Signed-off-by: Lijo Lazar
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |
HDP flush is used early in the init sequence as part of memory controller
block initialization. Hence remapping of HDP registers needed for flush
needs to happen earlier.
This also fixes the Unsupported Request error reported through AER during
driver load. The error happens as a write happens to
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