[AMD Official Use Only - General]
Hi Christian,
The details as follows:
> 1. Use unmap_queue package to trigger preemption on gfx9
> Add trailing fence to track the preemption done.
On gfx9, there is no single package to complete the mcbp request in a single
frame like gfx10 does.
To send
From: Alvin Lee
[Description]
Don't set DSC bit for phantom pipes, not
required since phantom pipe don't have
any actual output
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 +
1 file changed, 1 insertion(+)
From: Nicholas Kazlauskas
[Why & How]
Depending on how the clock table is constructed from PMFW we can run
into issues where we don't think we have enough bandwidth available
due to FCLK too low - eg. when the FCLK table contains invalid entries
or a single entry.
We should always pick up the ma
From: Charlene Liu
[why]
this is to ensure that driver will not reprogram hvm_prefetch_req again if
it is done.
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 8 +++-
1 file changed, 7 insertions(+), 1
From: Alvin Lee
[Description]
Use pitch when calculating size to cache in MALL
Reviewed-by: Samson Tam
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
From: Alvin Lee
[Description]
For SubVP scaling cases, we must include the scaling
info as part of the cmd. This is required when converting
OTG line to HUBP line for the MALL_START_LINE programming.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/display/
From: Samson Tam
[Why & How]
Add GC_11_0_3_A0 as a chip revision to the DCN32 family
Reviewed-by: Rodrigo Siqueira
Acked-by: Brian Chang
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/driv
From: Tom Chung
[Why]
Pipes for MPO primary and overlay will be power down and power up during
plug/unplug external monitor while MPO video playback.
But the pipes were the same after plug/unplug and should not need to be
power down and power up or it will make page flip interrupt disabled and
ca
From: Daniel Miess
[Why]
Need a way to retain default clock table to aid
the investigation into why 8k@30 display not
lighting up on dcn314
[How]
Use flag to prevent execution of bw_params helper
function and function for updating bw_bounding_box
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: J
From: Ian Chen
Reviewed-by: Anthony Koo
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/include/logger_types.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h
b/drivers/gpu/drm/amd/display
From: Aric Cyr
This version brings along following fixes:
-Fix edp panel missing event
-Set ARGB16161616 pixel format to 26
-Fix dcn32 interger issue
-Clear optc underflow bit after ODM clock off
-Fix issue with stereo3D
-Fix DML2 lightup issue
-Correct DTBCLK for dcn314
-Revert for a regression
From: Ilya Bakoulin
[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.
BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(
From: Ethan Wellenreiter
[WHY]
Limiting vscsdp_for_colorimetry for YCbCr420/BT2020 resulted in red/green
point failures in HDR10 DTN tests. The re-implementation of ARGB16161616
was to fix this however it did not actually fix this issue but a side effect of
the
issue.
[HOW]
Change ARGB16161616
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fix ARGB16161616 pixel format;
* Fix pixel clock in 10/12-bpc;
* Add reserved dc_log_type;
* Fix some variables widths in dc;
* Add chip version GC_11_0_3_A0 to DCN32 family;
* Fix light up bug with dcn314 with 8K@30;
For detection of the new explicit sync functionality without
having to try the ioctl.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/
To prep for allowing different sync modes in a follow-up patch.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 11 +++
drivers/gpu/
We want to take only a BOOKKEEP usage for contexts that are not
implicitly synced.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 2 +-
This should be okay because moves themselves use KERNEL usage and
hence still sync with BOOKKEEP usage. Then any later submits still
wait on any pending VM operations.
(i.e. we only made VM ops not wait on BOOKKEEP submits, not the other
way around)
Signed-off-by: Bas Nieuwenhuizen
---
drivers
This changes all BO usages in a submit to BOOKKEEP instead of READ,
which effectively disables implicit sync for these submits.
This is configured at a context level using the existing IOCTL.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 13 ++
drivers/g
This adds a context option to use DMA_RESV_USAGE_BOOKKEEP for userspace
submissions,
based on Christians TTM work.
Disabling implicit sync is something we've wanted in radv for a while for
resolving
some corner cases. A more immediate thing that would be solved here is avoiding
a
bunch of impli
This way callsites can choose between READ/BOOKKEEP reservations.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 1 +
drivers/gpu/d
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: August 12, 2022 6:12 PM
> To: Grodzovsky, Andrey ; Kim, Jonathan
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: fix reset domain xgmi hive info reference
> leak
>
>
> On 2022-08-12 18:05, Andrey Grodzovsky
On 2022-08-12 18:05, Andrey Grodzovsky wrote:
On 2022-08-12 14:38, Kim, Jonathan wrote:
[Public]
Hi Andrey,
Here's the load/unload stack trace. This is a 2 GPU xGMI system. I
put dbg_xgmi_hive_get/put refcount print post kobj get/put.
It's stuck at 2 on unload. If it's an 8 GPU system,
On 2022-08-12 14:38, Kim, Jonathan wrote:
[Public]
Hi Andrey,
Here's the load/unload stack trace. This is a 2 GPU xGMI system. I put
dbg_xgmi_hive_get/put refcount print post kobj get/put.
It's stuck at 2 on unload. If it's an 8 GPU system, it's stuck at 8.
e.g. of sysfs leak after drive
Hello,
On Fri, Aug 12, 2022 at 04:54:04PM -0400, Felix Kuehling wrote:
> In principle, I think IRQ routing to CPUs can change dynamically with
> irqbalance.
I wonder whether this is something which should be exposed to userland
rather than trying to do dynamically in the kernel and let irqbalance
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, August 12, 2022 5:27 PM
> To: Joshi, Mukul ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Fix interrupt handling on ih_soft ring
>
>
> On 2022-08-12 16:56, Mukul Joshi wr
On 2022-08-12 16:56, Mukul Joshi wrote:
There are no backing hardware registers for ih_soft ring.
As a result, don't try to access hardware registers for read
and write pointers when processing interrupts on the IH soft
ring.
Signed-off-by: Mukul Joshi
The patch looks good to me. But you pr
On 2022-08-12 02:20, Dan Carpenter wrote:
This code has two bugs. If kfd_topology_device_by_proximity_domain()
failed on the first iteration through the loop then "cpu_link" is
uninitialized and should not be dereferenced.
The second bug is that we cannot dereference a list iterator when it
poi
There are no backing hardware registers for ih_soft ring.
As a result, don't try to access hardware registers for read
and write pointers when processing interrupts on the IH soft
ring.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 7 ++-
1 file changed, 6 insertion
On 2022-08-12 16:30, Tejun Heo wrote:
On Fri, Aug 12, 2022 at 04:26:47PM -0400, Felix Kuehling wrote:
Hi workqueue maintainers,
In the KFD (amdgpu) driver we found a need to schedule bottom half interrupt
handlers on CPU cores different from the one where the top-half interrupt
handler runs to
On Fri, Aug 12, 2022 at 04:26:47PM -0400, Felix Kuehling wrote:
> Hi workqueue maintainers,
>
> In the KFD (amdgpu) driver we found a need to schedule bottom half interrupt
> handlers on CPU cores different from the one where the top-half interrupt
> handler runs to avoid the interrupt handler sta
Hi workqueue maintainers,
In the KFD (amdgpu) driver we found a need to schedule bottom half
interrupt handlers on CPU cores different from the one where the
top-half interrupt handler runs to avoid the interrupt handler stalling
the bottom half in extreme scenarios. See my latest patch that t
Hi Zhenneng,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v5.19 next-20220812]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
On Sat, 13 Aug 2022 at 04:11, Felix Kuehling wrote:
>
>
> On 2022-08-12 09:55, Philip Yang wrote:
> >
> > On 2022-08-11 15:04, Felix Kuehling wrote:
> >> On systems that support SMT (hyperthreading) schedule the bottom half of
> >> the KFD interrupt handler on the same core. This makes it possible
[Public]
Hi Andrey,
Here's the load/unload stack trace. This is a 2 GPU xGMI system. I put
dbg_xgmi_hive_get/put refcount print post kobj get/put.
It's stuck at 2 on unload. If it's an 8 GPU system, it's stuck at 8.
e.g. of sysfs leak after driver unload:
atitest@atitest:/sys/devices/pci
On 2022-08-12 09:55, Philip Yang wrote:
On 2022-08-11 15:04, Felix Kuehling wrote:
On systems that support SMT (hyperthreading) schedule the bottom half of
the KFD interrupt handler on the same core. This makes it possible to
reserve a core for interrupt handling and have the bottom half run
Hi,
On 12/08/2022 00:19, Jiapeng Chong wrote:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1658
dml32_TruncToValidBPP() warn: ignoring unreachable code.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1894
Reported-by: Abaci Robot
Signed-off-by: Jiapeng C
On Thu, Aug 11, 2022 at 6:36 PM Rodrigo Siqueira
wrote:
>
> After removing some code for fixing the PowerPC compilation, we had some
> leftover functions that are not used anymore. This commit drops
> optc3_fpu_set_vrr_m_const since we don't need it anymore.
>
> Signed-off-by: Rodrigo Siqueira
R
On Thu, Aug 11, 2022 at 6:38 PM Rodrigo Siqueira Jordao
wrote:
>
>
>
> On 2022-08-11 17:49, Alex Deucher wrote:
> > On Thu, Aug 11, 2022 at 3:56 PM Rodrigo Siqueira
> > wrote:
> >>
> >> We got a report from Stephen/Michael that the PowerPC build was failing
> >> with the following error:
> >>
> >
Series is:
Reviewed-by: Alex Deucher
On Fri, Aug 12, 2022 at 6:20 AM Tim Huang wrote:
>
> Enable AMD_CG_SUPPORT_IH_CG support.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
>
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
On 8/12/22 14:34, Christian König wrote:
>
>
> Am 10.08.22 um 20:53 schrieb Dmitry Osipenko:
>> On 8/10/22 21:25, Christian König wrote:
>>> Am 10.08.22 um 19:49 schrieb Dmitry Osipenko:
On 8/10/22 14:30, Christian König wrote:
> Am 25.07.22 um 17:18 schrieb Dmitry Osipenko:
>> This
1. The indentation of statements in the same curly bracket should be
consistent.
2. Variable declarations in the same function should be aligned.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888
Link: https://bugzilla.openanolis.cn
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 13 -
1 file changed, 8 insertions(+), 5
On Thu, Aug 11, 2022 at 06:52:40PM +0200, Daniel Vetter wrote:
> On Wed, Aug 03, 2022 at 04:13:05PM -0400, Jason Baron wrote:
> >
> >
> > On 8/3/22 15:56, jim.cro...@gmail.com wrote:
> > > On Wed, Jul 20, 2022 at 9:32 AM Jim Cromie wrote:
> > >>
> > >
> > >> Hi Jason, Greg, DRM-folk,
> > >>
> >
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_seq
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1658
dml32_TruncToValidBPP() warn: ignoring unreachable code.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1894
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../drm/amd/display/dc/dml/dcn32/displ
Hi all,
On Thu, 11 Aug 2022 18:10:48 +0100 "Sudip Mukherjee (Codethink)"
wrote:
>
> Not sure if it has been reported, builds of riscv, alpha, s390, arm,
> arm64, xtensa, mips, csky allmodconfig have failed to build next-20220811
> with the error:
>
> ERROR: modpost: "dc_dsc_compute_bandwidth_ra
On Thu, 11 Aug 2022, "Deucher, Alexander" wrote:
> [Public]
>
>> -Original Message-
>> From: amd-gfx On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 4, 2022 5:55 AM
>> To: Jouni Högander ; dri-
>> de...@lists.freedesktop.org; intel-...@lists.freedesktop.org; amd-
>> g...@lists.freed
On 2022-08-11 15:04, Felix Kuehling wrote:
On systems that support SMT (hyperthreading) schedule the bottom half of
the KFD interrupt handler on the same core. This makes it possible to
reserve a core for interrupt handling and have the bottom half run on
that same core.
On systems without SMT
Apply new intersect and compatible callback instead
of having a generic placement range verfications.
v2: Added a separate callback for compatiblilty
checks (Christian)
v3: Cleanups and removal of workarounds
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
driver
Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.
v3: move the bits that are specific to buddy_man (Matthew)
v4: consider the block size /range (Matthew)
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
Reviewed-by
Implemented a new intersect and compatible callback function
fetching the start offset from struct ttm_resource.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/nouveau/nouveau_mem.c | 29 +++
drivers/gpu/drm/nouveau/nouveau_mem
Implemented a new intersect and compatible callback function
fetching start offset from backend drm buddy allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 38 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_m
Implemented a new intersect and compatible callback functions
to ttm range manager fetching start offset from drm mm range
allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/ttm/ttm_range_manager.c | 33 +
1 file changed
We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.
v2: move the amdgpu and ttm_range_manager changes to
separate patches (Christian)
v3: rename "intersect" to "intersects" (Matthew)
v4: move !place check to the
Am 11.08.22 um 05:19 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
Signed-off-by: Jiadong.Zhu
---
driver
Hi Jiadong,
yeah, the bug fixes indeed sound like something we would want to have.
Just drop the part 3 for now.
Regards,
Christian.
Am 11.08.22 um 05:18 schrieb Zhu, Jiadong:
[AMD Official Use Only - General]
Hi Christian,
Thank you for the reply, I will update the patch to fix style issu
Am 10.08.22 um 20:53 schrieb Dmitry Osipenko:
On 8/10/22 21:25, Christian König wrote:
Am 10.08.22 um 19:49 schrieb Dmitry Osipenko:
On 8/10/22 14:30, Christian König wrote:
Am 25.07.22 um 17:18 schrieb Dmitry Osipenko:
This patch moves the non-dynamic dma-buf users over to the dynamic
loc
@Alex was that one already picked up?
Am 25.07.22 um 18:40 schrieb Andrey Grodzovsky:
Reviewed-by: Andrey Grodzovsky
Andrey
On 2022-07-19 06:39, Andrey Strachuk wrote:
Local variable 'rq' is initialized by an address
of field of drm_sched_job, so it does not make
sense to compare 'rq' with N
Am 11.08.22 um 09:25 schrieb Zhenneng Li:
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() function has called
pci_set_power_state()
The driver needs to set EnableGfxImu message parameter to tell the PMFW
to set the flag that enables the GFXOFF feature.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsm
Enable AMD_CG_SUPPORT_IH_CG support.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6c3440e7ed3f..1ff7fc7bb340 100644
--- a/drivers/gpu/drm/amd/amdg
Only amdgpu_get_xgmi_hive but no amdgpu_put_xgmi_hive
which will leak the hive reference.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgp
The amdgpu_xgmi_remove_device function will send unload command
to psp through psp ring to terminate xgmi, but psp ring has been
destroyed in psp_hw_fini.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff -
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