On Fri, Jul 22, 2022 at 2:23 PM Jason Baron wrote:
>
>
>
> On 7/20/22 11:32, Jim Cromie wrote:
> > DECLARE_DYNDBG_CLASSMAP lets modules declare a set of classnames, this
> > opt-in authorizes dyndbg to allow enabling of prdbgs by their class:
> >
> >:#> echo class DRM_UT_KMS +p > /proc/dynamic
On 2022-07-20 18:54, Melissa Wen wrote:
On 07/17, Tales Lelo da Aparecida wrote:
On 16/07/2022 19:25, Melissa Wen wrote:
AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
to DC color correction entities. Part of this mapping is already
documented as code comments and ca
On 7/20/22 11:32, Jim Cromie wrote:
> DECLARE_DYNDBG_CLASSMAP lets modules declare a set of classnames, this
> opt-in authorizes dyndbg to allow enabling of prdbgs by their class:
>
>:#> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control
>
> This is just the setup; following commits de
On 7/20/22 11:32, Jim Cromie wrote:
> Add kernel_param_ops and callbacks to apply a class-map to a
> sysfs-node, which then can control classes defined in that class-map.
> This supports uses like:
>
> echo 0x3 > /sys/module/drm/parameters/debug
>
> IE add these:
>
> - int param_set_dyndbg
Hi Dan,
[ Cc += linuxppc-dev ]
Dan Horák writes:
> Commit d11219ad53dc disabled the DCN driver for all platforms that
> define PPC64 due long build issues during "make allmodconfig" using
> cross-compilation. Cross-compilation defaults to the ppc64_defconfig
> and thus big-endian toolchain conf
Hi Siqueira,
On 7/22/22 17:11, Rodrigo Siqueira Jordao wrote:
> Hi Maira,
>
> First of all, thanks a lot for this patch. This change is really helpful
> for reducing the stack size. I just have few comments inline.
Thank you for the feedback!
>
> On 2022-07-21 14:36, Maíra Canal wrote:
>> Acr
From: Anthony Koo
This version brings along following fixes:
- Copy crc_skip_count when duplicating CRTC state
- Add debug option for idle optimizations on cursor updates
- Disable MPC split for DCN32/321
- Add missing ODM 2:1 policy logic
- Update DCN32 and DCN321 SR latencies
- Add reinstate d
From: Leo Li
[Why]
crc_skip_count is used to track how many frames to skip to allow the OTG
CRC engine to "warm up" before it outputs correct CRC values.
Experimentally, this seems to be 2 frames.
When duplicating CRTC states, this value was not copied to the
duplicated state. Therefore, when t
From: Alvin Lee
For optimizations and debug purposes we added an option to exit idle
operations on cursor updates.
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
2 f
From: Alvin Lee
Due to CRB, no need to rely on MPC splitting to maximize use of DET
anymore.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
From: Samson Tam
Phantom pipes must use the same configuration used in main pipes. This
commit add this check.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn32/dcn
From: Alvin Lee
Update worst case SR latencies according to values measured by hardware
team.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
From: Rodrigo Siqueira
In order to handle FPO correctly, we need to reinstate the dram values.
This function adds the required code to handle the vblank stretch and
the dram calculation.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 3
From: Aurabindo Pillai
[Why&How]
Preparation to enable run time initialization of register offsets to add
dc_context to the link_enc_create callback. This is needed to get the
dc_ctx handle where register offset initialization routine is called.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alan Liu
From: Chris Park
[Why]
When Static screen from MALL, the cursor needs to be
cached if cursor exceeds 64x64 size.
[How]
Program the bit that cache cursor in MALL when size
of the cursor exceeds 64x64.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Acked-by: Alex Hung
Signed-off-by: Chris Park
---
From: Alvin Lee
[Description]
- Calculation for NumWays in MALL should be based on
number of MBlks
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
.../amd/display/dc/dcn32/dcn32_resource_helpers.c | 15 ++
From: Anthony Koo
- Add is_drr parameter to indicate DRR is enabled on
the panel to determine whether SubVP MCLK switch
logic should be enabled
- Add DRR manual trigger in FW (instead of driver)
because manual trigger programming triggers DRR
update pending and can block SubVP MCLK switches
from
From: Michael Strauss
[WHY]
Needed to program audio dto
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/displa
From: Michael Strauss
[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source
[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc
From: Michael Strauss
[WHY]
Required for correct OTG_H_TIMING_CNTL programming
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_optc.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/driver
From: Michael Strauss
[WHY]
Previously was pointing to DCN3 clock constructor rather than DCN31's
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Michael Strauss
[WHY]
DP DTO isn't used for 128b/132b encoding
[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c |
From: Michael Strauss
[WHY/HOW]
Need to calculate and set some pixel rate divisors on correct otg_inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 17 +
.../drm/amd/display/dc/dcn314/dcn314_hw
From: Rodrigo Siqueira
In the DCN30 resource, we have a small patch to the bounding box struct;
this patch uses FPU operations. This commit moves that specific part to
its function under the DML folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../d
From: Rodrigo Siqueira
At this stage, we must have all the FPU code for DCN30 isolated in the
DML folder. Drop FPU flags from Makefile.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 30 ---
From: Rodrigo Siqueira
The function responsible for calculating the MCLK switching has FPU
operations. This commit moves it to the dcn30_fpu file.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 38 --
From: Rodrigo Siqueira
We have some FPU operations on the resource part of the DCN201. This
commit drops FPU flags and moves any required FPU code to the DML
folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn201/Makefile
From: Alvin Lee
[Description]
- For SubVP cursor cannot be cached in MALL, therefore
we will switch to SW cursor if the cursor size exceeds
what can fit in the local DCN buffers (64x64x4)
- Returning false / failure for set_cursor_attributes will
fallback to SW cursor
Reviewed-by: Jun Lei
Acked
From: hersen wu
[Why]
event_property_update does not check NULL pointer
[How]
check aconnector->base.state equals NULL
Reviewed-by: Bhawanpreet Lakha
Acked-by: Alex Hung
Signed-off-by: hersen wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 34 ---
1 file changed, 22 i
From: Rodrigo Siqueira
We already isolated the DCN302 code in the DML folder, but we forgot to
drop the FPU flags from the Makefile. This commit drops those flags.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn302/Makefile
From: Taimur Hassan
[Why]
Coding error in DET allocation was resulting in too few DET segments
being allocated, causing underflow.
[How]
Reset pipe count each time we begin iterating through pipes for a stream.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Taimur Hassan
---
driv
From: Samson Tam
[Why]
In single display ODM combine mode, two MPO videos ( three
planes ) are not working
[How]
When we detect three planes, don't set odm combine 2to1 policy
for the MPO planes. Otherwise, we run out of pipes available
Add support for two MPO videos in dc_add_plane_to_contex
From: Nicholas Kazlauskas
[Why]
If BIOS doesn't specify number of memory channels then bandwidth
validation will fail due to insufficient BW in DML.
[How]
If BIOS is setting zero channels then use the default in the table.
If no entry is in the table and no BIOS value is specified then
throw an
From: Alvin Lee
[Description]
- For any DRR cases in SubVP, don't lock for VSYNC flips
- For DCN32/321 use FW to do DRR manual trigger programming
- Add bit in SubVP cmd to indicate if the SubVP pipe is DRR
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm
From: Nicholas Kazlauskas
[Why]
Access violation occurs when swapping between HDMI and FRL monitors
because we're missing the immediate_disable_crtc callback and it's
required for the DCN314 clk manager.
[How]
Update the table to match the DCN31 optc functions for ones that
should be the same:
-
From: Nicholas Kazlauskas
[Why]
We don't write out attributes after disabling and re-enabling the link
on some monitors, causing some, but not all, HDMI displays to fail to
lightup on DCN314.
[How]
Firmware used to do this after DIG link setup.
Since firmware is no longer doing this to support
From: Aric Cyr
[why]
In some cases MPC tree bottom pipe ends up point to itself. This causes
iterating from top to bottom to hang the system in an infinite loop.
[how]
When looping to next MPC bottom pipe, check that the pointer is not same
as current to avoid infinite loop.
Reviewed-by: Josip
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Copy crc_skip_count when duplicating CRTC state
* Add debug option for idle optimizations on cursor updates
* Disable MPC split for DCN32/321
* Add missing ODM 2:1 policy logic
* Update DCN32 and DCN321 SR latenci
Add comments to document gfx_off related members of struct amdgpu_gfx.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/a
Add documentation explaining those two new files.
Signed-off-by: André Almeida
---
Documentation/gpu/amdgpu/thermal.rst | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/gpu/amdgpu/thermal.rst
b/Documentation/gpu/amdgpu/thermal.rst
index 997231b6adcf..c31f94c6c68
Implement functions to get and set GFXOFF's entry count and residency
for vangogh.
Signed-off-by: André Almeida
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 5 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 +++
Add debugfs interface to log GFXOFF statistics:
- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
time of query since system power-up
- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
Read it to get average GFXOFF residency % multiplied by 100
during
This series adds new logging features for GFXOFF available for vangogh
and documentation for it.
I've created a small userspace program to interact with this new debugfs
interface and it can be found at:
https://gitlab.freedesktop.org/andrealmeid/gfxoff_tool
André Almeida (4):
drm/amd: Add de
Hi Maira,
First of all, thanks a lot for this patch. This change is really helpful
for reducing the stack size. I just have few comments inline.
On 2022-07-21 14:36, Maíra Canal wrote:
Across all DCN's (except DCN32, that has a separate
rq_dlg_get_dlg_reg), the parameters const bool vm_en, co
Applied. Thanks!
Alex
On Thu, Jul 21, 2022 at 3:26 AM Slark Xiao wrote:
>
> Replace 'the the' with 'the' in the comment.
>
> Signed-off-by: Slark Xiao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
> drivers/gpu/drm/amd/include/atombios.h| 4 ++--
> 2 files changed, 3 insertion
On Fri, Jul 22, 2022 at 1:56 PM Rodrigo Siqueira
wrote:
>
> When we use the allmodconfig option we see the following error:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
> function 'dml32_ModeSupportAndSystemConfigurationFull':
> drivers/gpu/drm/amd/amdgpu/../di
When we use the allmodconfig option we see the following error:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
error: the frame s
On 2022-07-21 01:13, Alex Deucher wrote:
Move additional dummy structures off the stack and into
the dummy vars structure.
Fixes the following:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
Hi Tvrtko,
scratching my head what exactly is going on here.
I've build tested drm-tip a couple of test in the last week and it
always worked flawlessly.
It looks like that some conflict resolution is sometimes not applied
correctly, but I have no idea why.
Regards,
Christian.
Am 22.07.22
On 14/07/2022 09:45, Thomas Zimmermann wrote:
Hi
Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:
This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.
This commit is only present in drm-misc-next. Should the revert be
cherry-picked into drm-misc-next-fixes?
Seemed like an
[Public]
Reviewed-by: Alex Deucher
Looks like gmc11 is missing this too. Care to send a patch for that as well?
Alex
From: Liu, Aaron
Sent: Thursday, July 21, 2022 10:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liu, Aaron
On Fri, 22 Jul 2022 22:32:06 +1000
Michael Ellerman wrote:
> Hi Dan,
>
> [ Cc += linuxppc-dev ]
>
> Dan Horák writes:
> > Commit d11219ad53dc disabled the DCN driver for all platforms that
> > define PPC64 due long build issues during "make allmodconfig" using
> > cross-compilation. Cross-com
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> SRIOV needs to initialize mmsch instead of multimedia engines
> directly. So currently remove them for SR-IOV until the code and
> firmwares are ready.
>
> Signed-off-by: Horace Chen
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/a
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> SR-IOV may need to load different firmwares for different ASIC inside
> VF.
> So create a new function in amdgpu_virt to check whether FW load needs
> to be skipped.
>
> Signed-off-by: Horace Chen
Acked-by: Alex Deucher
> ---
> drivers/gp
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> [Why]
> under SR-IOV, the nbio doorbell range will be defined by PF. So VF
> nbio doorbell range registers will be blocked. It will cause violation
> if VF access those registers directly.
>
> [How]
> create an nbio_v4_3_sriov_funcs for sriov
On Thu, Jul 21, 2022 at 11:32 PM Chen, Horace wrote:
>
> [AMD Official Use Only - General]
>
> Hi Alex,
>
> By current design, we will keep this register same for all new asics.
> Also, the amdgpu_detect_virtualization will be called before we read the IP
> discovery table (virtualization needs t
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> [Why]
> Under SR-IOV, if VF is switched out then its doorbell will be disabled,
> SDMA rely on WPTR_POLL to get doorbells which was sent during VF
> switched-out time.
>
> [How]
> For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1.
>
> Signed-off-by:
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> [Why]
> Under SR-IOV, we are not sure whether pipe status is
> good or not when doing initialization. The compute engine
> maybe fail to bringup if pipe status is bad.
Seems like this should be safe for bare metal too. Can we just do
this fo
On Fri, 22 Jul 2022 22:32:06 +1000
Michael Ellerman wrote:
> Hi Dan,
>
> [ Cc += linuxppc-dev ]
>
> Dan Horák writes:
> > Commit d11219ad53dc disabled the DCN driver for all platforms that
> > define PPC64 due long build issues during "make allmodconfig" using
> > cross-compilation. Cross-com
Commit d11219ad53dc disabled the DCN driver for all platforms that
define PPC64 due long build issues during "make allmodconfig" using
cross-compilation. Cross-compilation defaults to the ppc64_defconfig
and thus big-endian toolchain configuration. The ppc64le platform uses a
different ABI and does
Am 20.07.22 um 18:05 schrieb Alex Deucher:
Move additional dummy structures off the stack and into
the dummy vars structure.
Fixes the following:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPe
Well NAK to the debugfs approach, stuff like that is usually a module
parameter.
Apart from that this series needs to be reviewed by Andrey.
Regards,
Christian.
Am 22.07.22 um 09:34 schrieb Victor Zhao:
Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of rese
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |
For some hang caused by slow tests, engine cannot be stopped which
may cause resume failure after reset. In this case, force halt
engine by reverting context addresses
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h |
Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of reset. Also helps blocking unwanted type of
resets.
By default, mode2 reset will not be enabled
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 26 +++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 72 +++
drivers/gpu/dr
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid. Adding a AMDGPU_SKIP_MODE2_RESET
flag so driver can fallback to default reset method when mode2
reset failed and retry.
- add mode2 reset ha
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