Am 02.06.22 um 01:19 schrieb Felix Kuehling:
Am 2022-06-01 um 19:12 schrieb Philip Yang:
Update PDEs, PTEs don't need flush TLB after updating mapping, this will
remove the unnecessary TLB flush to reduce map to GPUs time.
This description is unclear. I think what this change does is, flush
T
Am 01.06.22 um 19:47 schrieb Bas Nieuwenhuizen:
On Wed, Jun 1, 2022 at 2:40 PM Christian König wrote:
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM updates and a bunch of prototype patches.
I've been thinking about that stuff for quite some
Am 01.06.22 um 19:39 schrieb Felix Kuehling:
Am 2022-06-01 um 13:22 schrieb Christian König:
Am 01.06.22 um 19:07 schrieb Felix Kuehling:
Am 2022-06-01 um 12:29 schrieb Christian König:
Am 01.06.22 um 17:05 schrieb Felix Kuehling:
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys
[AMD Official Use Only - General]
> -Original Message-
> From: Christian König
> Sent: Monday, May 30, 2022 3:12 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH] drm/amdgpu: suppress compile warnings
>
> Am 30.05.22 um 08:50 schrieb E
Dan: I also ran Smatch which resulted in the following discussion:
https://lists.freedesktop.org/archives/amd-gfx/2022-May/079228.html
Regards
Den ons 1 juni 2022 kl 20:44 skrev Alex Deucher :
> On Fri, May 27, 2022 at 3:46 AM Dan Carpenter
> wrote:
> >
> > [ kbuild bot sent this warning on Ma
Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc()
with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code
that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with
-Werror=unused-function.
Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for
Am 2022-06-01 um 19:12 schrieb Philip Yang:
Update PDEs, PTEs don't need flush TLB after updating mapping, this will
remove the unnecessary TLB flush to reduce map to GPUs time.
This description is unclear. I think what this change does is, flush
TLBs when existing PDEs are updated (because a
Update PDEs, PTEs don't need flush TLB after updating mapping, this will
remove the unnecessary TLB flush to reduce map to GPUs time.
Suggested-by: Christian König
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
From: Daniel Phillips
Add a new KFD ioctl to return the largest possible memory size that
can be allocated as a buffer object using
kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same
accept/reject criteria as that function so that allocating a new
buffer object of the size returne
On Wed, Jun 1, 2022 at 4:53 PM David Yat Sin wrote:
>
> From: Daniel Phillips
>
> Add a new KFD ioctl to return the largest possible memory size that
> can be allocated as a buffer object using
> kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same
> accept/reject criteria as that f
From: Daniel Phillips
Add a new KFD ioctl to return the largest possible memory size that
can be allocated as a buffer object using
kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same
accept/reject criteria as that function so that allocating a new
buffer object of the size returne
The EDID of an HDR display defines EOTFs that are supported
by the display and can be set in the HDR metadata infoframe.
Userspace is expected to read the EDID and set an appropriate
HDR_OUTPUT_METADATA.
In drm_parse_hdr_metadata_block the kernel reads the supported
EOTFs from the EDID and stores
Applied. Thanks!
Alex
On Mon, May 30, 2022 at 7:42 AM Dan Carpenter wrote:
>
> We know that "grbm_soft_reset" is true because we're already inside an
> if (grbm_soft_reset) condition. No need to test again.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 24
On Fri, May 27, 2022 at 3:46 AM Dan Carpenter wrote:
>
> [ kbuild bot sent this warning on May 4 but I never heard back and it's
> May 27 now so sending a duplicate warning is probably for the best. -dan]
>
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
>
[AMD Official Use Only - General]
Thanks, added the tag before pushing.
Thanks,
Candice
-Original Message-
From: Alex Deucher
Sent: Thursday, June 2, 2022 2:02 AM
To: Li, Candice
Cc: amd-gfx list
Subject: Re: [PATCH v2] drm/amdgpu: Resolve RAS GFX error count issue v2
On Wed, Jun
On Wed, Jun 1, 2022 at 2:01 PM Alex Deucher wrote:
>
> On Wed, Jun 1, 2022 at 1:57 PM Candice Li wrote:
> >
> > Fix misleading indentation and add ras unsupported checking
> > for gfx ras late init.
> >
> > Signed-off-by: Candice Li
>
> Reviewed-by: Alex Deucher
Also, if this was a recent chan
On Wed, Jun 1, 2022 at 1:57 PM Candice Li wrote:
>
> Fix misleading indentation and add ras unsupported checking
> for gfx ras late init.
>
> Signed-off-by: Candice Li
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +---
> 1 file changed, 5 insertions(+), 3
Fix misleading indentation and add ras unsupported checking
for gfx ras late init.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdg
On Wed, Jun 1, 2022 at 2:40 PM Christian König wrote:
>
> Hey guys,
>
> so today Bas came up with a new requirement regarding the explicit
> synchronization to VM updates and a bunch of prototype patches.
>
> I've been thinking about that stuff for quite some time before, but to
> be honest it's o
Am 2022-06-01 um 13:22 schrieb Christian König:
Am 01.06.22 um 19:07 schrieb Felix Kuehling:
Am 2022-06-01 um 12:29 schrieb Christian König:
Am 01.06.22 um 17:05 schrieb Felix Kuehling:
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys,
so today Bas came up with a new requirement r
[Public]
Thanks for the review.
To fix the indentation will require the else case to let
amdgpu_ras_block_late_init can go to ras unsupported code path.
That's why I want to keep them in one patch.
I will update the commit message and coding style as you suggested.
Thanks,
Candice
-Origi
On Mon, May 30, 2022 at 10:27 PM Sunil Khatri wrote:
>
> Add IP GC 10.3.7 in the list of target to have
> tmz enabled by default.
>
> Signed-off-by: Sunil Khatri
Assuming this is validated and working,
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 ++--
> 1 fil
Am 01.06.22 um 19:07 schrieb Felix Kuehling:
Am 2022-06-01 um 12:29 schrieb Christian König:
Am 01.06.22 um 17:05 schrieb Felix Kuehling:
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM update
On Wed, Jun 1, 2022 at 1:10 PM Candice Li wrote:
>
> Fix misleading indentation
>
Might want to split this into two patches, one to fix the indentation
and one to fix the missing function call. Also you should mention the
missing function call in the else case.
> Signed-off-by: Candice Li
> --
Fix misleading indentation
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 99c1a2d3dae84d..424990e1bec10c 10
Am 2022-06-01 um 12:29 schrieb Christian König:
Am 01.06.22 um 17:05 schrieb Felix Kuehling:
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM updates and a bunch of prototype patches.
I've bee
[AMD Official Use Only - General]
Hi Rodrigo,
Sorry, my bad! Thanks for the fix, but only adjust the indentation will miss
another code path for amdgpu_ras_block_late_init.
Let me submit a new one to fix it.
Thanks,
Candice
-Original Message-
From: Siqueira, Rodrigo
Sent: Wednesday
Am 2022-05-31 um 13:03 schrieb Ramesh Errabolu:
Extend KFD device topology to surface peer-to-peer links among
GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is
REQUIRED to surface peer-to-peer links.
This patch needs more of an explanation.
Old upstream KFD did not expose to us
Bas has the problem that CS implicitly waits for VM updates.
Currently when you unmap a BO the operation will only be executed after
all the previously made CS are finished.
Similar for mapping BOs. The next CS will only start after all the
pending page table updates are completed.
The mapp
Am 01.06.22 um 17:05 schrieb Felix Kuehling:
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM updates and a bunch of prototype patches.
I've been thinking about that stuff for quite some time b
Can you please summarize what this is about?
Thanks,
Marek
On Wed, Jun 1, 2022 at 8:40 AM Christian König
wrote:
> Hey guys,
>
> so today Bas came up with a new requirement regarding the explicit
> synchronization to VM updates and a bunch of prototype patches.
>
> I've been thinking about that
Am 2022-05-31 um 13:01 schrieb Ramesh Errabolu:
Add support for peer-to-peer communication, in both data and control
planes, among AMD GPUs that are connected PCIe and have large BAR vBIOS.
Please don't use the "control plane", "data plane" terminology here.
This is not common usage in this
Am 2022-05-31 um 13:02 schrieb Ramesh Errabolu:
Extend current kernel config requirements of amdgpu by adding
config HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support
peer-to-peer communication, in both data and control planes, among
AMD GPU devices that are connected via PCIe and have lar
Am 2022-06-01 um 08:40 schrieb Christian König:
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM updates and a bunch of prototype patches.
I've been thinking about that stuff for quite some time before, but to
be honest it's one of the most
Am 01.06.22 um 16:55 schrieb Alex Deucher:
On Fri, May 27, 2022 at 8:58 AM Michal Kubecek wrote:
On Fri, May 27, 2022 at 11:00:39AM +0200, Michal Kubecek wrote:
Hello,
while testing 5.19 merge window snapshots (commits babf0bb978e3 and
7e284070abe5), I keep getting errors like below. I have n
Yes, this is a good change--abstracting the SMU messaging registers for ASICs.
Reviewed-by: Luben Tuikov
Regards,
Luben
On 2022-05-26 14:00, Alex Deucher wrote:
> Use the per asic offsets so the we don't have to have
> asic specific logic in the common code.
>
> Signed-off-by: Alex Deucher
>
On Fri, May 27, 2022 at 8:58 AM Michal Kubecek wrote:
>
> On Fri, May 27, 2022 at 11:00:39AM +0200, Michal Kubecek wrote:
> > Hello,
> >
> > while testing 5.19 merge window snapshots (commits babf0bb978e3 and
> > 7e284070abe5), I keep getting errors like below. I have not seen them
> > with 5.18 f
On Wed, Jun 1, 2022 at 3:27 AM ZhenGuo Yin wrote:
>
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Missing your signed-off-by.
GCC is complaining about misleading indentation:
error: this ‘if’ clause does not guard... [-Werror=misleading-indentation]
603 | if (r)
This commit adjusts the commit indentation.
Cc: Candice Li
Cc: Hawking Zhang
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.
On Tue, May 31, 2022 at 6:56 PM Hans de Goede wrote:
>
> Hi,
>
> On 5/30/22 13:34, Hsin-Yi Wang wrote:
> > On Mon, May 30, 2022 at 4:53 PM Hans de Goede wrote:
> >>
> >> Hi,
> >>
> >> On 5/30/22 10:19, Hsin-Yi Wang wrote:
> >>> Some drivers, eg. mtk_drm and msm_drm, rely on the panel to set the
>
[why]
A gfx job may be processed but not finished when reset begin from
compute job timeout. drm_sched_resubmit_jobs_ext in sched_main
assume submitted job unsignaled and always put parent fence.
Resubmission for that job cause underflow. This fix is done in
device reset to avoid changing drm sched
[Public]
Hi Christian,
No other comments. With p->jobs[i] fixed, the test case worked. I have to clean
up the code and send it for review.
I wanted to add comparing the time with and without gang submission and fail
test case if former is slow. I will do this later. I will send the test case
f
Hey guys,
so today Bas came up with a new requirement regarding the explicit
synchronization to VM updates and a bunch of prototype patches.
I've been thinking about that stuff for quite some time before, but to
be honest it's one of the most trickiest parts of the driver.
So my current thi
Am 01.06.22 um 14:09 schrieb Mohan Marimuthu, Yogesh:
[SNIP]
- /* Make sure all BOs are remembered as writers */
- amdgpu_bo_list_for_each_entry(e, p->bo_list)
+ list_for_each_entry(e, &p->validated, tv.head) {
+
+ /* Everybody except for the gang leader uses BO
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Thursday, March 3, 2022 1:53 PM
To: amd-gfx@lists.freedesktop.org; Olsak, Marek
Cc: Koenig, Christian
Subject: [PATCH 10/10] drm/amdgpu: add gang submit frontend
Allows submitting j
Am 01.06.22 um 09:27 schrieb ZhenGuo Yin:
The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.
Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Maybe better but the register offset into a
Am 26.05.22 um 19:58 schrieb Alex Deucher:
Enable the AGP aperture on chips with GMC v11.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 7 ---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 1 +
drivers/gpu/drm/amd/amdgpu/mmhu
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Wednesday, June 1, 2022 18:01
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH] drm/amdgpu: Resolve RAS GFX error count issue af
Adjust the sequence for ras late init and separate ras reset error status
from query status.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 27 -
2 files changed, 26 insertions(+), 8 deletions(
The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.
Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
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