[Public]
You need to add a Fix tag in the commit message, and pls document the null
pointer calltrace as well.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Asher Song
Sent: Friday, November 5, 2021 12:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Song, Asher
Subject: [P
To avoid NULL pointer, assign dpms for amdgpu_vkms_crtc_helper_funcs.
Signed-off-by: Asher Song
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 +++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
b/drivers/gpu/drm/am
On 2021-11-04 4:19 a.m., Evan Quan wrote:
It's confirmed that on some APUs the interaction with SMU about DPM disablement
will power off the UVD completely. Thus the succeeding interactions with UVD
during the reboot will trigger hard hang. To workaround this issue, we will skip
the dpm disable
Reviewed-By: Ramesh Errabolu
Sent: Thursday, November 4, 2021 6:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Errabolu, Ramesh
Subject: [PATCH 1/1] drm/amdgpu: Fix dangling kfd_bo pointer for shared BOs
If a kfd_bo was shared (e.g. a dmabuf export), the original kfd_bo may be freed
when the amdg
If a kfd_bo was shared (e.g. a dmabuf export), the original kfd_bo may be
freed when the amdgpu_bo still lives on. Free the kfd_bo struct in the
release_notify callback then the amdgpu_bo is freed.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 ++--
driv
From: Jimmy Kizito
[Why]
Stream ordering and count can vary from one state to the next. Only
checking a subset of entries in the encoder assignment table can lead to
invalid encoder assignments.
[How]
Check all entries in encoder assignment table when querying it.
Reviewed-by: Jun Lei
Acked-by
From: Jimmy Kizito
[Why]
Link encoder assignment tracking variables need to be (re)initialised
whenever dc_state is (re)initialised. Otherwise variables used for
dynamic encoder assignment (especially the link encoder availability
pool) are out of sync with dc_state and future encoder assignments
From: Aric Cyr
This version brings along following fixes:
- Improvements to INBOX0 HW Lock
- Add support for sending TPS3 pattern
- Fix Coverity Issues
- Fixes for DMUB
- Fix RGB MPO underflow with multiple displays
- WS fixes and code restructure
Acked-by: Anson Jacob
Signed-off-by: Aric Cyr
From: Meenakshikumar Somasundaram
[Why]
For dpia link, link->hpd_status indicates current state, but driver
fails to capture hpd transitions in certain scenarios such as during
link training.
[How]
Added link->hpd_pending flag that captures arrival of new hpd.
Reviewed-by: Jun Lei
Acked-by: An
From: Alvin Lee
[Why]
In DC we want to wait for the INBOX0 HW Lock
command to ACK before continuing. This is to
ensure that the lock has been successfully acquired
before programming HW in DC.
[How]
Add interfaces to send messages on INBOX0,
poll for their completation and clear the ack.
Review
From: Nicholas Kazlauskas
[Why]
We need HPD IRQ notifications (RX, short pulse) to properly handle
DP MST for DPIA connections.
[How]
A null pointer exception currently occurs when these are received
so add a check to validate that we have a handler installed for
the notification.
Extend the HP
From: Robin Chen
[Why]
Some panels require to use TPS3 pattern to wake up link in PSR mode.
[How]
To add TPS3 selection information in PSR settings command and pass to
DMUB FW.
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dce/dm
From: Charlene Liu
Reviewed-by: Sung joon Kim
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/cor
From: Chris Park
[Why]
Coverity discovers holes in logic that
needs to be addressed for improved
code integrity.
[How]
Address issues found by coverity without
changing the actual logic.
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc
From: Nicholas Kazlauskas
[Why]
Per DRM spec we only need to hold that lock when touching
connector->state - which we do not do in that handler.
Taking this locking introduces unnecessary dependencies with other
threads which is bad for performance and opens up the potential for
a deadlock since
From: Sung Joon Kim
[why]
At every reference to stream pointer, we need
to increment/decrement the kref_count.
Not doing so will result in invalid stream
pointer still alive after hibernate cycle.
[how]
Call stream retain/release whenever
the link encoder assignment is set to
true/false since it
From: Roy Chan
[Why]
The link encoder assignment leaves the old stream data when it
was unassigned. When the clear encoder assignment is called,
it based on the old stale data to access the de-allocated stream.
[How]
There should be no need to explicitly clean up the link encoder
assignment if t
From: "Huang, ChiaWen"
[Why & How]
According to eDP spec, DPCD 1.3 is only for eDP DPCD v1.4
In dpcd_set_link_settings function, the driver is just above v1.3
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by: ChiawenHuang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +
From: Dmytro Laktyushkin
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 8
.../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h | 7 +++
2 files changed, 11 insertions(+
From: Angus Wang
[WHY]
With RGB MPO enabled, playing a video with multiple displays
connected results in underflow when closing the video window
[HOW]
Reverted the old change to fix this problem, which prevented
pipe splits for multiple display configurations and caused
high MCLK speeds during i
From: Nicholas Kazlauskas
[Why]
A built firmware binary may be aligned to 16-bytes with padding at the
end as necessary. In the case that padding was applied the meta info
will not be detected correctly and we won't be able to allocate the
appropriate firmware and tracebuffer sizes.
[How]
To mai
From: Charlene Liu
[why]
reduce az indirect register dump. need add az
clock_gating control field used in some project.
[how]
conditional output indrect register in the log.
add clock_gating feild
Reviewed-by: Sung joon Kim
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/d
From: Mikita Lipski
[why]
PSR set power command wasn't setting panel instance
and command version which caused both streams
to overwrite the same PSR state.
[how]
Pass panel instance to the set power command function
and to DMUB and set command version enum
Reviewed-by: Anthony Koo
Acked-by: An
From: Jimmy Kizito
[Why]
The link_enc_cfg API operates in one of two modes depending on
the stage of application of dc_state to hardware. The API is the
safest way to query link encoder assignments.
[How]
Use results of link encoder assignment query using link_enc_cfg
API.
Reviewed-by: Jun Lei
From: Charlene Liu
[why]
matching the dmcub_support with all other dcn version.
Reviewed-by: Sung joon Kim
Reviewed-by: Martin Leung
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 --
1 file changed, 2 deletions(-)
diff --g
From: "Leo (Hanghong) Ma"
[Why & How]
1. The code to blank all dp display have been called many times,
so add helpers in dc_link to make it more concise.
2. Add some check to fix the dmesg errors at boot and resume from S3
on dcn3.1 during DQE's promotion test.
Reviewed-by: Alvin Lee
Reviewed-b
This DC patchset brings improvements in multiple areas. In summary, we
have:
* Improvements to INBOX0 HW Lock
* Add support for sending TPS3 pattern
* Fix Coverity Issues
* Fixes for DMUB
* Fix RGB MPO underflow with multiple displays
* WS fixes and code restructure
Alvin Lee (1):
drm/amd/displ
Trivial patch which adds a comment for macro
endif's in amdgpu_dm.c
Reviewed-by: Ariel Bernstein
Reviewed-by: Harry Wentland
Acked-by: Anson Jacob
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
drivers/gpu/drm/amd/display/dc/core/dc.c |
The HPD flush registers are not directly accessible on SRIOV. For kernel
usage, use WREG32, which uses KIQ on SRIOV. For user mode, don't allow
mapping the MMIO register on SRIOV.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 -
drivers/gpu/drm/amd/amdgpu/h
Hello Jani,
On 11/4/21 20:57, Jani Nikula wrote:
> On Thu, 04 Nov 2021, Javier Martinez Canillas wrote:
>> +/**
>> + * drm_drv_enabled - Checks if a DRM driver can be enabled
>> + * @driver: DRM driver to check
>> + *
>> + * Checks whether a DRM driver can be enabled or not. This may be the case
From: Mark Yacoub
[Why]
drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
sizes. There is no need to check it within amdgpu_dm_atomic_check.
[How]
Remove the local call to verify LUT sizes and use DRM Core function
instead.
Tested on ChromeOS Zork.
v1:
Remove amdgpu_dm_v
On Thu, 04 Nov 2021, Javier Martinez Canillas wrote:
> +/**
> + * drm_drv_enabled - Checks if a DRM driver can be enabled
> + * @driver: DRM driver to check
> + *
> + * Checks whether a DRM driver can be enabled or not. This may be the case
> + * if the "nomodeset" kernel command line parameter is
On Thu, 04 Nov 2021, Sam Ravnborg wrote:
> Hi Javier,
>
>>
>> >>>
>> >>> -if (vgacon_text_force() && i915_modparams.modeset == -1)
>> >>> +ret = drm_drv_enabled(&driver);
>> >>
>> >> You pass the local driver variable here - which looks wrong as this is
>> >> not the same as the
Hi Javier,
>
> >>>
> >>> - if (vgacon_text_force() && i915_modparams.modeset == -1)
> >>> + ret = drm_drv_enabled(&driver);
> >>
> >> You pass the local driver variable here - which looks wrong as this is
> >> not the same as the driver variable declared in another file.
> >
>
> Yes, Jani ment
Hello Sam,
On 11/4/21 18:57, Jani Nikula wrote:
> On Thu, 04 Nov 2021, Sam Ravnborg wrote:
>> Hi Javier,
>>
>> On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote:
>>> Some DRM drivers check the vgacon_text_force() function return value as an
>>> indication on whether they sh
On 11/4/21 17:24, Jani Nikula wrote:
[snip]
>> index ab2295dd4500..45cb3e540eff 100644
>> --- a/drivers/gpu/drm/i915/i915_module.c
>> +++ b/drivers/gpu/drm/i915/i915_module.c
>> @@ -18,9 +18,12 @@
>> #include "i915_selftest.h"
>> #include "i915_vma.h"
>>
>> +static const struct drm_driver dri
Some DRM drivers check the vgacon_text_force() function return value as an
indication on whether they should be allowed to be enabled or not.
This function returns true if the nomodeset kernel command line parameter
was set. But there may be other conditions besides this to determine if a
driver s
There is a lot of historical baggage on this parameter. It is defined in
the vgacon driver as nomodeset, but its set function is called text_mode()
and the value queried with a function named vgacon_text_force().
All this implies that it's about forcing text mode for VGA, yet it is not
used in nei
The "nomodeset" kernel cmdline parameter is handled by the vgacon driver
but the exported vgacon_text_force() symbol is only used by DRM drivers.
It makes much more sense for the parameter logic to be in the subsystem
of the drivers that are making use of it.
Let's move the vgacon_text_force() fu
From: Mark Yacoub
[Why]
drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
sizes. There is no need to check it within amdgpu_dm_atomic_check.
[How]
Remove the local call to verify LUT sizes and use DRM Core function
instead.
Tested on ChromeOS Zork.
v1:
Remove amdgpu_dm_v
On Thu, 04 Nov 2021, Sam Ravnborg wrote:
> Hi Javier,
>
> On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote:
>> Some DRM drivers check the vgacon_text_force() function return value as an
>> indication on whether they should be allowed to be enabled or not.
>>
>> This functi
Hi Javier,
On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote:
> Some DRM drivers check the vgacon_text_force() function return value as an
> indication on whether they should be allowed to be enabled or not.
>
> This function returns true if the nomodeset kernel command lin
When kfd need to be reset, sent command to HWS might cause hang and get
unnecessary timeout.
This change try not to touch HW in pre_reset and keep queues to be in the
evicted state
when the reset is done, so they are not put back on the runlist. These queues
will be destroied
on process terminat
On Thu, Nov 4, 2021 at 12:09 PM Mario Limonciello
wrote:
>
> Previously there was a check based on chip # for chips that aligned to
> >=CHIP_NAVI10 to have RLC stopped as part of DPMS check. This was because
> of gfxclk being controlled by RLC in the newer designs.
>
> As part of IP version check
On Thu, 04 Nov 2021, Javier Martinez Canillas wrote:
> Some DRM drivers check the vgacon_text_force() function return value as an
> indication on whether they should be allowed to be enabled or not.
>
> This function returns true if the nomodeset kernel command line parameter
> was set. But there
[AMD Official Use Only]
> -Original Message-
> From: amd-gfx On Behalf Of Felix
> Kuehling
> Sent: September 13, 2021 5:23 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH v2 1/1] drm/amdkfd: Add sysfs bitfields and enums to
> uAPI
>
> [CAUTION: External Email]
>
> These bits are
Previously there was a check based on chip # for chips that aligned to
>=CHIP_NAVI10 to have RLC stopped as part of DPMS check. This was because
of gfxclk being controlled by RLC in the newer designs.
As part of IP version checking though, this got changed to match IP
version for SMU. Because Re
On Thu, Nov 04, 2021 at 09:48:41AM +0100, Maxime Ripard wrote:
> Hi Ville,
>
> On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote:
> > On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > > > --- a/driver
On Thu, Nov 4, 2021 at 4:20 AM Evan Quan wrote:
>
> There was a change(below) target for such issue:
> cdccf1ffe1a3 drm/amdgpu: Fix crash on device remove/driver unload
proper formatting for a patch reference:
cdccf1ffe1a3 ("drm/amdgpu: Fix crash on device remove/driver unload")
> But the fix fo
On Thu, Nov 4, 2021 at 2:20 AM Evan Quan wrote:
>
> As part of the ib padding process, accessing the RLC_SPM_* register may
> trigger gfx hang. Since gfxoff may be already kicked during the whole period.
> To address that, we manually toggle gfx on/off around the RLC_SPM_*
> register access.
>
> T
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Thursday, November 4, 2021 17:01
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Clements, John ; Yang, Stanley
Cc: Zhou1, Tao
Subject: [PATCH] drm/amdgpu: correct xgmi r
Am 04.11.21 um 10:40 schrieb YuBiao Wang:
[Why]
csb bo is not unpinned in gfx 9. It will lead to pin_count leak on
driver unload.
[How]
Call bo_free_kernel corresponding to bo_create_kernel in
gfx_rlc_init_csb. This will also unify the code path with other gfx
versions.
Signed-off-by: YuBiao Wa
[Why]
csb bo is not unpinned in gfx 9. It will lead to pin_count leak on
driver unload.
[How]
Call bo_free_kernel corresponding to bo_create_kernel in
gfx_rlc_init_csb. This will also unify the code path with other gfx
versions.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0
Hi Ville,
On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4966,
The error count reset for xgmi3x16 pcs is missed.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 978ac927ac11..
On 11/4/2021 1:49 PM, Evan Quan wrote:
It's confirmed that on some APUs the interaction with SMU about DPM disablement
will power off the UVD completely. Thus the succeeding interactions with UVD
during the reboot will trigger hard hang. To workaround this issue, we will skip
the dpm disableme
Am 04.11.21 um 09:49 schrieb Matthew Auld:
On 04/11/2021 07:34, Christian König wrote:
Am 03.11.21 um 20:25 schrieb Matthew Auld:
On 25/10/2021 14:00, Arunpravin wrote:
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
Signed-off-by
On 04/11/2021 07:34, Christian König wrote:
Am 03.11.21 um 20:25 schrieb Matthew Auld:
On 25/10/2021 14:00, Arunpravin wrote:
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
Signed-off-by: Arunpravin
+ spin_lock(&mgr->
Am 04.11.21 um 09:19 schrieb Evan Quan:
It's confirmed that on some APUs the interaction with SMU about DPM disablement
will power off the UVD completely. Thus the succeeding interactions with UVD
during the reboot will trigger hard hang. To workaround this issue, we will skip
the dpm disablement
There was a change(below) target for such issue:
cdccf1ffe1a3 drm/amdgpu: Fix crash on device remove/driver unload
But the fix for VI ASICs was missing there. This is a supplement for
that.
Signed-off-by: Evan Quan
Change-Id: Iedc25e2f572f04772511d56781b01b481e22fd00
---
drivers/gpu/drm/amd/amdg
It's confirmed that on some APUs the interaction with SMU about DPM disablement
will power off the UVD completely. Thus the succeeding interactions with UVD
during the reboot will trigger hard hang. To workaround this issue, we will skip
the dpm disablement on APUs.
Signed-off-by: Evan Quan
Chang
Am 04.11.21 um 08:49 schrieb Christian König:
Am 04.11.21 um 03:55 schrieb YuBiao Wang:
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.
[How]
Skip writing GMC registers under sriov.
Signed-off-by: YuBiao Wang
--
As discussed previous I don't think this is the right approach.
The distinction between sysfs_emit() and sysfs_emit_at() is exactly to
avoid that kind of stuff.
Instead we should probably add the size parameter to the functions in
question and so fix the calling convention.
Or even better m
Am 04.11.21 um 03:55 schrieb YuBiao Wang:
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.
[How]
Skip writing GMC registers under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c |
Am 03.11.21 um 20:25 schrieb Matthew Auld:
On 25/10/2021 14:00, Arunpravin wrote:
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
Signed-off-by: Arunpravin
+ spin_lock(&mgr->lock);
+ r = drm_buddy_alloc(mm, (uin
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