get_wave_state acquires the mmap_lock on copy_to_user but so do
mmu_notifiers. mmu_notifiers allows dqm locking so do get_wave_state
outside the dqm_lock to prevent circular locking.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 27
On 2021-06-11 1:51 p.m., Alex Deucher wrote:
> On Fri, Jun 11, 2021 at 1:30 PM Luben Tuikov wrote:
>> On 2021-06-11 1:16 p.m., Alex Deucher wrote:
>>> On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
Add "ras_eeprom_size" file in debugfs, which
reports the maximum size allocated to th
Am 2021-06-11 um 1:55 p.m. schrieb philip yang:
>
>
> On 2021-06-10 7:29 p.m., Felix Kuehling wrote:
>> When some GPUs don't support SVM, don't disabe it for the entire process.
>> That would be inconsistent with the information the process got from the
>> topology, which indicates SVM support per
On 2021-06-10 7:29 p.m., Felix Kuehling
wrote:
When some GPUs don't support SVM, don't disabe it for the entire process.
That would be inconsistent with the information the process got from the
topology, which indicates SVM support per GPU.
Instead disable S
On 2021-06-11 1:17 p.m., Luben Tuikov wrote:
> On 2021-06-11 1:01 p.m., Alex Deucher wrote:
>> On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>>> Consult the i2c_adapter.quirks table for
>>> the maximum read/write data length per bus
>>> transaction. Do not exceed this transaction
>>> limit.
>
On 2021-06-11 1:16 p.m., Alex Deucher wrote:
> On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>> Add "ras_eeprom_size" file in debugfs, which
>> reports the maximum size allocated to the RAS
>> table in EEROM, as the number of bytes and the
>> number of records it could store. For instance,
>>
On 2021-06-11 1:01 p.m., Alex Deucher wrote:
> On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>> Consult the i2c_adapter.quirks table for
>> the maximum read/write data length per bus
>> transaction. Do not exceed this transaction
>> limit.
>>
>> Cc: Jean Delvare
>> Cc: Alexander Deucher
>>
For ASICs that need to load sys_drv_aux and sos_aux,
the sys_start_addr is not the start address of psp
ucode array because the sys_drv_aux and sos_aux actaully
located at the end of the ucode array, instead, the
psp ucode arrary start address should be sos_hdr +
sos_hdr_offset.
Signed-off-by: Haw
Just a heads up, your sender email and your signed-off-by don't match
and you had some assignments in if clauses. I've fixed those up.
Alex
On Fri, Jun 11, 2021 at 1:35 PM Alex Deucher wrote:
>
> Applied. Thanks!
>
> On Thu, Jun 10, 2021 at 5:14 PM Harry Wentland wrote:
> >
> >
> >
> > On 20
[Why&How]
PG registers are absent in beige goby, so programming these registers
generate call trace. Fix this by adding a dummy function in dcn303
initialization function which prevents writing to non existant registers.
Fixes: 54f910c6372e ("drm/amd/display: Initial DC support for Beige Goby")
Si
Am 2021-06-10 um 11:32 p.m. schrieb Alex Sierra:
> CoherentHostAccess flag support has moved from HSA_MEMORYPROPERTY
> to HSA_CAPABILITY struct. Proper changes have made also at the thunk
> to support this change.
>
> CoherentHostAccess: whether or not device memory can be coherently
> accessed by
On Fri, Jun 11, 2021 at 1:30 PM Luben Tuikov wrote:
>
> On 2021-06-11 1:16 p.m., Alex Deucher wrote:
> > On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
> >> Add "ras_eeprom_size" file in debugfs, which
> >> reports the maximum size allocated to the RAS
> >> table in EEROM, as the number of by
Applied. Thanks!
On Thu, Jun 10, 2021 at 5:14 PM Harry Wentland wrote:
>
>
>
> On 2021-06-07 10:53 a.m., Mark Yacoub wrote:
> > On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland
> > wrote:
> >>
> >>
> >>
> >> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
> >>> From: Mark Yacoub
> >>>
> >>> For each
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> Add "ras_eeprom_size" file in debugfs, which
> reports the maximum size allocated to the RAS
> table in EEROM, as the number of bytes and the
> number of records it could store. For instance,
>
> $cat /sys/kernel/debug/dri/0/ras/ras_eeprom_siz
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> Rename update_table_header() to
> write_table_header() as this function is actually
> writing it to EEPROM.
>
> Use kernel types; use u8 to carry around the
> checksum, in order to take advantage of arithmetic
> modulo 8-bits (256).
>
> Tidy u
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Consult the i2c_adapter.quirks table for
> the maximum read/write data length per bus
> transaction. Do not exceed this transaction
> limit.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanle
On Fri, Jun 11, 2021 at 11:48 AM Aurabindo Pillai
wrote:
>
> [Why&How]
> PG registers are absent in beige goby, so programming these registers
> generate call trace. Fix this by adding a dummy function in dcn303
> initialization function which prevents writing to non existant registers.
>
> Fixes:
On Fri, Jun 11, 2021 at 12:12:45PM +0200, Christian König wrote:
> Am 11.06.21 um 11:17 schrieb Daniel Vetter:
> > On Thu, Jun 10, 2021 at 11:18:00AM +0200, Christian König wrote:
> > > Drop the workaround and instead implement a better solution.
> > >
> > > Basically we are now chaining all submi
On Fri, Jun 11, 2021 at 12:09:19PM +0200, Christian König wrote:
> Am 11.06.21 um 11:07 schrieb Daniel Vetter:
> > On Thu, Jun 10, 2021 at 11:17:59AM +0200, Christian König wrote:
> > > Unwrap a the explicit fence if it is a dma_fence_chain and
> > > sync to the first fence not matching the owner r
On Fri, Jun 11, 2021 at 12:07:00PM +0200, Christian König wrote:
> Am 11.06.21 um 10:58 schrieb Daniel Vetter:
> > On Thu, Jun 10, 2021 at 11:17:57AM +0200, Christian König wrote:
> > > Add some rather sophisticated lockless garbage collection
> > > for dma_fence_chain objects.
> > >
> > > For thi
Am 11.06.21 um 16:56 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 02:03:01PM +0200, Christian König wrote:
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma
On Fri, Jun 11, 2021 at 02:03:01PM +0200, Christian König wrote:
> Drop the workaround and instead implement a better solution.
>
> Basically we are now chaining all submissions using a dma_fence_chain
> container and adding them as exclusive fence to the dma_resv object.
>
> This way other drive
On Fri, Jun 11, 2021 at 04:53:11PM +0200, Christian König wrote:
>
>
> Am 11.06.21 um 16:47 schrieb Daniel Vetter:
> > On Fri, Jun 11, 2021 at 02:02:57PM +0200, Christian König wrote:
> > > As the name implies if testing all fences is requested we
> > > should indeed test all fences and not skip
Am 11.06.21 um 16:52 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 02:02:59PM +0200, Christian König wrote:
Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
and some unused code in the selftest.
v2: polish kernel doc a bit
Signed-off-by: Christian König
Reviewed-by: D
Am 11.06.21 um 16:47 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 02:02:57PM +0200, Christian König wrote:
As the name implies if testing all fences is requested we
should indeed test all fences and not skip the exclusive
one because we see shared ones.
Signed-off-by: Christian König
Hm I
On Fri, Jun 11, 2021 at 02:02:59PM +0200, Christian König wrote:
> Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
> and some unused code in the selftest.
>
> v2: polish kernel doc a bit
>
> Signed-off-by: Christian König
> Reviewed-by: Daniel Vetter
Given how absolutely
[AMD Official Use Only]
Acked-by: Jingwen Chen
Best Regards,
JingWen Chen
-Original Message-
From: Yifan Zha
Sent: Friday, June 11, 2021 6:49 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk ; Chen, JingWen ; Zha,
YiFan(Even)
Subject: [PATCH] drm/amd/pm: Disable SMU messages in nav
[Why]
sriov vf send unsupported SMU message lead to fail.
[How]
disable related messages in sriov.
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_p
On Fri, Jun 11, 2021 at 02:02:57PM +0200, Christian König wrote:
> As the name implies if testing all fences is requested we
> should indeed test all fences and not skip the exclusive
> one because we see shared ones.
>
> Signed-off-by: Christian König
Hm I thought we've had the rule that when b
[Public]
Reviewed-by: Lijo Lazar
-Original Message-
From: Sundararaju, Sathishkumar
Sent: Thursday, June 10, 2021 10:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Sharma, Shashank ; Sundararaju,
Sathishkumar
Subject: [PATCH] drm/amd/pm: support ss me
On Fri, Jun 11, 2021 at 1:48 PM Christian König
wrote:
>
> Am 11.06.21 um 09:54 schrieb Daniel Vetter:
> > On Thu, Jun 10, 2021 at 11:17:55AM +0200, Christian König wrote:
> >> Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
> >> and some unused code in the selftest.
> >>
>
add support to read smart shift apu and dgpu power share
on renoir.
Signed-off-by: Sathishkumar S
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/s
add support to read smart shift apu and dgpu power share
on yellow_carp
Signed-off-by: Sathishkumar S
Reviewed-by: Lijo Lazar
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp
Unwrap the explicit fence if it is a dma_fence_chain and
sync to the first fence not matching the owner rules.
Signed-off-by: Christian König
Acked-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 118 +--
1 file changed, 68 insertions(+), 50 deletions(-)
di
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma_resv object.
This way other drivers can still sync to the single exclusive fence
while amdgpu only sync to fen
The callback and the irq work are never used at the same
time. Putting them into an union saves us 24 bytes and
makes the structure only 120 bytes in size.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-fence-chain.c | 2 +-
include/linux/dma-fence-chain.h
Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
and some unused code in the selftest.
v2: polish kernel doc a bit
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/st-dma-fence-chain.c | 16 -
drivers/gpu/drm/amd/amdgpu/am
As the name implies if testing all fences is requested we
should indeed test all fences and not skip the exclusive
one because we see shared ones.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 33 -
1 file changed, 12 insertions(+), 21 deletions(
Am 11.06.21 um 09:54 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:55AM +0200, Christian König wrote:
Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
and some unused code in the selftest.
Signed-off-by: Christian König
---
drivers/dma-buf/st-dma-fence-chain.c
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Dennis Li
Sent: Friday, June 11, 2021 15:16
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Zhang,
Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH] drm/
when the address is -1, TA will do error injection for all instances of
the specail sram.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 885a78301bbf..c828ce9525d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
PSP will dump various boot up information into a
portion of local frame buffer, called runtime database.
The helper function is used for driver to query those
shared information.
v2: init ret and check !ret to exit loop as soon as
found the entry
Signed-off-by: Hawking Zhang
Reviewed-by: John Cl
PSP runtime database is used to share various
boot up information with driver.
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 54 +
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/
GECC and G6 mem training are mutually exclusive
functionalities. VBIOS/PSP will set the flag
(BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in
runtime database to indicate whether dram memory
training need to be disabled or not.
For Navi1x families, two stage mem training is always
enabled.
Signed-of
PSP runtime boot_cfg_bitmask carries various psp bl
feature bit mask that can be used by driver. Cache
it in sw_init for further usage.
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++
drivers/gpu/drm/amd/a
More boot configs need to be supported via
BOOTCFG_CMD_SET
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_p
Dynamic GECC allows user to specify GECC enablement
status, which will take effect in next boot cycle.
v2: initialize boot_cfg to 0xFF
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 57 -
1
Query GECC enablement status in boot config
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/driver
psp_gfx_uresp_bootcfg is used to inform driver
bootcfg settings maintained by tOS
Signed-off-by: Hawking Zhang
Reviewed-by: John Clements
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/driver
Am 11.06.21 um 11:17 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:18:00AM +0200, Christian König wrote:
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma
Am 11.06.21 um 11:07 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:59AM +0200, Christian König wrote:
Unwrap a the explicit fence if it is a dma_fence_chain and
sync to the first fence not matching the owner rules.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_s
Am 11.06.21 um 10:58 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:57AM +0200, Christian König wrote:
Add some rather sophisticated lockless garbage collection
for dma_fence_chain objects.
For this keep all initialized dma_fence_chain nodes an a
queue and trigger garbage collection befor
Am 11.06.21 um 09:58 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:56AM +0200, Christian König wrote:
Exercise the newly added functions.
Signed-off-by: Christian König
I have honestly no idea what this checks. Spawning a few threads to
validate kmalloc/kfree feels a bit silly. Now tes
Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check that was performed in the
drm_mode_is_420_only() case, but not in the drm_mode_is_420_also() &&
force_yuv420_output case.
Without further knowledge if YCbCr 4:2:0 is supported outside of HDMI, there is
no reason to use RGB when the display reports d
On Thu, Jun 10, 2021 at 11:18:00AM +0200, Christian König wrote:
> Drop the workaround and instead implement a better solution.
>
> Basically we are now chaining all submissions using a dma_fence_chain
> container and adding them as exclusive fence to the dma_resv object.
>
> This way other drive
On Thu, Jun 10, 2021 at 11:17:59AM +0200, Christian König wrote:
> Unwrap a the explicit fence if it is a dma_fence_chain and
> sync to the first fence not matching the owner rules.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 118 +--
On Thu, Jun 10, 2021 at 11:17:57AM +0200, Christian König wrote:
> Add some rather sophisticated lockless garbage collection
> for dma_fence_chain objects.
>
> For this keep all initialized dma_fence_chain nodes an a
> queue and trigger garbage collection before a new one is
> allocated.
>
> Sign
[Why]
Avoid duplicated memory allocation for address ranges
that have been already allocated by either
ioctl_alloc_memory_of_gpu or SVM mechanisms first.
[How]
For SVM first allocations
Check if the address range passed into ioctl memory
alloc does not exist already in the kfd_process
svms->object
On Thu, Jun 10, 2021 at 11:17:56AM +0200, Christian König wrote:
> Exercise the newly added functions.
>
> Signed-off-by: Christian König
I have honestly no idea what this checks. Spawning a few threads to
validate kmalloc/kfree feels a bit silly. Now testing whether we correctly
rcu-delay the f
On Thu, Jun 10, 2021 at 11:17:55AM +0200, Christian König wrote:
> Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
> and some unused code in the selftest.
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/st-dma-fence-chain.c | 16 --
> driver
On Thu, Jun 10, 2021 at 11:17:54AM +0200, Christian König wrote:
> The callback and the irq work are never used at the same
> time. Putting them into an union saves us 24 bytes and
> makes the structure only 120 bytes in size.
Yeah pushing below 128 bytes makes sense.
>
> Signed-off-by: Christia
CoherentHostAccess flag support has moved from HSA_MEMORYPROPERTY
to HSA_CAPABILITY struct. Proper changes have made also at the thunk
to support this change.
CoherentHostAccess: whether or not device memory can be coherently
accessed by the host CPU.
Signed-off-by: Alex Sierra
---
drivers/gpu/
Hi,
On Wed, Jun 09, 2021 at 09:23:27PM +, Simon Ser wrote:
> This function sends a hotplug uevent with a CONNECTOR property.
>
> Signed-off-by: Simon Ser
> ---
> drivers/gpu/drm/drm_sysfs.c | 25 +
> include/drm/drm_sysfs.h | 1 +
> 2 files changed, 26 insertion
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