[AMD Official Use Only - Internal Distribution Only]
If it is not in manual mode, we should give the user a hint.
if possible, we should move this check into amdgpu_pm.c , it is also can be
used swsmu backend.
the patch is
Acked-by: Kevin Wang
Best Regards,
Kevin
__
[AMD Official Use Only - Internal Distribution Only]
+ Alex
Hi all,
Recently, many users reported the issue to us that fine grain not enabled.
Actually, most of them are just caused by not switching to “manual” mode.
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
-
On 2/8/21 2:27 AM, Daniel Vetter wrote:
On Mon, Feb 8, 2021 at 6:59 AM Andrey Grodzovsky
wrote:
On 1/20/21 10:59 AM, Daniel Vetter wrote:
On Wed, Jan 20, 2021 at 3:20 PM Andrey Grodzovsky
wrote:
On 1/20/21 4:05 AM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 01:18:15PM -0500, Andrey Gro
On 2/8/21 11:23 AM, Daniel Vetter wrote:
On Mon, Feb 8, 2021 at 3:00 PM Christian König wrote:
Am 08.02.21 um 11:11 schrieb Daniel Vetter:
On Mon, Feb 08, 2021 at 11:03:15AM +0100, Christian König wrote:
Am 08.02.21 um 10:48 schrieb Daniel Vetter:
On Mon, Feb 08, 2021 at 10:37:19AM +0100, C
On 2/8/21 4:37 AM, Christian König wrote:
Am 07.02.21 um 22:50 schrieb Daniel Vetter:
[SNIP]
Clarification - as far as I know there are no page fault handlers for kernel
mappings. And we are talking about kernel mappings here, right ? If there were
I could solve all those issues the same as I
[AMD Public Use]
Hi Alex,
Thanks for catching it.
But, please discard this patch as it was send out incorrectly.
-- Anson
From: Deucher, Alexander
Sent: Monday, February 8, 2021 2:58 PM
To: Jacob, Anson ; amd-gfx@lists.freedesktop.org
Cc: Brol, Eryk ; Li, Sun
On Mon, Feb 8, 2021 at 1:34 AM Alexander E. Patrakov wrote:
>
> пн, 8 февр. 2021 г. в 08:32, Alexander E. Patrakov :
> >
> > чт, 4 февр. 2021 г. в 09:31, Alex Deucher :
> > >
> > > On Wed, Feb 3, 2021 at 7:56 PM Eric W. Biederman
> > > wrote:
> > > >
> > > > Alex Deucher writes:
> > > >
> > > >
[AMD Official Use Only - Internal Distribution Only]
Patch is missing your signed-off-by. Please also give some details as to the
regression (blank screen, segfault, etc.) and affected platforms.
Alex
From: amd-gfx on behalf of Anson Jacob
Sent: Monday, Feb
On 2021-02-08 2:25 p.m., Anson Jacob wrote:
This reverts commit de6571ecbb88643fa4bb4172e65c12795a2f3124.
Patch causes regression in resume time.
Shouldn't affect any system that has an eDP connector on the board since
it's expected to be present in end user configuration.
If we want to rep
This reverts commit de6571ecbb88643fa4bb4172e65c12795a2f3124.
Patch causes regression in resume time.
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 40 +++-
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 --
2 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/driv
From: Victor Lu
[ Upstream commit 2abaa323d744011982b20b8f3886184d56d23946 ]
[why]
drm_atomic_commit was changed so that the caller must free their
drm_atomic_state reference on successes.
[how]
Add drm_atomic_commit_put after drm_atomic_commit call in
dm_force_atomic_commit.
Signed-off-by: Vi
From: Victor Lu
[ Upstream commit 3ddc818d9bb877c64f5c649beab97af86c403702 ]
[why]
prev_sink is not used anywhere else in the function and the reference to
it from dc_link is replaced with a new dc_sink.
[how]
Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink).
Signed-off-by: Victo
From: Victor Lu
[ Upstream commit 8e92bb0fa75bca9a57e4aba2e36f67d8016a3053 ]
[why]
An old dc_sink state is causing a memory leak because it is missing a
dc_sink_release before a new dc_sink is assigned back to
aconnector->dc_sink.
[how]
Decrement the dc_sink refcount before reassigning it to a
From: Victor Lu
[ Upstream commit 2abaa323d744011982b20b8f3886184d56d23946 ]
[why]
drm_atomic_commit was changed so that the caller must free their
drm_atomic_state reference on successes.
[how]
Add drm_atomic_commit_put after drm_atomic_commit call in
dm_force_atomic_commit.
Signed-off-by: Vi
From: Victor Lu
[ Upstream commit 3ddc818d9bb877c64f5c649beab97af86c403702 ]
[why]
prev_sink is not used anywhere else in the function and the reference to
it from dc_link is replaced with a new dc_sink.
[how]
Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink).
Signed-off-by: Victo
From: Sung Lee
[ Upstream commit 1622711beebe887e4f0f8237fea1f09bb48e9a51 ]
[WHY]
When enabling HDMI on ComboPHY, there are not
enough clock sources to complete display detection.
[HOW]
Initialize more clock sources.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Anson Jacob
Test
From: Victor Lu
[ Upstream commit 2abaa323d744011982b20b8f3886184d56d23946 ]
[why]
drm_atomic_commit was changed so that the caller must free their
drm_atomic_state reference on successes.
[how]
Add drm_atomic_commit_put after drm_atomic_commit call in
dm_force_atomic_commit.
Signed-off-by: Vi
From: Victor Lu
[ Upstream commit 8e92bb0fa75bca9a57e4aba2e36f67d8016a3053 ]
[why]
An old dc_sink state is causing a memory leak because it is missing a
dc_sink_release before a new dc_sink is assigned back to
aconnector->dc_sink.
[how]
Decrement the dc_sink refcount before reassigning it to a
From: Victor Lu
[ Upstream commit 3ddc818d9bb877c64f5c649beab97af86c403702 ]
[why]
prev_sink is not used anywhere else in the function and the reference to
it from dc_link is replaced with a new dc_sink.
[how]
Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink).
Signed-off-by: Victo
From: Mikita Lipski
[ Upstream commit 58180a0cc0c57fe62a799a112f95b60f6935bd96 ]
[why]
Need to unassign DSC from pipes that are not using it
so other pipes can acquire it. That is needed for
asic's that have unmatching number of DSC engines from
the number of pipes.
[how]
Before acquiring dsc t
From: Sung Lee
[ Upstream commit 1622711beebe887e4f0f8237fea1f09bb48e9a51 ]
[WHY]
When enabling HDMI on ComboPHY, there are not
enough clock sources to complete display detection.
[HOW]
Initialize more clock sources.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Anson Jacob
Test
From: George Shen
[ Upstream commit 2b6b7ab4b1cabfbee1af5d818efcab5d51d62c7e ]
[Why]
The translation between the DPCD value and the specified AUX_RD_INTERVAL
in the DP spec do not match.
[How]
Update values to match the spec.
Signed-off-by: George Shen
Reviewed-by: Wenjing Liu
Acked-by: Anso
thx for info
Von: Christian König
Gesendet: Montag, 8. Februar 2021 13:14:49
An: Walter Harms; Colin King; Alex Deucher; David Airlie; Daniel Vetter; Huang
Rui; Junwei Zhang; amd-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org
Cc: kernel-janit.
On Mon, Feb 8, 2021 at 3:00 PM Christian König wrote:
>
> Am 08.02.21 um 11:11 schrieb Daniel Vetter:
> > On Mon, Feb 08, 2021 at 11:03:15AM +0100, Christian König wrote:
> >> Am 08.02.21 um 10:48 schrieb Daniel Vetter:
> >>> On Mon, Feb 08, 2021 at 10:37:19AM +0100, Christian König wrote:
>
On 2021-01-24 11:00 p.m., Aurabindo Pillai wrote:
On 2021-01-21 2:05 p.m., Kazlauskas, Nicholas wrote:
On 2021-01-19 10:50 a.m., Aurabindo Pillai wrote:
[Why]
A seamless transition between modes can be performed if the new incoming
mode has the same timing parameters as the optimized mode on
[AMD Public Use]
> -Original Message-
> From: Takashi Iwai
> Sent: Saturday, February 6, 2021 7:29 AM
> To: Alex Deucher
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Li, Sun peng (Leo) ;
> Wentland, Harry ; Maling list - DRI developers
> ; amd-gfx list g...@lists.freedesktop.org>
>
On Sat, Feb 6, 2021 at 10:16 PM Kenneth Feng wrote:
>
> v1:
> Enable LCLK deep sleep and it works if we enable ASPM:
> modprobe amdgpu aspm=1
>
> v2:
> Add the amdgpu_aspm flag check
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
> 1 file
Fix the following coccicheck warning:
./drivers/gpu/drm/radeon/rs690.c:190:6-35: WARNING: Comparison to bool.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/radeon/rs690.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/rs69
Fix the following coccicheck warning:
./drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h:319:11-23:
WARNING: Comparison to bool.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 4 ++--
1 file changed, 2 insertions(+),
i am curious:
what is the win to have a unsigned 64 bit integer in the first
place ?
re,
wh
Von: Christian König
Gesendet: Montag, 8. Februar 2021 10:17:42
An: Colin King; Alex Deucher; David Airlie; Daniel Vetter; Huang Rui; Junwei
Zhang; amd-gfx@lists.
Am 08.02.21 um 11:11 schrieb Daniel Vetter:
On Mon, Feb 08, 2021 at 11:03:15AM +0100, Christian König wrote:
Am 08.02.21 um 10:48 schrieb Daniel Vetter:
On Mon, Feb 08, 2021 at 10:37:19AM +0100, Christian König wrote:
Am 07.02.21 um 22:50 schrieb Daniel Vetter:
[SNIP]
Clarification - as far
For start and end? The hardware has 48 bit address space and that won't
fit into 32bits.
Only the fragment handling can't do more than 2GB at the same time.
Christian.
Am 08.02.21 um 12:05 schrieb Walter Harms:
i am curious:
what is the win to have a unsigned 64 bit integer in the first
plac
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily.Deng
>-Original Message-
>From: Christian König
>Sent: Monday, February 8, 2021 6:05 PM
>To: Gu, JiaWei (Will) ; Koenig, Christian
>; amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: Re: [PATCH] drm/amdgpu:
On Mon, Feb 08, 2021 at 11:03:15AM +0100, Christian König wrote:
> Am 08.02.21 um 10:48 schrieb Daniel Vetter:
> > On Mon, Feb 08, 2021 at 10:37:19AM +0100, Christian König wrote:
> > > Am 07.02.21 um 22:50 schrieb Daniel Vetter:
> > > > [SNIP]
> > > > > Clarification - as far as I know there are n
Hi Jiawei,
ok in this case it's fine with me.
Just please also get a reviewed-by from somebody which has more KIQ
background than I have.
Thanks,
Christian.
Am 08.02.21 um 11:00 schrieb Gu, JiaWei (Will):
[AMD Official Use Only - Internal Distribution Only]
Hi Christian,
That's how many t
Am 08.02.21 um 10:48 schrieb Daniel Vetter:
On Mon, Feb 08, 2021 at 10:37:19AM +0100, Christian König wrote:
Am 07.02.21 um 22:50 schrieb Daniel Vetter:
[SNIP]
Clarification - as far as I know there are no page fault handlers for kernel
mappings. And we are talking about kernel mappings here,
[AMD Official Use Only - Internal Distribution Only]
Hi Christian,
That's how many times it would retry before give up.
And we always skip this retry routine if we are in interrupt, so it's fine for
interrupt condition.
Best regards,
Jiawei
-Original Message-
From: Christian König
Se
On Mon, Feb 08, 2021 at 10:37:19AM +0100, Christian König wrote:
> Am 07.02.21 um 22:50 schrieb Daniel Vetter:
> > [SNIP]
> > > Clarification - as far as I know there are no page fault handlers for
> > > kernel
> > > mappings. And we are talking about kernel mappings here, right ? If
> > > there
Am 07.02.21 um 22:50 schrieb Daniel Vetter:
[SNIP]
Clarification - as far as I know there are no page fault handlers for kernel
mappings. And we are talking about kernel mappings here, right ? If there were
I could solve all those issues the same as I do for user mappings, by
invalidating all e
Am 08.02.21 um 06:45 schrieb Jiawei Gu:
Extend retry times of KIQ to avoid starvation situation caused by
long time full access of GPU by other VFs.
In what units is that? We also need the KIQ during interrupt handling
and that looks like *way* to big for that.
Christian.
Signed-off-by: J
Am 06.02.21 um 19:17 schrieb Mikhail Gavrilov:
On Sun, 31 Jan 2021 at 22:22, Christian König
wrote:
Yeah, known issue. I already pushed Michel's fix to drm-misc-fixes.
Should land in the next -rc by the weekend.
Regards,
Christian.
I checked this patch [1] for several days.
And I can confirm
Am 08.02.21 um 00:07 schrieb Colin King:
From: Colin Ian King
The left shift of int 32 bit integer constant 1 is evaluated using 32
bit arithmetic and then assigned to an unsigned 64 bit integer. In the
case where *frag is 32 or more this can lead to an oveflow. Avoid this
by shifting 1ULL.
I was wondering why I can't set the resolution to 2560x1080, while in windows 7
I can without a problem.
I looked at the radeon driver code and found it doesn't support this
resolution. So I made some changes.
I added the hdmi_mhz parameter. In cmdline I set radeon.hdmi_mhz=190
Only tested on the
From: Colin Ian King
The left shift of int 32 bit integer constant 1 is evaluated using 32
bit arithmetic and then assigned to an unsigned 64 bit integer. In the
case where *frag is 32 or more this can lead to an oveflow. Avoid this
by shifting 1ULL.
Addresses-Coverity: ("Unintentional integer
пн, 8 февр. 2021 г. в 08:32, Alexander E. Patrakov :
>
> чт, 4 февр. 2021 г. в 09:31, Alex Deucher :
> >
> > On Wed, Feb 3, 2021 at 7:56 PM Eric W. Biederman
> > wrote:
> > >
> > > Alex Deucher writes:
> > >
> > > > On Wed, Feb 3, 2021 at 3:36 AM Dave Young wrote:
> > > >>
> > > >> Hi Baoquan,
чт, 4 февр. 2021 г. в 09:31, Alex Deucher :
>
> On Wed, Feb 3, 2021 at 7:56 PM Eric W. Biederman
> wrote:
> >
> > Alex Deucher writes:
> >
> > > On Wed, Feb 3, 2021 at 3:36 AM Dave Young wrote:
> > >>
> > >> Hi Baoquan,
> > >>
> > >> Thanks for ccing.
> > >> On 01/28/21 at 01:29pm, Baoquan He w
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