Enable VCN 3.0 PG and CG for Yellow Carp by setting up flags.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/amdgpu/nv.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 801cf79353dd..903e1ae166c
Fix the following coccicheck warnings:
./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:
1009:6-16: WARNING: Assignment of 0/1 to bool variable.
./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:
200:2-10: WARNING: Assignment of 0/1 to bool variable.
Reported
Hi Dave, Daniel,
More new stuff for 5.12. Now with non-x86 fixed.
The following changes since commit 044a48f420b9d3c19a135b821c34de5b2bee4075:
drm/amdgpu: fix DRM_INFO flood if display core is not supported (bug 210921)
(2021-01-08 15:18:57 -0500)
are available in the Git repository at:
On 1/19/21 3:48 AM, Christian König wrote:
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5
drivers/gpu/drm/amd/amdgpu/amd
[AMD Public Use]
Thanks Darren. We have the fix already a few days ago.
drm/amdgpu: toggle on DF Cstate after finishing xgmi injection
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Darren Powell
Sent: Wednesday, January 20, 2021 12:46 PM
To: amd-gfx@lists.freedesktop.or
Typo in amdgpu_ras_error_inject_xgmi() does not set df_state back to ALLOW
after test
this can be tested with the command
echo inject xgmi_wafl ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
Fixes patch 5c23e9e05e42b5ea56a87a17f1da9ccf9b100465
Signed-off-by: Darren Powell
---
drive
On 1/19/21 5:01 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 10:22 PM Andrey Grodzovsky
wrote:
On 1/19/21 8:45 AM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 09:48:03AM +0100, Christian König wrote:
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related d
[AMD Official Use Only - Internal Distribution Only]
From: Du, Xiaojian
Sent: Wednesday, January 20, 2021 11:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Wang,
Kevin(Yang) ; Lazar, Lijo ; Du,
Xiaojian ; Du, Xiaojian
Subject: [PATCH] d
From: Xiaojian Du
From: Xiaojian Du
This patch is to make the error log more clear for fine grian tuning
function, it covers Raven/Raven2/Picasso/Renoir/Vangogh.
The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage,
but only when another sysfs file -- power_dpm_force_performa
On Wed, Jan 20, 2021 at 11:09:11AM +0800, Su, Jinzhou (Joe) wrote:
> Driver should enable the CGPG feature for RLC in safe mode to
> prevent any misalignment or conflict in middle of any power
> feature entry/exit sequence.
> Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
> and RLC_
On Wed, Jan 20, 2021 at 11:11:26AM +0800, Liu, Aaron wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> This patch has been Verfied on Van Gogh.
>
Thanks.
Reviewed-by: Huang Rui
> --
> Best Regards
> Aaron Liu
>
> > -Original Message-
> > From: Huang, Ray
> > Sent: We
[AMD Official Use Only - Internal Distribution Only]
This patch has been Verfied on Van Gogh.
--
Best Regards
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Wednesday, January 20, 2021 10:06 AM
> To: Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>
> Sub
Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in re
On Wed, Jan 20, 2021 at 09:57:32AM +0800, Liu, Aaron wrote:
> Starting from vangogh, the ATCL2 and DAGB0 registers relative
> to mgcg/ls has changed.
>
> For MGCG:
> Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
>
> For MGLS:
> Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_C
Starting from vangogh, the ATCL2 and DAGB0 registers relative
to mgcg/ls has changed.
For MGCG:
Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
For MGLS:
Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers.
Signed-off-by: Aaron Liu
-
[AMD Public Use]
+da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
This looks to be one coding style issue. It's better to modify it to
kzalloc(sizeof(*da),...)
https://www.kernel.org/doc/html/latest/process/coding-style.html#allocating-memory
Regards,
Guchun
-Original Message
From: Wayne Lin
[ Upstream commit 02ce73b01e09e388614b22b7ebc71debf4a588f0 ]
[Why]
Find out when we try to disable CRC calculation,
crc generation is still enabled. Main reason is
that dc_stream_configure_crc() will never get
called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE.
[How]
Add c
From: Victor Zhao
[ Upstream commit f14a5c34d143f6627f0be70c0de1d962f3a6ff1c ]
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux,
according to psp, linux cmds are not correct.
v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD.
Signed-off-by: Victor Zhao
Reviewed-by: Emily.Deng
Signe
From: Wayne Lin
[ Upstream commit 02ce73b01e09e388614b22b7ebc71debf4a588f0 ]
[Why]
Find out when we try to disable CRC calculation,
crc generation is still enabled. Main reason is
that dc_stream_configure_crc() will never get
called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE.
[How]
Add c
From: Victor Zhao
[ Upstream commit f14a5c34d143f6627f0be70c0de1d962f3a6ff1c ]
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux,
according to psp, linux cmds are not correct.
v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD.
Signed-off-by: Victor Zhao
Reviewed-by: Emily.Deng
Signe
From: "Li, Roman"
[ Upstream commit 9d03bb102028b4a3f4a64d6069b219e2e1c1f306 ]
[Why]
The initial purpose of dcn10 pipe split is to support some high
bandwidth mode which requires dispclk greater than max dispclk. By
initial bring up power measurement data, it showed power consumption is
less wit
On Fri, 15 Jan 2021 at 03:43, Mikhail Gavrilov
wrote:
>
In rc4, the number of warnings has dropped dramatically.
No more errors "kasan slab-out-of-bounds" and no "DMA-API device
driver failed to check map error".
But still not fixed "sleeping function called from invalid context at
include/linux/
On 1/15/21 2:21 AM, Chen, Xiaogang wrote:
On 1/14/2021 1:24 AM, Grodzovsky, Andrey wrote:
On 1/14/21 12:11 AM, Chen, Xiaogang wrote:
On 1/12/2021 10:54 PM, Grodzovsky, Andrey wrote:
On 1/4/21 1:01 AM, Xiaogang.Chen wrote:
From: Xiaogang Chen
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT int
On 2021-01-19 3:40 p.m., Bhawanpreet Lakha wrote:
From: Harry Wentland
[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.
[How]
Call amdgpu_bo_create_kernel to allocate GPU memory and use a
list in amdgpu_display
On 2021-01-19 3:38 p.m., Bhawanpreet Lakha wrote:
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Joshua Aberback
Series is:
Reviewed-by: Nic
On Tue, Jan 19, 2021 at 10:22 PM Andrey Grodzovsky
wrote:
>
>
> On 1/19/21 8:45 AM, Daniel Vetter wrote:
>
> On Tue, Jan 19, 2021 at 09:48:03AM +0100, Christian König wrote:
>
> Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
>
> Handle all DMA IOMMU gropup related dependencies before the
> group
On 1/19/21 8:45 AM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 09:48:03AM +0100, Christian König wrote:
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/
From: Harry Wentland
[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.
[How]
Call amdgpu_bo_create_kernel to allocate GPU memory and use a
list in amdgpu_display_manager to track our allocations so we
can clean th
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../drm/amd/display/dc
[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.
[How]
- consider cursor bpp when calculating if the cursor fits
Signed-off-by: Bhawanpreet Lakha
Signed-off-
uncomment watermark set d
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_
There is some missing mall code, this series updates the code.
-enable watermark programming
-dynamic cursor cache
-updates to mall eligibility check
Bhawanpreet Lakha (3):
drm/amd/display: Enable programing of MALL watermarks
drm/amd/display: Dynamic cursor cache size for MALL eligibility che
On Tue, Jan 19, 2021 at 02:04:48PM -0500, Alex Deucher wrote:
> On Tue, Jan 19, 2021 at 1:26 PM Greg KH wrote:
> >
> > On Tue, Jan 19, 2021 at 11:36:01AM -0500, Andrey Grodzovsky wrote:
> > >
> > > On 1/19/21 2:34 AM, Greg KH wrote:
> > > > On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovs
On 1/19/21 1:59 PM, Christian König wrote:
Am 19.01.21 um 19:22 schrieb Andrey Grodzovsky:
On 1/19/21 1:05 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 4:35 PM Andrey Grodzovsky
wrote:
There is really no other way according to this article
https://nam11.safelinks.protection.outlook.com/
On 1/19/21 2:04 PM, Alex Deucher wrote:
On Tue, Jan 19, 2021 at 1:26 PM Greg KH wrote:
On Tue, Jan 19, 2021 at 11:36:01AM -0500, Andrey Grodzovsky wrote:
On 1/19/21 2:34 AM, Greg KH wrote:
On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovsky wrote:
static struct pci_driver amdgpu
On Tue, Jan 19, 2021 at 11:36:01AM -0500, Andrey Grodzovsky wrote:
>
> On 1/19/21 2:34 AM, Greg KH wrote:
> > On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovsky wrote:
> > > static struct pci_driver amdgpu_kms_pci_driver = {
> > > .name = DRIVER_NAME,
> > > .id_table
On Tue, Jan 19, 2021 at 1:26 PM Greg KH wrote:
>
> On Tue, Jan 19, 2021 at 11:36:01AM -0500, Andrey Grodzovsky wrote:
> >
> > On 1/19/21 2:34 AM, Greg KH wrote:
> > > On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovsky wrote:
> > > > static struct pci_driver amdgpu_kms_pci_driver = {
> >
Am 19.01.21 um 19:22 schrieb Andrey Grodzovsky:
On 1/19/21 1:05 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 4:35 PM Andrey Grodzovsky
wrote:
There is really no other way according to this article
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flwn.net%2FArticles%2F76788
On Tue, Jan 19, 2021 at 5:08 PM Pillai, Aurabindo
wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Hi Daniel,
>
> Could you please be more specific about the _unsafe API options you mentioned
> ?
module_param_named_unsafe()
Cheers, Daniel
>
> --
>
> Thanks & Regards,
> Aur
Am 19.01.21 um 18:47 schrieb Luben Tuikov:
On 2021-01-19 2:53 a.m., Christian König wrote:
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
From: Luben Tuikov
This patch does not change current behaviour.
The driver's job timeout handler now returns
status indicating back to the DRM layer whe
On 1/19/21 1:05 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 4:35 PM Andrey Grodzovsky
wrote:
There is really no other way according to this article
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flwn.net%2FArticles%2F767885%2F&data=04%7C01%7CAndrey.Grodzovsky%40amd.com%7
On 1/19/21 1:08 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2021 at 6:31 PM Andrey Grodzovsky
wrote:
On 1/19/21 9:16 AM, Daniel Vetter wrote:
On Mon, Jan 18, 2021 at 04:01:09PM -0500, Andrey Grodzovsky wrote:
Until now extracting a card either by physical extraction (e.g. eGPU with
thunderbol
On Tue, Jan 19, 2021 at 6:31 PM Andrey Grodzovsky
wrote:
>
>
> On 1/19/21 9:16 AM, Daniel Vetter wrote:
> > On Mon, Jan 18, 2021 at 04:01:09PM -0500, Andrey Grodzovsky wrote:
> >> Until now extracting a card either by physical extraction (e.g. eGPU with
> >> thunderbolt connection or by emulation
On Tue, Jan 19, 2021 at 4:35 PM Andrey Grodzovsky
wrote:
>
> There is really no other way according to this article
> https://lwn.net/Articles/767885/
>
> "A perfect solution seems nearly impossible though; we cannot acquire a mutex
> on
> the user
> to prevent them from yanking a device and we c
On 2021-01-19 2:53 a.m., Christian König wrote:
> Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
>> From: Luben Tuikov
>>
>> This patch does not change current behaviour.
>>
>> The driver's job timeout handler now returns
>> status indicating back to the DRM layer whether
>> the task (job) was su
On 1/19/21 9:16 AM, Daniel Vetter wrote:
On Mon, Jan 18, 2021 at 04:01:09PM -0500, Andrey Grodzovsky wrote:
Until now extracting a card either by physical extraction (e.g. eGPU with
thunderbolt connection or by emulation through syfs ->
/sys/bus/pci/devices/device_id/remove)
would cause rando
[AMD Public Use]
What about changing the lock hive logic like
If (this device locked) return;
Lock hive -> lock this device.
In the regular flow, lock every thing in the list except this device.
Thanks,
Lijo
From: amd-gfx On Behalf Of Andrey
Grodzovsky
Sent: Tuesday, January 19
Well, it shouldn't happen with the hive locked as I am browsing the code but
then your code should
reflect that and if you do fail to lock particular adev AFTER the hive is locked
you should not silently break
iteration but throw an error, WARN_ON or BUG_ON then. Or alternatively bail out
with u
[AMD Official Use Only - Internal Distribution Only]
OK, I understand. You mean one device in the hive may be locked up
independently without locking up the whole hive.
It could happen, I'll change my code.
Thanks & Regards,
Horace.
发件人: Grodzovsky, Andrey
发送时
On 1/19/21 11:39 AM, Chen, Horace wrote:
[AMD Official Use Only - Internal Distribution Only]
Hi Andrey,
I think the list in the XGMI hive won't be break in the middle if we lock the
device before we change the list. Because if 2 devices in 1 hive went into the
function, it will follow the
[AMD Official Use Only - Internal Distribution Only]
Hi Andrey,
I think the list in the XGMI hive won't be break in the middle if we lock the
device before we change the list. Because if 2 devices in 1 hive went into the
function, it will follow the same sequence to lock the devices. So one of
On 1/19/21 2:34 AM, Greg KH wrote:
On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovsky wrote:
static struct pci_driver amdgpu_kms_pci_driver = {
.name = DRIVER_NAME,
.id_table = pciidlist,
@@ -1595,6 +1607,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {
[AMD Official Use Only - Internal Distribution Only]
Hi Daniel,
Could you please be more specific about the _unsafe API options you mentioned ?
--
Thanks & Regards,
Aurabindo Pillai
From: Daniel Vetter
Sent: Tuesday, January 19, 2021 8:11 AM
To: Pekka Paalanen
[Why]
A seamless transition between modes can be performed if the new incoming
mode has the same timing parameters as the optimized mode on a display with a
variable vtotal min/max.
Smooth video playback usecases can be enabled with this seamless transition by
switching to a new mode which has a r
[Why]
While possible for userspace to create and add custom mode based off the
optimized mode for the connected display which differs only in front porch
timing, this patch set adds a list of common video modes in advance.
The list of common video refresh rates is small, well known and the optimiz
[Why]
This option shall be opt-in by default since it is a temporary solution
until long term solution is agreed upon which may require userspace interface
changes. There has been precedent of manufacturing modes in the kernel. In
AMDGPU, the existing usage are for common modes and scaling modes. O
Changes in V5
=
* More info in commit messages on the rationale of changes being added
to the kernel.
* Minor fixes
Changes in V4
=
1) Add module parameter for freesync video mode
* Change module parameter name to freesync_video
2) Add freesync video modes based on pref
The is also the possibility to have the drm_dev_enter/exit much more
high level.
E.g. we should it have anyway on every IOCTL and what remains are work
items, scheduler threads and interrupts.
Christian.
Am 19.01.21 um 16:35 schrieb Andrey Grodzovsky:
There is really no other way according t
There is really no other way according to this article
https://lwn.net/Articles/767885/
"A perfect solution seems nearly impossible though; we cannot acquire a mutex on
the user
to prevent them from yanking a device and we cannot check for a presence change
after every
device access for perfo
Reviewed-by: Andrey Grodzovsky
Andrey
On 1/19/21 7:22 AM, Horace Chen wrote:
If 2 jobs on 2 different ring timed out the at a very short
period, the reset for second job will be skipped because the
reset is already in progress.
But it doesn't mean the second job is not guilty since it
also ti
On 1/19/21 7:22 AM, Horace Chen wrote:
Fix a racing issue when jobs on 2 rings timeout simultaneously.
If 2 rings timed out at the same time, the amdgpu_device_gpu_recover
will be reentered. Then the adev->gmc.xgmi.head will be grabbed
by 2 local linked list, which may cause wild pointer issue
On Mon, Jan 18, 2021 at 04:01:09PM -0500, Andrey Grodzovsky wrote:
> Until now extracting a card either by physical extraction (e.g. eGPU with
> thunderbolt connection or by emulation through syfs ->
> /sys/bus/pci/devices/device_id/remove)
> would cause random crashes in user apps. The random
On Tue, Jan 19, 2021 at 2:20 AM Liang, Prike wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> > -Original Message-
> > From: Huang, Ray
> > Sent: Tuesday, January 19, 2021 2:57 PM
> > To: Liang, Prike
> > Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> >
> > S
On Tue, Jan 19, 2021 at 06:48:54PM +0800, Su, Jinzhou (Joe) wrote:
> Copy from RLC MAS:
Remove this line.
>
> Driver should enable the CGPG feature for RLC while it is in
> safe mode to prevent any misalignment or conflict while it is
> in middle of any power feature entry/exit sequence. This ca
On Mon, Jan 18, 2021 at 04:01:10PM -0500, Andrey Grodzovsky wrote:
> On device removal reroute all CPU mappings to dummy page.
>
> v3:
> Remove loop to find DRM file and instead access it
> by vma->vm_file->private_data. Move dummy page installation
> into a separate function.
>
> v4:
> Map the e
On Tue, Jan 19, 2021 at 09:48:03AM +0100, Christian König wrote:
> Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
> > Handle all DMA IOMMU gropup related dependencies before the
> > group is removed.
> >
> > Signed-off-by: Andrey Grodzovsky
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h
On Tue, Jan 19, 2021 at 9:35 AM Pekka Paalanen wrote:
>
> On Mon, 18 Jan 2021 09:36:47 -0500
> Aurabindo Pillai wrote:
>
> > On Thu, 2021-01-14 at 11:14 +0200, Pekka Paalanen wrote:
> > >
> > > Hi,
> > >
> > > please document somewhere that ends up in git history (commit
> > > message,
> > > code
Copy from RLC MAS:
Driver should enable the CGPG feature for RLC while it is in
safe mode to prevent any misalignment or conflict while it is
in middle of any power feature entry/exit sequence. This can
be achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIV
Added a CC: stable tag and pushed it.
Thanks,
Christian.
Am 19.01.21 um 09:42 schrieb Christian König:
This is a bug fix and should probably be pushed separately to
drm-misc-next.
Christian.
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
To avoid any possible use after free.
Signed-off-by
[Why]
when vram lost happened in guest, try to write vram can lead to
kernel stuck.
[How]
When the readback data is invalid, don't do write work, directly
reschedule a new work.
Signed-off-by: Jingwen Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +-
1 file changed, 5 insertions(+),
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
This should prevent writing to memory or IO ranges possibly
already allocated for other uses after our device is removed.
Wow, that adds quite some overhead to every register access. I'm not
sure we can do this.
Christian.
Signed-off-by: And
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
This allows to remove explicit creation and destruction
of those attrs and by this avoids warnings on device
finilizing post physical device extraction.
Signed-off-by: Andrey Grodzovsky
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdg
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
On device removal reroute all CPU mappings to dummy page
per drm_file instance or imported GEM object.
v4:
Update for modified ttm_bo_vm_dummy_page
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgp
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
We can't allocate and submit IBs post device unplug.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 +++
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
Some of the stuff in amdgpu_device_fini such as HW interrupts
disable and pending fences finilization must be done right away on
pci_remove while most of the stuff which relates to finilizing and
releasing driver data structures can be kept until
dr
This is a bug fix and should probably be pushed separately to drm-misc-next.
Christian.
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
To avoid any possible use after free.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_main.c | 3 +++
1
Am 18.01.21 um 22:01 schrieb Andrey Grodzovsky:
On device removal reroute all CPU mappings to dummy page.
v3:
Remove loop to find DRM file and instead access it
by vma->vm_file->private_data. Move dummy page installation
into a separate function.
v4:
Map the entire BOs VA space into on demand a
On Mon, Jan 18, 2021 at 04:01:19PM -0500, Andrey Grodzovsky wrote:
> static struct pci_driver amdgpu_kms_pci_driver = {
> .name = DRIVER_NAME,
> .id_table = pciidlist,
> @@ -1595,6 +1607,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {
> .shutdown = amdgpu_pci_shutdown,
>
On Mon, 18 Jan 2021 09:36:47 -0500
Aurabindo Pillai wrote:
> On Thu, 2021-01-14 at 11:14 +0200, Pekka Paalanen wrote:
> >
> > Hi,
> >
> > please document somewhere that ends up in git history (commit
> > message,
> > code comments, description of the parameter would be the best but
> > maybe
>
Am 19.01.21 um 04:23 schrieb Deng, Emily:
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: amd-gfx On Behalf Of
Christian König
Sent: Tuesday, January 19, 2021 12:04 AM
To: Deng, Emily ; Koenig, Christian
; Sun, Roy ; amd-
g...@lists.freedesktop.org
Subject
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