On Thu, Dec 31, 2020 at 12:08 AM Hawking Zhang wrote:
>
> global noretry setting is cached to gmc.noretry
>
> Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Dennis Li
Sent: Thursday, December 31, 2020 13:38
To: amd-gfx@lists.freedesktop.org; Chen, Jiansong (Simon)
; Zhang, Hawking ; Koenig,
Christian
Cc: Li, Dennis
Subject: [PATCH v2] drm/amdgpu: fix
When GFXOFF is enabled and GPU is idle, driver will fail to access some
registers. Therefore change to disable power gating before all access
registers with MMIO.
Dmesg log is as following:
amdgpu :03:00.0: amdgpu: amdgpu: finishing device.
amdgpu: cp queue pipe 4 queue 0 preemption failed
amd
[AMD Official Use Only - Internal Distribution Only]
Hi Paul
Thanks for you kindly instruction,
I have no hardware spec.
--
BW
Pengju Zhou
-Original Message-
From: Paul Menzel
Sent: Friday, December 25, 2020 6:53
global noretry setting is cached to gmc.noretry
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index b72c8e4ca36b..0710
On Tue, 29 Dec 2020 at 20:15, Deucher, Alexander
wrote:
>
> It looks like the driver is not able to access the firmware for some reason.
> Please make sure it is available in your initrd or compiled into the kernel
> depending on your config.
Exactly! Thanks!
# lsinitrd
/boot/initramfs-5.10.
[AMD Public Use]
Reviewed-by: Roman Li mailto:roman...@amd.com>>
From: Wu, Hersen
Sent: Wednesday, December 30, 2020 12:12 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Li, Roman
Subject: [PATCH] drm/amd/display: disable dcn10 pipe split by default
[Why] the initial purpose of
[AMD Official Use Only - Internal Distribution Only]
[Why] the initial purpose of dcn10 pipe split is to support
some high bandwidth mode which requires dispclk greater
than max dispclk. By initial bring up power measurement
data, it showed power consumption is less with pipe split
for dcn block.
From: Jake Wang
[ Upstream commit 410066d24cfc1071be25e402510367aca9db5cb6 ]
[Why]
For certain timings, Renoir may underflow due to sr exit
latency being too slow.
[How]
Updated wm table for renoir.
Signed-off-by: Jake Wang
Reviewed-by: Yongqiang Sun
Acked-by: Qingqing Zhuo
Signed-off-by: A
[AMD Public Use]
Good catch.
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Jiansong Chen
Sent: Wednesday, December 30, 2020 19:50
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Jiansong (Simon) ; Zhou1, Tao
; Zhang, Hawking
Subject: [PATCH] dr
[AMD Public Use]
Hi Dennis,
Thanks for digging this out.
I'd like to understand where the mmio register access is from prior to driver
call amdgpu_device_set_pg_state to disable gfxoff in ip_fini phase. I think we
already move ungate gfx pg in very early stage of device_fini. The only GC
reg
When GFXOFF is enabled and GPU is idle, driver will fail to access some
registers. Therefore disable GFXOFF before unload device.
amdgpu :03:00.0: amdgpu: amdgpu: finishing device.
amdgpu: cp queue pipe 4 queue 0 preemption failed
amdgpu :03:00.0: amdgpu: failed to write reg 2890 wait reg
For sdma5.2, all sdma instances will share the same fw,
remove unnecessary asic check to be more generic.
Signed-off-by: Jiansong Chen
Change-Id: I8b67dd588de9e7d54618404092a77b768bf0ddbd
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 31 +-
1 file changed, 5 insertions(+),
Ok, I will send another patch.
Regards,
Jiansong
-Original Message-
From: Zhang, Hawking
Sent: Wednesday, December 30, 2020 6:02 PM
To: Chen, Jiansong (Simon) ;
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
Subject: RE: [PATCH] drm/amdgpu: correct releasing the
[AMD Public Use]
Shall we ignore this patch and wait for your latest fixes that remove the asic
type check for sdma_v5_2.
I agree with you that should be more reasonable approach.
Regards,
Hawking
-Original Message-
From: Jiansong Chen
Sent: Wednesday, December 30, 2020 17:23
To: amd
Same as sienna_cichlid, dimgrey_cavefish and navy_flounder
reuse sdma0 fw for other instances, so free it only once.
Signed-off-by: Jiansong Chen
Change-Id: I9dda4a9b73e20243ee48f54d8f0c7593d7e7354b
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-
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