[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chen, Guchun
Sent: Wednesday, September 30, 2020 12:38
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Li, Dennis
; Zhou1, Tao ; Clements, John
Cc: Chen, Guchu
gfx timeout and GPU reset while hundreds apps run on AMD GPU, the error happen
about weekly.
Env:
Linux version 5.3.15-050315.2020063001-generic (root@k8snode) (gcc version
7.5.0 (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04)) #appstream SMP PREEMPT Sat Jul 4
10:28:24 CST 2020
vainfo: VA-API version:
The same ECC check has been executed in amdgpu_ras_init for vega10,
prior to gmc_v9_0_late_init.
v2: drop all atombios helper callings
v3: use bit operation
v4: correct inline comment, remove parity check statement
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 19 ++
As the dpm clock table is needed during DC HW initialization.
And that (DC HW initialization) comes before smu_late_init()
where current APU dpm clock table setup is performed. So, NULL
pointer dereference will be triggered. By moving APU dpm clock
table setup to smu_hw_init(), this can be avoided.
[AMD Official Use Only - Internal Distribution Only]
Thanks, I will send out a fix for this.
During DC hw init, pp_smu->rn_funcs.get_dpm_clock_table is called.
However, the dpm_clock_table is not setup yet at that time.
And that will trigger NULL pointer dereference.
BR
Evan
-Original Messag
[AMD Official Use Only - Internal Distribution Only]
Minor correction in the commit message. I think you are planning to report CU
occupancy and not CU usage.
-Original Message-
From: amd-gfx On Behalf Of Ramesh
Errabolu
Sent: Tuesday, September 29, 2020 2:00 PM
To: amd-gfx@lists.free
On Tue, Sep 29, 2020 at 4:43 PM Bhawanpreet Lakha
wrote:
>
> From: Dmytro Laktyushkin
>
> Add code to gracefuly handle any pipe reassignment
> occuring on dcn3 hardware. This should only happen when new
> surfaces are used for an update rather than old ones updated.
>
> Fixes: f64d8ebe9ed2 ("amd/
From: Dmytro Laktyushkin
Add code to gracefuly handle any pipe reassignment
occuring on dcn3 hardware. This should only happen when new
surfaces are used for an update rather than old ones updated.
Fixes: f64d8ebe9ed2 ("amd/drm/display: avoid dcn3 on flip opp change for slave
pipes")
Signed-of
On Tue, Sep 29, 2020 at 2:59 PM Luben Tuikov wrote:
>
> On 2020-09-29 10:57 a.m., Alex Deucher wrote:
> >>> +#ifndef __VANGOGH_IP_OFFSET_H__
> >>> +#define __VANGOGH_IP_OFFSET_H__
> >>> +
> >>> +#define MAX_INSTANCE8
> >>> +#define MAX_SEGMENT
On Tue, Sep 29, 2020 at 8:31 AM Jan Kiszka wrote:
>
> On 10.09.20 20:18, Deucher, Alexander wrote:
> > [AMD Public Use]
> >
> >
> >
> >> -Original Message-
> >> From: amd-gfx On Behalf Of
> >> Daniel Vetter
> >> Sent: Monday, September 7, 2020 3:15 AM
> >> To: Jan Kiszka ; amd-gfx list >
On Tue, Sep 29, 2020 at 2:00 PM Ramesh Errabolu wrote:
>
> [Why]
> Allow user to know number of compute units (CU) that are in use at any
> given moment.
>
> [How]
> Read registers of SQ that give number of waves that are in flight
> of various queues. Use this information to determine number of C
On Tue, Sep 29, 2020 at 1:25 PM Ramesh Errabolu wrote:
>
> [Why]
> Header file exports functions get_gpu_clock_counter(), get_cu_info() and
> select_se_sh() that are defined to be static
>
> Signed-off-by: Ramesh Errabolu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
On 2020-09-29 11:09 a.m., Alex Deucher wrote:
> On Mon, Sep 28, 2020 at 6:26 PM Luben Tuikov wrote:
>>
>> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
>>> From: Huang Rui
>>>
>>> APU needs load toc firmware for gfx10 series on psp front door loading.
>>>
>>> v2: rebase against latest code
>>>
>>>
On 2020-09-29 10:57 a.m., Alex Deucher wrote:
>>> +#ifndef __VANGOGH_IP_OFFSET_H__
>>> +#define __VANGOGH_IP_OFFSET_H__
>>> +
>>> +#define MAX_INSTANCE8
>>> +#define MAX_SEGMENT 6
>> No. No "max". Use "num" instead, as:
[Why]
Allow user to know number of compute units (CU) that are in use at any
given moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/a
Hi Christian
Am 29.09.20 um 17:35 schrieb Christian König:
> Am 29.09.20 um 17:14 schrieb Thomas Zimmermann:
>> The new helper ttm_kmap_obj_to_dma_buf() extracts address and location
>> from and instance of TTM's kmap_obj and initializes struct dma_buf_map
>> with these values. Helpful for TTM-bas
On Tue, Sep 29, 2020 at 1:26 PM Ramesh Errabolu wrote:
>
> [Why]
> Allow user to know number of compute units (CU) that are in use at any
> given moment.
>
> [How]
> Read registers of SQ that give number of waves that are in flight
> of various queues. Use this information to determine number of C
[Why]
Allow user to know how many compute units (CU) are in use at any given
moment.
[How]
Surface files in Sysfs that allow user to determine the number of compute
units that are in use for a given process. One Sysfs file is used per
device.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/a
[Why]
Allow user to know how many compute units (CU) are in use at any given
moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu
---
.../gpu/drm/amd/amdgpu/amdg
[Why]
Allow user to know number of compute units (CU) that are in use at any
given moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/a
[Why]
Header file exports functions get_gpu_clock_counter(), get_cu_info() and
select_se_sh() that are defined to be static
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
b/dr
On Tue, Sep 29, 2020 at 5:35 PM Christian König
wrote:
>
> Am 29.09.20 um 17:14 schrieb Thomas Zimmermann:
> > The new helper ttm_kmap_obj_to_dma_buf() extracts address and location
> > from and instance of TTM's kmap_obj and initializes struct dma_buf_map
> > with these values. Helpful for TTM-ba
Am 29.09.20 um 17:14 schrieb Thomas Zimmermann:
The new helper ttm_kmap_obj_to_dma_buf() extracts address and location
from and instance of TTM's kmap_obj and initializes struct dma_buf_map
with these values. Helpful for TTM-based drivers.
We could completely drop that if we use the same struct
Am 2020-09-29 um 11:08 a.m. schrieb Kent Russell:
> The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may
> not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU
> variants (D131 or D134) until a more general solution can be determined.
>
> v2: Remove string-b
From: Huang Rui
APU needs load toc firmware for gfx10 series on psp front door loading.
v2: rebase against latest code
v3: clarify error message
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11
drivers/gpu
From: Huang Rui
The interrupts are not stable while uses guest physical address (GPA)
for interrupt packet write space even on direct loading case.
v2: make condition more readable
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nav
From: Huang Rui
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.
v2: make vangogh_reg_base_init void, align equality sign
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |
From: Huang Rui
This patch adds common ip support for van gogh.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd
The new helper ttm_kmap_obj_to_dma_buf() extracts address and location
from and instance of TTM's kmap_obj and initializes struct dma_buf_map
with these values. Helpful for TTM-based drivers.
Signed-off-by: Thomas Zimmermann
---
include/drm/ttm/ttm_bo_api.h | 24
include
The parameters map and is_iomem are always of the same value. Removed them
to prepares the function for conversion to struct dma_buf_map.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_vram_helper.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --gi
GEM's vmap and vunmap interfaces now wrap memory pointers in struct
dma_buf_map.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_client.c | 18 +++---
drivers/gpu/drm/drm_gem.c | 28 ++--
drivers/gpu/drm/drm_internal.h | 5 +++--
drivers/gpu/d
DRM's fbdev console uses regular load and store operations to update
framebuffer memory. The bochs driver on sparc64 requires the use of
I/O-specific load and store operations. We have a workaround, but need
a long-term solution to the problem.
This patchset changes GEM's vmap/vunmap interfaces to
Instances of struct dma_buf_map should be useful throughout DRM's
memory management code. Furthermore, several drivers can now use
generic fbdev emulation.
Signed-off-by: Thomas Zimmermann
---
Documentation/gpu/todo.rst | 24 ++--
1 file changed, 22 insertions(+), 2 deletions
At least sparc64 requires I/O-specific access to framebuffers. This
patch updates the fbdev console accordingly.
For drivers with direct access to the framebuffer memory, the callback
functions in struct fb_ops test for the type of memory and call the rsp
fb_sys_ of fb_cfb_ functions.
For drivers
Kernel DRM clients now store their framebuffer address in an instance
of struct dma_buf_map. Depending on the buffer's location, the address
refers to system or I/O memory.
Callers of drm_client_buffer_vmap() receive a copy of the value in
the call's supplied arguments. It can be accessed and modi
This patch replaces the vmap/vunmap's use of raw pointers in GEM object
functions with instances of struct dma_buf_map. GEM backends are
converted as well.
For most GEM backends, this simply change the returned type. GEM VRAM
helpers are also updated to indicate whether the returned framebuffer
ad
On Mon, Sep 28, 2020 at 6:48 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Huang Rui
> >
> > This patch is to add power gating handle for gfx10.
>
> Ray, you can just say:
>
> "This patch adds power gating handler for gfx10."
>
> You can drop "is to" and just u
The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may
not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU
variants (D131 or D134) until a more general solution can be determined.
v2: Remove string-based logic, correct the VBIOS string comment
Signed-off-by
On Mon, Sep 28, 2020 at 6:26 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Huang Rui
> >
> > APU needs load toc firmware for gfx10 series on psp front door loading.
> >
> > v2: rebase against latest code
> >
> > Signed-off-by: Huang Rui
> > Acked-by: Alex Deuc
The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may
not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU
variants (D131 or D134) until a more general solution can be determined.
v2: Remove string-based logic, correct the VBIOS string comment
Signed-off-by
On Mon, Sep 28, 2020 at 4:57 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui
> >
> > The interrupts are not stable while uses guest physical address (GPA)
> > for interrupt packet write space even on direct loading case.
> >
> > Signed-off-by: Huang Rui
On Mon, Sep 28, 2020 at 4:49 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui
> >
> > This patch adds vangogh_reg_base_init function to init the register base for
> > van gogh.
> >
> > Signed-off-by: Huang Rui
> > Reviewed-by: Alex Deucher
> > Signed-o
[AMD Public Use]
> -Original Message-
> From: Kuehling, Felix
> Sent: Tuesday, September 29, 2020 10:37 AM
> To: Russell, Kent ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Use SKU instead of DID for FRU check
>
>
> Am 2020-09-29 um 7:31 a.m. schrieb Kent Russell:
On Mon, Sep 28, 2020 at 5:41 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:10 p.m., Alex Deucher wrote:
> > From: Xiaojian Du
> >
> > This patch is to add smu v11.5 driver interface header for vangogh.
> >
> > Signed-off-by: Xiaojian Du
> > Reviewed-by: Kevin Wang
> > Reviewed-by: Huang Rui
> > S
Am 2020-09-29 um 7:31 a.m. schrieb Kent Russell:
> The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may
> not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU
> variants (D131 or D134) until a more general solution can be determined.
>
> Signed-off-by: Kent
On Mon, Sep 28, 2020 at 4:52 PM Luben Tuikov wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui
> >
> > Van gogh only has one sdma.
> >
> > v2: use num_instances rather than APU flag
> >
> > Signed-off-by: Huang Rui
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/g
On Thu, Sep 17, 2020 at 7:16 PM Oak Zeng wrote:
>
> gfxhub functions are now called from function pointers,
> instead of from asic-specific functions.
>
> Signed-off-by: Oak Zeng
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 ++
> drivers/gpu/drm/am
On Sun, Sep 27, 2020 at 5:18 AM Dirk Gouders wrote:
>
> Alex Deucher writes:
>
> > On Wed, Sep 23, 2020 at 3:45 PM Dirk Gouders wrote:
> >>
> >> Dirk Gouders writes:
> >>
> >> > Alex Deucher writes:
> >> >
> >> >> On Wed, Sep 23, 2020 at 8:54 AM Dirk Gouders wrote:
> >> >>>
> >> >>> Dirk Goud
Applied. Thanks!
Alex
On Mon, Sep 28, 2020 at 3:07 AM Dirk Gouders wrote:
>
> Commit 78fe9f63947a2b (drm/amd/display: Remove DISPCLK Limit Floor
> for Certain SMU Versions) added a call to
> rn_vbios_smu_get_smu_version() to set clk_mgr->smu_ver. That field is
> initialized prior to the if-sta
Make us an offer on the following clean pull tested Intel CPU's located in USA.Intel Xeon E5-4669 V3 SR22MQty 33pcsIntel Xeon E5-4669 V4 SR2SGQty 13pcsIntel Xeon E5-2699A V4 SR30YQty 10pcsDell Laptop Latitude E6430u Core I7 3687u @ 2.10GHz, 256GB SSD, 16GB, WIN 7 PRO Quantity 40If you are I
On 10.09.20 20:18, Deucher, Alexander wrote:
> [AMD Public Use]
>
>
>
>> -Original Message-
>> From: amd-gfx On Behalf Of
>> Daniel Vetter
>> Sent: Monday, September 7, 2020 3:15 AM
>> To: Jan Kiszka ; amd-gfx list > g...@lists.freedesktop.org>; Wentland, Harry ;
>> Kazlauskas, Nicholas
>
On Tue, 29 Sep 2020 08:14:04 +0200, Jean Delvare wrote:
> On Mon, 28 Sep 2020 17:44:28 -0400, Alex Deucher wrote:
> > Nice analysis. I've applied the patch.
>
> Unfortunately, further testing shows that this partial revert is
> insufficient to fully fix the problem.
Argh, scratch this. Acciden
The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may
not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU
variants (D131 or D134) until a more general solution can be determined.
Signed-off-by: Kent Russell
---
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
The same ECC check has been executed in amdgpu_ras_init for vega10,
prior to gmc_v9_0_late_init.
v2: drop all atombios helper callings
v3: use bit operation
v4: correct inline comment, remove parity check statement
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 ++
[AMD Public Use]
Will squash all into patch v4. Sorry for confusion.
Regards,
Guchun
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, September 29, 2020 4:39 PM
To: Zhang, Hawking ; Chen, Guchun ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander ;
Li, Dennis ; Zhou1, Tao ; Cle
[AMD Public Use]
BTW, this workaround is actually used to fix vbios issue that the partial
writes was enabled on board without ECC capability and result to performance
drop. I don't think this is related to parity check or something. So the
comment inline is also not correct.
Regards,
Hawking
[AMD Public Use]
+ if (adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC)) {
if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
Hmm... this is still not correct. If the UM
On Tue, 29 Sep 2020 08:14:04 +0200, Jean Delvare wrote:
> I'm not familiar enough with the amdgpu driver to efficiently continue
> debugging this issue on my own, so I'll do what I can, but some
> guidance would be welcome.
As an additional data point, here's what I found this morning in my
kernel
Hi Alex,
On Mon, 28 Sep 2020 17:44:28 -0400, Alex Deucher wrote:
> On Mon, Sep 28, 2020 at 9:23 AM Jean Delvare wrote:
> > I have recently experienced a regression in stable kernel series 5.8.
> > The problem is that my display will randomly turn to black after just a
> > few seconds of inactivit
Philip already stumbled over this issue as well, but this is the wrong
place to fix this.
dma_resv_reserve_shared() needs to be called after we reserved the page
tables and before we do the update in amdgpu_vm_handle_fault().
Reserved slots are freed (in a debug build) as soon as we release t
60 matches
Mail list logo
