[AMD Public Use]
Ok I will refine it.
Brs
Wenhui
-Original Message-
From: Zhang, Hawking
Sent: Friday, July 10, 2020 2:51 PM
To: Zhang, Hawking ; Sheng, Wenhui
; amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: RE: [PATCH 1/4] drm/amd/powerplay: add SMU mode1 reset
[AMD Public
[AMD Public Use]
Hi @Zhang, Hawking
I tried to hide mp0/mp1 mode1 reset under AMD_RESET_METHOD_MODE1, while it
seems that we need to tackle the difference in function
amdgpu_device_gpu_recover, like following change in 3rd patch:
@@ -4275,16 +4277,18 @@ int amdgpu_device_gpu_recover(struct am
[AMD Public Use]
BTW, we'd better make the 500ms setting to be a MACRO. We haven't passed the
stress test so might need to extend the waiting in near future.
+ ret = smu_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+ if (!ret)
+ msleep(500);
Regards,
Hawking
-Orig
[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Xiao, Jack
Sent: Friday, July 10, 2020 13:45
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
Cc: Xiao, Jack
Subject: [PATCH 2/2] drm/amdgpu: fix preemption unit te
[AMD Public Use]
We shall consider add smu mode 1 reset interface in amdgpu_dpm.c, where we have
amdgpu_dpm_mode2_reset and amdgpu_dpm_baco_reset already.
So totally three interfaces there
amdgpu_dpm_baco_reset
amdgpu_dpm_mode2_reset
amdgpu_dpm_mode1_reset
Does it make sense to you? Thoughts?
[AMD Public Use]
How about we expose the reset_method as a new amdgpu module parameter?
Regards,
Hawking
-Original Message-
From: Sheng, Wenhui
Sent: Friday, July 10, 2020 13:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Sheng, Wenhui
; Gao, Likun
Subject: [PATCH 4/4] drm/
[AMD Public Use]
Hi @Sheng, Wenhui,
I'm thinking of hiding the MP0/MP1 mode 1 reset under AMD_RESET_METHOD_MODE1.
the callback function reset is per ASIC function, where nv_asic_reset and
soc15_aisc_reset serve for NV series and pre-NV series respectively.
The new mode 1 reset will be used sta
For sienna cichlid, defaut path is baco reset, only
when parameter mode1_reset is set, mode1 reset will
be chosen.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 8
drivers/gpu/drm/
>From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 37 +++
.../gpu/drm/amd/power
For sienna cichlid, add mode1 reset path for sGPU.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 24 --
drivers/gpu/drm/amd/amdgpu/nv.c | 32 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c|
AMD_RESET_METHOD_MODE1 will be used by SMU
mode1 reset for sienna cichlid, so add
AMD_RESET_METHOD_PSP_MODE1 for psp mode1 reset.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
d
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
Remove signaled jobs from job list and ensure the
job was indeed preempted.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gp
[AMD Official Use Only - Internal Distribution Only]
Thanks. Other ASICs from SMU V11 should need this also.
A new patch was created to apply this for all SMU V11 ASICs.
Please see the updated patch series.
BR,
Evan
-Original Message-
From: Alex Deucher
Sent: Friday, July 10, 2020 4:45 A
[AMD Official Use Only - Internal Distribution Only]
Just sent out the updated patch series with this one splitted into two as
commented.
BR,
Evan
-Original Message-
From: Alex Deucher
Sent: Friday, July 10, 2020 4:39 AM
To: Quan, Evan
Cc: amd-gfx list ; Deucher, Alexander
Subject: R
Leftover of previous performance level setting cleanups.
Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++--
d
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I04c810859794b07ce8905a8df797ed6b5ae116a8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 178 +-
1 file ch
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I2c8831b9d00618c6578ee42b34e26892c5dba515
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 248 +
1 file ch
These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 234 --
1 file changed, 211 insertions(+), 23 d
Use the common smu_v11_0_set_soft_freq_limited_range.
Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++-
drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
drivers/gpu/drm/amd/powerplay/smu_
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0
By calling the target APIs directly.
Change-Id: I0f24f603d2fcb94d2078a35c405a1406093ba5e3
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/dr
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.
Change-Id: I6f7a594235dffdf75b56d1de5b9dc6d49833d7e8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 -
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 17
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Change-Id: I3f2ef5ee2e6e433518f726988bbe5970848b99c8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: Icd96ce42218d78d670dd0c1f88663fd42108b311
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 170 ---
1 file ch
Preparing for coming code sharing around performance level
setting.
Change-Id: I51b1536b62995f0fecd51b91f238793f57485aa9
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 6 +-
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 47 ++---
dr
Maximum the code sharing around smu V11.
Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++
2 files changed, 42 insertions(+)
diff --git
So that it can be more widely shared around SMU v11 ASICs.
Change-Id: Ie110edf2ec519699448d3ff3215188ba243d2415
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 91 +++
1 file changed, 77 insertions(+), 14 deletions(-)
diff
Preparing for coming code sharing around performance level
setting.
Change-Id: Iaa77af7a272121503f09ad5fbfbe9dff2d2597b1
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 ---
1 file changed, 119 insertions(+), 178 deletions(-)
diff --git a/drivers/
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 182 ++---
1 file changed, 158 insertions(+), 24 d
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Friday, July 10, 2020 11:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth
; Gao, Likun
Subject: [PATCH] drm/amd/po
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/d
[AMD Official Use Only - Internal Distribution Only]
There is already a patch for this.
https://lists.freedesktop.org/archives/amd-gfx/2020-July/051134.html
-Original Message-
From: chen gong
Sent: Thursday, July 9, 2020 6:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Gong, Cu
On Thu, Jul 9, 2020 at 3:15 PM Nirmoy Das wrote:
>
> Cleanup of phase1 suspend code to reduce unnecessary indentation.
>
> Signed-off-by: Nirmoy Das
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 --
> 1 file changed, 13 insertions(+), 10 de
On Fri, Jul 3, 2020 at 4:59 AM Evan Quan wrote:
>
> Leftover of previous cleanups.
>
> Change-Id: I36a018349647125513e47edda66db2005bd8b0c5
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 32 ---
> .../gpu
On Fri, Jul 3, 2020 at 4:55 AM Evan Quan wrote:
>
> The LCLK dpm table setup should be performed in .update_pcie_parameters().
> Otherwise, the updated GenSpeed and LaneCount information will be lost.
>
> Change-Id: I028c26ca0e54098cb93d9e9266719f1762ba2d7e
> Signed-off-by: Evan Quan
Series is:
On Fri, Jul 3, 2020 at 4:34 AM Evan Quan wrote:
>
> Leftover of previous performance level setting cleanups.
>
> Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412
> Signed-off-by: Evan Quan
patches 5-10, 12-14:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
On Fri, Jul 3, 2020 at 4:34 AM Evan Quan wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++-
> drivers/gpu/drm/amd/powe
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Cache all clocks levels for every dpm table. They are needed
> by other APIs.
>
> Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Cache all clocks levels for every dpm table. They are needed
> by other APIs.
>
> Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c |
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> These members can help to cache the clock frequencies for all
> dpm levels. Then simplifying the code for dpm level switching
> is possible.
>
> Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
> Signed-off-by: Evan Quan
Reviewed-by: Alex D
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Preparing for coming code sharing around performance level
> setting.
>
> Change-Id: Ie32b6af39f22d05c08096959bab0e02e53856170
> Signed-off-by: Evan Quan
You might want to split this into two patches, one to split out the
smu_v11_0_set_single_d
On Fri, Jul 3, 2020 at 4:54 AM Evan Quan wrote:
>
> This seemed a typo.
>
> Change-Id: I1e4da590829395617e90d0d43562f934a1ae0234
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Thu, Jul 2, 2020 at 5:47 AM Evan Quan wrote:
>
> As designed the common code shared among all smu v11 ASCIs go to
> smu_v11_0.c. This helps to maintain clear code layers.
>
> Change-Id: I1f848eba0b6b56f8b5ef6f0888ee6955ba1d2070
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
On Thu, Jul 2, 2020 at 5:45 AM Evan Quan wrote:
>
> Clean code by dropping unnecessary ones.
>
> Change-Id: Idf89ef6fa787b61cd8baf8ded7e3f323bdcef189
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 8 +++-
> .../gpu/drm/
Cleanup of phase1 suspend code to reduce unnecessary indentation.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 --
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/am
Hi Dave, Daniel,
Fixes for 5.8.
The following changes since commit dcb7fd82c75ee2d6e6f9d8cc71c52519ed52e258:
Linux 5.8-rc4 (2020-07-05 16:20:22 -0700)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.8-2020-07-09
for you to fetch chang
[AMD Public Use]
-Original Message-
From: Christian König
Sent: Thursday, July 9, 2020 8:40 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Chauhan, Madhav
Subject: [PATCH 2/2] drm/amdgpu: stop allocating dummy GTT nodes v2
Now that TTM is fixed up we can fina
[AMD Public Use]
-Original Message-
From: Christian König
Sent: Thursday, July 9, 2020 8:40 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Chauhan, Madhav
Subject: [PATCH 1/2] drm/ttm: further cleanup ttm_mem_reg handling
Stop touching the backend private poi
Now that TTM is fixed up we can finally stop that nonsense.
v2: Update the documentation as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 106 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++-
2 files changed, 43 insertions(+),
Stop touching the backend private pointer alltogether and
make sure we never put the same mem twice by.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 46 +++--
include/drm/ttm/ttm_bo_driver.h | 2 --
2 files changed, 26 insertions(+), 22 deleti
Am 09.07.20 um 14:31 schrieb Daniel Vetter:
On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote:
On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
Comes up every few years, gets so
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads or workloads where userspace fencing is allowe
On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote:
>
> On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
> > On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
> > > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> > > > Comes up every few years, gets somewhat tedious to discuss, l
On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
> On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
> > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> > > Comes up every few years, gets somewhat tedious to discuss, let's
> > > write this down once and for all.
> >
> > Thanks fo
Am 07.07.20 um 22:12 schrieb Daniel Vetter:
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads
Corresponding to smu_workload_get_type(smu, type) is "get_workload_type"
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu
Hi Jason,
Below the paragraph I've added after our discussions around dma-fences
outside of drivers/gpu. Good enough for an ack on this, or want something
changed?
Thanks, Daniel
> + * Note that only GPU drivers have a reasonable excuse for both requiring
> + * &mmu_interval_notifier and &shrink
On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
> Hi,
>
> On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> > Comes up every few years, gets somewhat tedious to discuss, let's
> > write this down once and for all.
>
> Thanks for writing this up! I wonder if any of the notes from
On Thu, Jul 09, 2020 at 08:29:21AM +0100, Daniel Stone wrote:
> Hi,
> Jumping in after a couple of weeks where I've paged most everything
> out of my brain ...
>
> On Fri, 19 Jun 2020 at 10:43, Daniel Vetter wrote:
> > On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote:
> > > > The prop
On Thu, Jul 09, 2020 at 08:32:41AM +0100, Daniel Stone wrote:
> Hi,
>
> On Wed, 8 Jul 2020 at 16:13, Daniel Vetter wrote:
> > On Wed, Jul 8, 2020 at 4:57 PM Christian König
> > wrote:
> > > Could we merge this controlled by a separate config option?
> > >
> > > This way we could have the checks
Hi,
On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> Comes up every few years, gets somewhat tedious to discuss, let's
> write this down once and for all.
Thanks for writing this up! I wonder if any of the notes from my reply
to the previous-version thread would be helpful to more explicitly
Hi,
On Wed, 8 Jul 2020 at 16:13, Daniel Vetter wrote:
> On Wed, Jul 8, 2020 at 4:57 PM Christian König
> wrote:
> > Could we merge this controlled by a separate config option?
> >
> > This way we could have the checks upstream without having to fix all the
> > stuff before we do this?
>
> Since
Dear Linux folks,
Building Linux v5.8-rc4-25-gbfe91da29bfad with Clang/LLD
1:11~++20200701093119+ffee8040534-1~exp1 from Debian experimental for
32-bit (`ARCH=i386`), starting Weston (Wayland) or X.Org Server results
in non-working screen, and Linux shows the trace below [1].
[ 502.044997
Hi,
Jumping in after a couple of weeks where I've paged most everything
out of my brain ...
On Fri, 19 Jun 2020 at 10:43, Daniel Vetter wrote:
> On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote:
> > > The proposed patches might very well encode the wrong contract, that's
> > > all up
Am 08.07.20 um 18:11 schrieb Suraj Upadhyay:
Hii AMD Maintainers,
I plan to convert logging of information, error and warnings
inside the AMD driver(s) to drm_* functions and macros for loggin,
as described by the TODO list in the DRM documentation[1].
I need your approval for the change
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