[AMD Public Use]
Or make it in more reasonable place.
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Friday, May 22, 2020 14:16
To: Liu, Monk ; Chen, Guchun ; Wan,
Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG se
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Sub
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, M
[AMD Official Use Only - Internal Distribution Only]
Patch1, 2 are reviewed-by: Evan Quan
Patch3 is acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:16 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 1/3] dr
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, May 6, 2020 3:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: simplify ATIF backlight handlin
[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
the flag of "ATTR_STATE_[UN]SUPPORTED" should be binding to device not device
attribute node,
when inserting two different video cards, the driver may be need to create
different node according device type (vega, navi,...),
and when
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.free
[AMD Official Use Only - Internal Distribution Only]
Series is reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:17 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 1/7] drm/amdgpu/sdma4: add renoir to power
[AMD Official Use Only - Internal Distribution Only]
please add a detailed description of the reason for this patch,
after finshed, the patch is
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Hua Zhang
Sent: Friday, May 22, 2020 1:31 P
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix pp_clk_voltage handling
F
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, May 22, 2020 12:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix pm sysfs node handling (v2)
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, May 22, 2020 5:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix sysfs power controls with mul
i2c eeprom init/fini is only needed under bare mental mode.
Signed-off-by: Hua Zhang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24 +-
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/power
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Fo
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG s
[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Kevin Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, May 22, 2020 4:23 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/3] Rever
The current codebase makes use of one-element arrays in the following
form:
struct something {
int length;
u8 data[1];
};
struct something *instance;
instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
instance->length = size;
memcpy(instance->data, source, size);
but the preferre
Hi Dave, Daniel,
Fixes for 5.7.
The following changes since commit 5a3f610877e9d08968ea7237551049581f02b163:
drm/edid: Add Oculus Rift S to non-desktop list (2020-05-20 12:56:49 +1000)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.7-
[Why]
Previously we used the s3 codepath for gpu reset. This can lead to issues in
certain case where we end of waiting for fences which will never come (because
parts of the hw are off due to gpu reset) and we end up waiting forever causing
a deadlock.
[How]
Handle GPU reset separately from norma
Reset the SUPPORTED attribute.
Signed-off-by: Alex Deucher
---
This fixes multi-GPU, but I think we could still race without some sort
of locking around the attr array.
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgp
On Thu, May 21, 2020 at 4:45 PM Alan Swanson wrote:
>
> Even with the "Above 4G decoding" (or similar) BIOS option enabled,
> many BIOS do not assign the PCI root bus a 64-bit address space.
>
> If available, "MMIOH Base" and "MMIO High Size" (or similar) BIOS
> options should allow mapping to the
On Thu, May 21, 2020 at 4:48 PM Alan Swanson wrote:
>
> Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
> code with previous gfx generations from commit d6895ad39f3b39
> ("drm/amdgpu: resize VRAM BAR for CPU access v6").
>
> Signed-off-by: Alan Swanson
Tested and applied. Thanks
Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
code with previous gfx generations from commit d6895ad39f3b39
("drm/amdgpu: resize VRAM BAR for CPU access v6").
Signed-off-by: Alan Swanson
---
Unfortunately cannot test this with my RX5700 on my AMD X470
motherboard as its BIOS "Ab
Even with the "Above 4G decoding" (or similar) BIOS option enabled,
many BIOS do not assign the PCI root bus a 64-bit address space.
If available, "MMIOH Base" and "MMIO High Size" (or similar) BIOS
options should allow mapping to the desired address spaces.
Signed-off-by: Alan Swanson
---
Usefu
Hi Mukul,
This looks pretty good. See some suggestions inline.
Am 2020-05-14 um 4:33 p.m. schrieb Mukul Joshi:
> Track SDMA usage on a per process basis and report it through sysfs.
> The value in the sysfs file indicates the amount of time SDMA has
> been in-use by this process since the creatio
On Thu, May 21, 2020 at 3:53 PM Gavin Wan wrote:
>
> For SRIOV, since the CGCG is set on host side. The Guest should
> not program CGCG again.
>
> The patch ignores setting CGCG for SRIOV.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
Acked-by: Alex Deucher
This reverts commit b41d9df2b680b96913cc3ccf929252e2dce71b24.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f
This reverts commit e04aba8a382d86646a2a2cc194c3fc2441b64917.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
i
This reverts commit 3fc62b9b9cfed72fd7acf2f594c9a4930dbc0467.
This breaks multi-GPU. Since the attribute array is global
whatever gets set for the first device more or less ends up
what gets set all the other GPUs in the system.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu
For SRIOV, since the CGCG is set on host side. The Guest should
not program CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 ins
Please provide your dmesg output and xorg log.
Alex
On Thu, May 21, 2020 at 3:03 PM Javad Karabi wrote:
>
> Alex,
> yea, youre totally right i was overcomplicating it lol
> so i was able to get the radeon to run super fast, by doing as you
> suggested and blacklisting i915.
> (had to use module_
Alex,
yea, youre totally right i was overcomplicating it lol
so i was able to get the radeon to run super fast, by doing as you
suggested and blacklisting i915.
(had to use module_blacklist= though because modprobe.blacklist still
allows i915, if a dependency wants to load it)
but with one caveat:
Sorry I missed this.
Series is Reviewed-By: Kent Russell
Kent
KENT RUSSELL
Sr. Software Engineer | Linux Compute Kernel
1 Commerce Valley Drive East
Markham, ON L3T 7X6
O +(1) 289-695-2122 | Ext 72122
From: amd-gfx on behalf of Zhao, Yong
Sent: Thursday, May
[AMD Official Use Only - Internal Distribution Only]
The series are
Reviewed-by: Yong Zhao
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, May 21, 2020 12:52 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu: drop navi pc
Am 2020-05-21 um 9:50 a.m. schrieb Christian König:
> Am 21.05.20 um 00:51 schrieb Felix Kuehling:
>> This fixes an intermittent bug where a root PD clear operation still in
>> progress could overwrite a PDE update done by the CPU, resulting in a
>> VM fault.
>
> Mhm, maybe better add this to amdg
On Thu, May 21, 2020 at 6:43 AM chen gong wrote:
>
> [Problem description]
> 1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
> into "gfxoff" state)
> 2. Remote login to platform using SSH, then type the command line:
> sudo su -c "echo manual >
> /sys/class/dr
Ping on this series?
On Tue, May 19, 2020 at 5:10 PM Alex Deucher wrote:
>
> It's not implemented yet so just drop it so the sysfs
> pcie bw file returns an appropriate error instead of
> garbage.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 8
> 1 file cha
Fix typos that prevented them from showing up.
v2: switch other files in addition to pp_clk_voltage
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/am
Am 2020-05-21 um 10:42 a.m. schrieb Philip Yang:
> In free memory of gpu path, remove bo from validate_list to make sure
> restore worker don't access the BO any more, then unregister bo MMU
> interval notifier. Otherwise, the restore worker will crash in the
> middle of validating BO user pages if
[AMD Official Use Only - Internal Distribution Only]
Hi Harry,
" Michael, does this "fix" your issue?"
Yes, the change "fixes" the issue. It has the same effect as removing
renoir_dmcu.bin work-around, where backlight control starts to work.
Thanks again,
Michael
-Original Message-
In free memory of gpu path, remove bo from validate_list to make sure
restore worker don't access the BO any more, then unregister bo MMU
interval notifier. Otherwise, the restore worker will crash in the
middle of validating BO user pages if MMU interval notifer is gone.
Signed-off-by: Philip Yan
Ping on this series? It fixes an ordering issue for raven2.
Alex
On Fri, May 15, 2020 at 2:31 PM Alex Deucher wrote:
>
> Move it into the fw_info function since it's logically part
> of the same functionality.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Ping on this series?
Alex
On Tue, May 19, 2020 at 11:44 AM Alex Deucher wrote:
>
> Looks like renoir should be handled here as well.
>
> Signed-off-by: Alex Deucher
> ---
>
> Can someone test this on renoir?
>
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
Ping?
On Tue, May 12, 2020 at 4:15 PM Alex Deucher wrote:
>
> Ping?
>
> Alex
>
> On Thu, May 7, 2020 at 12:09 PM Alex Deucher wrote:
> >
> > Ping?
> >
> > On Tue, May 5, 2020 at 3:48 PM Alex Deucher wrote:
> > >
> > > Just register the a pointer to the backlight device and use
> > > that. Unifi
Fix a typo with pp_clk_voltage that prevented it from
showing up.
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
1 file changed, 1
Am 21.05.20 um 00:51 schrieb Felix Kuehling:
This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.
Mhm, maybe better add this to amdgpu_vm_cpu_prepare().
This way we could (in theory) switch betwe
Am 21.05.20 um 02:09 schrieb Ahmed S. Darwish:
On Wed, May 20, 2020, Christian König wrote:
Am 19.05.20 um 23:45 schrieb Ahmed S. Darwish:
A sequence counter write side critical section must be protected by some
form of locking to serialize writers. If the serialization primitive is
not disabli
On 05/20, Felix Kuehling wrote:
> Am 2020-05-20 um 9:53 a.m. schrieb Aurabindo Pillai:
> > The buffer allocated is of 1024 bytes. Allocate this from
> > heap instead of stack.
> >
> > Also remove check for stack size since we're allocating from heap
> >
> > Signed-off-by: Aurabindo Pillai
> > Test
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Likun Gao
Sent: Thursday, May 21, 2020 19:10
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: [PATCH] drm/amdgpu: change memory traini
From: Likun Gao
Change memory training init and finit a common function, as it only have
software behavior do not relay on the IP version of PSP.
Signed-off-by: Likun Gao
Change-Id: I0a81d3c3cd1813480781876101e9bfb6787bce3b
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 42 +
[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual >
/sys/class/drm/card0/device/power_dpm_force_performance_level"
sudo s
[AMD Official Use Only - Internal Distribution Only]
[AMD Official Use Only - Internal Distribution Only]
+ if (adev != hive->adev) {
+ sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
+ }
Please drop the braces in above code segment. Other than that, the patch is
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