On 3/19/20 5:14 PM, Jason Gunthorpe wrote:
On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
+static int dmirror_fault(struct dmirror *dmirror, unsigned long start,
+unsigned long end, bool write)
+{
+ struct mm_struct *mm = dmirror->mm;
+ uns
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.
[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per
register.
[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
1 file cha
This macro calculates the IH ring register offset based on
the three ring numbers and asic type.
The parameters needed are the register's name without the prefix mmIH
and the ring number taken from RING0, RING1 or RING2 macros.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.
[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
[How]
Setting IH_CLIE
[Why]
Replace the way reads and writes are done to the IH ring registers at the
vega10_ih.
This is due to different IH ring registers offset between Vega10 and Arcturus.
[How]
mmIH_RING_REG macro is used to calculate the register address first. Then
RREG32 and WREG32 macros
are used to directly
Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amd
Adding linux-kselft...@vger.kernel.org for the test config question.
On 3/19/20 11:17 AM, Jason Gunthorpe wrote:
On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
On 3/17/20 5:59 AM, Christoph Hellwig wrote:
On Tue, Mar 17, 2020 at 09:47:55AM -0300, Jason Gunthorpe wrote:
I've
Hi Dave, Daniel,
This just adds Mario's pageflip fix on top of yesterday's 5.6 pull.
The following changes since commit a3c33e7a4a116f8715c0ef0e668e6aeff009c762:
drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check (2020-03-18 18:21:57 -0400)
are available in the Git repository at:
git://peo
That looks like a nice cleanup. Some nit-picks inline ...
On 2020-03-19 9:41, Christian König wrote:
Cleanup amdgpu_ttm_copy_mem_to_mem by using fewer variables
for the same value.
Rename amdgpu_map_buffer to amdgpu_ttm_map_buffer, move it
to avoid the forward decleration, cleanup by moving the
On Tue, Mar 17, 2020 at 9:50 AM Yassine Oudjana
wrote:
>
> Signed-off-by: Yassine Oudjana
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 -
> drivers/gpu/drm/radeon/si_dpm.c | 1 -
> 2 files changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm
On Thu, Mar 19, 2020 at 08:16:33AM +0100, Christoph Hellwig wrote:
> On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > > Changes since v1:
> > > - split out the pgmap->owner addition into a separate patch
> > > - check pgmap->owner is set for device private mappings
> > > - re
On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
>
> On 3/17/20 5:59 AM, Christoph Hellwig wrote:
> > On Tue, Mar 17, 2020 at 09:47:55AM -0300, Jason Gunthorpe wrote:
> > > I've been using v7 of Ralph's tester and it is working well - it has
> > > DEVICE_PRIVATE support so I think i
[AMD Public Use]
Hi Alex,
https://github.com/RadeonOpenCompute/rocm_smi_lib will use this interface.
Those functions will be added to this library:
/* Get a handler for watching events */
rsmi_status_t rsmi_event_init(rsmi_event_handle_t *handle);
/* Register events for the device using the han
Hi Dave, Daniel,
Last round of stuff for 5.7. Mostly bug fixes.
The following changes since commit 69ddce0970d9d1de63bed9c24eefa0814db29a5a:
Merge tag 'amd-drm-next-5.7-2020-03-10' of
git://people.freedesktop.org/~agd5f/linux into drm-next (2020-03-13 09:09:11
+1000)
are available in the G
On Thu, Mar 19, 2020 at 03:19:54PM +0100, Sam Ravnborg wrote:
> On Fri, Mar 13, 2020 at 09:17:41PM +0100, Sam Ravnborg wrote:
> > Thomas Zimmermann had made a nice patch-set that introduced
> > drm_simple_encoder_init() which is already present in drm-misc-next.
> >
> > While looking at this it wa
Can we do similar setting for vg10 to fix infinite retry?
Philip
On 2020-03-18 7:38 p.m., Alex Sierra wrote:
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIM
Looks good to me.
Reviewed-by: Andrey Grodzovsky
Andrey
On 3/19/20 10:16 AM, Kent Russell wrote:
Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
s
On Fri, Mar 13, 2020 at 09:17:41PM +0100, Sam Ravnborg wrote:
> Thomas Zimmermann had made a nice patch-set that introduced
> drm_simple_encoder_init() which is already present in drm-misc-next.
>
> While looking at this it was suddenly obvious to me that
> this was functionalty that really should
Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
server cards, as consumer cards do not feature the FRU chip, which
contains this information.
v2: Add d
Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
server cards, as consumer cards do not feature the FRU chip, which
contains this information.
v2: Add d
On Wed, Mar 18, 2020 at 7:38 PM Alex Sierra wrote:
>
> [Why]
> nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per
> register.
>
> [How]
> Change ih doorbell size from 2 to 4. This means two Dwords per ring.
> Current configuration uses two ih rings.
>
> Change-Id: Iae28c22d
Cleanup amdgpu_ttm_copy_mem_to_mem by using fewer variables
for the same value.
Rename amdgpu_map_buffer to amdgpu_ttm_map_buffer, move it
to avoid the forward decleration, cleanup by moving the map
decission into the function and add some documentation.
No functional change.
Signed-off-by: Chri
This should allow us to also support VRAM->GTT moves.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 36 +++--
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/am
On Thu, Mar 19, 2020 at 07:42:04PM +0800, Pan, Xinhui wrote:
>
>
> > 2020年3月19日 18:51，Huang Rui 写道：
> >
> > The queue buffer index starts from position 0, so the available buffer size
> > which starts from position 0 to rptr should be "rptr" index value. While the
> > packet_size_in_dwords == r
On Thu, Mar 19, 2020 at 08:16:33AM +0100, Christoph Hellwig wrote:
> On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > > Changes since v1:
> > > - split out the pgmap->owner addition into a separate patch
> > > - check pgmap->owner is set for device private mappings
> > > - re
> 2020年3月19日 18:51，Huang Rui 写道：
>
> The queue buffer index starts from position 0, so the available buffer size
> which starts from position 0 to rptr should be "rptr" index value. While the
> packet_size_in_dwords == rptr, the available buffer is just good enough.
>
> Signed-off-by: Huang Ru
The queue buffer index starts from position 0, so the available buffer size
which starts from position 0 to rptr should be "rptr" index value. While the
packet_size_in_dwords == rptr, the available buffer is just good enough.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_que
PMFW may boots those ASICs with DC mode. Need to set it back
to AC mode.
Change-Id: I56ffd0e747f778aa013da43a8693ddfb5da31e3c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 15 +++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/a
On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > Changes since v1:
> > - split out the pgmap->owner addition into a separate patch
> > - check pgmap->owner is set for device private mappings
> > - rename the dev_private_owner field in struct migrate_vma to src_owner
> > - re
[AMD Public Use]
The register offset of IH_RB_RING1|RING2 register group is the major
differences between osssys 4.0 and osssys 4.2. Other than that, 4.2 share the
same registers as 4.0. So just centralize ih ring1 and ring2 related functions
into a separated file, and invoke ih ring1 and ring2
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Clements, John
Sent: Thursday, March 19, 2020 00:43
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset
[AMD Public Use]
Submitting patch for review to protect RA
32 matches
Mail list logo
