For multiple GPUs which has the same BDF, but has different domain ID,
the drmOpenByBusid will return the wrong fd when startx.
The reproduce sequence as below:
1. Call drmOpenByBusid to open Card0, then will return the right fd0, and the
fd0 is master privilege;
2. Call drmOpenByBusid to open Car
> -Original Message-
> From: Bo YU
> Sent: Thursday, February 14, 2019 12:46 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; airl...@linux.ie; dan...@ffwll.ch; Zhu, Rex
> ; Grodzovsky, Andrey
> ; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.o
Hi David,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.0-rc4 next-20190213]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
Looks like you are still running this without the latest hang fix since i see
the deadlock again, but actually what i forgot to ask you is to load amdgpu
with vm_fault_stop=2 to freeze the ASIC once VM_FAULT is encountered - sorry
about that. So please retest with amdgpu.vm_fault_stop=2 paramete
On Wed, Feb 13, 2019 at 09:45:36AM -0500, David Francis wrote:
> The function drm_dsc_pps_infoframe_pack only
> packed the payload portion of the infoframe.
> Change the input struct to the PPS payload
> to clarify the function's purpose and allow
> for drivers with their own handling of sdp.
> (e.
On Wed, Jan 30, 2019 at 5:43 AM Christian König
wrote:
>
> Am 30.01.19 um 02:53 schrieb Bas Nieuwenhuizen:
> > Some blocks in amdgpu can have 0 rqs.
> >
> > Job creation already fails with -ENOENT when entity->rq is NULL,
> > so jobs cannot be pushed. Without a rq there is no scheduler to
> > pop
On Wed, Feb 13, 2019 at 07:10:00PM +0100, Mario Kleiner wrote:
> On Wed, Feb 13, 2019 at 5:03 PM Daniel Vetter wrote:
> >
> > On Wed, Feb 13, 2019 at 4:46 PM Kazlauskas, Nicholas
> > wrote:
> > >
> > > On 2/13/19 10:14 AM, Daniel Vetter wrote:
> > > > On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, N
Add amd-gfx and some DC people.
Alex
On Sun, Feb 10, 2019 at 5:13 AM wrote:
>
> From: Mathias Fröhlich
>
> Reference counting in amdgpu_dm_connector for amdgpu_dm_connector::dc_sink
> and amdgpu_dm_connector::dc_em_sink as well as in dc_link::local_sink seems
> to be out of shape. Thus make ref
Hi Dave, Daniel,
A few small fixes for 5.0.
amdgpu:
- Vega20 psp fix
- Add vrr range to debugfs for freesync debugging
sched:
- Scheduler race fix
The following changes since commit 78eb1ca47589f0cd9db2ceb28b60434e8d512131:
Merge branch 'vmwgfx-fixes-5.0-2' of
git://people.freedesktop.org/~
This patch is
Reviewed-by: James Zhu
Tested-by: James Zhu
On 2019-02-12 10:29 p.m., Zhang, Hawking wrote:
> Reviewed-by: Hawking Zhang
>
> Regards,
> Hawking
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher via amd-gfx
> Sent: 2019年2月13日 5:11
> To: amd-gfx@lists.freedesk
This patch is
Reviewed-by: James Zhu
Tested-by: James Zhu
On 2019-02-13 3:10 p.m., Alex Deucher via amd-gfx wrote:
> Missing firmware declaration caused firmware requirement to
> not be noted by the module and may cause firmware to not
> be available in initrd.
>
> Fixes: bc4b539e385088 "drm/am
Missing firmware declaration caused firmware requirement to
not be noted by the module and may cause firmware to not
be available in initrd.
Fixes: bc4b539e385088 "drm/amdgpu: remove old CI DPM implementation"
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 4
From: Eric Bernstein
This enum definition is shared, so move it to a shared location.
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c| 7 ---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 7 ---
d
From: Anthony Koo
[Why]
We want boot to desktop to be seamless
[How]
During init pipes, avoid touching the pipes where GOP has already
enabled the HW to the state we want.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
.../amd/display/dc/dce110/dce110_hw_sequencer.c
From: Gary Kattan
[Why]
Certain tests fail after a fresh reboot. This is caused by writing to
registers prior to ungating the stream we're trying to program.
[How]
Make sure the stream is ungated before writing to its registers.
This also enables power-gating plane resources before init_hw
initi
From: Roman Li
[Why]
The visual corruption due to low display clock value.
Observed on Carrizo 4K@60Hz.
[How]
There was earlier patch for dce_update_clocks:
Adding +15% workaround also to to dce11_update_clocks
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
dr
From: Yongqiang Sun
[Why]
Current periodic interrupt start point calc in optc
is not clear.
[How]
1. DM convert delta time to lines number and dc will calculate the
start position as per lines number and interrupt type.
2. hwss calculates the start point as per line offset.
3. optc programs v
From: Dmytro Laktyushkin
This change changes dc add plane logic to allow plane-less resource
reservation (pipe split).
If a free pipe_ctx (no plane_state attached) is the head pipe, and is
found with a bottom pipe attached, assign the plane to add on the bottom
pipe.
In addition, prepend dcn10
From: Nicholas Kazlauskas
[Why]
Whenever a stream or plane is added or removed from the context the
pointer will change from old to new. We set lock and validation
needed in these cases. But not all of these cases match update_type
from dm_determine_update_type_for_commit - an example being overl
From: Wesley Chalmers
[WHY]
When doing split pipe, if one pipe is pending on flip, the entire
plane's status should be flip pending, otherwise corruption can occur
when OS writes to a surface prematurely.
[HOW]
Clear the flip pending bit before checking pipes, then OR the flip
pending bits from
From: Eryk Brol
[Why]
For later use by the DC VM implementation
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
b/dri
From: Anthony Koo
[Why]
For MST, link not disabled until all streams disabled
[How]
Add check for stream_count before setting link_active = false for MST
Signed-off-by: Anthony Koo
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +++--
From: Fatemeh Darbehani
[Why]
DM has impelemented new pp_smu interface. 'Else' is not longer needed.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Eric Yang
Acked-by: Leo Li
Acked-by: Yongqiang Sun
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 8
1 file changed, 8 dele
From: Nicholas Kazlauskas
[Why]
This format isn't supported in DC and some IGT tests fail since we
expose support for it.
[How]
Remove it.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
1 file c
From: Anthony Koo
[Why]
We are currently losing precision when we convert from
16 bit --> 8 bit --> 16 bit.
[How]
We shouldn't down convert unnecessarily and lose precision.
Keep values at 16 bit and use directly.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
.../drm
From: Nicholas Kazlauskas
[Why]
If the cursor pos passed from DM is less than the plane_state->dst_rect
top left corner then the unsigned cursor pos wraps around to a large
positive number since cursor pos is a u32.
There was an attempt to guard against this in hubp1_cursor_set_position
by check
From: Jun Lei
Add a dc_bounding_box_overrides struct to define bb overrides. It is
loaded in during DC init.
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 10 ++
2 files
From: Nicholas Kazlauskas
[Why]
Seamless boot tries to reuse planes that were enabled for the first
commit applied.
In the case where Raven is booting with two monitors connected and the
first commit contains two streams the screen corruption would occur
because the second stream was trying to r
From: Anthony Koo
[Why]
Seamless boot code not working on all ASICs because of
some underflow issues caused by some uninitialized HW
state.
[How]
Keep some logical and power gating init code in hw_init.
Move some per pipe init code to enable accelerated mode
Signed-off-by: Anthony Koo
Reviewed
From: Josip Pavic
[Why]
eDP v1.4 allows panels to report link rates other than RBR/HBR/HBR2, that
may be more optimal for the panel's timing. Power can be saved by using
a link rate closer to the required bandwidth of the panel's timing.
[How]
Scan the table of reported link rates from the panel
From: Jun Lei
Will be used to signify if P-state change is supported.
Signed-off-by: Jun Lei
Reviewed-by: Eric Yang
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/
From: Anthony Koo
[Why]
AUX arbitration occurs between SW and FW components.
When AUX acquire fails, it causes engine->ddc to be NULL,
which leads to an exception when we try to release the AUX
engine.
[How]
When AUX engine acquire fails, it should return from the
function without trying to cont
From: Bhawanpreet Lakha
[Why]
When a dce80 asic was suspended, the clocks were not set to 0.
Upon resume, the new clock was compared to the existing clock,
they were found to be the same, and so the clock was not set.
This resulted in a blackscreen.
[How]
In atomic commit, check to see if there
From: David Francis
[Why]
The wait_for_vblank boolean in commit_tail was passed by reference
into each stream commit, and if that commit was an asynchronous
flip, it would disable vblank waits on all subsequent flips.
This made the behaviour depend on crtc order in a non-intuitive way,
although
From: David Francis
[Why]
dc_commit_updates_for_stream is called twice per stream: once
with the flip data and once will all other data. This causes
problems when these DC calls have different numbers of planes
For example, a commit with a pageflip on plane A and a
non-pageflip change on plane B
From: Mark McGarrity
Signed-off-by: Mark McGarrity
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index ed11b3c5..eb
From: Jun Lei
[Why]
Make dml and integration with pplib clearer.
[How]
Change the way the dml formula is initialized to make its values more
clear. Restructure DC interface with pplib into rv_funcs.
Cap clocks received from pplib.
Signed-off-by: Jun Lei
Signed-off-by: Eryk Brol
Reviewed-by: D
From: Nicholas Kazlauskas
[Why]
If a commit updates an overlay plane via the legacy plane IOCTL
then the only plane in the state will be the overlay plane.
Overlay planes need to be added first to the DC context, but in the
scenario above the plane will be added last. This will result in wrong
z
From: mmcgarri
Signed-off-by: mmcgarri
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1b8eaf5..9adb801 100644
From: Charlene Liu
Added a "disable_tri_buf" DC debug option. When set to 1 feature will
be off.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/displ
From: Charlene Liu
Driver need to poll the SURFACE_INUSE register to determine when to
start the new task and write data to the checked surface.
Implement the wait functions, and add the necessary hubbub registers.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
From: Nicholas Kazlauskas
[Why]
Cursor updates used to happen after vblank/flip/stream updates before
the stream update refactor. They now happen before stream updates
which means that they're not going to be synced with fb changes
and that they're going to programmed for pipes that we're disabli
From: Nicholas Kazlauskas
[Why]
The stream->mode_changed flag can persist in the following sequence
of atomic commits:
Commit 1:
Enable CRTC0 (mode_changed = true), Enable CRTC1 (mode_changed = true)
Commit 2:
Disable CRTC1 (mode_changed = false)
In this sequence we want to keep the exiting CR
From: Bhawanpreet Lakha
[Why]
optimize_bandwidth was using dce100_prepare_bandwidth this is incorrect
[How]
change it to dce100_optimize_bandwidth
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 4
From: Josip Pavic
[Why]
Previously, a change removed code that would send a pipe set command
to dmcu each time the backlight was set, as it was thought to be
superfluous. However, it is possible for the backlight to be set
before a valid pipe has been set, which causes DMCU to hang after a
DPMS r
From: "Leo (Hanghong) Ma"
[Why]
drm_dp_mst_topology_mgr_suspend() is added into the new reboot
sequence, which disables the UP request at the beginning.
Therefore sideband messages are blocked.
[How]
Finish MST sideband message transaction before UP request is
suppressed.
Signed-off-by: Leo (Ha
From: Leo Li
Summary of change:
* Fix S3 resume black screen on DCE8
* Fix dissapearing cursor on Raven sytems
* Cleanup DM plane commit logic
* Fixes for multiplane commits
* Fixes for seamless boot
Anthony Koo (5):
drm/amd/display: remove screen flashes on seamless boot
drm/amd/display: In
From: Josip Pavic
[Why]
When stream is blanked, pipe set command is sent to dmcu to notify it
that the abm pipe is disabled. When stream is unblanked, no notification is
made to dmcu that the abm pipe has been enabled, resulting in abm not
being enabled in the firmware.
[How]
When stream is unbl
On 2/13/19 2:21 PM, Grodzovsky, Andrey wrote:
>
> On 2/13/19 2:16 PM, Kazlauskas, Nicholas wrote:
>> On 2/13/19 2:10 PM, Grodzovsky, Andrey wrote:
>>> On 2/13/19 2:00 PM, Kazlauskas, Nicholas wrote:
On 2/13/19 1:58 PM, Andrey Grodzovsky wrote:
> When ring hang happens amdgpu_dm_commit_pla
On 2/13/19 2:16 PM, Kazlauskas, Nicholas wrote:
> On 2/13/19 2:10 PM, Grodzovsky, Andrey wrote:
>> On 2/13/19 2:00 PM, Kazlauskas, Nicholas wrote:
>>> On 2/13/19 1:58 PM, Andrey Grodzovsky wrote:
When ring hang happens amdgpu_dm_commit_planes during flip is holding
the BO reserved and th
On 2/13/19 2:10 PM, Grodzovsky, Andrey wrote:
>
> On 2/13/19 2:00 PM, Kazlauskas, Nicholas wrote:
>> On 2/13/19 1:58 PM, Andrey Grodzovsky wrote:
>>> When ring hang happens amdgpu_dm_commit_planes during flip is holding
>>> the BO reserved and then stack waiting for fences to signal in
>>> reserva
On 2/13/19 2:00 PM, Kazlauskas, Nicholas wrote:
> On 2/13/19 1:58 PM, Andrey Grodzovsky wrote:
>> When ring hang happens amdgpu_dm_commit_planes during flip is holding
>> the BO reserved and then stack waiting for fences to signal in
>> reservation_object_wait_timeout_rcu (which won't signal becau
On 2/13/19 1:58 PM, Andrey Grodzovsky wrote:
> When ring hang happens amdgpu_dm_commit_planes during flip is holding
> the BO reserved and then stack waiting for fences to signal in
> reservation_object_wait_timeout_rcu (which won't signal because there
> was a hnag). Then when we try to shutdown d
When ring hang happens amdgpu_dm_commit_planes during flip is holding
the BO reserved and then stack waiting for fences to signal in
reservation_object_wait_timeout_rcu (which won't signal because there
was a hnag). Then when we try to shutdown display block during reset
recovery from drm_atomic_he
On Wed, Feb 13, 2019 at 09:45:35AM -0500, David Francis wrote:
> Native 420 and 422 transfer modes are new in DSC1.2
>
> In these modes, each two pixels of a slice are treated as one
> pixel, so the slice width is half as large (round down) for
> the purposes of calucating the groups per line and
On 2/13/19 1:10 PM, Mario Kleiner wrote:
> On Wed, Feb 13, 2019 at 5:03 PM Daniel Vetter wrote:
>>
>> On Wed, Feb 13, 2019 at 4:46 PM Kazlauskas, Nicholas
>> wrote:
>>>
>>> On 2/13/19 10:14 AM, Daniel Vetter wrote:
On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, Nicholas
wrote:
>
>
On Wed, Feb 13, 2019 at 09:45:34AM -0500, David Francis wrote:
> The function intel_compute_rc_parameters is part of the dsc spec
> and is not driver-specific. Other drm drivers might like to use
> it. The function is not changed; just moved and renamed.
>
Yes this sounds fair since its DSC spec
Change-Id: Icc9167771ad9539d8e31b40058e3b22be825a585
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 6 ++
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
3 files changed, 12 insertions(+)
diff --git a/dr
We can directly calculate sdma doorbell indexes in the process doorbell
pages through the doorbell_index structure in amdgpu_device, so no need
to cache them in kgd2kfd_shared_resources any more. This alleviates the
adaptation needs when new SDMA configurations are introduced.
Change-Id: Ic6577998
The similar definitions should be consecutive.
Change-Id: I936cf076363e641c60e0704d8405ae9493718e18
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/
Reserved doorbells for SDMA IH and VCN were not properly masked out
when allocating doorbells for CP user queues. This patch fixed that.
Change-Id: I670adfc3fd7725d2ed0bd9665cb7f69f8b9023c2
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 16
driver
On Wed, Feb 13, 2019 at 5:03 PM Daniel Vetter wrote:
>
> On Wed, Feb 13, 2019 at 4:46 PM Kazlauskas, Nicholas
> wrote:
> >
> > On 2/13/19 10:14 AM, Daniel Vetter wrote:
> > > On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, Nicholas
> > > wrote:
> > >>
> > >> On 2/13/19 4:50 AM, Daniel Vetter wrote:
Pushed. Thanks.
Yong
On 2019-02-08 5:09 p.m., Kuehling, Felix wrote:
> The series is Reviewed-by: Felix Kuehling
>
> On 2019-02-07 5:23 p.m., Zhao, Yong wrote:
>> They are no longer used, so delete them to avoid confusion.
>>
>> Change-Id: I3cf23fe7110ff88f53c0c279b2b4ec8d1a53b87c
>> Signed-off-
On Wed, Feb 13, 2019 at 4:46 PM Kazlauskas, Nicholas
wrote:
>
> On 2/13/19 10:14 AM, Daniel Vetter wrote:
> > On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, Nicholas
> > wrote:
> >>
> >> On 2/13/19 4:50 AM, Daniel Vetter wrote:
> >>> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> >
On 2/13/19 10:14 AM, Daniel Vetter wrote:
> On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, Nicholas
> wrote:
>>
>> On 2/13/19 4:50 AM, Daniel Vetter wrote:
>>> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
>
> On Mon,
On 2019-02-13 9:45 a.m., David Francis wrote:
> The function drm_dsc_pps_infoframe_pack only
> packed the payload portion of the infoframe.
> Change the input struct to the PPS payload
> to clarify the function's purpose and allow
> for drivers with their own handling of sdp.
> (e.g. drivers with t
On 2019-02-13 9:45 a.m., David Francis wrote:
> Native 420 and 422 transfer modes are new in DSC1.2
>
> In these modes, each two pixels of a slice are treated as one
> pixel, so the slice width is half as large (round down) for
> the purposes of calucating the groups per line and chunk size
> in b
On 2019-02-13 9:45 a.m., David Francis wrote:
> The function intel_compute_rc_parameters is part of the dsc spec
> and is not driver-specific. Other drm drivers might like to use
> it. The function is not changed; just moved and renamed.
>
> Signed-off-by: David Francis
Reviewed-by: Harry Wentl
OK, just apply the following to your amdgpu_dm_do_flip function and see
if GPU reset does proceed after you experience the hang.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d59bafc..586301f 100644
--- a/drivers/gpu/drm/
On Wed, Feb 13, 2019 at 3:33 PM Kazlauskas, Nicholas
wrote:
>
> On 2/13/19 4:50 AM, Daniel Vetter wrote:
> > On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> >> On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
> >>>
> >>> On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
>
The function drm_dsc_pps_infoframe_pack only
packed the payload portion of the infoframe.
Change the input struct to the PPS payload
to clarify the function's purpose and allow
for drivers with their own handling of sdp.
(e.g. drivers with their own struct for
all SDP transactions)
Signed-off-by:
drm_dsc could use some work so that drm drivers other than
i915 can make use of it their own DSC implementations
Move rc compute, a function that forms part of the DSC spec,
into drm. Update it to DSC 1.2. Also change the packing function
to operate only on the packing struct, to allow for drivers
Native 420 and 422 transfer modes are new in DSC1.2
In these modes, each two pixels of a slice are treated as one
pixel, so the slice width is half as large (round down) for
the purposes of calucating the groups per line and chunk size
in bytes
In native 422 mode, each pixel has four components,
The function intel_compute_rc_parameters is part of the dsc spec
and is not driver-specific. Other drm drivers might like to use
it. The function is not changed; just moved and renamed.
Signed-off-by: David Francis
---
drivers/gpu/drm/drm_dsc.c | 133 ++
driv
On 2/13/19 4:50 AM, Daniel Vetter wrote:
> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
>> On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
>>>
>>> On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
>>> wrote:
On 2/11/19 3:35 AM, Daniel Vetter wrote:
> On Mon
On Wed, Feb 13, 2019 at 11:54 AM Michel Dänzer wrote:
>
> On 2019-02-13 10:53 a.m., Daniel Vetter wrote:
> > On Mon, Feb 11, 2019 at 04:01:12PM +0100, Michel Dänzer wrote:
> >> On 2019-02-09 7:52 a.m., Mario Kleiner wrote:
> >>> In VRR mode, keep track of the vblank count of the last
> >>> complet
On Wed, Feb 13, 2019 at 12:05 PM Mario Kleiner
wrote:
>
> On Wed, Feb 13, 2019 at 10:56 AM Chris Wilson
> wrote:
> >
> > Quoting Daniel Vetter (2019-02-13 09:50:55)
> > > On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > > > I think all kms drivers try to call drm_crtc_handle_vb
Hello Yongqiang Sun,
The patch 810ece19ee74: "drm/amd/display: Calc vline position in dc."
from Jan 24, 2019, leads to the following static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_optc.c:152
calc_vline_position()
warn: inconsistent indenting
drivers
On Wed, Feb 13, 2019 at 10:50 AM Daniel Vetter wrote:
>
> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
> > >
> > > On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
> > > wrote:
> > > >
> > > > On 2/11/19 3:35 AM, Dani
On Wed, Feb 13, 2019 at 10:56 AM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2019-02-13 09:50:55)
> > On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > > I think all kms drivers try to call drm_crtc_handle_vblank() at start
> > > of vblank to give Mesa the most time for frontbu
On 2019-02-13 10:53 a.m., Daniel Vetter wrote:
> On Mon, Feb 11, 2019 at 04:01:12PM +0100, Michel Dänzer wrote:
>> On 2019-02-09 7:52 a.m., Mario Kleiner wrote:
>>> In VRR mode, keep track of the vblank count of the last
>>> completed pageflip in amdgpu_crtc->last_flip_vblank, as
>>> recorded in th
Quoting Daniel Vetter (2019-02-13 09:50:55)
> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > I think all kms drivers try to call drm_crtc_handle_vblank() at start
> > of vblank to give Mesa the most time for frontbuffer rendering for
> > classic X. But vblank events are also use
On Mon, Feb 11, 2019 at 04:01:12PM +0100, Michel Dänzer wrote:
> On 2019-02-09 7:52 a.m., Mario Kleiner wrote:
> > In VRR mode, keep track of the vblank count of the last
> > completed pageflip in amdgpu_crtc->last_flip_vblank, as
> > recorded in the pageflip completion handler after each
> > compl
On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
> >
> > On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
> > wrote:
> > >
> > > On 2/11/19 3:35 AM, Daniel Vetter wrote:
> > > > On Mon, Feb 11, 2019 at 04:22:24AM +0100, Mari
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