Re: [PATCH 2/2] drm/amd/vega10: allow increased power limit

On Thu, Oct 4, 2018 at 3:17 AM Aleksandr Mezin wrote: > > Allow setting the power limit to 150% of the default one, like > Windows driver does. Please see this patch: https://patchwork.freedesktop.org/patch/255970/ This matches what the windows driver does. Alex > > Signed-off-by: Aleksandr Mez

Re: [PATCH] drm/amd/pp: enable power limit increase in OD mode

On Wed, Oct 10, 2018 at 7:25 PM Greathouse, Joseph wrote: > > OverDrive mode allows users to increase the maximum SCLK and MCLK > frequencies beyond the default on the GPU. However, this may not > results in large performance gains if the GPU then runs into its TDP > power limit. This patch adds t

[pull] amdgpu, amdkfd, scheduler, radeon, ttm drm-next-4.20

Hi Dave, Fixes for 4.20. A little bigger than I'd like, but there are a lot of fixes for new asics that were introduced in 4.20 (Vega20, RV2, PCO). Highlights: - Add a new list.h helper for doing bulk updates. Used by ttm. - Fixes for display underflow on VI APUs at 4K with UVD running - Endian

[PATCH] drm/amd/pp: enable power limit increase in OD mode

OverDrive mode allows users to increase the maximum SCLK and MCLK frequencies beyond the default on the GPU. However, this may not results in large performance gains if the GPU then runs into its TDP power limit. This patch adds the capability to increase the power limit of a GPU above its default

[PATCH 26/26] drm/amd/display: Disable 4k 60 HDMI on DCE11

From: David Francis [Why] Carrizo and Stoney have severe corruption when trying to power 4k 60 monitors over HDMI connectors that support 4k 60. Carrizo and Stoney require retimers and redrivers to support 4k 60 over HDMI. This driver does not currently support these. Thus, 4k 60 HDMI (and all

[PATCH 25/26] drm/amd/display: Check if hubp function hooks exist before calling them

From: Charlene Liu Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw

[PATCH 24/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part3

From: Fatemeh Darbehani [Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also sim

[PATCH 23/26] drm/amd/display: Remove stream_res tg null check in commit planes

From: SivapiriyanKumarasamy [Why] TG in pipe_ctx stream resource is not null where used in commit_planes_do_stream_update since it is assigned the same time the stream is set in pipe_ctx - when the pipe is acquired. This null check produced a static code analysis warning and should be removed to

[PATCH 19/26] drm/amd/display: dc 3.2.02

From: SivapiriyanKumarasamy Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Harry Wentland Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/displ

[PATCH 22/26] drm/amd/display: Fix incorrect end slope of EETF

From: SivapiriyanKumarasamy Force the E2 to dc_fixpt_one when E1 exceeds that value. This is the correct thing to do to avoid corruption. Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Krunoslav Kovac Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/modules/color/color_gamma.c

[PATCH 21/26] drm/amd/display: rename cstate_pstate_watermarks_st1

cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st Signed-off-by: vikrant mhaske Signed-off-by: Bhawanpreet Lakha Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH 20/26] drm/amd/display: explicit uint64_t casting

explicitly cast uint64_t in div64_u64_rem() Signed-off-by: vikrant mhaske Signed-off-by: Bhawanpreet Lakha Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/dr

[PATCH 18/26] drm/amd/display: add dccg block

From: Dmytro Laktyushkin This adds the hw block as well as hooks up dppclk dto programming Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h | 7 +++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer

[PATCH 16/26] drm/amd/display: rename dccg to clk_mgr

From: Dmytro Laktyushkin In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/core/dc_reso

[PATCH 17/26] drm/amd/display: implement PERF_TRACE on Linux

From: David Francis [Why] A quick-and-dirty way of getting performance data for the amdgpu driver would make performance improvements easier [How] The PERF_TRACE functionality is a tic-toc style debug method. Put PERF_TRACE calls on either side of the code you want to test. PERF_TRACE requires a

[PATCH 15/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part2

From: Fatemeh Darbehani [Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also sim

[PATCH 12/26] drm/amd/display: fix report display count logic

From: Eric Yang [Why] Previous logic to update display count in commit_planes_do_stream_update doesn't cover all cases. [How] Update display count as part of clock updates. Count virtual stream as active to work around headless situation. Signed-off-by: Eric Yang Reviewed-by: Dmytro Laktyushki

[PATCH 13/26] drm/amd/display: Add link encoder dp_ycbcr420_supported feature flag

From: Eric Bernstein [Why] Need separate feature flag for DP 4:2:0 support, since existing flag is used for HDMI [How] Added dp_ycbcr420_supported to struct encoder_feature_support Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/disp

[PATCH 14/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part1

From: Fatemeh Darbehani [Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also sim

[PATCH 11/26] drm/amd/display: expose hwseq functions and add registers

From: Nevenko Stupar Make these functions non static and define registers for future use is_lower_pipe_tree_visible(); is_upper_pipe_tree_visible(); is_pipe_tree_visible(); dcn10_program_pte_vm(); set_hdr_multiplier(); update_dchubp_dpp() f

[PATCH 10/26] drm/amd/display: initialize dc_transfer_func->ctx

From: David Francis [Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by: David Francis Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/

[PATCH 09/26] drm/amd/display: Build ColorSpace and Transfer Function

From: SivapiriyanKumarasamy [Why] Need to build correct regamma curve to make use of display native parameters for HDR and more closely match content range to display. [How] Enable freesync hdr curve building after reading display capabilities and receiving setsourcecontentinfo call. This will

[PATCH 08/26] drm/amd/display: split dccg clock manager into asic folders

From: Dmytro Laktyushkin Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/

[PATCH 09/26] drm/amd/display: Add support for Freesync 2 HDR and Content to Display Mapping

From: SivapiriyanKumarasamy [Why] Freesync 2 HDR and support for HDR content outside the range of the HDR display require implementation on Dal 3 to better match Dal2. [How] Add support for Freesync HDR and mapping of source content to display ranges for better representation of HDR content. Si

[PATCH 07/26] drm/amd/display: clean up base dccg struct

From: Dmytro Laktyushkin Move things not accessed outside dccg block into dce specific struct Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 49 +- drivers/gpu/drm/amd/display/

[PATCH 06/26] drm/amd/display: Freesync does not engage on some displays

From: Harmanprit Tatla [Why] Current render margin time is not sufficient to compute exit frame time for most monitors. [How] Declared render margin in FPS to compute a exit frame rate that is 4 FPS above the minimum FPS required to engage FreeSync. Also did code clean-up to remove redundancie

[PATCH 05/26] drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead

From: Dmytro Laktyushkin This is done to keep things more readable, avoids a true/false flag in dc interface layer. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++--- .../amd/display/dc/dce1

[PATCH 04/26] drm/amd/display: move pplib/smu notification to dccg block

From: Dmytro Laktyushkin This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update. This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality. Signed-off-by: Dmytro Lakt

[PATCH 03/26] drm/amd/display: handle max_vstartup larger than vblank_end

From: Dmytro Laktyushkin When vstartup is larger than vblank end we need to set v_fp2 to allow for this early start Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +-- 1 file changed, 5

[PATCH 01/26] drm/amd/display: fix bug of accessing invalid memory

From: Su Sung Chung [Why] A loop inside of build_evenly_distributed_points function that traverse through the array of points become an infinite loop when m_GammaUpdates does not get assigned to any value. [How] In DMColor, clear m_gammaIsValid bit just before writting all Zeromem for m_GammaUpd

[PATCH 02/26] drm/amd/display: dc 3.2.01

From: Fatemeh Darbehani Signed-off-by: Fatemeh Darbehani Reviewed-by: Steven Chiu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h

[PATCH 00/26] DC Patches 10 Oct, 2018

Summary of Changes *Refactor dce clocks *Implement PERF_TRACE on linux *Refactor dc to smu interface Bhawanpreet Lakha (2): drm/amd/display: explicit uint64_t casting drm/amd/display: rename cstate_pstate_watermarks_st1 Charlene Liu (1): drm/amd/display: Check if hubp function hooks exist b

[PATCH 15/18] drm/amdgpu/vcn:Remove SPG mode unused steps during vcn start

Remove Sitatic Power Gate mode unused steps during vcn start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 30 ++ 1 file changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/

[PATCH 09/18] drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start

Remove Dynamic Power Gate mode unused steps during VCN start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +--- 1 file changed, 1 insertion(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn

[PATCH 11/18] drm/amdgpu/vcn:Update SPG mode VCN memory control

Update Static Power Gate mode VCN memory control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 624a255..733

[PATCH 02/18] drm/amdgpu/vcn:Update latest UVD_MPC register for VCN

Update latest UVD_MPC register for VCN. Use defined macro to replace value for readability. Signed-off-by: James Zhu Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 52 +++ 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/

[PATCH 00/18] VCN start/stop clean up

Clean up current VCN start/stop function, and update with latest firmware/hardware implemention. James Zhu (18): drm/amdgpu/vcn:Add new register offset/mask for VCN drm/amdgpu/vcn:Update latest UVD_MPC register for VCN drm/amdgpu/vcn:Update latest spg mode stop for VCN drm/amdgpu/vcn:Add r

[PATCH 07/18] drm/amdgpu/vcn:Update DPG mode VCN global tiling registers

Update Dynamic Power Gate mode VCN global tiling registers Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c in

[PATCH 05/18] drm/amdgpu/vcn:Reduce unnecessary local variable

Reduce unnecessary local variable. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index a609486..e597116 10064

[PATCH 18/18] drm/amdgpu/vcn:Update SPG mode UVD status clear

Update Static Power Gate mode UVD status clear Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index d8fe14d..bc64706 100644

[PATCH 14/18] drm/amdgpu/vcn:Add SPG mode Register XX check

Add Static Power Gate mode Register XX check Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 3275eaf..afb174f 100644 --- a/drivers/gpu/d

[PATCH 04/18] drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop

Add ring write/read pointer check for VCN dynamic power gate mode stop,to make sure that no job is left in ring before turn off DPG mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/

[PATCH 08/18] drm/amdgpu/vcn:Add DPG mode Register XX check

Add Dynamic Power Gate mode Register XX check Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index de57e6d..afc7a1d 100644 --- a/drivers/

[PATCH 10/18] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start

Apply new UMC enable for VNC Dynamic Power Gate mode start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 5740cca.

[PATCH 17/18] drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG start

Set VCPU busy after gate power during vcn Static Power Gate start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 153f23a..d8fe14d 10064

[PATCH 13/18] drm/amdgpu/vcn:Move SPG mode mc resume after MPC control

Move Static Power Gate mode mc resume after MPC control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 29f711b..3275eaf

[PATCH 16/18] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode

Apply new UMC enable for VNC Dynamic Power Gate mode Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 93e2a40..15

[PATCH 06/18] drm/amdgpu/vcn:Update DPG mode VCN memory control

Update Dynamic Power Gate mode VCN memory control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index e5971

[PATCH 12/18] drm/amdgpu/vcn:Update SPG mode VCN global tiling

Update Static Power Gate mode VCN global tiling Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 73301a9..29f711b 100644

[PATCH 01/18] drm/amdgpu/vcn:Add new register offset/mask for VCN

Add new register offset/mask for VCN to support latest VCN implementation. Signed-off-by: James Zhu --- .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 14 ++ .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 18 ++ 2 files changed, 32 insertions(+) d

[PATCH 03/18] drm/amdgpu/vcn:Update latest spg mode stop for VCN

Update latest static power gate mode stop function for VCN Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 41 ++- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amd

Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'header'

On Wed, Sep 26, 2018 at 11:01 AM YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo': > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning: > variable 'header' set but not used [-Wunused-but-

Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop

On Mon, Oct 1, 2018 at 3:26 AM YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop': > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning: > variable 'ring' set but not used [-Wunused-but-set-variabl

Re: [PATCH -next] drm/amdkfd: Remove set but not used variable 'preempt_all_queues'

On Tue, Oct 9, 2018 at 3:37 AM YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function > 'destroy_queue_cpsch': > drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning: > variable 'preempt_all_que

Re: [PATCH][drm-next] drm/amdgpu/powerplay: fix missing break in switch statements

On Tue, Oct 9, 2018 at 6:44 AM Huang Rui wrote: > > On Mon, Oct 08, 2018 at 05:22:28PM +0100, Colin King wrote: > > From: Colin Ian King > > > > There are several switch statements that are missing break statements. > > Add missing breaks to handle any fall-throughs corner cases. > > > > Detected

Re: [PATCH] drm/amdgpu: Suppress keypresses from ACPI_VIDEO events

On Fri, Sep 21, 2018 at 8:44 PM Lyude Paul wrote: > > Currently we return NOTIFY_DONE for any event which we don't think is > ours. However, many laptops will send more then just an ATIF event and > will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't > check for this, we return

Re: [PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning

Series is: Reviewed-by: Alex Deucher From: amd-gfx on behalf of Rex Zhu Sent: Wednesday, October 10, 2018 9:28:15 AM To: amd-gfx@lists.freedesktop.org Cc: Zhu, Rex Subject: [PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning Remove the warning messag

Re: [PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not supported

Series is: Reviewed-by: Alex Deucher From: amd-gfx on behalf of Evan Quan Sent: Wednesday, October 10, 2018 4:13:15 AM To: amd-gfx@lists.freedesktop.org Cc: Quan, Evan Subject: [PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not supported G

Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg

I think it's useful to keep around for bringup and early in the asic lifecycle. Alex From: Zhu, Rex Sent: Tuesday, October 9, 2018 11:39:49 PM To: Deucher, Alexander; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in

amdgpu ac adaptor bug

I just bisected the kernel and i have found the commit that caused the bug: https://github.com/torvalds/linux/commit/320b164abb32db876866a4ff8c2cb710524ac6ea ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/li

Re: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay

Sounds good to me. Alex From: amd-gfx on behalf of Zhu, Rex Sent: Tuesday, October 9, 2018 9:44 PM To: Alex Deucher Cc: amd-gfx list Subject: RE: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay > -Original Message- > Fr

Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start

Good question, I asked the same one :) One problem seems to be a firmware bug in the VCE firmware which seems to write to the wrong location in this case. Another one is probably a coding error in the SDMA handling. Christian. Am 10.10.2018 um 16:32 schrieb Liu, Shaoyun: Just curious , why

RE: [PATCH] drm/amdgpu: Limit the max mc address to hole start

Just curious , why the gart range form 0x to 0x1FFF will cause the engine hang ? Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Emily Deng Sent: Wednesday, October 10, 2018 3:31 AM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: [PAT

Re: [PATCH libdrm v2 2/2] amdgpu/test: Fix deadlock tests for AI and RV v2

Sorry for late response, just back from vacation. Indeed I do have commit rights, I am back now and will finalize this work soon. Thanks for the reviews. Andrey On 10/03/2018 02:22 PM, Marek Olšák wrote: Yes, Andrey has commit rights. Marek On Wed, Oct 3, 2018 at 10:34 AM Christian König

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On 10/10/2018 03:14 AM, Pekka Paalanen wrote: On Fri, 5 Oct 2018 12:21:20 -0400 "Kazlauskas, Nicholas" wrote: On 10/05/2018 04:10 AM, Pekka Paalanen wrote: Hi, I have a somewhat of my own view on what would be involved with VRR, and I'd like to hear what you think of it. Comments inline. O

[PATCH 2/3] drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2

Extract the function of fw loading out of powerplay. Do fw loading between hw_init/resuem_phase1 and phase2 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 61 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 drivers/gpu/drm/amd

[PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning

Remove the warning message: "-1 is not supported on VI" the -1 is the default fw load type, mean auto. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 1/3] drm/amdgpu: split ip hw_init into 2 phases

We need to do some IPs earlier to deal with ordering issues similar to how resume is split into two phases. Do fw loading via smu/psp between the two phases. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 66 -- 1 file changed, 53 insertions(

Re: [PATCH 2/5] drm/amdgpu/rlc: gfx_v6 change the method to call rlc function

Am 10.10.2018 um 13:42 schrieb likun Gao: From: Likun Gao Use struct pointer to call rlc function. When you do this please do the next step as well and separate our the RLC functions into another file. Otherwise I don't see the point in actually doing the change. Christian. Signed-off-

Re: [PATCH 1/5] drm/amdgpu/rlc: unify rlc function into structure

Am 10.10.2018 um 13:42 schrieb likun Gao: From: Likun Gao Put function rlc_init,rlc_fini,rlc_resume,rlc_stop,rlc_start into structure amdgpu_rlc_funcs. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu

[PATCH 3/5] drm/amdgpu/rlc: gfx_v7 change the method to call rlc function

From: Likun Gao Use struct pointer to call rlc function. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/g

[PATCH 5/5] drm/amdgpu/rlc: gfx_v9 change the method to call rlc function

From: Likun Gao Use struct pointer to call rlc function. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/g

[PATCH 4/5] drm/amdgpu/rlc: gfx_v8 change the method to call rlc function

From: Likun Gao Use struct pointer to call rlc function. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 28 +--- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx

[PATCH 2/5] drm/amdgpu/rlc: gfx_v6 change the method to call rlc function

From: Likun Gao Use struct pointer to call rlc function. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_

[PATCH 1/5] drm/amdgpu/rlc: unify rlc function into structure

From: Likun Gao Put function rlc_init,rlc_fini,rlc_resume,rlc_stop,rlc_start into structure amdgpu_rlc_funcs. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/dr

[PATCH 0/5] RLC kernel code update for unified RLC function

From: Likun Gao Hi all, Code modified about RLC will be operated to improve the resuability of RLC's code, and this process will operated with two steps: STEP1(completed): - Unify RLC's function into the structure amdgpu_rlc_funcs and use structure pointer to call RLC functions. - The modifie

[PATCH 1/2] drm/amd/powerplay: translate power_profile mode to pplib workload type

Correctly translate the power profile specified by user to workload type accepted by SMU fw. Change-Id: I4de525d6a84a80c2fcfc1a6de2a465a7a07868a4 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 42 +-- 1 file changed, 39 insertions(+), 3 deletions(-)

[PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not supported

Give user some hints when the power profile setting is not supported. Change-Id: Iba2b938d02a039ccdee32f9aca185f79fd818796 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/p

RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV

Thanks Sigil Hi Christian Looks we can enable/disable ctx-switch for SDMA at will, no dependency or conflict on SRIOV /Monk -Original Message- From: Ma, Sigil Sent: Wednesday, October 10, 2018 3:25 PM To: Liu, Monk ; Koenig, Christian ; Huang, Ray ; Min, Frank Cc: amd-gfx@lists.fre

Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start

Am 10.10.2018 um 09:31 schrieb Emily Deng: Use "AMDGPU_GMC_HOLE_START - 1" For the vram_start is 0 case, the gart range will be from 0x to 0x1FFF, which will cause the engine hang. So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq Signed-of

[PATCH] drm/amdgpu: Limit the max mc address to hole start

Use "AMDGPU_GMC_HOLE_START - 1" For the vram_start is 0 case, the gart range will be from 0x to 0x1FFF, which will cause the engine hang. So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/am

RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV

Hi Monk, AUTO_CTXSW_ENABLE is not relevant to worldswitch preemption. it only applies for ring buffer preemption. SDMA will do worldswitch whatever AUTO_CTXSW_ENABLE is 1 or 0. -Original Message- From: Liu, Monk Sent: Wednesday, October 10, 2018 2:54 PM To: Koenig, Christian ; Huang,

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On Fri, 5 Oct 2018 12:21:20 -0400 "Kazlauskas, Nicholas" wrote: > On 10/05/2018 04:10 AM, Pekka Paalanen wrote: > > Hi, > > > > I have a somewhat of my own view on what would be involved with VRR, > > and I'd like to hear what you think of it. Comments inline. > > > > > > On Tue, 25 Sep 2018 0

Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start

Am 10.10.2018 um 08:45 schrieb Emily Deng: Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START and add the comment. For the vram_start is 0 case, the gart range will be from 0x to 0x1FFF, which will cause the engine hang. So to avoid the hole, limit the max mc ad

Re: [PATCH 04/12] drm/amdgpu: move IV prescreening into the GMC code

Yeah, exactly my thinking. Basically the long term goal is to move most of the reporting and handling of faults into amdgpu_gmc.c. Otherwise we would duplicate a lot of handling for future hw generations. On the other hand if the approach with the second IH ring buffer works as expected we m