Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 9da4a1b..517a721 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/d
On Mon, Sep 24, 2018 at 6:07 PM Nick Desaulniers
wrote:
>
> On Fri, Sep 21, 2018 at 2:01 PM Nathan Chancellor
> wrote:
> >
> > Clang generates warnings when one enumerated type is implicitly
> > converted to another.
> >
> > drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57:
> >
On Mon, Sep 24, 2018 at 03:07:16PM -0700, Nick Desaulniers wrote:
> On Fri, Sep 21, 2018 at 2:55 PM Nathan Chancellor
> wrote:
> >
> > Clang warns when one enumerated type is implicitly converted to another.
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning:
> > implic
On Fri, Sep 21, 2018 at 2:55 PM Nathan Chancellor
wrote:
>
> Clang warns when one enumerated type is implicitly converted to another.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning:
> implicit conversion from enumeration type 'enum
> aux_channel_operation_result' to dif
On Fri, Sep 21, 2018 at 2:01 PM Nathan Chancellor
wrote:
>
> Clang generates warnings when one enumerated type is implicitly
> converted to another.
>
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57:
> warning: implicit conversion from enumeration type 'enum
> atom_smu11_sysp
On Mon, Sep 24, 2018 at 10:35 PM Jason Gunthorpe wrote:
> On Mon, Sep 24, 2018 at 10:18:52PM +0200, Arnd Bergmann wrote:
> > On Tue, Sep 18, 2018 at 7:59 PM Jason Gunthorpe wrote:
> > > On Tue, Sep 18, 2018 at 10:51:08AM -0700, Darren Hart wrote:
> > > > On Fri, Sep 14, 2018 at 09:57:48PM +0100,
On Mon, Sep 24, 2018 at 10:18:52PM +0200, Arnd Bergmann wrote:
> On Tue, Sep 18, 2018 at 7:59 PM Jason Gunthorpe wrote:
> >
> > On Tue, Sep 18, 2018 at 10:51:08AM -0700, Darren Hart wrote:
> > > On Fri, Sep 14, 2018 at 09:57:48PM +0100, Al Viro wrote:
> > > > On Fri, Sep 14, 2018 at 01:35:06PM -07
On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote:
> On 09/24/2018 02:38 PM, Ville Syrjälä wrote:
> > On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote:
> >> Variable refresh rate algorithms have typically been enabled only
> >> when the display is covered by a
On Tue, Sep 18, 2018 at 7:59 PM Jason Gunthorpe wrote:
>
> On Tue, Sep 18, 2018 at 10:51:08AM -0700, Darren Hart wrote:
> > On Fri, Sep 14, 2018 at 09:57:48PM +0100, Al Viro wrote:
> > > On Fri, Sep 14, 2018 at 01:35:06PM -0700, Darren Hart wrote:
> > >
> > > > Acked-by: Darren Hart (VMware)
> >
Only print the warning if there was actually some fence processed
from the SW fallback timer.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 +
On 09/24/2018 02:38 PM, Ville Syrjälä wrote:
On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote:
Variable refresh rate algorithms have typically been enabled only
when the display is covered by a single source of content.
This patch introduces a new default CRTC property that h
On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote:
> Variable refresh rate algorithms have typically been enabled only
> when the display is covered by a single source of content.
>
> This patch introduces a new default CRTC property that helps
> hint to the driver when the CRTC
On Mon, Sep 24, 2018 at 02:15:35PM -0400, Nicholas Kazlauskas wrote:
> Modern display hardware is capable of supporting variable refresh rates
> and adaptive sync technologies. The properties for querying and
> controlling these features should be exposed on the DRM connector.
>
> This patch intro
The AMDGPU specific FreeSync properties and IOCTLs are dropped
from amdgpu_dm in favor of the DRM variable refresh properties.
The AMDGPU connector properties freesync_capable and freesync_enabled
are mostly direct mappings to the DRM variable_refresh_capable and
variable_refresh_enabled.
The AMD
Variable refresh rate algorithms have typically been enabled only
when the display is covered by a single source of content.
This patch introduces a new default CRTC property that helps
hint to the driver when the CRTC composition is suitable for variable
refresh rate algorithms. Userspace can set
Modern display hardware is capable of supporting variable refresh rates
and adaptive sync technologies. The properties for querying and
controlling these features should be exposed on the DRM connector.
This patch introduces two new properties for variable refresh rate
support:
- variable_refresh
These patches are part of a proposed new interface for supporting variable
refresh rate via DRM properties.
=== Changes from v1 ===
For drm:
* The variable_refresh_capable property is now flagged as
DRM_MODE_PROP_IMMUTABLE
For drm/gpu/amd/display:
* Patches no longer pull in IOCTL/FreeSync r
Am 24.09.2018 um 17:32 schrieb Andrey Grodzovsky:
On 09/24/2018 11:19 AM, Christian König wrote:
Thanks.
One more thing which came to my mind is that we might want to print
the warning only when amdgpu_fence_process has actually done some
processing.
Otherwise we could get warnings for l
On Mon, Sep 24, 2018 at 05:16:50PM +0200, Christian König wrote:
> Am 24.09.2018 um 17:03 schrieb Daniel Vetter:
> > On Mon, Sep 24, 2018 at 01:58:12PM +0200, Christian König wrote:
> > > The reservation object shared slot function only allowed to reserve one
> > > slot at a time.
> > >
> > > Imp
On 09/24/2018 11:19 AM, Christian König wrote:
Thanks.
One more thing which came to my mind is that we might want to print
the warning only when amdgpu_fence_process has actually done some
processing.
Otherwise we could get warnings for long running jobs.
Do you mean that you want to kno
Thanks.
One more thing which came to my mind is that we might want to print the
warning only when amdgpu_fence_process has actually done some processing.
Otherwise we could get warnings for long running jobs.
Christian.
Am 24.09.2018 um 17:14 schrieb Andrey Grodzovsky:
P.S I pushed it.
T
Am 24.09.2018 um 17:03 schrieb Daniel Vetter:
On Mon, Sep 24, 2018 at 01:58:12PM +0200, Christian König wrote:
The reservation object shared slot function only allowed to reserve one slot at
a time.
Improve that and allow to reserve multiple slots to support atomically
submission to multiple
P.S I pushed it.
Thanks,
Andrey
On 09/24/2018 11:13 AM, Andrey Grodzovsky wrote:
Reviewed-and-Tested-by: Andrey Grodzovsky
Andrey
On 09/24/2018 10:31 AM, Deucher, Alexander wrote:
Acked-by: Alex Deucher
*From:
Reviewed-and-Tested-by: Andrey Grodzovsky
Andrey
On 09/24/2018 10:31 AM, Deucher, Alexander wrote:
Acked-by: Alex Deucher
*From:* amd-gfx on behalf of
Christian König
*Sent:* Monday, September 24, 2018 8:10:22 AM
On Mon, Sep 24, 2018 at 01:58:12PM +0200, Christian König wrote:
> The reservation object shared slot function only allowed to reserve one slot
> at a time.
>
> Improve that and allow to reserve multiple slots to support atomically
> submission to multiple engines.
I think you can do this alrea
Acked-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Monday, September 24, 2018 8:10:22 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: Deactivate SW interrupt fallback in
amdgpu_fence_process v2
From: Andrey Grodzovsky
On 2018-09-24 1:58 p.m., Christian König wrote:
> And drop the now superflous extra reservations.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
> 2 files changed, 5 insertions(+), 13 dele
The shortlog should say "allow reserving more than one shared fence
slot", same as patch 2.
On 2018-09-24 1:58 p.m., Christian König wrote:
> Let's support simultaneous submissions to multiple engines.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/ttm/ttm_execbuf_util.c | 6 -
[Why]
In multi-monitor scenario, if first crtc's flip done event occurs delayed
(but within timeout), due to non-blocking design of commit_tail(), there
are more than one commit's scheduled by the time the second crtc's
wait_for_completion_timeout() is called in drm_atomic_helper_wait_for_flip_done
Add a callback to amdgpu_ih_process to remove most of the IV logic.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 24 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 31 ++
The entries are ignored for now, but it at least stops crashing the
hardware when somebody tries to push something to the other IH rings.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 4 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 129 +--
That is superflous here.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 2e87414422f9..e9bf70e2ac51 100644
We always want those to be setup correctly.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 20
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3 +
Calculate all the addresses and pointers in amdgpu_ih.c
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 34 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 23 -
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 -
dri
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/dr
One for the ring buffer and one for the IV handling.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++-
drivers/gpu/drm/amd/amdgpu/cik_ih.c |
Let's start to support multiple rings.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 16 +---
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 16 ++
Everything that isn't related to the IH ring.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h| 22 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 10 -
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 25 +
From: Andrey Grodzovsky
Deactivate SW interrupt fallback when all emited fences are completed.
Also switch interrupt SW fallback message from INFO to WARN.
v2: shorten the warnign message a bit and only re-activate the timer during
processing if it was already activated before.
Signed-off-by: A
And drop the now superflous extra reservations.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
This allows us to drop the extra reserve in TTM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/g
Let's support simultaneous submissions to multiple engines.
Signed-off-by: Christian König
---
drivers/dma-buf/reservation.c| 13 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
drivers/gpu/drm/amd/amdgpu/a
Let's support simultaneous submissions to multiple engines.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_execbuf_util.c | 6 --
include/drm/ttm/ttm_execbuf_util.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c
No need for that any more. Just replace the list when there isn't enough
room any more for the additional fence.
Signed-off-by: Christian König
---
drivers/dma-buf/reservation.c | 178 ++
include/linux/reservation.h | 4 -
2 files changed, 58 insertion
The reservation object shared slot function only allowed to reserve one slot at
a time.
Improve that and allow to reserve multiple slots to support atomically
submission to multiple engines.
Please comment and review,
Christian.
___
amd-gfx mailing l
It is perfectly possible that the BO list is created before the BO is
exported. While at it cleanup setting shared to one instead of true.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 13 ++---
2 file
The driver is now responsible to allocate enough shared slots.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 27 ++-
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 461b31
Am 20.09.2018 um 13:03 schrieb Chunming Zhou:
syncobj wait/signal operation is appending in command submission.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 114 +++--
include/uapi/drm/amdgpu_d
Am 20.09.2018 um 13:03 schrieb Chunming Zhou:
user mode can query timeline payload.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 ++
drivers/gpu/drm/drm_ioctl.c| 2 ++
drivers/gpu/drm/drm_syncobj.c | 53 ++
include/uapi/drm/drm.
Am 24.09.2018 um 04:07 schrieb Huang Rui:
While the apg_end address is 0x, if add 1 with it, the value will be
overflow and roll back to 0. So when 0 is written to
mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And
so any access to vram will trigger a page fa
50 matches
Mail list logo