On Wed, Sep 12, 2018 at 10:54:38AM +0200, Christian König wrote:
> Both a leaf as well as dfs iterator to walk over all the PDs/PTs.
>
> v2: update comments and fix for_each_amdgpu_vm_pt_dfs_safe
>
> Signed-off-by: Christian König
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd
Am 13.09.2018 um 04:15 schrieb zhoucm1:
On 2018年09月12日 19:05, Christian König wrote:
[SNIP]
+static void drm_syncobj_find_signal_pt_for_wait_pt(struct
drm_syncobj *syncobj,
+ struct drm_syncobj_wait_pt *wait_pt)
+{
That whole approach still looks horrible complica
I think I'm missing something. I thought the whole discussion we were having
about tracking current and future locations of page tables was about swapping
out page tables that are managed by HMM. We currently do swap out page tables
that don't have fence on them and that are not managed by HMM.
On 09/12/2018 04:54 PM, Christian König wrote:
Both a leaf as well as dfs iterator to walk over all the PDs/PTs. v2:
update comments and fix for_each_amdgpu_vm_pt_dfs_safe Signed-off-by:
Christian König
Reviewed-by: Junwei Zhang
--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 224
++
On 09/12/2018 04:54 PM, Christian König wrote:
Less code and easier to maintain.
v2: rename the function as well
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 32
1 file changed, 8 insertions(+), 24
On 2018年09月12日 19:05, Christian König wrote:
Am 12.09.2018 um 12:20 schrieb zhoucm1:
[SNIP]
Drop the term semaphore here, better use syncobj.
This is from VK_KHR_timeline_semaphore extension describe, not my
invention, I just quote it. In kernel side, we call syncobj, in UMD,
they still cal
On 2018-09-12 09:55 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling wrote:
>> From: Emily Deng
>>
>> Correct the format
>>
>> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
>> same setting with host driver, or it will happen conflicts.
>>
>> Signe
On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling wrote:
>
> From: Emily Deng
>
> Correct the format
>
> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
> same setting with host driver, or it will happen conflicts.
>
> Signed-off-by: Emily Deng
> Acked-by: Alex Deucher
> Si
From: Shaoyun Liu
Vega20 supports 8 SDMA queues per engine
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 -
drivers/gpu/drm/amd/amdkfd/kfd_device_que
From: Shaoyun Liu
Add Vega20 support in amdgpu_amdkfd_device_probe.
Signed-off-by: Shaoyun Liu
Acked-by: Alex Deucher
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
1 file changed, 1 insertion(+)
From: Emily Deng
Correct the format
For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.
Signed-off-by: Emily Deng
Acked-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
From: Shaoyun Liu
amdgpu_gpuvm_get_process_page_dir should return the page table address
in the format expected by the pm4_map_process packet for all ASIC
generations.
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
driver
This patch series is based on amd-staging-drm-next + the patch series
"KFD upstreaming September 2018".
Emily Deng (1):
drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of
Vega10
Shaoyun Liu (5):
drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
drm/amdkfd
From: Shaoyun Liu
Add Vega20 device IDs, device info and enable it in KFD.
Signed-off-by: Shaoyun Liu
Acked-by: Alex Deucher
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/
From: Shaoyun Liu
Change doorbell assignments to allow routing doorbells for 8 user
mode SDMA queues per engine.
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14
From: Eric Huang
Add the flags of properties according to Asic type and pcie
capabilities.
Signed-off-by: Eric Huang
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_t
struct vi_sdma_mqd is defined in vi_structs.h.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index f58
This patch series is based on amd-staging-drm-next.
Patches 1-3 are important fixes that would be good to be included in
drm-fixes for 4.19.
Patches 3-8 are small feature enhancements.
Patch 9 is random cleanup.
I'll send a separate patch series that adds Vega20 support to KFD on top of
this.
From: Jay Cornwall
Wavefront context save data is of interest to userspace clients for
debugging static wavefront state. The MQD contains two parameters
required to parse the control stack and the control stack itself
is kept in the MQD from gfx9 onwards.
Add an ioctl to fetch the context save a
From: Emily Deng
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV
environment, it will let compute ring IB test fail.
Signed-off-by: Emily Deng
Reviewed-by: Shaoyun.liu
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 16
1
From: Harish Kasiviswanathan
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in
response to bad opcodes in a CP queue.
Signed-off-by: Harish Kasiviswanathan
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 3 ++-
1 file changed, 2 inser
Also save the version in struct kfd_dev so we only need to query
it once.
Signed-off-by: Philip Yang
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 +++---
3
From: Yong Zhao
CWSR fails on Raven if the control stack is MTYPE_UC, which is used
for regular GART mappings. As a workaround we map it using MTYPE_NC.
The MEC firmware expects the control stack at one page offset from the
start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU
ad
From: Yong Zhao
Because CRAT_CU_FLAGS_IOMMU_PRESENT was not set in some BIOS crat, we
need to workaround this.
For future compatibility, we also overwrite the bit in capability according
to the value of needs_iommu_device.
Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
Signed-off-by: Fe
From: Amber Lin
A wrong register bit was examinated for checking SDMA status so it reports
false failures. This typo only appears on gfx_v7. gfx_v8 checks the correct
bit.
Signed-off-by: Amber Lin
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu
On Wed, Sep 12, 2018 at 1:24 PM Richard Smith wrote:
>
> On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
> wrote:
>>
>> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
>> wrote:
>> >
>> > Clang warns if there are missing braces around a subobject
>> > initializer.
>> >
>> > drivers/gpu/drm/
The series is Reviewed-by: Felix Kuehling
On 2018-09-12 04:54 AM, Christian König wrote:
> Both a leaf as well as dfs iterator to walk over all the PDs/PTs.
>
> v2: update comments and fix for_each_amdgpu_vm_pt_dfs_safe
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdg
Is the small reduction in memory footprint (8 bytes per page table on a
64-bit kernel) really worth the trouble of open-coding a single-linked
list implementation? I guess this change makes a bigger difference for
2-level page tables than it does for 4-level, because the amdgpu_vm_pt
array is alloc
Hey,
I had some time to bisect again tonight and it seems
018d82e5f02ef3583411bcaa4e00c69786f46f19
got back in again through:
# first bad commit: [d98c71dadc2d0debdb80beb5a478baf1e6f98758] Merge
drm-upstream/drm-next into drm-misc-next
/ Daniel
On Wed, 29 Aug 2018 at 16:02, Daniel Andersson wrot
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback. Enable CONFIG_HMM and CONFIG_HMM_MIRROR as a dependency in
DRM_AMDGPU_USERPTR Kconfig.
It supports both KFD userptr and gfx userptr paths.
This depends on several HMM patchset from Jérôme Glisse queued for
upstream.
On Wed, Sep 12, 2018 at 4:44 PM Harry Wentland wrote:
>
>
>
> On 2018-09-12 04:10 PM, Alex Deucher wrote:
> > On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
> >>
> >> From: Bhawanpreet Lakha
> >>
> >> Add Raven2 definitions in the dc code
> >>
> >> Signed-off-by: Bhawanpreet Lakha
> >> Rev
Problem:
After GPU reset pflip completion IRQ is disabled and hence
any subsequent mode set or plane update leads to hang.
Fix:
Unless acrtc->otg_inst is initialized to -1 during display
block initializtion then durng resume from GPU reset
amdgpu_irq_gpu_reset_resume_helper will override CRTC 0 pf
On 2018-09-12 04:10 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
>>
>> From: Bhawanpreet Lakha
>>
>> Add Raven2 definitions in the dc code
>>
>> Signed-off-by: Bhawanpreet Lakha
>> Reviewed-by: Harry Wentland
>> Reviewed-by: Huang Rui
>> Acked-by: Alex Deuche
On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
wrote:
> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> wrote:
> >
> > Clang warns if there are missing braces around a subobject
> > initializer.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > around init
On Wed, Sep 12, 2018 at 01:24:34PM -0700, Richard Smith wrote:
> On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
> wrote:
>
> > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns if there are missing braces around a subobject
> > > initializer.
> > >
> > > dri
From: Marek Olšák
I've chosen to do it like this because it's easy and allows an arbitrary
number of processes.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 10 --
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
On 2018-09-12 04:55 AM, Christian König wrote:
> We can get that just by casting tv.bo.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 42 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
On Wed, Sep 5, 2018 at 12:24 PM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> Fixes server reset.
>
> Pointed out by clang:
>
> ../../src/radeon_kms.c:2721:9: warning: variable 'pitch' is used
> uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
> if (!info->front_
Clang warns if there are missing braces around a subobject
initializer. Adding these braces only initializes the first
subobject; an empty set of braces initializes the structure
and all of its subobjects.
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
around initialization
On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
>
> From: Bhawanpreet Lakha
>
> Add Raven2 definitions in the dc code
>
> Signed-off-by: Bhawanpreet Lakha
> Reviewed-by: Harry Wentland
> Reviewed-by: Huang Rui
> Acked-by: Alex Deucher Signed-off-by: Alex Deucher
> ---
> .../amd/display/
On Wed, Sep 12, 2018 at 02:44:34PM -0400, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 2:40 PM Nathan Chancellor
> wrote:
> >
> > On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> > > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > > wrote:
> > > >
> > > > Clang warns if
On Wed, Sep 12, 2018 at 3:25 PM Christian König
wrote:
>
> While cutting the lists we sometimes accidentally added a list_head from
> the stack to the LRUs, effectively corrupting the list.
>
> Remove the list cutting and use explicit list manipulation instead.
>
> Signed-off-by: Christian König
From: Huang Rui
Raven2 has a HW issue that it is unable to use the vram which is out of
MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system
aperture high address to get rid of the VM fault and hardware hang.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewe
From: Huang Rui
Raven2 does not enable all of the CG flags that raven1 does.
v2: rebase (Alex)
Signed-off-by: Huang Rui
Reviewed-by: Feifei Xu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 57 +-
1 file changed, 37 insertions(+), 20
From: Evan Quan
Check the raven2 version number as well.
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/driver
From: Evan Quan
Since the clock value there may be like 2 10Khz.
v2: rebase (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 --
1 file changed, 8 insertions(+
From: Bhawanpreet Lakha
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
---
.../amd/display/dc/bios/command_table_helper2.c| 5 +++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
From: Evan Quan
It's not supported yet.
v2: rebase (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr
From: Feifei Xu
Golden register settings from the hw team.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/
It's different from raven1.
Signed-off-by: Huang Rui
Reviewed-by: Feifei Xu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
From: Feifei Xu
Specify raven2 vcn firmware on amdgpu_vce_sw_init.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/a
From: Feifei Xu
use raven2 sdma firmware.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/d
From: Feifei Xu
Add gpu_info firmware for raven2.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
From: Likun Gao
Modified for using raven2_asd.bin to replace raven_asd.bin for raven2
Signed-off-by: Likun Gao
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Huang Rui
Rev id is used for identifying Raven2 series of chips. So we would better to
initialize it at first.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +++--
1 file
From: Feifei Xu
Golden register settings from the hw team.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/
From: Feifei Xu
use raven2 gfx firmware.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/
From: Bhawanpreet Lakha
Add DRM_AMD_DC_DCN1_01 config flag for Raven2
v2: Make DC select DRM_AMD_DC_DCN1_01 (Alex)
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 6 ++
1 file changed,
Raven2 is a new Raven APU.
Alex Deucher (1):
drm/amdgpu: set external rev id for raven2
Bhawanpreet Lakha (2):
drm/amd/display: Add Raven2 definitions in dc
drm/amd/display: Add DC config flag for Raven2 (v2)
Evan Quan (3):
drm/amd/powerplay: update smu10_verify_smc_interface() to be rav
While cutting the lists we sometimes accidentally added a list_head from
the stack to the LRUs, effectively corrupting the list.
Remove the list cutting and use explicit list manipulation instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 51 ++---
Yes, at least Jeromes original patch for amdgpu already did this.
Christian.
Am 12.09.2018 um 20:58 schrieb Felix Kuehling:
Should we add HMM as a dependency in the Kconfig? At least for KFD
functionality we depend on userptrs.
Regards,
Felix
On 2018-09-12 03:15 AM, Christian König wrote:
Should we add HMM as a dependency in the Kconfig? At least for KFD
functionality we depend on userptrs.
Regards,
Felix
On 2018-09-12 03:15 AM, Christian König wrote:
> Am 11.09.2018 um 21:31 schrieb Philip Yang:
>> Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
>> call
Rather than checking the asic type, check whether the UVD
or VCE IP blocks exist. This way we don't have to update
the check with new asics that use VCN.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Likun Gao
Add sdma support to picasso
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
From: Huang Rui
This patch is to add new pci device for raven series.
Signed-off-by: Huang Rui
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd
From: Kenneth Feng
Remove some functions due to the design change.
All the mmhub power gating sequence is moved to
smu fw.Driver sends the message to enable mmhub
powergating.We can also skip the fw version check
since the old fw version is in a very early stage
and we don't use that fw for relea
From: Kenneth Feng
enable gfxoff in non-sriov and stutter mode by default
Signed-off-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff
From: Huang Rui
Add PCO IPs.
V2: enable VCN as well
Signed-off-by: Huang Rui
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amd
From: Likun Gao
Add gfx support to picasso
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/driv
From: Kenneth Feng
Add pg support for gfxoff.
Signed-off-by: Kenneth Feng
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/am
From: Likun Gao
Add picasso for amdgpu kms
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
From: Kenneth Feng
Enable SDMA power gating
Signed-off-by: Kenneth Feng
Acked-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
From: Kenneth Feng
enable vcn pg
Signed-off-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 53159f1d7a39..7
From: Likun Gao
Add support for picasso to the display manager.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
This patch set adds support for Picasso. Picasso is a new APU
similar to raven.
Alex Deucher (1):
drm/amdgpu: use IP presence to free uvd and vce handles
Huang Rui (2):
drm/amdgpu: add ip blocks for picasso (v2)
drm/amdgpu: add new raven series device
Kenneth Feng (5):
drm/amdgpu: Add p
From: Likun Gao
Add picasso to amd_asic_type enum and amdgpu_asic_name[].
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files cha
From: Likun Gao
Treat it the same as raven for now.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/d
From: Likun Gao
Same as raven for now.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 4
2 files changed, 5 insertions(+)
diff --git a/dr
From: Likun Gao
Same as raven.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd
From: Likun Gao
Add vm support for picasso.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amd
From: Likun Gao
Add vcn support for picasso.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/
From: Likun Gao
Add the IP blocks, clock and powergating flags, and common clockgating support.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/soc15
From: Likun Gao
add powerplay support for picasso, treat it the same as raven now.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/hwmgr/proce
From: Likun Gao
Same as raven.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm
On Wed, Sep 12, 2018 at 2:40 PM Nathan Chancellor
wrote:
>
> On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns if there are missing braces around a subobject
> > > initializer.
> > >
> > > dri
On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> wrote:
> >
> > Clang warns if there are missing braces around a subobject
> > initializer.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > arou
On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
wrote:
>
> Clang warns if there are missing braces around a subobject
> initializer.
>
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> around initialization of subobject [-Wmissing-braces]
> struct amdgpu_
On Wed, Sep 12, 2018 at 05:08:52PM +0200, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architect
On 09/12/2018 12:22 PM, Michel Dänzer wrote:
On 2018-09-12 2:48 p.m., Kazlauskas, Nicholas wrote:
On 09/12/2018 04:13 AM, Michel Dänzer wrote:
On 2018-09-11 6:18 p.m., Nicholas Kazlauskas wrote:
These patches are part of a proposed new interface for supporting
variable refresh rate via DRM pro
On 2018-09-12 2:48 p.m., Kazlauskas, Nicholas wrote:
> On 09/12/2018 04:13 AM, Michel Dänzer wrote:
>> On 2018-09-11 6:18 p.m., Nicholas Kazlauskas wrote:
>>> These patches are part of a proposed new interface for supporting
>>> variable refresh rate via DRM properties.
>>>
>>> https://patchwork.fr
Am 12.09.2018 um 18:10 schrieb Michel Dänzer:
From: Michel Dänzer
The entries were only initialized once in amdgpu_sa_bo_new. If a fence
wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then
got signalled before a later amdgpu_sa_bo_next_hole call, it could
destroy the fence b
From: Michel Dänzer
The entries were only initialized once in amdgpu_sa_bo_new. If a fence
wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then
got signalled before a later amdgpu_sa_bo_next_hole call, it could
destroy the fence but leave its pointer in the array, resulting in
Em Wed, 12 Sep 2018 17:08:52 +0200
Arnd Bergmann escreveu:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architectur
Am 12.09.2018 um 17:29 schrieb Felix Kuehling:
On 2018-09-12 02:56 AM, Christian König wrote:
Am 12.09.2018 um 00:00 schrieb Felix Kuehling:
On 2018-09-11 03:19 AM, Christian König wrote:
Hi Felix,
let me try to explain the problem on an example:
1. We have a running job which needs recovera
On Wed, Sep 12, 2018 at 05:08:52PM +0200, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architect
On Wed, Sep 12, 2018 at 5:08 PM, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture, wher
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of David
Francis
Sent: Wednesday, September 12, 2018 10:34:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Francis, David
Subject: [PATCH v2 0/3] Add DMCU fw loading on raven
v2: measure intv offset in
Hi Dave,
A few fixes for 4.19:
- Fix a small memory leak
- SR-IOV reset fix
- Fix locking in MMU-notifier error path
- Updated SDMA golden settings to fix a PRT hang
The following changes since commit 67c6ed7cf9ebe53815f15bfdeb49ad91801c2235:
Merge tag 'drm-intel-fixes-2018-09-05' of
git://an
On 2018-09-12 02:56 AM, Christian König wrote:
> Am 12.09.2018 um 00:00 schrieb Felix Kuehling:
>> On 2018-09-11 03:19 AM, Christian König wrote:
>>> Hi Felix,
>>>
>>> let me try to explain the problem on an example:
>>>
>>> 1. We have a running job which needs recoverable page faults for
>>> acces
The .ioctl and .compat_ioctl file operations have the same prototype so
they can both point to the same function, which works great almost all
the time when all the commands are compatible.
One exception is the s390 architecture, where a compat pointer is only
31 bit wide, and converting it into a
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