On 2017-11-28 04:52 AM, Christian König wrote:
> Am 28.11.2017 um 00:29 schrieb Felix Kuehling:
>> Use a reference counter instead of a lock to prevent process
>> destruction while functions running out of process context are using
>> the kfd_process structure. In many cases these functions don't
On 12/01/2017 02:59 PM, Christian König wrote:
Am 01.12.2017 um 20:39 schrieb Andrey Grodzovsky:
Instead mark fence as explicit in it's amdgpu_sync_entry.
v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +--
drivers/gpu/drm/amd/amdgpu/
Please ignore this change , forgot to include uvd related changes as suggested
.
Regards
Shaoayun.liu
-Original Message-
From: Liu, Shaoyun
Sent: Friday, December 01, 2017 2:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OF
Am 01.12.2017 um 20:39 schrieb Andrey Grodzovsky:
Instead mark fence as explicit in it's amdgpu_sync_entry.
v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +--
drivers/gpu/drm/amd/amdgpu/
Thanks Alex. The series is Acked-by: Felix Kuehling
On 2017-11-30 09:30 PM, Alex Deucher wrote:
> Was missing license text.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/acp/Makefile | 21
> drivers/gpu/drm/amd/amdgpu/Makefile
Instead mark fence as explicit in it's amdgpu_sync_entry.
v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/a
On 2017-11-30 06:51 PM, Jan Vesely wrote:
>
> It's not a userspace queue that stops. I'm using kernel dbgdev to issue
> wave_resume commands. (waves are halted after executing
> s_sendmsg_halt).
> I bumped KFD_KERNEL_QUEUE_SIZE to 16KB to make sure all 320 resume
> commads fit (otherwise I get spu
Please ignore this patch, there is a bug in this patch which I will fix
and resend the patch soon.
Thanks,
Andrey
On 12/01/2017 01:59 PM, Andrey Grodzovsky wrote:
Instead mark fence as explicit in it's amdgpu_sync_entry.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amd
On 2017-12-01 11:56 AM, Michel Dänzer wrote:
From: Michel Dänzer
The first two patches are preparatory for patch 3, which is the meat of
the series.
Michel Dänzer (3):
amdgpu: Clean up amdgpu_parse_asic_ids error handling
amdgpu: Simplify error handling in parse_one_line
amdgpu: Only
Instead mark fence as explicit in it's amdgpu_sync_entry.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
To answer your questions about decoding MQDs, take a look at struct
vi_mqd in drivers/gpu/drm/amd/include/vi_structs.h. What you're looking
at is a binary dump of that structure, one per queue.
The information in the MQD may not always be up to date, because the MQD
represents an unmapped queue. I
DIQ is the debug interface queue. Are you running a GPU debugger?
Otherwise I would not expect to even see a DIQ.
Are you not seeing any compute queues in mqds? If there are no compute
queues in mqds, that means your queue has been destroyed. That would
explain why the read pointer is not advancin
From: Michel Dänzer
* Move empty/commented line check before the strdup and return -EAGAIN
directly
* Initialize r = -EAGAIN and remove redundant assignments
* Set r = -ENOMEM if last strdup fails, and remove redundant goto
Signed-off-by: Michel Dänzer
---
amdgpu/amdgpu_asic_id.c | 45 ++
From: Michel Dänzer
The first two patches are preparatory for patch 3, which is the meat of
the series.
Michel Dänzer (3):
amdgpu: Clean up amdgpu_parse_asic_ids error handling
amdgpu: Simplify error handling in parse_one_line
amdgpu: Only remember the device's marketing name
amdgpu/Andr
From: Michel Dänzer
* Move error message printing into amdgpu_parse_asic_ids and make it
return void
* Print only "Invalid format" error message if parse_one_line returns
-EINVAL
* Use strerror instead of printing the (negative) error code in hex
Signed-off-by: Michel Dänzer
---
amdgpu/amd
From: Michel Dänzer
There's no point in keeping around the full table of marketing names,
when amdgpu_get_marketing_name only ever returns the device's marketing
name.
Signed-off-by: Michel Dänzer
---
amdgpu/Android.mk| 3 +-
amdgpu/Makefile.am | 5 +--
amdgpu/amdgpu_asic_id.c
On 2017-12-01 03:31 AM, Christian König wrote:
> Am 01.12.2017 um 03:30 schrieb Alex Deucher:
>> Was missing license text.
>>
>> Signed-off-by: Alex Deucher
>
> We need copyright text on the Makefiles as well? Well, yeah makes sense.
> Going to keep that in mind.
>
Yes, this is something I nev
Am Freitag, den 01.12.2017, 16:55 +0100 schrieb Christian König:
> Am 01.12.2017 um 16:28 schrieb Lucas Stach:
> > Hi all,
> >
> > so this is the first step to make the marvelous AMDGPU scheduler
> > useable
> > for other drivers. I have a (mostly) working prototype of Etnaviv
> > using
> > the sc
Am 01.12.2017 um 16:28 schrieb Lucas Stach:
Hi all,
so this is the first step to make the marvelous AMDGPU scheduler useable
for other drivers. I have a (mostly) working prototype of Etnaviv using
the scheduler, but those patches need to keep baking for a while.
I'm sending this out as I want t
This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
forward rename with no code changes.
One notable exception is the function to_drm_sched_fence(), which is no
longer a inline header function to avoid th
Hi all,
so this is the first step to make the marvelous AMDGPU scheduler useable
for other drivers. I have a (mostly) working prototype of Etnaviv using
the scheduler, but those patches need to keep baking for a while.
I'm sending this out as I want to avoid rebasing this change too much
and don'
This is the only part of the scheduler which must not be called from
different drivers. Move it to module init/exit so it is done a single
time when loading the scheduler.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
drivers/gpu/drm/scheduler/sched_fence.
On Fri, Dec 01, 2017 at 08:19:16AM +0100, Daniel Vetter wrote:
> On Thu, Nov 30, 2017 at 11:49:53PM +, Sudip Mukherjee wrote:
> > Hi Daniel,
> >
> >
> >
> > > > > >
> > > > > > Greg?
> > > > >
> > > > > Yes, if no one is working to get it out of staging, that means no one
> > > > > cares a
From: amd-gfx on behalf of Michel
Dänzer
Sent: Friday, December 1, 2017 9:56 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati] Add radeon_dirty_src_drawable helper
From: Michel Dänzer
Allows tidying up radeon_dirty_src_equals and redisplay_d
From: Michel Dänzer
Allows tidying up radeon_dirty_src_equals and redisplay_dirty slightly.
(Cherry picked from amdgpu commit 1d65ac395971571094df21ca0408d5972c6b56ec)
Signed-off-by: Michel Dänzer
---
src/radeon.h | 18 +-
src/radeon_kms.c | 7 ++-
2 files changed, 11
On 30 November 2017 at 23:49, Sudip Mukherjee
wrote:
> Hi Daniel,
>
> On Wed, Nov 29, 2017 at 10:56:34AM +0100, Daniel Vetter wrote:
>> On Tue, Nov 28, 2017 at 12:30:30PM +, Sudip Mukherjee wrote:
>> > On Tue, Nov 28, 2017 at 12:32:38PM +0100, Greg KH wrote:
>> > > On Tue, Nov 28, 2017 at 11:2
From: Dmytro Laktyushkin
This reverts commit 978482d0de86 Revert noisy assert messages
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/driv
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +++-
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 +--
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drive
This has proven helpful on other OSes to give a quick state of the
DC driver when a bug is reported.
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h| 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 -
drivers/gpu/drm/amd/display/dc/inc/core_types.h
From: Eric Bernstein
Move OPP initialization of mpc tree parameters to hw_init function.
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 939fa6f85826
From: Yongqiang Sun
It may take over 200ms for wait hpd ready. To optimize the resume time,
we can power on eDP in init_hw, wait for hpd ready when doing link
training.
also create separate eDP enable function to make sure eDP is powered up
before doing and DPCD access, as HPD low will result in
From: Eric Bernstein
Use REG_UPDATE instead of REG_SET for programming MPC out mux.
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/
Signed-off-by: Harry Wentland
Reviewed-by: Jordan Lazare
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/TODO | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/TODO b/drivers/gpu/drm/amd/display/TODO
index 46464678f2b3..357d59648401 100644
--- a/drivers
From: Tony Cheng
REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 +++--
1 file changed
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 24 ++
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 14 ++---
drivers/gpu/drm/amd/display/in
From: Vitaly Prosyak
When convert from fixed31_32 to other fixed point
format use math operation round instead of floor.
Signed-off-by: Vitaly Prosyak
Reviewed-by: Roman Li
Reviewed-by: Krunoslav Kovac
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/conversion.c | 2 +-
1
* Bunch of fixes for DCN BW
* DCN programming sequence optimizations
* Leave Freesync disabled unless usermode turns it on
* Print DC version at initialization
Dmytro Laktyushkin (4):
drm/amd/display: set chroma taps to 1 when not scaling
drm/amd/display: Add dppclk to dcn_bw_clocks
drm/
We already check this a couple lines earlier.
Signed-off-by: Harry Wentland
Reviewed-by: Jordan Lazare
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/d
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Eric Bernstein
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
b/drivers/gpu/drm/amd/display/dc/d
Signed-off-by: Harry Wentland
Reviewed-by: Jordan Lazare
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/Makefile | 2 +-
.../gpu/drm/amd/display/dc/basics/grph_object_id.c | 75 --
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 46 +
From: Eric Yang
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Reviewed-by: Andrew Jiang
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/driver
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 +-
.../amd/display/dc/dcn10/dcn10_timing_generator.c | 316 ++--
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 9 -
2 files changed, 13 insertions(+), 5 deletions(-)
di
From: Vitaly Prosyak
Also handle fixpoint y values for CM curves
Signed-off-by: Vitaly Prosyak
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h| 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 6 --
drivers/gpu/dr
From: "Leo (Sunpeng) Li"
Freesync properties are being set to the 'freesync_capable' flag,
which will enable freesync on all freesync capable displays. Don't do
this, since freesync should be disabled by default regardless of
capabilities.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Harry Went
Am 01.12.2017 um 03:30 schrieb Alex Deucher:
Was missing license text.
Signed-off-by: Alex Deucher
We need copyright text on the Makefiles as well? Well, yeah makes sense.
Going to keep that in mind.
Acked-by: Christian König for both patches.
Regards,
Christian.
---
drivers/gpu/drm/
Am 01.12.2017 um 01:23 schrieb Lyude Paul:
I haven't gone to see where it started, but as of late a good number of
pretty nasty deadlock issues have appeared with the kernel. Easy
reproduction recipe on a laptop with i915/amdgpu prime with lockdep enabled:
DRI_PRIME=1 glxinfo
Acked-by: Christi
Am 30.11.2017 um 23:53 schrieb Shaoyun Liu:
Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
Signed-off-by: Shaoyun Liu
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 126 ++
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ++-
static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_UVD,
.align_mask = 0xf,
.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
That one is trivial. There is an .insert_nop callback a bit further down:
.insert_nop = amdgpu_ring_
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