By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
drivers/gpu/drm/
On Tue, Apr 4, 2017 at 11:16 PM, Alex Deucher wrote:
> On Tue, Apr 4, 2017 at 6:05 PM, Andres Rodriguez wrote:
>> Previously the queue/pipe split with kfd operated with pipe
>> granularity. This patch allows amdgpu to take ownership of an arbitrary
>> set of queues.
>>
>> It also consolidates the
Signed-off-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 57 --
1 file changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
b/drivers/gpu/drm/amd/powerplay/inc/smu9_dri
On Tue, Apr 4, 2017 at 6:05 PM, Andres Rodriguez wrote:
> Previously the queue/pipe split with kfd operated with pipe
> granularity. This patch allows amdgpu to take ownership of an arbitrary
> set of queues.
>
> It also consolidates the last few magic numbers in the compute
> initialization proce
On Tue, Apr 4, 2017 at 11:06 PM, Alex Deucher wrote:
> On Tue, Apr 4, 2017 at 6:05 PM, Andres Rodriguez wrote:
>> Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's
>> ring ids from the kernel's ring ids.
>>
>> The queue manager maintains a per-file descriptor map of user ring i
On Tue, Apr 4, 2017 at 6:05 PM, Andres Rodriguez wrote:
> Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's
> ring ids from the kernel's ring ids.
>
> The queue manager maintains a per-file descriptor map of user ring ids
> to amdgpu_ring pointers. Once a map is created it is pe
On 04/05/2017 10:27 AM, Alex Deucher wrote:
On Tue, Apr 4, 2017 at 10:11 PM, Zhang, Jerry (Junwei)
wrote:
On 04/04/2017 03:34 AM, Deucher, Alexander wrote:
-Original Message-
From: Junwei Zhang [mailto:jerry.zh...@amd.com]
Sent: Friday, March 31, 2017 10:44 PM
To: Deucher, Alexander;
On 04/04/2017 03:23 AM, Alex Deucher wrote:
On Mon, Apr 3, 2017 at 8:39 AM, Christian König wrote:
From: Christian König
Match our defines with what the hw uses.
Signed-off-by: Christian König
Patches 1-4, 6-7:
Reviewed-by: Alex Deucher
With the Alex's comments.
Patches 1~7:
Reviewed-b
On Tue, Apr 4, 2017 at 10:11 PM, Zhang, Jerry (Junwei)
wrote:
> On 04/04/2017 03:34 AM, Deucher, Alexander wrote:
>>>
>>> -Original Message-
>>> From: Junwei Zhang [mailto:jerry.zh...@amd.com]
>>> Sent: Friday, March 31, 2017 10:44 PM
>>> To: Deucher, Alexander; Koenig, Christian
>>> Cc: a
On 04/04/2017 03:34 AM, Deucher, Alexander wrote:
-Original Message-
From: Junwei Zhang [mailto:jerry.zh...@amd.com]
Sent: Friday, March 31, 2017 10:44 PM
To: Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Zhang, Jerry
Subject: [PATCH] drm/amdgpu: fix vm size and
On Tue, Apr 4, 2017 at 4:50 PM, Alex Xie wrote:
> Change-Id: I1266af0697146369c9fb720b241bfa02280571c9
> Signed-off-by: Alex Xie
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 --
> 2 files changed, 2 inserti
On 04/04/2017 07:02 AM, Harry Wentland wrote:
Reviewed-by: Harry Wentland
Reviewed-by: Junwei Zhang
On 2017-04-03 04:58 PM, Alex Deucher wrote:
vega10 is the only soc15 asic at the moment so these
warnings are invalid, but add a default case to silence
the warnings.
Fixes: 220ab9bd1ccf:
Change-Id: I1266af0697146369c9fb720b241bfa02280571c9
Signed-off-by: Alex Xie
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 --
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/dr
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.
A new ring function set_priority() c
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over
other queues on the same pipe. Multiple queues on a pipe are timesliced
so this gives us full precedence over other queues.
Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the
wave as follows:
0x2: CS_
The assumption that we are only using the first pipe no longer holds.
Instead, calculate the queue_mask from the queue_bitmap.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 20 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 23 +--
Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's
ring ids from the kernel's ring ids.
The queue manager maintains a per-file descriptor map of user ring ids
to amdgpu_ring pointers. Once a map is created it is permanent (this is
required to maintain FIFO execution guarantees fo
Use an LRU policy to map usermode rings to HW compute queues.
Most compute clients use one queue, and usually the first queue
available. This results in poor pipe/queue work distribution when
multiple compute apps are running. In most cases pipe 0 queue 0 is
the only queue that gets used.
In orde
Spreading the load across multiple SDMA engines can increase memory
transfer performance.
Signed-off-by: Andres Rodriguez
Reviewed-by: Nicolai Hähnle
---
drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/
Depending on usage patterns, the current LRU policy may create a
non-injective mapping between userspace ring ids and kernel rings.
This behaviour is undesired as apps that attempt to fill all HW blocks
would be unable to reach some of them.
This change forces the LRU policy to create bijective m
The MQD structure matches the reg layout. Take advantage of this to
simplify HQD programming.
Note that the ACTIVE field still needs to be programmed last.
Suggested-by: Felix Kuehling
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 44 +--
drivers/g
Tonga based asics may experience hangs when an HQD's EOP parameters
are modified.
Workaround this HW issue by avoiding writes to these registers for
tonga asics.
Based on the following ROCm commit:
2a0fb8 - drm/amdgpu: Synchronize KFD HQD load protocol with CP scheduler
From the ROCm git reposit
Add a new context creation parameter to express a global context priority.
Contexts allocated with AMDGPU_CTX_PRIORITY_HIGH will receive higher
priority to schedule their work than AMDGPU_CTX_PRIORITY_NORMAL
(default) contexts.
v2: Instead of using flags, repurpose __pad
v3: Swap enum values of _
Replace adev->srbm_mutex with a spinlock adev->srbm_lock
v2: rebased on 4.12 and included gfx9
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_
Handle HQD deactivation timeouts instead of ignoring them.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/d
Pipes provide better concurrency than queues, therefore we want to make
sure that apps use queues from different pipes whenever possible.
Optimize for the trivial case where an app will consume rings in order,
therefore we don't want adjacent rings to belong to the same pipe.
Reviewed-by: Edward
This information is already available in adev.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 12 ++--
2 files changed
Update the KGD to KFD interface to allow sharing pipes with queue
granularity instead of pipe granularity.
This allows for more interesting pipe/queue splits.
v2: fix overflow check for res.queue_mask
v3: fix shift overflow when setting res.queue_mask
v4: fix comment in is_pipeline_enabled()
Rev
Instead of taking the first pipe and giving the rest to kfd, take the
first 2 queues of each pipe.
Effectively, amdgpu and amdkfd own the same number of queues. But
because the queues are spread over multiple pipes the hardware will be
able to better handle concurrent compute workloads.
amdgpu go
The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers
are not HQD specific.
They only need to be set once if at least 1 pipe requested doorbell
support.
v2: move doorbell_enable to amdgpu_gfx instead of amdgpu_device
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Si
The current implementation is hardcoded to enable ME1/PIPE0 interrupts
only.
This patch allows amdgpu to enable interrupts for any pipe of ME1.
v2: added gfx9 support
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 48 -
drivers/gpu/dr
Take ownership of pipe initialization away from KFD.
Note that hpd_eop_gpu_addr was already large enough to accomodate all
pipes.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/radeon/cik.c| 27 ++-
Make amdgpu the owner of all per-pipe state of the HQDs.
This change will allow us to split the queues between kfd and amdgpu
with a queue granularity instead of pipe granularity.
This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which
goes unused.
v2: support for gfx9
Reviewed-
Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths.
This removes the last duplicates of this programming sequence.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 51 ++--
The MQD programming sequence currently exists in 3 different places.
Refactor it to absorb all the duplicates.
The success path remains mostly identical except for a slightly
different order in the non-kiq case. This shouldn't matter if the HQD
is disabled.
The error handling paths have been upda
This is the v6 series rebased on the 4.12-wip branch.
It now also includes support for gfx9. I've tried to minimize the changes
to gfx9 since I don't have pre-release hardware. The small changes made can
be found in patches:
patches/0007-drm-amdgpu-take-ownership-of-per-pipe-configuration.patch
pa
Previously the queue/pipe split with kfd operated with pipe
granularity. This patch allows amdgpu to take ownership of an arbitrary
set of queues.
It also consolidates the last few magic numbers in the compute
initialization process into mec_init.
v2: support for gfx9
Reviewed-by: Edward O'Calla
The gfxv7 contains a slightly different version of cik_mqd called
bonaire_mqd. This can introduce subtle bugs if fixes are not applied in
both places.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 135 +
Rename straggler instances of r(adeon)dev to a(mdgpu)dev
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 70 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 14 +++---
drivers
This should be the the linux-firmware repository @ commit
6d3bc8886517d171068fd1263176b8b5c51df204
I reverted back to that firmware since I didn't want to deal with
possible bugs when testing my patches.
Regards,
Andres
On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
wrote:
>> -Original
> -Original Message-
> From: Andres Rodriguez [mailto:andre...@gmail.com]
> Sent: Tuesday, April 04, 2017 4:01 PM
> To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
> g...@lists.freedesktop.org
> Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"
>
> This is my i
This is my info in case that is useful:
umr.version == ea8e49bb15ed
fw.VCE == .feature==0 .firmware==0x34040300
fw.UVD == .feature==0 .firmware==0x014f1000
fw.MC == .feature==0 .firmware==0x
fw.ME == .feature==37 .firmware==0x0094
fw.PFP == .feature==37 .firmw
I'm using the latest from all open (our internal FC24 repo). I'll fetch
the exact later with "umr -c".
Tom
On Tue, Apr 4, 2017 at 3:48 PM Deucher, Alexander
wrote:
> > -Original Message-
> > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Andres Rodriguez
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Andres Rodriguez
> Sent: Tuesday, April 04, 2017 3:39 PM
> To: StDenis, Tom; amd-gfx@lists.freedesktop.org
> Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"
>
>
>
> On
On 2017-04-04 08:27 AM, Tom St Denis wrote:
On 03/04/17 04:25 PM, Andres Rodriguez wrote:
Commit e579f56 results in a KCQ initialization error for polaris10
cards. Providing the full SET_RESOURCES packet instead of the truncated
version fixes the problem.
I think this patch may have been one
On Tue, Apr 4, 2017 at 12:05 PM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>
Had the wrong sense in the loop
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 5191c45ffdf3..0900fdf0651b 100644
--- a/d
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 0900fdf0651b..c3588d1c7cb0 100644
--- a/drivers/gpu/drm/amd/a
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, April 04, 2017 10:20 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: cleanup get_invalidate_req v2
>
> From: Christian König
>
> The t
On Mon, Apr 3, 2017 at 4:24 AM, Christian König wrote:
> Am 03.04.2017 um 05:35 schrieb r...@ubuntu.com:
>>
>> From: Christopher James Halse Rogers
>>
>>
>> BOs shared via dma-buf, either imported or exported, cannot sensibly be
>> migrated to VRAM
>> without breaking the dma-buf sharing. Refuse
This exposes amdgpu_query_sensor_info().
v2: - add amdgpu_query_sensor_info() to the symbols list
Signed-off-by: Samuel Pitoiset
---
amdgpu/amdgpu-symbol-check | 1 +
amdgpu/amdgpu.h| 18 ++
amdgpu/amdgpu_gpu_info.c | 15 +++
3 files changed, 34 insert
On 04/04/2017 03:11 PM, Andreas Boll wrote:
Please make sure that make check still passes with this patch applied.
I guess amdgpu/amdgpu-symbol-check needs to be updated with the new symbol.
Correct. Thanks for noticing this, I will update the patch.
Thanks,
Andreas
2017-04-04 10:37 GMT+0
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, April 04, 2017 10:29 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH] drm/amd/amdgpu: Fix srbm_indexing in init/inactive hqd
> code
>
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5a8e8aea99b9..3571c4895120 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/d
On 04.04.2017 14:48, Christian König wrote:
From: Christian König
This avoids merging them together on page fault.
Signed-off-by: Christian König
Acked-by: Michel Dänzer
Thanks for the explanations in the earlier thread. Both patches are
Reviewed-by: Nicolai Hähnle
---
drivers/gpu/dr
On 04.04.2017 13:33, Christian König wrote:
Am 03.04.2017 um 18:22 schrieb Nicolai Hähnle:
On 31.03.2017 11:47, Christian König wrote:
From: Christian König
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS
instead of a placement limit. That allows us to better handle C
From: Christian König
The two hubs are just instances of the same hardware,
so the register bits are identical.
v2: keep the function pointer
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +-
drivers/gpu/drm/
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, April 04, 2017 9:20 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: cleanup VMHUB bit definitions v2
>
> From: Christian König
>
> The
Am 04.04.2017 um 16:03 schrieb Tom St Denis:
Use new WREG32_FIELD_OFFSET() to clean up code.
Signed-off-by: Tom St Denis
Reviewed-by: Christian König for the whole
series.
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++---
Use new WREG32_FIELD_OFFSET() to clean up code.
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++
2 files changed, 15 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amd
Clean up a toggle with ?:.
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 46e2367405de..5a8e8aea99b9 100644
Swap read/write pattern for WREG32_FIELD()
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3c43c10d0ada..d09
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d09d69b0d096..46e2367405de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx
Swap read/write pattern for WREG32_FIELD()
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 595dc14019dd..3c43c10d0ad
From: Christian König
The two hubs are just instances of the same hardware,
so the register bits are identical.
v2: only remove get_vm_protection_bits for now
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12
Please make sure that make check still passes with this patch applied.
I guess amdgpu/amdgpu-symbol-check needs to be updated with the new symbol.
Thanks,
Andreas
2017-04-04 10:37 GMT+02:00 Samuel Pitoiset :
> This exposes amdgpu_query_sensor_info().
>
> Signed-off-by: Samuel Pitoiset
> ---
> a
Hello Alex Deucher,
The patch d766e6a39338: "drm/amdgpu: switch ih handling to two levels
(v3)" from Mar 29, 2016, leads to the following static checker
warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:319 amdgpu_irq_add_id()
warn: double check that we're allocating correct size:
On 03/04/17 04:25 PM, Andres Rodriguez wrote:
Commit e579f56 results in a KCQ initialization error for polaris10
cards. Providing the full SET_RESOURCES packet instead of the truncated
version fixes the problem.
I think this patch may have been one of the stabs at fixing the KCQ
suspend/resume e
From: Christian König
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS
instead of a placement limit. That allows us to better handle CPU
accessible placements.
v2: prevent virtual BO start address from overflowing
Signed-off-by: Christian König
Acked-by: Michel Dänzer
From: Christian König
This avoids merging them together on page fault.
Signed-off-by: Christian König
Acked-by: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 16
2 files changed, 13 insertions(+), 7 deleti
Am 03.04.2017 um 18:22 schrieb Nicolai Hähnle:
On 31.03.2017 11:47, Christian König wrote:
From: Christian König
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS
instead of a placement limit. That allows us to better handle CPU
accessible placements.
Signed-off-by: Chr
Am 03.04.2017 um 18:25 schrieb Nicolai Hähnle:
On 31.03.2017 11:47, Christian König wrote:
From: Christian König
[SNIP]
mem->bus.offset = mem->start << PAGE_SHIFT;
/* check if it's visible */
if ((mem->bus.offset + mem->bus.size) >
adev->mc.visible_vram_size)
I bel
This exposes amdgpu_query_sensor_info().
Signed-off-by: Samuel Pitoiset
---
amdgpu/amdgpu.h | 18 ++
amdgpu/amdgpu_gpu_info.c | 15 +++
2 files changed, 33 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 6b2ded83..55884b24 100644
--- a/amd
I also haven't tested it on hardware (all my hardware seems to be supported
by amdgpu), but the only times we touch prime_shared_count are:
1) It's set to 1 in radeon_gem_prime_import_sg_table. This shouldn't be
called in the self-import case (and isn't, as far as I can tell), and
2) It's increment
Am 03.04.2017 um 21:31 schrieb Alex Deucher:
On Mon, Apr 3, 2017 at 8:39 AM, Christian König wrote:
From: Christian König
The two hubs are just instances of the same hardware,
so the register bits are identical.
Removing get_vm_protection_bits makes sense since those are limited to
the gmc m
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