Michel Dänzer writes:
> This does mean though that if one has only up to patch 3 applied (e.g.
> during a bisection), one is exposed to the issues fixed by patch 4. So
> maybe patch 4 should be squashed into patch 3.
That's a very important point -- developing code in small logical steps
is a mo
On 19/08/16 11:02 AM, Yu, Qiang wrote:
>
> Each point of the patch set is not broken. Patches are arranged like
> this to show how I do it:
> 1. create a pageflip.c to host common page flip code
> 2. copy amdgpu DDX DRI2 page flip code to modesetting dri2.c
> 3. merge common DRI2 and present page
Hi Emil,
Each point of the patch set is not broken. Patches are arranged like
this to show how I do it:
1. create a pageflip.c to host common page flip code
2. copy amdgpu DDX DRI2 page flip code to modesetting dri2.c
3. merge common DRI2 and present page flip code to pageflip.c
Patch 4 is not a
On 2016年08月18日 19:58, Christian König wrote:
Am 18.08.2016 um 13:17 schrieb Chunming Zhou:
V2:
1. don't directly submit to many jobs at the same time.
2. delete unrelated printk.
Change-Id: I963598ba6eb44bc8620d70e026c0175d1a1de120
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgp
Thanks Michel. I'll update patches in V2 according to your comments.
Regards,
Qiang
From: Michel Dänzer
Sent: Thursday, August 18, 2016 4:18:11 PM
To: Yu, Qiang
Cc: xorg-de...@lists.x.org; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH xserver 0/6] mod
if it is required, we can continue to optimize driver in the future.
Thanks
JimQu
发件人: Zhu, Rex
发送时间: 2016年8月18日 23:24:19
收件人: Christian König; Qu, Jim; amd-gfx@lists.freedesktop.org
主题: Re: [PATCH] drm/amd/amdgpu: S3 resumed failed after 4-5 times loop
d
On Thu, Aug 18, 2016 at 5:59 AM, Christian König
wrote:
> From: Christian König
>
> Adding a BO can make it the insertion point for larger sizes as well.
>
> v2: add a comment about the guard structure.
>
> Signed-off-by: Christian König
> Acked-by: Alex Deucher
Patches 1-4 are:
Reviewed-by: A
On Thu, Aug 18, 2016 at 5:59 AM, Christian König
wrote:
> From: Christian König
>
> Add a flag noting that a BO must be created using linear VRAM
> and set this flag on all in kernel users where appropriate.
>
> Hopefully I haven't missed anything.
>
> Signed-off-by: Christian König
How about i
Am 18.08.2016 um 19:48 schrieb Marek Olšák:
From: Marek Olšák
For profiling.
Signed-off-by: Marek Olšák
Reviewed-by: Christian König .
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
include/uapi/drm/amdgpu_drm.h | 2 ++
3
From: Marek Olšák
For profiling.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
include/uapi/drm/amdgpu_drm.h | 2 ++
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
OK. Feel free to add my Reviewed-by.
On 16-08-18 03:54 AM, Christian König wrote:
>> /* custom LRU management */
>> struct amdgpu_mman_lrulog2_size[AMDGPU_TTM_LRU_SIZE];
>> +struct amdgpu_mman_lruguard;
>> [FK] It would be safer to make the array AMDGPU_TTM
No problem. Unfortunately tail [1]'s are all over the PP code. There access
to some entries (voltage tables for instance) using & on the [1] members. I'll
see if I can gather a list.
Tom
From: amd-gfx on behalf of Christian
König
Sent: Thursday, August
Either way like I said I'm not strongly motivated to change it just
caught my attention.
Well if you have time it would be really cool if you could a) identify
such cases before we run into issues with some gcc versions again and b)
leave the people who added the code and/or are responsible fo
Thanks Alex and Christian,
Yup turns out [0] is not ISO C but [] is (from the googles)
C99 6.7.2.1, §16: As a special case, the last element of a structure with more
than one named member may have an incomplete array type; this is called a
flexible array member.
Either way like I said I'm n
IIRC, zero sized arrays are not technically allowed in C, although gcc allows
them. As I said, some versions of gcc worked, others didn't. I'm not sure
why. Also, my example was slightly wrong. atombios.h uses arrays of size 1,
not 0. So my example should look like:
struct table {
uint1
theory would be better with [0]
It depends on the gcc version you have and well that is probably the
difference between theory and practice.
In theory it should work, but in practice we had tons of problems with that.
Best practice I think is to still calculate the end of the structure
manu
It had to be something more complicated because this demo program
#include
#include
struct one {
char *foo;
int bar[0];
};
struct two {
char *foo;
int bar[1];
};
int main(void)
{
struct one *a = calloc(1, sizeof(struct one) + 4 * sizeof(int));
struct two *b = calloc(1, sizeof(struct two) + 3
The problem we ran into was when we had a struct like this:
struct table {
uint16_t size;
struct element elements[0];
};
and then we would try and index the array:
for (i = 0; i < table->size; i++) {
element = &table->elements[i];
}
element ended up off in the weeds. The only thing tha
do we need to check those status(lmi status,firmware loaded, vce status and
etc) when vce suspend?
it is weird that we didn't implement vce suspend function as hw spec suggested.
Best Regards
Rex
From: amd-gfx on behalf of Christian
König
Sent: Thursday, A
Any modern GCC should support [0] at the tail of a struct. This came up
because when I was reading the code I saw they allocated 7 slots (plus the size
of the struct) but then fill 8 slots. It's just weird [😊]
Using [0] in the struct and allocating for 8 entries makes more sense and is
clear
Am 18.08.2016 um 17:18 schrieb Alex Deucher:
On Thu, Aug 18, 2016 at 9:40 AM, Deucher, Alexander
wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Christian König
Sent: Thursday, August 18, 2016 5:51 AM
To: amd-gfx@lists.freedesktop.org
> -Original Message-
> From: Christian König [mailto:deathsim...@vodafone.de]
> Sent: Thursday, August 18, 2016 11:19 AM
> To: Alex Deucher; Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/radeon: only apply the SS fractional workaround to
> RS[78]80
>
> A
On Thu, Aug 18, 2016 at 9:40 AM, Deucher, Alexander
wrote:
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Christian König
>> Sent: Thursday, August 18, 2016 5:51 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subj
Has a [1] array at the tail which is then kzalloc'ed with N-1 entries.
Shouldn't that just be a [0] with N entries allocated for clarity?
Actually the starting address of a dynamic array should be manually
calculated instead of using [1] or [0].
We had tons of problems with that because some g
Clean up whitespace and formatting.
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 53 +++---
1 file changed, 13 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmg
Tidying up cz_hwmgr.c I noted a couple of things but first is
static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
unsigned long check_feature);
Which will return "true" if the smu call fails or the feature is set.
The structure
struct phm_clock_voltage_dependency_table;
Has a [1] ar
Tidy the print_current_perforce_level() functions as well
as make the Carrizo version a bit more comparable.
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 20 ++--
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 13 -
dr
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Thursday, August 18, 2016 5:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/radeon: only apply the SS fractional workaround to
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Flora Cui
> Sent: Thursday, August 18, 2016 1:37 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cui, Flora
> Subject: [PATCH 2/3] drm/amdgpu: update gart_pin_size only if the bo is
> pined to GT
Am 18.08.2016 um 14:42 schrieb jimqu:
phenomenon: software hang when device resume back, read UVD fence is 0x
and read pcie pid is 0x.
the issue is caused by VCE reset when update cg setting. according to HW
programming
guide, adjust update VCE cg sequence.
Change-Id: I18b12eea21c04
phenomenon: software hang when device resume back, read UVD fence is 0x
and read pcie pid is 0x.
the issue is caused by VCE reset when update cg setting. according to HW
programming
guide, adjust update VCE cg sequence.
Change-Id: I18b12eea21c045908cdd23f93a0b196b87bfed6c
Signed-off-b
Hi Qiang,
On 17 August 2016 at 11:29, Qiang Yu wrote:
> Hi guys,
>
> This patch set is for adding DRI2 page flip support to modesetting
> driver. I mainly take reference of amdgpu DDX and reuse present
> page flip code in the modesetting driver.
>
> Regards,
> Qiang
>
> Qiang Yu (6):
> modesett
Am 18.08.2016 um 13:17 schrieb Chunming Zhou:
V2:
1. don't directly submit to many jobs at the same time.
2. delete unrelated printk.
Change-Id: I963598ba6eb44bc8620d70e026c0175d1a1de120
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 58 +
V2:
1. don't directly submit to many jobs at the same time.
2. delete unrelated printk.
Change-Id: I963598ba6eb44bc8620d70e026c0175d1a1de120
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 58 +-
1 file changed, 57 insertions(+), 1 deleti
From: Christian König
Add a flag noting that a BO must be created using linear VRAM
and set this flag on all in kernel users where appropriate.
Hopefully I haven't missed anything.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu
From: Christian König
Make it more clear what this function does. No intendet functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 112 +++--
1 file changed, 60 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/am
From: Christian König
Adding a BO can make it the insertion point for larger sizes as well.
v2: add a comment about the guard structure.
Signed-off-by: Christian König
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +
From: Christian König
Make it more obvious what we are doing here.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +++--
3 files changed, 13 insertion
From: Christian König
AMDGPU_GEM_CREATE_NO_CPU_ACCESS and AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED are
obviously mutual exclusive. So stop adding a dummy entry without effect when
both are specified.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 +++-
1 fil
Am 18.08.2016 um 11:51 schrieb Christian König:
From: Christian König
Looks like some RV6xx have problems with that.
Signed-off-by: Christian König
Ups, here should be a CC:stable as well.
Christian.
---
drivers/gpu/drm/radeon/atombios_crtc.c | 4 +++-
1 file changed, 3 insertions(+),
From: Christian König
Looks like some RV6xx have problems with that.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/atombios_crtc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
Patch #1-#6 are Reviewed-by: Christian König
A few comments on this one:
Am 18.08.2016 um 07:18 schrieb Chunming Zhou:
Change-Id: I963598ba6eb44bc8620d70e026c0175d1a1de120
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 60 +-
1 fil
Am 18.08.2016 um 11:18 schrieb Flora Cui:
Change-Id: I425a7a8a2126ace85f1ea8a9b91333911692c794
Signed-off-by: Flora Cui
Reviewed-by: Michel Dänzer
Patch is Reviewed-by: Christian König .
A nice cleanup,
Christian.
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 45 +--
dri
Change-Id: I425a7a8a2126ace85f1ea8a9b91333911692c794
Signed-off-by: Flora Cui
Reviewed-by: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 45 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 78 +
Am 18.08.2016 um 10:12 schrieb Flora Cui:
On Thu, Aug 18, 2016 at 10:05:09AM +0200, Christian König wrote:
NAK, we explicitly moved them to amdgpu_gds.h.
In general when some code needs those defines it should include the
appropriate header.
But it would make sense to move them into a (to be c
Am 18.08.2016 um 10:50 schrieb zhoucm1:
On 2016年08月04日 17:58, Christian König wrote:
Am 04.08.2016 um 05:35 schrieb zhoucm1:
On 2016年08月03日 22:01, Christian König wrote:
Well patch #10 is incorrect. The SA BO will be set to NULL by
amdgpu_sa_bo_free(), so it can't be freed twice and so you
In that case my patch should clearly help with that.
Going to release what I have so far today, but looks like I need more
time actually fixing this.
In the meantime you could try the "drm/amdgpu: fix lru size grouping"
patch as well. It fixes a bug related to this and could help as well.
R
On 2016年08月04日 17:58, Christian König wrote:
Am 04.08.2016 um 05:35 schrieb zhoucm1:
On 2016年08月03日 22:01, Christian König wrote:
Well patch #10 is incorrect. The SA BO will be set to NULL by
amdgpu_sa_bo_free(), so it can't be freed twice and so you can't
reference the fence twice.
I see
On 17/08/16 07:29 PM, Qiang Yu wrote:
> Hi guys,
>
> This patch set is for adding DRI2 page flip support to modesetting
> driver. I mainly take reference of amdgpu DDX and reuse present
> page flip code in the modesetting driver.
>
> Regards,
> Qiang
>
> Qiang Yu (6):
> modesetting: make ms_do
NAK to the whole approach.
If we want to share dependencies in the form of fences between devices
and especially processes we must use android fences and the sync file
framework.
Sharing numbers in the form of the IDR is a security nightmare we
already ran into with the GEM flink design.
R
On 17/08/16 07:29 PM, Qiang Yu wrote:
>
> +static void
> +ms_dri2_flip_free(struct ms_crtc_pageflip *flip)
> +{
> +struct ms_flipdata *flipdata = flip->flipdata;
> +
> +free(flip);
> +if (--flipdata->flip_count > 0)
> +return;
> +free(flipdata);
> +}
> +
> +static void
> +m
On Thu, Aug 18, 2016 at 10:05:09AM +0200, Christian König wrote:
> NAK, we explicitly moved them to amdgpu_gds.h.
>
> In general when some code needs those defines it should include the
> appropriate header.
>
> But it would make sense to move them into a (to be created) amdgpu_ttm.h,
> cause tho
Am 18.08.2016 um 07:36 schrieb Flora Cui:
abort if the bo is pined to other domain already
Change-Id: I0e8eb3e0af0fad1edaf647050399e5a36226a5d9
Signed-off-by: Flora Cui
Reviewed-by: Christian König for the whole
series.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +
1 file
NAK, we explicitly moved them to amdgpu_gds.h.
In general when some code needs those defines it should include the
appropriate header.
But it would make sense to move them into a (to be created)
amdgpu_ttm.h, cause those defines are more TTM related than GDS related.
Regards,
Christiuan.
A
This function is never called without a pagelist at the moment.
So there is no justification for this change.
Christian.
Am 18.08.2016 um 04:58 schrieb Flora Cui:
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Change-Id: I69b5c8d86f9e1ed32bb20e899b74ad4146c0e988
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu_cs.c | 36 +---
amdgpu/amdgpu_internal.h | 2 ++
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index
They are used for sharing semaphore across process.
Change-Id: I262adf10913d365bb93368b492e69140af522c64
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h | 40 ++
amdgpu/amdgpu_cs.c | 63 ++--
amdgpu/amdgpu_in
after ctx id is valid in global side, we share semaphore across process based
on BO sharing mechanism.
That means we map semaphore object to a bo, then sharing bo with other process,
the other process can
get the semaphore object from the sharing bo.
Chunming Zhou (4):
amdgpu: use drm_amdgpu_f
Change-Id: I6e8c8cfa1a05f51f3c03670baea68ed6da94fa11
Signed-off-by: Chunming Zhou
---
tests/amdgpu/basic_tests.c | 131 +
1 file changed, 131 insertions(+)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 02e863a..c7da54d 1006
semaphore just need to store ctx id not context itself,
which will bring convenience for sharing semaphore accross process.
Change-Id: I46cf54c61ee6143a77d18510c3591bcc97fa8b24
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu_cs.c | 20 ++--
amdgpu/amdgpu_internal.h | 2 +-
/* custom LRU management */
struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
+ struct amdgpu_mman_lru guard;
[FK] It would be safer to make the array AMDGPU_TTM_LRU_SIZE+1, instead
of adding a separate guard afterwards. That way the gua
benifits:
1. don't block userspace release at all.
2. make sure userspace can look up dependency if fence isn't signaled.
If they cannot find ctx, that means the dependecy is signaled.
Change-Id: I9184a7bb4f5bb6858c2dd49cfb113159cf71
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgp
It makes sure userspace can look up dependency.
Change-Id: Ie26086776de7df276fa041d977f0ea8264b32387
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/d
If ctx id is removed before ctx itself, the dependecy from umd couldnot be found
although ctx is still alive.
Change-Id: I129ce74f5524f74ef95a343444ba3fd9c0afdba5
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 +---
Change-Id: I0e36d8b842a29b67afcc411330700238b428e746
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 963a14e..357
If we want to share semaphore/dependency across process across device, we
must make ctx id be global, so that we can index it everywhere.
Chunming Zhou (6):
drm/amdgpu: use global ctx mgr instead of vm specified
drm/amdgpu: clean up for amdgpu ctx
drm/amdgpu: allocate progressively higher id
ctx id will be used across process and across device.
Change-Id: I3f4f99b75f457d60ae0e5c2a9ab126dff6f3418f
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 59 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++
2 files changed, 23 inserti
No used more.
Change-Id: I54ddd3f492354863a055ad2356bc749ff420
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 27 ++-
drivers/
On 17/08/16 07:29 PM, Qiang Yu wrote:
>
> -DebugPresent(("\t\tms:fq %lld c %d -> %d seq %llu\n",
> - (long long) flipdata->event->event_id,
> - flipdata->flip_count, flipdata->flip_count + 1,
> - (long long) seq));
Might be nice to move this
Change-Id: I975a0a97d570bd14b8031c4033cb447a3b3d2b1a
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0a0f3cb..
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