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momchil-velikov wrote:
/cherry-pick 7939ce6295e7fc0214cd307f97dfccc0cabde381
https://github.com/llvm/llvm-project/pull/124968
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@@ -2808,6 +2812,7 @@ void MicrosoftCXXNameMangler::mangleType(const
BuiltinType *T, Qualifiers,
#define SVE_TYPE(Name, Id, SingletonId) \
case BuiltinType::Id:
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits)
momchil-velikov wrote:
> Wit
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/125051
Saves including 4 files, reduces the number of switch cases, less error prone
when adding new types,
at the "cost" of adding a` default:`.
>From 8719394b628da73a0f9ed7088d771f14fe238144 Mon Sep 17 00:00
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@@ -2808,6 +2812,7 @@ void MicrosoftCXXNameMangler::mangleType(const
BuiltinType *T, Qualifiers,
#define SVE_TYPE(Name, Id, SingletonId) \
case BuiltinType::Id:
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits)
momchil-velikov wrote:
> Als
@@ -2808,6 +2812,7 @@ void MicrosoftCXXNameMangler::mangleType(const
BuiltinType *T, Qualifiers,
#define SVE_TYPE(Name, Id, SingletonId) \
case BuiltinType::Id:
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits)
momchil-velikov wrote:
It ca
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/124968
Fixes #124907
>From e490f9684aa8784299a9195a195433270f2cec79 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 29 Jan 2025 18:31:18 +
Subject: [PATCH] [AArch64] Add MSVC mangling for the __
momchil-velikov wrote:
> Is `__mfp8` a floating type? `isFloatingType()` on it returns `false`, was
> that the case before as well?
It was the case before and it's intentional. That type is more like a union of
two floating-point types.
https://github.com/llvm/llvm-project/pull/123604
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>From ffb554ea1ff638237ffc9cb9a491e5a6ad66d8f6 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 17 Dec 2024 17:10:38 +
Subject: [PATCH 1/2] [AArch64] Implement NEON FP8 fused multiply-add
i
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>From ae09723ecc1cc9bc2cbcef300b05aa2ce5ced448 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 17 Dec 2024 11:42:42 +
Subject: [PATCH 1/2] [AArch64] Add FP8 Neon intrinsics for dot-product
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/123613
>From ae09723ecc1cc9bc2cbcef300b05aa2ce5ced448 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 17 Dec 2024 11:42:42 +
Subject: [PATCH] [AArch64] Add FP8 Neon intrinsics for dot-product
THi
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>From 7ff7e9588f6a76dcbe7deb2dc5f78055f71b476b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 19:24:16 +
Subject: [PATCH] [AArch64] Add Neon FP8 conversion intrinsics
[fixup] A
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>From e825bc0f660eb3dce41ee062d04e4e39bbac5d2a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
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https://github.com/llvm/llvm-project/pull/123796
If an intrinsic has an `fpm_t` parameter, automatically set the flag `SetsFPMR`
and append "_fpm" to the name.
>From c807a4eb627919cb3161fe89c0623039dc6906d0 Mon Sep 17 00:00:00 2001
From: Momchil Velik
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/123585
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/123604
- The FP8 scalar type (`__mfp8`) was described as a vector type
- The FP8 vector types were described/assumed to have integer element type (the
element type ought to be `__mfp8`)
- Add support for `m` ty
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/123603
Reimplement Neon FP8 vector types using attribute `neon_vector_type` instead of
having them as builtin types.
This allows to implement FP8 Neon intrinsics without the need to add special
cases for these
@@ -2280,15 +2280,15 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2"
in {
let SVETargetGuard = "sve2p1", SMETargetGuard = InvalidMode in {
// ZIPQ1, ZIPQ2, UZPQ1, UZPQ2
- def SVZIPQ1 : SInst<"svzipq1[_{d}]", "ddd", "cUcsUsiUilUlbhfd", MergeNone,
"aarch64_sve_zip
momchil-velikov wrote:
I've implemented all the relevant Neon FP8 intrinsics on top of two alternative
implementations for Neon FP8 vector types:
* builtin vector types: https://github.com/llvm/llvm-project/pull/121804 (top
of PR stack, this PR right here is a part of it)
* using `neon_vector_t
https://github.com/momchil-velikov ready_for_review
https://github.com/llvm/llvm-project/pull/120476
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momchil-velikov wrote:
Abandon for now, the follow-up patch
(https://github.com/llvm/llvm-project/pull/121802) was reduced in scope and
does not need to update tests.
https://github.com/llvm/llvm-project/pull/121801
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momchil-velikov wrote:
I reduced the scope of this PR to just fixing the immediate UB.
https://github.com/llvm/llvm-project/pull/121802
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@@ -1382,14 +1382,15 @@ void Intrinsic::emitBodyAsBuiltinCall() {
Type CastToType = T;
// Check if an explicit cast is needed.
-if (CastToType.isVector() &&
-(LocalCK == ClassB || (T.isHalf() && !T.isScalarForMangling( {
- CastToType.makeInteger(8,
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>From 6a565f4a894fcc7abf35f8bbd3f141ccee5cb301 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 14 Jan 2025 14:49:11 +
Subject: [PATCH] [AArch64] Fix generating a code with UB in NeonEmitter
@@ -0,0 +1,22 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon
-target-feature +bf16 -target-feature +faminmax -target-feature +fp8 -emit-llvm
-verify %s -o /dev/null
momchil-velikov wrote:
They are needed.
https://github.com/llvm/llvm-pr
@@ -0,0 +1,143 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+
+// RUN: %clang_cc1-triple aarch64-none-linux-gnu -target-feature +neon
-target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2
-target-f
@@ -0,0 +1,54 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon
-target-feature +bf16 -target-feature +faminmax -target-feature +fp8 -emit-llvm
-verify %s -o /dev/null
momchil-velikov wrote:
They are needed.
https://github.com/llvm/llvm-pr
@@ -0,0 +1,308 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1-triple aarch64-none-linux-gnu -target-feature +neon
-target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall
-e
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -triple aarch64 -fsyntax-only -verify %s
+
+// REQUIRES: aarch64-registered-target
+
+typedef __attribute__((neon_vector_type(8))) signed char int8x8_t;
+typedef __attribute__((neon_vector_type(16))) signed char int8x16_t;
+
+typedef __MFloat8x
@@ -0,0 +1,123 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple aarch64-linux -target-feature +neon
-disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
+
+// REQUIRES: a
@@ -2578,6 +2576,19 @@ bool Type::isSveVLSBuiltinType() const {
return false;
}
+bool Type::isNeonVectorBuiltinType() const {
momchil-velikov wrote:
Done
https://github.com/llvm/llvm-project/pull/119031
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@@ -650,6 +655,8 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
// An ext_vector_type of Bool is really a vector of bits.
llvm::Type *IRElemTy = VT->isExtVectorBoolType()
? llvm::Type::getInt1Ty(getLLVMContext())
+
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/122893
The intrinsics generated in `arm_neon.h` heavily rely on C-style cast operator
having
bitcast semantics for vector operands. This patch allows such expressions to
"convert"
to/from FP8 builtin Neon vect
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119031
>From e8a216c5effbf426ada5b9deb89fc2b5d9405f7c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/5] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From e8a216c5effbf426ada5b9deb89fc2b5d9405f7c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/2] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov edited
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@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon
-target-feature +bf16 -target-feature +faminmax -emit-llvm -verify %s -o
/dev/null
momchil-velikov wrote:
No, they are both required by `fp8`.
https://github.com/llvm/llvm-pro
@@ -57,6 +57,11 @@
// - IsBF true for vector of brain float elements.
//===--===//
+#ifndef SVE_SCALAR_TYPE
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits) \
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@@ -557,6 +557,10 @@ def invoke_tool(exe, cmd_args, ir, preprocess_cmd=None,
verbose=False):
UTC_AVOID = "NOTE: Do not autogenerate"
UNUSED_NOTE = "NOTE: These prefixes are unused and the list is autogenerated.
Do not add tests below this line:"
+DATA_LAYOUT_RE = re.compile(
@@ -650,6 +655,16 @@ def get_triple_from_march(march):
print("Cannot find a triple. Assume 'x86'", file=sys.stderr)
return "x86"
+def get_global_underscores(raw_tool_output):
+m = DATA_LAYOUT_RE.search(raw_tool_output)
+if not m:
+return False
+data
@@ -122,6 +122,11 @@ def parse_clang_ast_json(node, loc, search):
if search is None:
search = spell
mangled = node.get("mangledName", spell)
+# Strip leading underscore from globals, so the name matches the LLVM
one
momchil-
@@ -650,6 +655,16 @@ def get_triple_from_march(march):
print("Cannot find a triple. Assume 'x86'", file=sys.stderr)
return "x86"
+def get_global_underscores(raw_tool_output):
+m = DATA_LAYOUT_RE.search(raw_tool_output)
+if not m:
+return False
+data
momchil-velikov wrote:
> Instead it could perform a load with the original type and then emit an LLVM
> IR `bitcast`, just like it does for "C-style"
Except that it does not work when aggregate types are involved.
Using `mem2reg,sroa` is a bit better than just `mem2reg`, even though `sroa`
gen
@@ -1382,14 +1382,15 @@ void Intrinsic::emitBodyAsBuiltinCall() {
Type CastToType = T;
// Check if an explicit cast is needed.
-if (CastToType.isVector() &&
-(LocalCK == ClassB || (T.isHalf() && !T.isScalarForMangling( {
- CastToType.makeInteger(8,
momchil-velikov wrote:
Another things that "works" is changing the codegen for `__builtin_bit_cast`
(https://github.com/llvm/llvm-project/blob/32bc029be6265838833623fdd88cc665d5658dc7/clang/lib/CodeGen/CGExprScalar.cpp#L2295).
It stores a value with one type and loads it back with another type w
momchil-velikov wrote:
> Isn't it a bug that clang reports an incorrect mangled name?
I reckon the mangled name reported by clang is correct in the sense it's the
final symbol name in the assembler/object file.
https://github.com/llvm/llvm-project/pull/121800
@@ -650,6 +655,16 @@ def get_triple_from_march(march):
print("Cannot find a triple. Assume 'x86'", file=sys.stderr)
return "x86"
+def get_global_underscores(raw_tool_output):
+m = DATA_LAYOUT_RE.search(raw_tool_output)
+if not m:
+return False
+data
momchil-velikov wrote:
> > This patch adds instcombine to some tests that were passing
> Can the instcombines be replaced with something simpler like dce or maybe
> instsimplify? It might be OK with just mem2reg.
Unfortunately just `mem2reg` does not cut it. The original issue it that Clang
ge
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>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/7] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119031
>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/3] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/118961
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momchil-velikov wrote:
Thanks!
https://github.com/llvm/llvm-project/pull/118961
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https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/120551
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https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/120549
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https://github.com/momchil-velikov converted_to_draft
https://github.com/llvm/llvm-project/pull/120476
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119033
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/7] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119031
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/3] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/118961
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118961
>From 7d4c0cded14845fe854157d550fafd4637bea14f Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 10:47:43 +
Subject: [PATCH] Fix SVE tuples
---
clang/lib/CodeGen/Targets/AArch64.
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/118126
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 15478424a10e531d42f197dae5e2083e8d183c23 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 26 Nov 2024 18:01:03 +
Subject: [PATCH 1/3] [AArch64] Implement FP8 SVE intrinsics for fused
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/118125
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 5bc5078af32cda3dbcf3ca8dd53b01996ad34ea1 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 17:21:55 +
Subject: [PATCH 1/5] [AArch64] Implements FP8 SVE intrinsics for dot-pr
@@ -0,0 +1,114 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mattr=+sve2,+fp8,+fp8fma < %s | FileCheck %s
+; RUN: llc -mattr=+sme,+fp8,+ssve-fp8fma --force-streaming < %s | FileCheck %s
+
+target triple = "aa
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