[PATCH v2] riscv: Fix incorrect gnu property alignment on rv32

Codegen is incorrectly emitting a ".p2align 3" that coerces the alignment of the .note.gnu.property section from 4 to 8 on rv32. 2025-04-11 Jesse Huang gcc/ChangeLog * config/riscv/riscv.cc (riscv_file_end): Fix .p2align value. gcc/testsuite/ChangeLog * gcc.target

[PATCH] riscv: Fix incorrect gnu property alignment on rv32

Codegen is incorrectly emitting a ".p2align 3" that coerces the alignment of the .note.gnu.property section from 4 to 8 on rv32. --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c | 12 gcc/testsuite/gcc.target/riscv/gnu-

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

https://github.com/jaidTw closed https://github.com/llvm/llvm-project/pull/132259 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

@@ -378,6 +370,14 @@ def FeatureStdExtZca "part of the C extension, excluding compressed " "floating point loads/stores">; +def FeatureStdExtC +: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>, + RISCVExte

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

Zca, Zcf and Zcd, the rule is that: > * C always implies Zca > * C+F implies Zcf (RV32 only) > * C+D implies Zcd >From e147dd68477b7e5ec9e6363a45fd7568fe595b04 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 20 Mar 2025 10:34:14 -0700 Subject: [PATCH] [RISCV] Implement the im

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

@@ -25,8 +25,8 @@ addi a0, a1, 0 # CHECK: # encoding: [0xe0,0x1f] addi s0, sp, 1020 -# CHECK: .option arch, -c -.option arch, -c +# CHECK: .option arch, -c, -zca +.option arch, -c, -zca jaidTw wrote: I tried but failed, seems like both are required https://

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/132259 >From e147dd68477b7e5ec9e6363a45fd7568fe595b04 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 20 Mar 2025 10:34:14 -0700 Subject: [PATCH 1/2] [RISCV] Implement the implications of C extens

[clang] [Clang][RISCV] Remove forced-sw-shadow-stack (PR #115355)

https://github.com/jaidTw closed https://github.com/llvm/llvm-project/pull/115355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Remove forced-sw-shadow-stack (PR #115355)

https://github.com/llvm/llvm-project/pull/112477 and https://github.com/llvm/llvm-project/pull/112478, now two implementation is represented by independent options and we no longer need it. >From d9203fbbcacf509defab5b7e8fb7816d2819f121 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Fri, 8

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw closed https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

jaidTw wrote: @mylai-mtk could you take a look at the latest version? I'm gonna merge it if it looks good to you too https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/5] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

jaidTw wrote: After a meeting with Kito, I will change the requirement of both patches (this and 112478) to Zicfiss, and lift it in a future patch I'm encountering a problem that cc1 tests cannot recognize the option and working of a fix now https://github.com/llvm/llvm-project/pull/112477 ___

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/9] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/8] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/7] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/6] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s -fcf-protection=return | FileCheck -check-prefix=NOTIGNORELISTED %s +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s | FileChec

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s -fcf-protection=return | FileCheck -check-prefix=NOTIGNORELISTED %s +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s | FileChec

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/5] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/3] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -607,6 +607,9 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo { auto *Fn = cast(GV); Fn->addFnAttr("interrupt", Kind); + +if (CGM.getCodeGenOpts().CFProtectionReturn) jaidTw wrote: Fixed, thanks! https://github.com/llvm/llvm-project

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

jaidTw wrote: Addressed comments https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/4] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/3] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [llvm] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -0,0 +1,30 @@ +; ModuleID = '/home/jhuang4/workspace/test.c' jaidTw wrote: Yeah definitely, I'll remove it https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[clang] [llvm] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -607,6 +607,9 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo { auto *Fn = cast(GV); Fn->addFnAttr("interrupt", Kind); + +if (CGM.getCodeGenOpts().CFProtectionReturn) jaidTw wrote: I'm not quite familiar with the code here, is it saf

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/3] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [llvm] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/3] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/3] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -899,6 +899,11 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, if (CodeGenOpts.PointerAuth.IndirectGotos) Fn->addFnAttr("ptrauth-indirect-gotos"); + // Add return control flow integrity attributes for RISCV. + if (CodeGenOpts.CFProtectionRetur

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/2] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/112477 >From fe4a28fb691b69d9af384f1dc2f0667761adef44 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 13 Oct 2024 15:11:06 +0800 Subject: [PATCH 1/2] [Clang][RISCV] Support -fcf-protection=return for RIS

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -899,6 +899,10 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, if (CodeGenOpts.PointerAuth.IndirectGotos) Fn->addFnAttr("ptrauth-indirect-gotos"); + // Add return control flow integrity attributes. + if (CodeGenOpts.CFProtectionReturn) +Fn

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw edited https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/jaidTw created https://github.com/llvm/llvm-project/pull/112477 This patches add a string attribute "hw-shadow-stack" to every function if `-fcf-protection=return` is set on RISC-V >From 2a7a6ef1b44f250abf840165bac4c91ca0af928b Mon Sep 17 00:00:00 2001 From

[clang] [llvm] [RISCV] Bump Pointer Masking extension version (PR #96715)

https://github.com/jaidTw approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/96715 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/jaidTw closed https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/jaidTw edited https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

@@ -119,6 +119,7 @@ on support follow. ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs``Supported (`See note <#riscv-profiles-extensions-note>`__) ``Zacas`` Supported (`See note <#riscv-zacas-note>`__) +

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/88474 >From 59b52163ff321d39128006c37ee38380ef5f9eec Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 11 Apr 2024 23:05:23 -0700 Subject: [PATCH 1/4] [RISCV] Support Zama16b1p0 This patch adds the support

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/88474 >From 59b52163ff321d39128006c37ee38380ef5f9eec Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 11 Apr 2024 23:05:23 -0700 Subject: [PATCH 1/3] [RISCV] Support Zama16b1p0 This patch adds the support

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/88474 >From 59b52163ff321d39128006c37ee38380ef5f9eec Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 11 Apr 2024 23:05:23 -0700 Subject: [PATCH 1/2] [RISCV] Support Zama16b1p0 This patch adds the support

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

/097819c2c668cbf693c80b8d25085462826d07d4/rva23-profile.adoc) >From 59b52163ff321d39128006c37ee38380ef5f9eec Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 11 Apr 2024 23:05:23 -0700 Subject: [PATCH] [RISCV] Support Zama16b1p0 This patch adds the support for Zama16b, which has been added to RVA23U64 optional extensi

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/jaidTw approved this pull request. https://github.com/llvm/llvm-project/pull/79929 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

jaidTw wrote: > > Should you also update the riscv32-toolchain-extra.c and > > riscv64-toolchain-extra.c? > > It is not immediately obvious to me what you had in mind for changing those > tests. Could you please clarify? I found I messed up the configuration so there were some test errors on

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/jaidTw commented: Should you also update the `riscv32-toolchain-extra.c` and `riscv64-toolchain-extra.c`? LGTM otherwise https://github.com/llvm/llvm-project/pull/79929 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:/

Re: [patch 02/18] sundance: PHY address form 0, only for device I D 0x0200 (IP100A) (20070605)

dev->name, phyx, mii_status, np->mii_if.advertising); } } So, we hope you can drop this patch "[patch 02/18] sundance: PHY address form 0, only for device I D 0x0200 (IP100A) (20070605)" Thanks a lot! Best Regards, Jesse Huang -Ori

Re: IP1000A network driver in Linux tree?

Dear All: Was IC Plus IP1000A Linux Driver in kernel tree or not? Our customer is pushing us to put it into kernel. Is there anything that we should do? Thanks. Best Regards, Jesse Huang -Original Message- From: Francois Romieu [mailto:[EMAIL PROTECTED] Sent: Tuesday, June 12, 2007 6

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A) (20070605)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |6 +- 1 files changed, 5 insertions(+),

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A) (20070605)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |6 +- 1 files changed, 5 insertions(+),

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A) (20070605)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |6 +- 1 files changed, 5 insertions(+),

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A) (20070605)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |6 +- 1 files changed, 5 insertions(+),

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |4 +++- 1 files changed, 3 insertions(+),

[PATCH] sundance: PHY address form 0, only for device ID 0x0200 (IP100A)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Search PHY address form 0, only for device ID 0x0200 (IP100A). Other device are from PHY address 1. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |4 +++- 1 files changed, 3 insertions(+),

Re: How about current IP100A status? 10/31/2006

Dear Jeff: Thanks for your help. We are happy to see new version of our driver will be support in the new kernel. Best Regards, Jesse Huang - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; &l

How about current IP100A status? 10/31/2006

Dear All: How about current IP100A, sundance.c status? Should it be put into kernel or not? Is there any sentence should I need to modify? Thanks for your help! Jesse Huang - Original Message - From: "Jesse Huang" <[EMAIL PROTECTED]> To: ; ; <[EMAIL PROTECTED]&

[PATCH 5/5] Solve host error problem in low performance embedded system when continune down and up.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Solve host error problem in low performance embedded system when continune down and up. It will cause IP100A DMA TargetAbort. So we need more safe process to up and down IP100A with wait hardware completely stop and software cur_tx/ di

[PATCH 2/5] Fix TX Pause bug (reset_tx, intr_handler)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Fix TX Pause bug (reset_tx, intr_handler). When MaxCollisions occurred, need to re-enable Tx. But just after re-enable, MaxCollisions maybe occurred again and with TxStatusOverflow. This will cause driver can't check new MaxColli

[PATCH 4/5] Correct initial and close hardware step.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Correct initial and close hardware step. In some embedded system down and up IP100A will cause DMA crash. We add some for safe down and up IP100A. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |8

[PATCH 1/5] remove TxStartThresh and RxEarlyThresh

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: For patent issue need to remove TxStartThresh and RxEarlyThresh. This patent is cut-through patent. If use this function, Tx will start to transmit after few data be move in to Tx FIFO. We are not allow to use those function in DFE530/

Re: What is current sundance.c status

Ok, I will generate those again with descriptions. Thank you! Best Regards, Jesse Huang. - Original Message - From: "Andrew Morton" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]> Sent: Thursday, October

Re: [PATCH 5/5] Solve host error problem in low performance embedded system when continune down and up.

In some low performance embedded CPU, if continued to ifconfig up and down driver. It will cause host error. Driver need to make sure all counter is clear to zero, and hardware actually stop. - Original Message - From: "Andrew Morton" <[EMAIL PROTECTED]> To: "

Re: [PATCH 2/5] Fix TX Pause bug (reset_tx, intr_handler)

When TxUnderrun happen, driver will re-enable tx. But during this enable process, TxUnderrun maybe happen again. So driver need to make sure Tx was actually enabled. - Original Message - From: "Andrew Morton" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAI

Re: [PATCH 1/5] remove TxStartThresh and RxEarlyThresh

Sorry, I had typed wrong word. It is because patent issue. Thnaks. - Original Message - From: "Roland Dreier" <[EMAIL PROTECTED]> To: "Andrew Morton" <[EMAIL PROTECTED]> Cc: "Jesse Huang" <[EMAIL PROTECTED]>; ; ; <[EMAIL PROTECTED]&

[PATCH 5/5] Solve host error problem in low performance embedded system when continune down and up.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Solve host error problem in low performance embedded system when continune down and up. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 26 +++--- 1 files changed, 23 inse

[PATCH 2/5] Fix TX Pause bug (reset_tx, intr_handler)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Fix TX Pause bug (reset_tx, intr_handler) Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 16 ++-- 1 files changed, 14 insertions(+), 2 deletions(-) e146d4c423de9c2e9d55fbf9c6b3abbee14ce9a

[PATCH 4/5] Correct initial and close hardware step.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: Correct initial and close hardware step. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |8 1 files changed, 8 insertions(+), 0 deletions(-) 1bbb3f6231fa1f52a9f61e299f22610d357f6041 diff --g

[PATCH 1/5] remove TxStartThresh and RxEarlyThresh

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: For pattern issue need to remove TxStartThresh and RxEarlyThresh. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |8 ++-- 1 files changed, 2 insertions(+),

Re: [PATCH] Restore the original TX FIFO overflow process.

Ok, I will generate new patch according to this. Thanks. - Original Message - From: "Andrew Morton" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Sent: Saturday, September 23, 2006 4:51 PM Subject: Re: [PATCH] Restore the original TX FIFO ov

[PATCH] Restore the original TX FIFO overflow process.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Restore the original TX FIFO overflow process. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 45 +++-- 1 files changed, 27 insertions(+),

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

Dear Philippe: (1)Because this is a patent issue, we are not allow to use it again, even it is in Data Sheet. (2)Ok, sorry for this, I will add it back. Should I resent those 4 patches? Or generate this as a new patch? Thanks very much! Best Regards, Jesse Huang. - Original Message

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

is. Thanks you very mutch. Best Regards, Jesse Huang. - Original Message - From: "Philippe De Muyter" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: Sent: Friday, September 15, 2006 7:44 PM Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug

[PATCH 3/4] IP100A: Correct initial and close hardware step. 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Correct initial and close hardware step. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |8 1 files changed, 8 insertions(+), 0 deletions(-) 419599b10f1253ccd7224bbd369924307e1e5bb6

[PATCH 4/4] IP100A: Solve host error problem in low performance embedded system when continune down and up. 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Solve host error problem in low performance embedded system when continune down and up. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 28 1 files changed, 2

[PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler) 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Fix TX Pause bug (reset_tx, intr_handler) Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 53 +++- 1 files changed, 30 insertions(+),

Re: What is current sundance.c status?

OK! I will resend my patchset. Thanks! Jesse - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]> Sent: Wednesday, September 13, 2006 12:05 AM Subject: Re: What is current

What is current sundance.c status?

Dear Jeff: Would you tell me what is current sundance.c status which support IP100A? Are those patches update to current tree or not? Is there anything should I need to add to it and generate new patches? Thank you very much. Best Regards, Jesse Huang - To unsubscribe from this list: send the

Re: [PATCH] IP1000A: IC Plus update 2006-08-22

ut > handler where it imho belongs. It is better to Use tx_timeout than the original one. Thanks for that. Best Regards, Jesse Huang - Original Message - From: "Francois Romieu" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <

Re: [PATCH] IP1000A: IC Plus update 2006-08-22

It's Ok. Thanks for that. Jesse - Original Message - From: "Francois Romieu" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; ; ; <[EMAIL PROTECTED]&g

[PATCH 3/4] IP100A: Correct initial and close hardware step. 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Correct initial and close hardware step. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c |8 1 files changed, 8 insertions(+), 0 deletions(-) 419599b10f1253ccd7224bbd369924307e1e5bb6

[PATCH 4/4] IP100A: Solve host error problem in low performance embedded system when continune down and up. 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Solve host error problem in low performance embedded system when continune down and up. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 28 1 files changed, 2

[PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler) 2006-08-24

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Fix TX Pause bug (reset_tx, intr_handler) Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- drivers/net/sundance.c | 53 +++- 1 files changed, 30 insertions(+),

Re: [PATCH 4/4] IP100A: Solve host error problem in low performance embedded system when continune down and up.

Hi Randy: Sorry for the file path. I will regenerate with path a/drivers/net/sundance.c and re-submit again. Thanks for your help! Best Regards, Jesse Huang - Original Message - From: "Randy.Dunlap" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTE

Re: [PATCH] IP1000A: IC Plus update 2006-08-22

Hi Francois: I am very appreciated what you do for IP1000A. I will follow those files. Thanks you very much! Best Regards, Jesse Huang - Original Message - From: "Francois Romieu" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <[E

[PATCH 3/4] IP100A: Correct initial and close hardware step.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Correct initial and close hardware step. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- sundance.c | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) ddfaae9a0f4bd37c155f21fb4779093eef059bf6 diff --git

[PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Fix TX Pause bug (reset_tx, intr_handler) Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- sundance.c | 53 ++--- 1 files changed, 30 insertions(+),

[PATCH 4/4] IP100A: Solve host error problem in low performance embedded system when continune down and up.

From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - Solve host error problem in low performance embedded system when continune down and up. Signed-off-by: Jesse Huang <[EMAIL PROTECTED]> --- sundance.c | 30 +- 1 files changed, 25 inse

[PATCH] IP1000A: IC Plus update 2006-08-22

Dear All: I had regenerate this patch from: git://git.kernel.org/pub/scm/linux/kernel/git/penberg/netdev-ipg-2.6.git And, submit those modifications as one patch. Add: "Remove and add some whitespace" From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - update mainta

Re: [PATCH] IP1000A: IC Plus update

remove those. Thanks for help. Jesse - Original Message - From: "Randy.Dunlap" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; ; Sen

Re: [PATCH 2/6] IP100A Fix Tx pause bug

- Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]> Sent: Friday, August 18, 2006 7:27 PM Subject: Re: [PATCH 2/6] IP100A Fix Tx pause bug (1) >> + iowrite8(127, ioadd

[PATCH] IP1000A: IC Plus update

Dear All: I had regenerate this patch from: git://git.kernel.org/pub/scm/linux/kernel/git/penberg/netdev-ipg-2.6.git And, submit those modifications as one patch. From: Jesse Huang <[EMAIL PROTECTED]> Change Logs: - update maintainer information - remove some default phy

Re: [PATCH 6/6] IP100A Solve host error problem when in low performance embedded

Hi Jeff: > (4) are you certain that DMACtrl should be read as a 32-bit register? > In other code, you treat it as a 16-bit register. DMACtrl can read and write both in 16-bit and 32-bit. I will modify all of then as 32-bit. Thanks. Jesse - To unsubscribe from this list: send the line "unsubscr

Re: [PATCH 4/6] IP100A Change search phy addr start form 0

Hi Jeff: In IP100A, phy address is 0. Because IP100A is a single chip, the in chip phy address is 0. so, we must search phy address for 0. Jesse - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ;

Re: [PATCH 6/6] IP100A Solve host error problem when in low performance embedded

Hi Jeff: I will follow those suggestions. Thanks. Jesse - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]> Sent: Friday, August 18, 2006 7:17 PM Subject: Re: [PATCH 6/6

Re: [PATCH 5/6] IP100A correct init and close step

Hi Jeff: (3)Yes, This is a bug, I will correct it. Thanks. (4)This will halt TxDMA and RxDMA, after that will let reseting safely. Should I add description in source code or in change log? Thanks! Jesse - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]>

Re: [PATCH 1/6] IP100A, add end of pci id table

Hi Jeff: Ok, I see. I will resend all of the patches after I finish modify. Thanks. Jesse - Original Message - From: "Jeff Garzik" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]> Sent: Friday, August 18, 2006 7

Re: [PATCH 5/7] ip1000: Modify coding style of ipg_config_autoneg()

Hi : Ok, I will remove the Mixed case variables. Thanks. Jesse - Original Message - From: "Francois Romieu" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>;

Re: [PATCH 2/7] ip1000: remove some default phy params

Hi David: Ok, I will add sign-off-by latter. Thanks for that. Jesse Huang - Original Message - From: "David Gomez" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]&g

Re: [PATCH 1/6] IP100A, add end of pci id table

Hi Alexey: I will remove that. Thanks for that. Jesse Huang - Original Message - From: "Alexey Dobriyan" <[EMAIL PROTECTED]> To: "Jesse Huang" <[EMAIL PROTECTED]> Cc: ; ; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]> Sent: Thursday, August 17, 2

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