[clang] [Driver] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

quic-garvgupt wrote: Hi @petrhosek, following up on our last RISC-V embedded sync-up, can you please review this patch? Thanks https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[clang] [Driver] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

quic-garvgupt wrote: Gentle Ping again! https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Driver] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

@@ -110,20 +111,93 @@ static std::string computeBaseSysRoot(const Driver &D, bool IncludeTriple) { return std::string(SysRootDir); } +// GCC sysroot here means form sysroot from either --gcc-install-dir, or from +// --gcc-toolchain or if the toolchain is installed alongside

[clang] [Driver] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

quic-garvgupt wrote: Gentle Ping! https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Driver] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

quic-garvgupt wrote: I have divided this PR into three separate PRs to streamline the review process and ensured that ARM and RISCV tests are not modified in the same PR. Please review them and provide any feedback or comments. Thanks! [RISCV] Teach Barmetal toolchain about GCC installation(1/

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/121829 >From 03b91a8d408bacec17391b995611dbbb0ea62edd Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Fri, 13 Dec 2024 05:31:56 -0800 Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/121829 >From 02d70a2c1fa746eafa87308f0c8109bb2c91164f Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Fri, 13 Dec 2024 05:31:56 -0800 Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt ready_for_review https://github.com/llvm/llvm-project/pull/121829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

quic-garvgupt wrote: * **#121829** https://app.graphite.dev/github/pr/llvm/llvm-project/121829?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-projec

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121829)

https://github.com/quic-garvgupt created https://github.com/llvm/llvm-project/pull/121829 This patch introduces the baretmetal toolchain object about GCC Installation. Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on commandline, then sysroot will be formed from th

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121821)

https://github.com/quic-garvgupt created https://github.com/llvm/llvm-project/pull/121821 This patch introduces the baretmetal toolchain object about GCC Installation. Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on commandline, then sysroot will be formed from

[clang] [RISCV] Teach Barmetal toolchain about GCC installation(1/3) (PR #121821)

https://github.com/quic-garvgupt closed https://github.com/llvm/llvm-project/pull/121821 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -78,8 +86,9 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain { using OrderedMultilibs = llvm::iterator_range::const_reverse_iterator>; OrderedMultilibs getOrderedMultilibs() const; - + bool UseLD; quic-garvgupt wrote: please see my

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -110,20 +111,95 @@ static std::string computeBaseSysRoot(const Driver &D, bool IncludeTriple) { return std::string(SysRootDir); } +// GCC sysroot here means form sysroot from either --gcc-install-dir, or from +// --gcc-toolchain or if the toolchain is installed alongside

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -6521,11 +6521,7 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: -if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args)) - TC = - std::make_

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/118809 >From b58f9dd197c78b1e39676022a421ca0e6d5552a5 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 13 Nov 2024 02:45:51 -0800 Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains Curr

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/118809 >From 569feb86c654be044781aa5968907a72ea882e88 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 13 Nov 2024 02:45:51 -0800 Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains Curr

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -503,12 +624,22 @@ void baremetal::Linker::ConstructJob(Compilation &C, const JobAction &JA, const llvm::Triple::ArchType Arch = TC.getArch(); const llvm::Triple &Triple = getToolChain().getEffectiveTriple(); - AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA); + if (!D

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/118809 >From b74795d44846b79252bd3fb1f1e8179311725c74 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 13 Nov 2024 02:45:51 -0800 Subject: [PATCH] [RISCV] Merging RISCVToolChain and BareMetal toolchains Cu

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

https://github.com/quic-garvgupt created https://github.com/llvm/llvm-project/pull/118809 Currently, LLVM has two RISC-V toolchain classes in Clang for baremetal development, creating unnecessary maintenance overhead. This patch extends the BareMetal toolchain to support an existing GCC instal

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (PR #83896)

quic-garvgupt wrote: I believe the patch is ready to be merged now, but since I am not the reviewer here, someone else must approve it as well. Thanks again for the patch! https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list c

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: Thanks for the prompt reply and latest patchset. 1. Do we need to add documentation in RISCVUsage.rst file for xsfcease? 2. Also, as we are adding cease instruction in this PR, can we rename the PR to include the cease instruction as well? https://github.com/llvm/llvm-proj

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: Thanks for clearing the confusion around whether rs1 would be optional or not. Can we also add lit tests for the aliases? https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: > > Also, I think we might need to update the extensions in the > > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller? > > This is a M-mode only extension, and we haven't historically been adding M or > S mode extensions to the -mcpu lists. Except for `xiangshan-n

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: > > Hi @topperc, can you add instruction alias for cflush and cdiscard > > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` > > respectively, as this register is optional according to spec? > > x0 has special meaning, but the spec never says it is "

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: Also, I think we might need to update the extensions in the `RISCVProcessors.td` file under SIFIVE_S76 microcontroller? https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

quic-garvgupt wrote: Hi @topperc, can you add instruction alias for cflush and cdiscard instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` respectively, as this register is optional according to spec? https://github.com/llvm/llvm-project/pull/83896 _

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

quic-garvgupt wrote: ping! for merging this PR https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

quic-garvgupt wrote: Hi @MaskRay, please review the updated changes and if they are fine, please merge this PR on my behalf. Thanks! https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/81727 >From 0d1f9be389a41ba2f1531bf13e8d1f14aadf9eeb Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 14 Feb 2024 03:00:20 -0800 Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

quic-garvgupt wrote: Hi @asb, I do not have write access, requesting to merge this PR on my behalf. Also, requesting to backport this PR onto the release branch. Thanks in advance! https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mai

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

@@ -421,3 +421,11 @@ // MIPSN32R6EL: "-target-cpu" "mips64r6" // MIPSN32R6EL: "-target-abi" "n32" // MIPSN32R6EL: "-mfloat-abi" "hard" + +// RUN: %clang --target=riscv32-unknown-elf --gcc-toolchain="" -### %s 2>&1 | FileCheck %s -check-prefix=NOUWTABLE quic-ga

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/81727 >From 8cc7535ed4c05d4cf14cdedc26077eccf06c8d53 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 14 Feb 2024 03:00:20 -0800 Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/81727 >From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 14 Feb 2024 03:00:20 -0800 Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/81727 >From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001 From: Garvit Gupta Date: Wed, 14 Feb 2024 03:00:20 -0800 Subject: [PATCH 1/2] [RISCV] Disable generation of asynchronous unwind tables

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

quic-garvgupt wrote: Hi @asb, since Petr already gave a good-ahead to this patch in the meeting, let me know if we can merge this PR if there are no new changes need to be made https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing li

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV ba… (PR #81727)

quic-garvgupt wrote: Hi @jonathonpenix @apazos @kito-cheng @asb @MaskRay - Requesting for adding as reviewers to review the PR. Thanks in advance! https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV ba… (PR #81727)

https://github.com/quic-garvgupt created https://github.com/llvm/llvm-project/pull/81727 The below culprit patch enabled the generation of asynchronous unwind tables (-funwind-tables=2) by default for RISCV for both linux and RISCVToolChain baremetal object. However, since there are 2 baremeta