Re: [9fans] Plan 9 C compiler for Xtensa CPUs

On Sat, 10 Aug 2019 16:18:16 +, Charles Forsyth wrote: I haven't had a lot of spare time, but I did the assembler and am about 3/4 through the loader. For the most part it's a straightforward RISC. Might do the disassembler next to help debug the rest, and finally the compiler. Did you ge

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

For IoT deployments, I suppose that one processor core on the ESP32 could run the WiFi / networking stack and the other act as a CPU-like server and thus run a small number of servers to expose the interface(s) in a 9P mountable fashion to more powerful nodes. A RT-ish kernel might suffice in most

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Charles Forsyth I haven't had a lot of spare time, but I did the assembler and am about > 3/4 through the loader. > For the most part it's a straightforward RISC. > Might do the disassembler next to help debug the rest, and finally the > compiler. Nowadays I do the disassembler first. Advantages

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

There is another existing variant of ESP32 with flash and RAM, and that one would provide the external memory MMU. It seems there could be a range from a small RT-ish kernel, with and without a user mode, on little ESP32, to a Plan 9 kernel with a few specialised processes on the bigger one. An Inf

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Charles Forsyth writes: > At a glance it looked as though the MMUs for the on-chip stuff were more > suitable for Unix Seventh Edition (no later) than "full" Plan 9. Wouldn't Inferno be a better fit for these sort of devices? In my experience these things are used primarily as I/O devices, with

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

At a glance it looked as though the MMUs for the on-chip stuff were more suitable for Unix Seventh Edition (no later) than "full" Plan 9. The MMU for the external memory looked fine, but as I said, the device I've got, and several other boards based on WROOM seem not to bother with external memory.

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Everything old is new again? On Sat, Aug 10, 2019 at 7:11 PM Cyber Fonic wrote: > The emergent problem with IoT is the lack of security. From my > understanding of Plan9's architecture. 9p protocol and the "root-less" > security model suggests to me that a Plan9 swarm of IoT devices could be >

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

The emergent problem with IoT is the lack of security. From my understanding of Plan9's architecture. 9p protocol and the "root-less" security model suggests to me that a Plan9 swarm of IoT devices could be the "killer app" where Plan9 emerges on the strength of the vision of decades ago. Looking

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

I'm not sure if the effort would be worth it; but if you add support for esp32, I think it would be better for the os to be something like the one you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9. Staying with FreeRTOS would need removal of GCC specific things from OS and

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

On Aug 9, 2019, at 2:34 PM, Charles Forsyth wrote: > > Since the resources are small if not tiny, a little systems analysis and > design is probably needed, but it looks like a bit of fun, until the > inevitable moment of "why am I here?". > > On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth >

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Wireless NinePea perhaps? https://github.com/echoline/NinePea On Sat, Aug 10, 2019 at 7:36 AM Charles Forsyth wrote: > Since the resources are small if not tiny, a little systems analysis and > design is probably needed, but it looks like a bit of fun, until the > inevitable moment of "why am I

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Since the resources are small if not tiny, a little systems analysis and design is probably needed, but it looks like a bit of fun, until the inevitable moment of "why am I here?". On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth wrote: > The device I've got is ESP32-WROOM-32. None of the boards I

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

The device I've got is ESP32-WROOM-32. None of the boards I've seen that use it bother with external memory, so memory is limited, especially the way it's partitioned. On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth wrote: > The ESP32 has got several MMUs. The characteristics are different > depe

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

The ESP32 has got several MMUs. The characteristics are different depending on the part that a given MMU accesses (flash, ROM, SRAM, external memory). Some things are accessed using Memory Protection Units instead, which control access by Process ID, but don't do mapping. Others including some of t

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

esp32 doesn’t have an mmu, right? > On Jul 26, 2019, at 03:30, Charles Forsyth wrote: > > I was thinking of doing that since I've got an ESP-32 for some reason > >> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic wrote: >> I was reading the post Why Didn't Plan 9 Succeed on Hacker News. >> >> Mad

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

On 8/7/19, Charles Forsyth wrote: > I've not previously seen an architecture where so many cache and TLB > control instructions were in the primary space and took up so much of it. > I guess the remainder is RISC :-). Lucio.

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

I've not previously seen an architecture where so many cache and TLB control instructions were in the primary space and took up so much of it. On Fri, Jul 26, 2019 at 11:30 AM Charles Forsyth wrote: > I was thinking of doing that since I've got an ESP-32 for some reason > > On Fri, Jul 26, 2019

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Richard Miller <9f...@hamnavoe.com> once said: > I see the above list uses .e and .j for riscv and riscv64 - > are these just reserved or are there actual compilers somewhere? No, it was just a suggestion on my part. If I remember correctly, I thought it was mildly clever that 'e' is the fifth let

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

> https://www.pbrane.org/comp.html I've used .x for riscv32 but it's easily changed. I see the above list uses .e and .j for riscv and riscv64 - are these just reserved or are there actual compilers somewhere?

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Charles Forsyth once said: > I'd need a letter or number and thought about reusing x (xa/xc/xl) since > the AT&T DSP is long gone https://github.com/0intro/plan9-mips/tree/master/sys/src/cmd/4c https://github.com/0intro/plan9-mips/blob/master/rc/bin/xc I think I sent this to the list once before

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

I'd need a letter or number and thought about reusing x (xa/xc/xl) since the AT&T DSP is long gone On Fri, Jul 26, 2019 at 11:30 AM Charles Forsyth wrote: > I was thinking of doing that since I've got an ESP-32 for some reason > > On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic wrote: > >> I was re

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

nope. charles is your man. -- cinap

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

Does anybody have any suggestions as to what it would take to create a C compiler for Xtensa (it is basically a 32 bit sorta-like RISC architecture)? Since C compilers do exist for Xtensa (both Arduino and ESIF) , is it at all possible to port Plan 9 C compilers using a "host" compiler as a semi-b

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

you are one of the few who could pull that off. the alternative would be to send the board to cinap, and he'd probably deploy a compiler+kernel in a couple of weeks. On Fri, Jul 26, 2019, 12:31 PM Charles Forsyth wrote: > I was thinking of doing that since I've got an ESP-32 for some reason > >

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

I was thinking of doing that since I've got an ESP-32 for some reason On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic wrote: > I was reading the post Why Didn't Plan 9 Succeed > on Hacker News. > > Made me think that Plan 9 for IoT system of systems co

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

there is not. contributions are welcome. :) -rodri On Fri, Jul 26, 2019, 8:38 AM Cyber Fonic wrote: > I was reading the post Why Didn't Plan 9 Succeed > on Hacker News. > > Made me think that Plan 9 for IoT system of systems could be viable. > >

[9fans] Plan 9 C compiler for Xtensa CPUs

I was reading the post Why Didn't Plan 9 Succeed on Hacker News. Made me think that Plan 9 for IoT system of systems could be viable. To that end, ESP-32 modules look capable enough to run Plan 9, but is there a Plan 9 C compiler for Xtensa ISA CPUs