[USRP-users] Re: Question: maximum single channel sample rate on X410 with DPDK
per...@o2.pl wrote: > Hello, > > It seems that I have to answer my own question. Currently I succeeded to get > 245.76MSamp/s in benchmark_rate for single channel with DPDK over single > 10Gbit link for an RFSoC device similar to USRP X410. > > My setup: > > * UHD 4.3, Ubuntu 20.04, DPDK 19.11 installed from packages > > * command: benchmark_rate --rx_subdev "A:0" --rx_channels 0 > --args="addr=192.168.10.2,mgmt_addr=192.168.0.39,use_dpdk=1" --rx_rate > 245.76e6 > > * Hardware: AMD Ryzen Threadripper 2990WX, 128GB RAM, motherboard Asus X399 > > This is not a mind-blowing rate, because I’m able to get quite stable 245.76 > MSamp/s without DPDK. > > But it is a good start taking into account number of different strange steps > during DPDK installation and setup and very poor performance at the beginning. > > Solutions to some issues were totally counterintuitive. I.e. in the end I > still had one \~oveflow per second at 245.76MSamp rate. The solution was to > run the program WITHOUT root rights/sudo (what requires additional steps that > were described by Rob Kossler). > > —\ > Best Regards,\ > Piotr Krysik > > Piotr Krysik wrote: > > > Hello all, > > > > Has anybody tried to use DPDK with USRP X410? > > > > If yes - can you share what was maximal sample rate for a single channel > > that you were able to stream over 10G or 100G Ethernet connection > > without loss and what was your setup (hardware and software)? Little update: currently with the same setup but with different clocks configuration I can record 256MS/s. This is with use of single 10GbE connection. I can’t use multiple connections simultaneously to transfer more channels with maximum rate yet. If someone tried that with USRP X410 I would be grateful for information how it worked (or didn’t work). Best Regards,\ Piotr Krysik ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: AXI_RAM_FIFO doesn´t return any information
You mentioned you don't receive any ready. Do you mean that the tready
signal never asserts on your output port? It is not allowed in AXI-Stream
to wait for tready to assert before asserting tvalid. Some devices will
assert tready before tvalid asserts, but some won't. You need to assert
tvalid when you have data to send. The receiving device will assert tready
when it is ready to accept data.
You also said that you do not receive any valid. I assume you mean that
tvalid never asserts on your input port. That would indicate that no data
is making it to your block. That could be a software issue, or perhaps
something wrong in your YAML file or your block's code. Perhaps a missing
clock connection?
Wade
On Thu, Oct 27, 2022 at 6:58 AM wrote:
> Hello everyone,
>
> I am trying to make use of axi_ram_fifo together with a rfnoc block of my
> own. Basically, my block receives 2 inputs (one from outside and one from
> FIFO) and sends 2 outputs (one to outside and one toFIFO) . These are
> converted to the payload and function of my block is to store the data my
> block receives from a specific value and receives them later from FIFO
> after some time. I had thought the control by means of the valid of sending
> to FIFO and the ready of reception from FIFO. However, when I synthesize
> and execute, I do not receive any data and checking I have realized that I
> do not receive any ready (when I am going to send) nor any valid (when I am
> going to receive) from the axi_ram_fifo block.
>
> I don't know if the error is in the conversion from chdr to payload
> because, I get the ready from the context but I really don't know.
>
> In my e320 synthesis file I have the connections like this:
>
> Memory characteristics are: 64 mem_data, 31 addres and 1 port.
>
> # MioRAM0 to fifo0(0)
>
> - { srcblk: MioRAM0,srcport: out_1, dstblk: fifo0, dstport: in_0 }
>
> - { srcblk: fifo0, srcport: out_0, dstblk: MioRAM0,dstport: in_1 }
>
> # Custom block connection: ep4 to MioRAM0 and MioRAM0 to ep4
>
> - { srcblk: ep2, srcport: out0, dstblk: MioRAM0, dstport: in_0 }
>
> - { srcblk: MioRAM0, srcport: out_0, dstblk: ep2, dstport: in0 }
>
>
>
> - { srcblk: fifo0,srcport: axi_ram, dstblk: _device_, dstport:
> dram}
>
>
> Thanks in advance.
>
>
> Adrian CR
> ___
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>
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[USRP-users] Re: Simulation for RFNoC block input signal
Yes. Take a look at the gain OOT RFNoC block example: https://github.com/EttusResearch/uhddev/blob/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain_tb.sv For example, here it generates test input data: https://github.com/EttusResearch/uhddev/blob/1be0f33bf32fd319facc654cb515449d968ea05f/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain_tb.sv#L258 This is then sent using send_items() and the block's output is received using recv_items(). Most of the RFNoC blocks have examples of doing something like this. Wade On Wed, Oct 26, 2022 at 9:41 PM Xingjian Chen wrote: > Hi there, > I am creating an OOT RFNoC block that does pulse average for X310. In a > simulation, can you generate and manipulate input payload stream data? > Could anyone point a direction about which file can feed the RFNoC > simulation a customized waveform? Thank you. > ___ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: AXI_RAM_FIFO doesn´t return any information
Hello,
I managed to receive the respective values of m_ready and s_valid. The
problem I think was that I was doing a conversion to chdr-payload and I was
not receiving data. Now I have done a chdr to chdr data and I am receiving
the expected values of these flags. Now I have the problem of how to create
the chdr data. I don't know if any of the 64 bits has to have a special
value. I have seen several schemes but I am not clear about the scheme.
Thanks in advance
Adrian
El vie, 28 oct 2022 16:03, Wade Fife escribió:
> You mentioned you don't receive any ready. Do you mean that the tready
> signal never asserts on your output port? It is not allowed in AXI-Stream
> to wait for tready to assert before asserting tvalid. Some devices will
> assert tready before tvalid asserts, but some won't. You need to assert
> tvalid when you have data to send. The receiving device will assert tready
> when it is ready to accept data.
>
> You also said that you do not receive any valid. I assume you mean that
> tvalid never asserts on your input port. That would indicate that no data
> is making it to your block. That could be a software issue, or perhaps
> something wrong in your YAML file or your block's code. Perhaps a missing
> clock connection?
>
> Wade
>
> On Thu, Oct 27, 2022 at 6:58 AM wrote:
>
>> Hello everyone,
>>
>> I am trying to make use of axi_ram_fifo together with a rfnoc block of my
>> own. Basically, my block receives 2 inputs (one from outside and one from
>> FIFO) and sends 2 outputs (one to outside and one toFIFO) . These are
>> converted to the payload and function of my block is to store the data my
>> block receives from a specific value and receives them later from FIFO
>> after some time. I had thought the control by means of the valid of sending
>> to FIFO and the ready of reception from FIFO. However, when I synthesize
>> and execute, I do not receive any data and checking I have realized that I
>> do not receive any ready (when I am going to send) nor any valid (when I am
>> going to receive) from the axi_ram_fifo block.
>>
>> I don't know if the error is in the conversion from chdr to payload
>> because, I get the ready from the context but I really don't know.
>>
>> In my e320 synthesis file I have the connections like this:
>>
>> Memory characteristics are: 64 mem_data, 31 addres and 1 port.
>>
>> # MioRAM0 to fifo0(0)
>>
>> - { srcblk: MioRAM0,srcport: out_1, dstblk: fifo0, dstport: in_0 }
>>
>> - { srcblk: fifo0, srcport: out_0, dstblk: MioRAM0,dstport: in_1 }
>>
>> # Custom block connection: ep4 to MioRAM0 and MioRAM0 to ep4
>>
>> - { srcblk: ep2, srcport: out0, dstblk: MioRAM0, dstport: in_0 }
>>
>> - { srcblk: MioRAM0, srcport: out_0, dstblk: ep2, dstport: in0 }
>>
>>
>>
>> - { srcblk: fifo0,srcport: axi_ram, dstblk: _device_, dstport:
>> dram}
>>
>>
>> Thanks in advance.
>>
>>
>> Adrian CR
>> ___
>> USRP-users mailing list -- usrp-users@lists.ettus.com
>> To unsubscribe send an email to usrp-users-le...@lists.ettus.com
>>
>
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