Re: [USRP-users] UBX coherence between TX and RX
Hello, If I remove the DSP from the equation by setting the DSP tuning policy to manual and assigning it to zero, I am coherent from tx to rx on all frequencies. I'm now beginning to think that the DSP is doing it's tuning differently for tx and rx. Or there is an accumulated error in opposite directions for both. Thoughts? Leaving the DSP to zero is not a good solution however as there is too much LO leakage. Mike On 03/27/2019 04:58 PM, Marcus D. Leech wrote: On 03/27/2019 04:48 PM, Michael R. Freedman wrote: This is on a single UBX card within a single USRP. ./uhd_usrp_probe --args=addr=192.168.40.100 [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501; UHD_3.14.0.0-0-unknown [INFO] [X300] X300 initialization sequence... [INFO] [X300] Maximum frame size: 8000 bytes. [INFO] [X300] Radio 1x clock: 200 MHz [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D000) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1320 MB/s) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1294 MB/s) [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0) [INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0) _ / | Device: X-Series Device | _ | / | | Mboard: X310 | | revision: 6 | | product: 30410 | | mac-addr0: 00:80:2f:0a:ff:98 | | mac-addr1: 00:80:2f:0a:ff:99 | | gateway: 192.168.10.1 | | ip-addr0: 192.168.10.100 | | subnet0: 255.255.255.0 | | ip-addr1: 192.168.20.100 | | subnet1: 255.255.255.0 | | ip-addr2: 192.168.30.100 | | subnet2: 255.255.255.0 | | ip-addr3: 192.168.40.100 | | subnet3: 255.255.255.0 | | serial: F5BE45 | | FW Version: 6.0 | | FPGA Version: 35.1 | | FPGA git hash: 4c165a5 | | RFNoC capable: Yes | | | | Time sources: internal, external, gpsdo | | Clock sources: internal, external, gpsdo | | Sensors: ref_locked | | _ | | / | | | RX Dboard: A | | | ID: UBX-40 v2 (0x007c) | | | Serial: 313C181 | | | _ | | | / | | | | RX Frontend: 0 | | | | Name: UBX RX | | | | Antennas: TX/RX, RX2, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | | / | | | | RX Codec: A | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _ | | / | | | RX Dboard: B | | | ID: UBX-40 v2 (0x007c) | | | Serial: 313C191 | | | _ | | | / | | | | RX Frontend: 0 | | | | Name: UBX RX | | | | Antennas: TX/RX, RX2, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | | / | | | | RX Codec: B | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _ | | / | | | TX Dboard: A | | | ID: UBX-40 v2 (0x007b) | | | Serial: 313C181 | | | _ | | | / | | | | TX Frontend: 0 | | | | Name: UBX TX | | | | Antennas: TX/RX, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: QI | | | | Uses LO offset: No | | | _ | | | / | | | | TX Codec: A | | | | Name: ad9146 | | | | Gain Elements: None | | _ | | / | | | TX Dboard: B | | | ID: UBX-40 v2 (0x007b) | | | Serial: 313C191 | | | _
Re: [USRP-users] UBX coherence between TX and RX
On 04/05/2019 11:43 AM, Michael R. Freedman wrote: Hello, If I remove the DSP from the equation by setting the DSP tuning policy to manual and assigning it to zero, I am coherent from tx to rx on all frequencies. I'm now beginning to think that the DSP is doing it's tuning differently for tx and rx. Or there is an accumulated error in opposite directions for both. Thoughts? Leaving the DSP to zero is not a good solution however as there is too much LO leakage. Mike I have a query in to Ettus R&D to see if anyone recognizes what might be going on. On 03/27/2019 04:58 PM, Marcus D. Leech wrote: On 03/27/2019 04:48 PM, Michael R. Freedman wrote: This is on a single UBX card within a single USRP. ./uhd_usrp_probe --args=addr=192.168.40.100 [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501; UHD_3.14.0.0-0-unknown [INFO] [X300] X300 initialization sequence... [INFO] [X300] Maximum frame size: 8000 bytes. [INFO] [X300] Radio 1x clock: 200 MHz [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D000) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1320 MB/s) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1294 MB/s) [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0) [INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0) _ / | Device: X-Series Device | _ |/ | | Mboard: X310 | | revision: 6 | | product: 30410 | | mac-addr0: 00:80:2f:0a:ff:98 | | mac-addr1: 00:80:2f:0a:ff:99 | | gateway: 192.168.10.1 | | ip-addr0: 192.168.10.100 | | subnet0: 255.255.255.0 | | ip-addr1: 192.168.20.100 | | subnet1: 255.255.255.0 | | ip-addr2: 192.168.30.100 | | subnet2: 255.255.255.0 | | ip-addr3: 192.168.40.100 | | subnet3: 255.255.255.0 | | serial: F5BE45 | | FW Version: 6.0 | | FPGA Version: 35.1 | | FPGA git hash: 4c165a5 | | RFNoC capable: Yes | | | | Time sources: internal, external, gpsdo | | Clock sources: internal, external, gpsdo | | Sensors: ref_locked | | _ | |/ | | | RX Dboard: A | | | ID: UBX-40 v2 (0x007c) | | | Serial: 313C181 | | | _ | | |/ | | | | RX Frontend: 0 | | | | Name: UBX RX | | | | Antennas: TX/RX, RX2, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | RX Codec: A | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _ | |/ | | | RX Dboard: B | | | ID: UBX-40 v2 (0x007c) | | | Serial: 313C191 | | | _ | | |/ | | | | RX Frontend: 0 | | | | Name: UBX RX | | | | Antennas: TX/RX, RX2, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | RX Codec: B | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _ | |/ | | | TX Dboard: A | | | ID: UBX-40 v2 (0x007b) | | | Serial: 313C181 | | | _ | | |/ | | | | TX Frontend: 0 | | | | Name: UBX TX | | | | Antennas: TX/RX, CAL | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB | | | | Bandwidth range: 4000.0 to 4000.0 step 0.0 Hz | | | | Connection Type: QI | | | | Uses LO offset: No | | | _ | | |/ | | | | TX Codec: A | | | | Name: ad9146 | | | | Gain Elements: None | | ___
[USRP-users] USRP X310 + UBX Daughtercard TX Issue
Hi all, I recently purchased a USRP X310, and a pair of UBX daughter boards, that I would like to use to for waveform testing. However, I have not been able to get basic operation on the radio working properly with GNURadio. I am able to receive a tone when running a receiving GNURadio flowgraph with a 'USRP Source' block using the attached GNURadio flowgraph "x310_receive_test.grc". On the other hand, when I try a transmitting flowgraph with a 'USRP Sink' block fed by any signal (complex sinusoid, noise, constant) using the attached flowgraph "x310_transmit_test.grc", GNURadio stops and no samples seem to be streaming to the device. Once I kill this flowgraph and try to restart it I get the following print out from GNURadio: _[32;1m[INFO] [UHD] _[39;0mlinux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_3.15.0.git-68-gac96d055 _[32;1m[INFO] [X300] _[39;0mX300 initialization sequence... _[32;1m[INFO] [X300] _[39;0mMaximum frame size: 1472 bytes. _[32;1m[INFO] [X300] _[39;0mRadio 1x clock: 200 MHz _[31;0m[ERROR] [UHD] _[39;0mException caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)0u] at /home/lab/latestgnuradio/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52 this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0u; uint64_t = long unsigned int] at /home/lab/latestgnuradio/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142 Traceback (most recent call last): File "/home/lab/x310_transmit_test.py", line 189, in main() File "/home/lab/x310_transmit_test.py", line 177, in main tb = top_block_cls() File "/home/lab/x310_transmit_test.py", line 84, in __init__ channels=range(1), File "/home/lab/latestgnuradio/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py", line 122, in constructor_interceptor return old_constructor(*args) File "/home/lab/latestgnuradio/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 3127, in make return _uhd_swig.usrp_sink_make(*args) RuntimeError: EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0u; uint64_t = long unsigned int] at /home/lab/latestgnuradio/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142 After this point I can't get the USRP to transmit or receive - it appears to be stuck in a bad state. The only way to get the USRP to even receive again is to power cycle the unit. I have a suspicion that something is going wrong between the UHD version/GNURadio version/FPGA image on the USRP, but am not sure how to proceed. I installed what I believe to be the newest version of GNURadio, version 3.7.13.4, using pybombs. For more context, here's what is printed when I call uhd_usrp_probe before getting the radio stuck in this bad state: uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_3.15.0.git-68-gac96d055 [INFO] [X300] X300 initialization sequence... [INFO] [X300] Maximum frame size: 1472 bytes. [INFO] [X300] Radio 1x clock: 200 MHz [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D000) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1318 MB/s) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1299 MB/s) [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001) [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0) [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0) [INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0) _ / | Device: X-Series Device | _ |/ | | Mboard: X310 | | revision: 8 | | revision_compat: 7 | | product: 30818 | | mac-addr0: 00:80:2f:22:c9:26 | | mac-addr1: 00:80:2f:22:c9:27 | | gateway: 192.168.10.1 | | ip-addr0: 10.242.208.15 | | subnet0: 255.255.255.0 | | ip-addr1: 192.168.20.2 | | subnet1: 255.255.255.0 | | ip-addr2: 192.168.30.2 | | subnet2: 255.255.255.0 | | ip-addr3: 192.168.40.2 | | subnet3: 255.255.255.0 | | serial: 3170B0A | | FW Version: 6.0 | | FPGA Version: 36.0 | | FPGA git hash: 4bc2c6f | | RFNoC capable: Yes | | | | Time sources: internal, external, gpsdo | | Clock sources: internal, external, gpsdo | | Sensors: ref_locked | | _ | |/ | | | RX Dboard: A | | |
