[PATCH] rockchip: dts: fix bootph tags for rv1126
RV1126 fails to boot on 2024.01-rc1.
Commit 9e64428 changed the behaviour of bootph-pre-ram, to limit
nodes to spl phase. This caused rv1126 boards to fail to boot
with the current dts.
This patch updates the pmu/grf nodes to bootph-all tags as they are
needed in all phases. This fixes the boot issue on rv1126 boards.
Signed-off-by: Tim Lunn
---
arch/arm/dts/rv1126-u-boot.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi
index 5e348278f2..918c307743 100644
--- a/arch/arm/dts/rv1126-u-boot.dtsi
+++ b/arch/arm/dts/rv1126-u-boot.dtsi
@@ -26,15 +26,15 @@
};
&grf {
- bootph-pre-ram;
+ bootph-all;
};
&pmu {
- bootph-pre-ram;
+ bootph-all;
};
&pmugrf {
- bootph-pre-ram;
+ bootph-all;
};
&xin24m {
--
2.40.1
[PATCH 0/2] rockchip: Support otp on rv1126
This series adds support for reading the otp on rv1126 and then uses this to generate a persistant MAC address from cpuid. Tim Lunn (2): rockchip: otp: Add support for RV1126 rockchip: rv1126: Read cpuid from otp and set ethaddr arch/arm/dts/rv1126-u-boot.dtsi | 12 ++ arch/arm/mach-rockchip/Kconfig | 2 + drivers/misc/rockchip-otp.c | 76 + 3 files changed, 90 insertions(+) base-commit: cbba1b7766bd93d74e28202c46e69095ac13760b -- 2.40.1
[PATCH 1/2] rockchip: otp: Add support for RV1126
Extend the otp driver to read rv1126 otp. This driver code was
adapted from the Rockchip BSP stack.
Signed-off-by: Tim Lunn
---
drivers/misc/rockchip-otp.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 4814e0e501..4f757083a1 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -61,11 +61,20 @@
#define RK3588_OTPC_INT_ST 0x0084
#define RK3588_RD_DONE BIT(1)
+#define RV1126_OTP_NVM_CEB 0x00
+#define RV1126_OTP_NVM_RSTB0x04
+#define RV1126_OTP_NVM_ST 0x18
+#define RV1126_OTP_NVM_RADDR 0x1C
+#define RV1126_OTP_NVM_RSTART 0x20
+#define RV1126_OTP_NVM_RDATA 0x24
+#define RV1126_OTP_READ_ST 0x30
+
struct rockchip_otp_plat {
void __iomem *base;
};
struct rockchip_otp_data {
+ int (*init)(struct udevice *dev);
int (*read)(struct udevice *dev, int offset, void *buf, int size);
int offset;
int size;
@@ -232,6 +241,48 @@ static int rockchip_rk3588_otp_read(struct udevice *dev,
int offset,
return 0;
}
+static int rockchip_rv1126_otp_init(struct udevice *dev)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ int ret;
+
+ writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
+ ret = rockchip_otp_poll_timeout(otp, 0x1, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
+ ret = rockchip_otp_poll_timeout(otp, 0x4, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_rv1126_otp_read(struct udevice *dev, int offset, void *buf,
+ int size)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ u32 status = 0;
+ u8 *buffer = buf;
+ int ret = 0;
+
+ while (size--) {
+ writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
+ ret = readl_poll_timeout(otp->base + RV1126_OTP_READ_ST,
+status, !status, OTPC_TIMEOUT);
+ if (ret)
+ return ret;
+
+ *buffer++ = (u8)(readl(otp->base + RV1126_OTP_NVM_RDATA) &
0xFF);
+ }
+
+ return 0;
+}
+
static int rockchip_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
@@ -286,6 +337,20 @@ static int rockchip_otp_of_to_plat(struct udevice *dev)
return 0;
}
+static int rockchip_otp_probe(struct udevice *dev)
+{
+ struct rockchip_otp_data *data;
+
+ data = (struct rockchip_otp_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ if (data->init)
+ return data->init(dev);
+
+ return 0;
+}
+
static const struct rockchip_otp_data px30_data = {
.read = rockchip_px30_otp_read,
.size = 0x40,
@@ -304,6 +369,12 @@ static const struct rockchip_otp_data rk3588_data = {
.block_size = 4,
};
+static const struct rockchip_otp_data rv1126_data = {
+ .init = rockchip_rv1126_otp_init,
+ .read = rockchip_rv1126_otp_read,
+ .size = 0x40,
+};
+
static const struct udevice_id rockchip_otp_ids[] = {
{
.compatible = "rockchip,px30-otp",
@@ -321,6 +392,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
},
+ {
+ .compatible = "rockchip,rv1126-otp",
+ .data = (ulong)&rv1126_data,
+ },
{}
};
@@ -331,4 +406,5 @@ U_BOOT_DRIVER(rockchip_otp) = {
.of_to_plat = rockchip_otp_of_to_plat,
.plat_auto = sizeof(struct rockchip_otp_plat),
.ops = &rockchip_otp_ops,
+ .probe = rockchip_otp_probe,
};
--
2.40.1
[PATCH 2/2] rockchip: rv1126: Read cpuid from otp and set ethaddr
Provide configuration to read cpuid and generate a persistant
MAC address in ethaddr
Signed-off-by: Tim Lunn
---
arch/arm/dts/rv1126-u-boot.dtsi | 12
arch/arm/mach-rockchip/Kconfig | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi
index 5e348278f2..811a3cee98 100644
--- a/arch/arm/dts/rv1126-u-boot.dtsi
+++ b/arch/arm/dts/rv1126-u-boot.dtsi
@@ -15,6 +15,18 @@
compatible = "rockchip,rv1126-dmc";
bootph-all;
};
+
+ otp: otp@ff5c {
+ compatible = "rockchip,rv1126-otp";
+ reg = <0xff5c 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
};
&gpio0 {
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a6c69c300d..5e993383cf 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -359,6 +359,8 @@ config ROCKCHIP_RV1126
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
+ imply ROCKCHIP_OTP
+ imply MISC_INIT_R
imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
--
2.40.1
Re: PSCI: prefetch abort with Mainline linux (even with rockchip u-boot)
Hi Jagan, On 10/23/22 01:35, Jagan Teki wrote: Hi Kever and Heiko, Rockchip 32-bit SoC, like rv1126 seems to depend on PSCI to bring SMP in linux. With rockchip u-boot and Mainline U-Boot the psci in linux-next triggers the abort. (note that I have added rockchip_smcc and enabled PSCI in u-boot) Did you ever find a solution to this? I am hitting the same issue building 6.1 kernel for rv1126. [0.00] Booting Linux on physical CPU 0xf00 [0.00] Linux version 6.1.0-rc1-00029-gb09e57e6064a (j@j-ThinkPad-E14-Gen-2) (arm-linux-gnueabihf-gcc (GCC) 11.0.1 20210310 (experimental) [master revision 5987d8a79cda1069c774e5c302d5597310270026], GNU ld (Linaro_Binutils-2021.03) 2.36.50.20210310) #12 SMP Sat Oct 22 19:44:56 IST 2022 [0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [0.00] CPU: div instructions available: patching division code [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] OF: fdt: Machine model: Edgeble Neu2 IO Board [0.00] earlycon: uart8250 at MMIO32 0xff57 (options '') [0.00] printk: bootconsole [uart8250] enabled [0.00] Memory policy: Data cache writealloc [0.00] efi: UEFI not found. [0.00] cma: Reserved 64 MiB at 0x7c00 [0.00] Zone ranges: [0.00] DMA [mem 0x-0x2fff] [0.00] Normal empty [0.00] HighMem [mem 0x3000-0x7fff] [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x-0x7fff] [0.00] Initmem setup node 0 [mem 0x-0x7fff] [0.00] psci: probing for conduit method from DT. [0.00] Bad mode in prefetch abort handler detected [0.00] Internal error: Oops - bad mode: 0 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 6.1.0-rc1-00029-gb09e57e6064a #12 [0.00] Hardware name: Generic DT based system [0.00] PC is at 0x133fd468 [0.00] LR is at __invoke_psci_fn_smc+0x38/0x58 [0.00] pc : [<133fd468>]lr : []psr: 61d6 [0.00] sp : c1e01e68 ip : c1e01ec0 fp : 8200 [0.00] r10: c1e01f58 r9 : 7fff r8 : c1e09410 [0.00] r7 : r6 : r5 : r4 : [0.00] r3 : r2 : r1 : r0 : 8400 [0.00] Flags: nZCv IRQs off FIQs off Mode MON_32 ISA ARM Segment none [0.00] Control: 10c5387d Table: 0020406a DAC: c1e09980 [0.00] Register r0 information: non-paged memory [0.00] Register r1 information: NULL pointer [0.00] Register r2 information: NULL pointer [0.00] Register r3 information: NULL pointer [0.00] Register r4 information: NULL pointer [0.00] Register r5 information: NULL pointer [0.00] Register r6 information: NULL pointer [0.00] Register r7 information: NULL pointer [0.00] Register r8 information: non-slab/vmalloc memory [0.00] Register r9 information: non-paged memory [0.00] Register r10 information: non-slab/vmalloc memory [0.00] Register r11 information: non-paged memory [0.00] Register r12 information: non-slab/vmalloc memory [0.00] Process swapper (pid: 0, stack limit = 0x(ptrval)) [0.00] Stack: (0xc1e01e68 to 0xc1e02000) [0.00] 1e60: 8400 [0.00] 1e80: c1e09410 7fff c1e01f58 8200 c1e01ec0 c1e01e68 [0.00] 1ea0: c0eb20f0 133fd468 61d6 c1e09980 c20891c0 c1b1c168 [0.00] 1ec0: c1e01edc c20891c0 c1245ac8 [0.00] 1ee0: ff8005a8 c1d2fca0 eefea2fc c1c93594 eefea2fc c1e09980 [0.00] 1f00: c20891c0 c1b1c168 c1e09410 c1c93a10 eefea2fc c1c939d8 c1d2fbdc [0.00] 1f20: 7fff c1caf854 c1e0afa0 c1c04c44 c1e01f4c c1e01f50 [0.00] 1f40: c1e09980 c198cfec c1e01f9c 8000 c1e09980 [0.00] 1f60: c2089064 0830 410fc075 10c5387d c039de88 c1e01f9c [0.00] 1f80: c1e09980 c1c00420 c1e04ec0 c1e09980 c2089064 0830 410fc075 10c5387d [0.00] 1fa0: c1c00b08 [0.00] 1fc0: c1cc8a6c c1c00420 0051 10c0387d [0.00] 1fe0: 0830 410fc075 10c5387d [0.00] __invoke_psci_fn_smc from 0xc1e01e68 [0.00] Code: bad PC value Any comments? Thanks, Jagan.
[PATCH 0/5] rockchip: Add support for rv1126 based Sonoff iHost Gateway
Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. It features Wifi, BT and Zigbee radios as required by many smart home devices. Features: - Rockchip RV1126 - 4GB DDR4 - 8GB eMMC - microSD slot - RMII Ethernet PHY - 1x USB 2.0 Host - 1x USB 2.0 OTG - Realtek RTL8723DS WiFi/BT - EFR32MG21 Silabs Zigbee radio - Speaker/Microphone Sync rv1126 dts from linux v6.8-rc1, add support for ddr4 ram and add board support for the Sonoff ihost. Tim Lunn (5): arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1 ram: rockchip: Add rv1126 ddr4 support board: rockchip: Add Sonoff iHost board rockchip: rv1126: select SPL_OPTEE_IMAGE rockchip: rv1126: Move RAM disk address arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70 +++ arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +- arch/arm/dts/rv1126-pinctrl.dtsi | 130 ++ arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 + arch/arm/dts/rv1126-sonoff-ihost.dts | 29 ++ arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ++ arch/arm/dts/rv1126.dtsi | 185 arch/arm/mach-rockchip/Kconfig| 1 + arch/arm/mach-rockchip/rv1126/Kconfig | 8 + board/itead/sonoff-ihost/Kconfig | 16 + board/itead/sonoff-ihost/MAINTAINERS | 6 + configs/sonoff-ihost-rv1126_defconfig | 60 +++ .../sdram-rv1126-ddr4-detect-1056.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 drivers/ram/rockchip/sdram_rv1126.c | 8 + include/configs/rv1126_common.h | 2 +- include/configs/sonoff-ihost.h| 18 + 22 files changed, 1491 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi create mode 100644 board/itead/sonoff-ihost/Kconfig create mode 100644 board/itead/sonoff-ihost/MAINTAINERS create mode 100644 configs/sonoff-ihost-rv1126_defconfig create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc create mode 100644 include/configs/sonoff-ihost.h -- 2.40.1
[PATCH 1/5] arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn
---
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +-
arch/arm/dts/rv1126-pinctrl.dtsi| 130
arch/arm/dts/rv1126-sonoff-ihost.dts| 29 ++
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404
arch/arm/dts/rv1126.dtsi| 185 +++
6 files changed, 835 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
index dded0a12f0..0c2396b8f8 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -20,6 +20,76 @@
chosen {
stdout-path = "serial2:150n8";
};
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ v3v3_sys: v3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&gmac {
+ assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+ <&cru CLK_GMAC_ETHERNET_OUT>;
+ assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+ assigned-clock-rates = <12500>, <0>, <2500>;
+ clock_in_out = "input";
+ phy-handle = <&phy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4
&clk_out_ethernetm1_pins>;
+ tx_delay = <0x2a>;
+ rx_delay = <0x1a>;
+ status = "okay";
+};
+
+&mdio {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916",
+"ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_phy_rst>;
+ reset-assert-us = <2>;
+ reset-deassert-us = <10>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm11 {
+ status = "okay";
};
&sdmmc {
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
index cc64ba4be3..7ea8d7d16f 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -11,15 +11,6 @@
mmc0 = &emmc;
};
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -52,7 +43,7 @@
bus-width = <8>;
non-removable;
pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_flash>;
@@ -301,6 +292,22 @@
status = "okay";
[PATCH 2/5] ram: rockchip: Add rv1126 ddr4 support
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn
---
.../sdram-rv1126-ddr4-detect-1056.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 +++
drivers/ram/rockchip/sdram_rv1126.c | 8 ++
8 files changed, 533 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
new file mode 100644
index 00..295b0871e0
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
@@ -0,0 +1,75 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x2,
+ .bw = 0x1,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x0,
+ .cs0_high16bit_row = 0x11,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x561d1219},
+ {0x10030703},
+ {0x0002},
+ {0x},
+ {0x000c},
+ {0x034b},
+ 0x00ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = DDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x, 0x43041010}, /* MSTR */
+ {0x0064, 0x008000b9}, /* RFSHTMG */
+ {0x00d0, 0x00020103}, /* INIT0 */
+ {0x00d4, 0x0069}, /* INIT1 */
+ {0x00d8, 0x0100}, /* INIT2 */
+ {0x00dc, 0x07340401}, /* INIT3 */
+ {0x00e0, 0x0010}, /* INIT4 */
+ {0x00e4, 0x0011}, /* INIT5 */
+ {0x00e8, 0x0420}, /* INIT6 */
+ {0x00ec, 0x0800}, /* INIT7 */
+ {0x00f4, 0x000f011f}, /* RANKCTL */
+ {0x0100, 0x0f102411}, /* DRAMTMG0 */
+ {0x0104, 0x0004041a}, /* DRAMTMG1 */
+ {0x0108, 0x0608060d}, /* DRAMTMG2 */
+ {0x010c, 0x0040400c}, /* DRAMTMG3 */
+ {0x0110, 0x08030409}, /* DRAMTMG4 */
+ {0x0114, 0x06060403}, /* DRAMTMG5 */
+ {0x0120, 0x07070d07}, /* DRAMTMG8 */
+ {0x0124, 0x00020309}, /* DRAMTMG9 */
+ {0x0180, 0x0140}, /* ZQCTL0 */
+ {0x0184, 0x}, /* ZQCTL1 */
+ {0x0190, 0x07060004}, /* DFITMG0 */
+ {0x0198, 0x07000101}, /* DFILPCFG0 */
+ {0x01a0, 0xc043}, /* DFIUPD0 */
+ {0x0240, 0x06000614}, /* ODTCFG */
+ {0x0244, 0x0201}, /* ODTMAP */
+ {0x0250, 0x1f00}, /* SCHED */
+ {0x0490, 0x0001}, /* PCTRL_0 */
+ {0x, 0x}
+ }
+ },
+ {
+ {
+ {0x0004, 0x008c}, /* PHYREG01 */
+ {0x0014, 0x0010}, /* PHYREG05 */
+ {0x0018, 0x}, /* PHYREG06 */
+ {0x001c, 0x000b}, /* PHYREG07 */
+ {0x, 0x
[PATCH 3/5] board: rockchip: Add Sonoff iHost board
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn
---
arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 +
arch/arm/mach-rockchip/rv1126/Kconfig| 8 +++
board/itead/sonoff-ihost/Kconfig | 16 ++
board/itead/sonoff-ihost/MAINTAINERS | 6 ++
configs/sonoff-ihost-rv1126_defconfig| 60
include/configs/sonoff-ihost.h | 18 ++
6 files changed, 121 insertions(+)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
create mode 100644 board/itead/sonoff-ihost/Kconfig
create mode 100644 board/itead/sonoff-ihost/MAINTAINERS
create mode 100644 configs/sonoff-ihost-rv1126_defconfig
create mode 100644 include/configs/sonoff-ihost.h
diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
new file mode 100644
index 00..a625660d58
--- /dev/null
+++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rv1126-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&sdio {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig
b/arch/arm/mach-rockchip/rv1126/Kconfig
index a6e2b5903c..55b1112120 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2
IO board and Neu2 needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
+config TARGET_RV1126_SONOFF_IHOST
+ bool "Sonoff iHost smart home hub"
+ help
+ Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC.
+ It features Wifi, Bluetooth and Zigbee radios that are used by many
+ smart home devices.
+
config SOC_SPECIFIC_OPTIONS # dummy
def_bool y
select HAS_CUSTOM_SYS_INIT_SP_ADDR
@@ -58,5 +65,6 @@ config TEXT_BASE
default 0x60
source board/edgeble/neural-compute-module-2/Kconfig
+source board/itead/sonoff-ihost/Kconfig
endif
diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig
new file mode 100644
index 00..30d9a6b3e6
--- /dev/null
+++ b/board/itead/sonoff-ihost/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_RV1126_SONOFF_IHOST
+
+config SYS_BOARD
+ default "sonoff-ihost"
+
+config SYS_VENDOR
+ default "itead"
+
+config SYS_CONFIG_NAME
+ default "sonoff-ihost"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_ROCKCHIP_DDR4
+
+endif
diff --git a/board/itead/sonoff-ihost/MAINTAINERS
b/board/itead/sonoff-ihost/MAINTAINERS
new file mode 100644
index 00..eff9274bea
--- /dev/null
+++ b/board/itead/sonoff-ihost/MAINTAINERS
@@ -0,0 +1,6 @@
+RV1126-SONOFF-IHOST
+M: Tim Lunn
+S: Maintained
+F: board/itead/sonoff-ihost
+F: include/configs/sonoff-ihost.h
+F: configs/sonoff-ihost-rv1126_defconfig
diff --git a/configs/sonoff-ihost-rv1126_defconfig
b/configs/sonoff-ihost-rv1126_defconfig
new file mode 100644
index 00..fe99bd92f9
--- /dev/null
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_SYS_MONITOR_LEN=614400
+CONFIG_ROCKCHIP_RV1126=y
+CONFIG_TARGET_RV1126_SONOFF_IHOST=y
+CONFIG_DEBUG_UART_BASE=0xff57
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xe00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+
[PATCH 4/5] rockchip: rv1126: select SPL_OPTEE_IMAGE
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux kernel will fail to boot without this. Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided when building. Signed-off-by: Tim Lunn --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911..cce118a004 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R -- 2.40.1
[PATCH 5/5] rockchip: rv1126: Move RAM disk address
OPTEE gets loaded into a memory region overlapping with the ram disk. Fix the ramdisk address so it doesn't overlap with the OPTEE memory region. Signed-off-by: Tim Lunn --- include/configs/rv1126_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c6364..6961dbe20b 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x0830\0" \ "fdtoverlay_addr_r=0x0200\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a20\0" + "ramdisk_addr_r=0x0a40\0" #include #define CFG_EXTRA_ENV_SETTINGS \ -- 2.40.1
Re: [PATCH 3/5] board: rockchip: Add Sonoff iHost board
Hi Tom, On 1/23/24 02:36, Tom Rini wrote: On Mon, Jan 22, 2024 at 11:46:01PM +1100, Tim Lunn wrote: Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. There is also a version with 2GB RAM based off the RV1109 dual core SoC however this works with the same config as the RV1126 for uboot purposes. [snip] diff --git a/include/configs/sonoff-ihost.h b/include/configs/sonoff-ihost.h new file mode 100644 index 00..8ed5d78687 --- /dev/null +++ b/include/configs/sonoff-ihost.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SONOFF_IHOST_H +#define __SONOFF_IHOST_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#include + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#endif /* __SONOFF_IHOST_H */ We should be using standard boot, which removes most of this, thanks. Thanks for the tip, I will check this out and fix for v2. Regards Tim
[PATCH v2 0/6] rockchip: Add support for rv1126 based Sonoff iHost Gateway
Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. It features Wifi, BT and Zigbee radios as required by many smart home devices. Features: - Rockchip RV1126 - 4GB DDR4 - 8GB eMMC - microSD slot - RMII Ethernet PHY - 1x USB 2.0 Host - 1x USB 2.0 OTG - Realtek RTL8723DS WiFi/BT - EFR32MG21 Silabs Zigbee radio - Speaker/Microphone Sync rv1126 dts from linux v6.8-rc1, add support for ddr4 ram and add board support for the Sonoff ihost. Changes in v2: - New patch to clean up distro boot from rv1126_common.h - Remove board config not required with standard boot Tim Lunn (6): arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1 ram: rockchip: Add rv1126 ddr4 support rockchip: Convert rv1126 to standard boot board: rockchip: Add Sonoff iHost board rockchip: rv1126: select SPL_OPTEE_IMAGE rockchip: rv1126: Move RAM disk address arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70 +++ arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +- arch/arm/dts/rv1126-pinctrl.dtsi | 130 ++ arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 + arch/arm/dts/rv1126-sonoff-ihost.dts | 29 ++ arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ++ arch/arm/dts/rv1126.dtsi | 185 arch/arm/mach-rockchip/Kconfig| 1 + arch/arm/mach-rockchip/rv1126/Kconfig | 8 + board/itead/sonoff-ihost/Kconfig | 16 + board/itead/sonoff-ihost/MAINTAINERS | 6 + configs/sonoff-ihost-rv1126_defconfig | 60 +++ doc/board/rockchip/rockchip.rst | 1 + .../sdram-rv1126-ddr4-detect-1056.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 drivers/ram/rockchip/sdram_rv1126.c | 8 + include/configs/neural-compute-module-2.h | 6 - include/configs/rv1126_common.h | 5 +- include/configs/sonoff-ihost.h| 10 + 24 files changed, 1485 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi create mode 100644 board/itead/sonoff-ihost/Kconfig create mode 100644 board/itead/sonoff-ihost/MAINTAINERS create mode 100644 configs/sonoff-ihost-rv1126_defconfig create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc create mode 100644 include/configs/sonoff-ihost.h -- 2.40.1
[PATCH v2 1/6] arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn
---
(no changes since v1)
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +-
arch/arm/dts/rv1126-pinctrl.dtsi| 130
arch/arm/dts/rv1126-sonoff-ihost.dts| 29 ++
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404
arch/arm/dts/rv1126.dtsi| 185 +++
6 files changed, 835 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
index dded0a12f0..0c2396b8f8 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -20,6 +20,76 @@
chosen {
stdout-path = "serial2:150n8";
};
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ v3v3_sys: v3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&gmac {
+ assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+ <&cru CLK_GMAC_ETHERNET_OUT>;
+ assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+ assigned-clock-rates = <12500>, <0>, <2500>;
+ clock_in_out = "input";
+ phy-handle = <&phy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4
&clk_out_ethernetm1_pins>;
+ tx_delay = <0x2a>;
+ rx_delay = <0x1a>;
+ status = "okay";
+};
+
+&mdio {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916",
+"ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_phy_rst>;
+ reset-assert-us = <2>;
+ reset-deassert-us = <10>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm11 {
+ status = "okay";
};
&sdmmc {
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
index cc64ba4be3..7ea8d7d16f 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -11,15 +11,6 @@
mmc0 = &emmc;
};
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -52,7 +43,7 @@
bus-width = <8>;
non-removable;
pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_flash>;
@@ -301,6 +292,22 @@
status
[PATCH v2 2/6] ram: rockchip: Add rv1126 ddr4 support
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn
---
(no changes since v1)
.../sdram-rv1126-ddr4-detect-1056.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 +++
drivers/ram/rockchip/sdram_rv1126.c | 8 ++
8 files changed, 533 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
new file mode 100644
index 00..295b0871e0
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
@@ -0,0 +1,75 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x2,
+ .bw = 0x1,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x0,
+ .cs0_high16bit_row = 0x11,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x561d1219},
+ {0x10030703},
+ {0x0002},
+ {0x},
+ {0x000c},
+ {0x034b},
+ 0x00ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = DDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x, 0x43041010}, /* MSTR */
+ {0x0064, 0x008000b9}, /* RFSHTMG */
+ {0x00d0, 0x00020103}, /* INIT0 */
+ {0x00d4, 0x0069}, /* INIT1 */
+ {0x00d8, 0x0100}, /* INIT2 */
+ {0x00dc, 0x07340401}, /* INIT3 */
+ {0x00e0, 0x0010}, /* INIT4 */
+ {0x00e4, 0x0011}, /* INIT5 */
+ {0x00e8, 0x0420}, /* INIT6 */
+ {0x00ec, 0x0800}, /* INIT7 */
+ {0x00f4, 0x000f011f}, /* RANKCTL */
+ {0x0100, 0x0f102411}, /* DRAMTMG0 */
+ {0x0104, 0x0004041a}, /* DRAMTMG1 */
+ {0x0108, 0x0608060d}, /* DRAMTMG2 */
+ {0x010c, 0x0040400c}, /* DRAMTMG3 */
+ {0x0110, 0x08030409}, /* DRAMTMG4 */
+ {0x0114, 0x06060403}, /* DRAMTMG5 */
+ {0x0120, 0x07070d07}, /* DRAMTMG8 */
+ {0x0124, 0x00020309}, /* DRAMTMG9 */
+ {0x0180, 0x0140}, /* ZQCTL0 */
+ {0x0184, 0x}, /* ZQCTL1 */
+ {0x0190, 0x07060004}, /* DFITMG0 */
+ {0x0198, 0x07000101}, /* DFILPCFG0 */
+ {0x01a0, 0xc043}, /* DFIUPD0 */
+ {0x0240, 0x06000614}, /* ODTCFG */
+ {0x0244, 0x0201}, /* ODTMAP */
+ {0x0250, 0x1f00}, /* SCHED */
+ {0x0490, 0x0001}, /* PCTRL_0 */
+ {0x, 0x}
+ }
+ },
+ {
+ {
+ {0x0004, 0x008c}, /* PHYREG01 */
+ {0x0014, 0x0010}, /* PHYREG05 */
+ {0x0018, 0x}, /* PHYREG06 */
+ {0x001c, 0x000b}, /* PHYREG07
[PATCH v2 3/6] rockchip: Convert rv1126 to standard boot
RV1126 soc appears to have been missed with the conversion of rockchip socs to standard boot. Remove remnants of distro boot for rv1126 common and the one existing board. Signed-off-by: Tim Lunn Link: https://lore.kernel.org/all/20230407223645.v8.8.I4cf7708a1ba953b9abd81375d93af34665c7b251@changeid/ --- Changes in v2: - New patch to clean up distro boot from rv1126_common.h include/configs/neural-compute-module-2.h | 6 -- include/configs/rv1126_common.h | 3 +-- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/include/configs/neural-compute-module-2.h b/include/configs/neural-compute-module-2.h index f0934ae00c..43a560906a 100644 --- a/include/configs/neural-compute-module-2.h +++ b/include/configs/neural-compute-module-2.h @@ -12,10 +12,4 @@ #include -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - #endif /* __NEURAL_COMPUTE_MODULE_2_H */ diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c6364..168cd8b167 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -28,7 +28,6 @@ "kernel_addr_r=0x02008000\0" \ "ramdisk_addr_r=0x0a20\0" -#include #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \ "initrd_high=0x0fff\0" \ @@ -36,6 +35,6 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + "boot_targets=" BOOT_TARGETS "\0" #endif /* __CONFIG_RV1126_COMMON_H */ -- 2.40.1
[PATCH v2 4/6] board: rockchip: Add Sonoff iHost board
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn
---
Changes in v2:
- Remove board config not required with standard boot
arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 +
arch/arm/mach-rockchip/rv1126/Kconfig| 8 +++
board/itead/sonoff-ihost/Kconfig | 16 ++
board/itead/sonoff-ihost/MAINTAINERS | 6 ++
configs/sonoff-ihost-rv1126_defconfig| 60
doc/board/rockchip/rockchip.rst | 1 +
include/configs/sonoff-ihost.h | 10
7 files changed, 114 insertions(+)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
create mode 100644 board/itead/sonoff-ihost/Kconfig
create mode 100644 board/itead/sonoff-ihost/MAINTAINERS
create mode 100644 configs/sonoff-ihost-rv1126_defconfig
create mode 100644 include/configs/sonoff-ihost.h
diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
new file mode 100644
index 00..a625660d58
--- /dev/null
+++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rv1126-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&sdio {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig
b/arch/arm/mach-rockchip/rv1126/Kconfig
index a6e2b5903c..55b1112120 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2
IO board and Neu2 needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
+config TARGET_RV1126_SONOFF_IHOST
+ bool "Sonoff iHost smart home hub"
+ help
+ Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC.
+ It features Wifi, Bluetooth and Zigbee radios that are used by many
+ smart home devices.
+
config SOC_SPECIFIC_OPTIONS # dummy
def_bool y
select HAS_CUSTOM_SYS_INIT_SP_ADDR
@@ -58,5 +65,6 @@ config TEXT_BASE
default 0x60
source board/edgeble/neural-compute-module-2/Kconfig
+source board/itead/sonoff-ihost/Kconfig
endif
diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig
new file mode 100644
index 00..30d9a6b3e6
--- /dev/null
+++ b/board/itead/sonoff-ihost/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_RV1126_SONOFF_IHOST
+
+config SYS_BOARD
+ default "sonoff-ihost"
+
+config SYS_VENDOR
+ default "itead"
+
+config SYS_CONFIG_NAME
+ default "sonoff-ihost"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_ROCKCHIP_DDR4
+
+endif
diff --git a/board/itead/sonoff-ihost/MAINTAINERS
b/board/itead/sonoff-ihost/MAINTAINERS
new file mode 100644
index 00..eff9274bea
--- /dev/null
+++ b/board/itead/sonoff-ihost/MAINTAINERS
@@ -0,0 +1,6 @@
+RV1126-SONOFF-IHOST
+M: Tim Lunn
+S: Maintained
+F: board/itead/sonoff-ihost
+F: include/configs/sonoff-ihost.h
+F: configs/sonoff-ihost-rv1126_defconfig
diff --git a/configs/sonoff-ihost-rv1126_defconfig
b/configs/sonoff-ihost-rv1126_defconfig
new file mode 100644
index 00..fe99bd92f9
--- /dev/null
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_SYS_MONITOR_LEN=614400
+CONFIG_ROCKCHIP_RV1126=y
+CONFIG_TARGET_RV1126_SONOFF_IHOST=y
+CONFIG_DEBUG_UART_BASE=0xff57
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xe00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_
[PATCH v2 5/6] rockchip: rv1126: select SPL_OPTEE_IMAGE
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux kernel will fail to boot without this. Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided when building. Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911..cce118a004 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R -- 2.40.1
[PATCH v2 6/6] rockchip: rv1126: Move RAM disk address
OPTEE gets loaded into a memory region overlapping with the ram disk. Fix the ramdisk address so it doesn't overlap with the OPTEE memory region. Signed-off-by: Tim Lunn --- (no changes since v1) include/configs/rv1126_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index 168cd8b167..ea290f763c 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x0830\0" \ "fdtoverlay_addr_r=0x0200\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a20\0" + "ramdisk_addr_r=0x0a40\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \ -- 2.40.1
Re: [PATCH] board: rockchip: Add Hardkernel ODROID-M1S
Hi, On 1/25/24 22:50, Jonas Karlman wrote: + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; Because this device tree is not yet in linux, hopefully correct props can be applied to device tree and u-boot do not need any overrides. I suppose this pinctrl override was copied from Odroid-M1 where the emmc_rst pin is shared with SPI flash. That is not the case on Odroid-M1S which doesnt have SPI flash. So should be ok to drop this override. Regards Tim
Re: [PATCH v2] rockchip: rv1126: Migrate to OF_UPSTREAM
Hi Anand,
On 5/10/24 14:43, Anand Moon wrote:
Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
Following targets is migrated to use OF_UPSTREAM:
- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.
This looks fine to me.
Tested on Sonoff iHost
Reviewed-By: Tim Lunn
Tested-By: Tim Lunn
Cc: Tim Lunn
Cc: Jagan Teki
Signed-off-by: Anand Moon
---
v2: remove the dt-bindings for clock and power
fix the typo in commit message
Tested on neu2 board.
---
arch/arm/dts/Makefile | 3 -
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 112
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 --
arch/arm/dts/rv1126-pinctrl.dtsi | 341 --
arch/arm/dts/rv1126-sonoff-ihost.dts | 29 -
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ---
arch/arm/dts/rv1126.dtsi | 623 -
arch/arm/mach-rockchip/Kconfig| 1 +
configs/neu2-io-rv1126_defconfig | 2 +-
configs/sonoff-ihost-rv1126_defconfig | 2 +-
.../dt-bindings/clock/rockchip,rv1126-cru.h | 632 --
.../dt-bindings/power/rockchip,rv1126-power.h | 35 -
12 files changed, 3 insertions(+), 2526 deletions(-)
delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
delete mode 100644 arch/arm/dts/rv1126.dtsi
delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 087645f354..79fc100dce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
- rv1126-edgeble-neu2-io.dtb
-
dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
- model = "Edgeble Neu2 IO Board";
- compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:150n8";
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200>;
- regulator-max-microvolt = <1200>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- v3v3_sys: v3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "v3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
- assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
- assigned-clock-rates = <12500>, <0>, <2500>;
- clock_in_out = "input";
- phy-handle = <&phy>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &am
