[PATCH] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
Legacy boot flow (SPL->U-Boot Proper->OS) boot to OS via Kernel Image and dtb files using booti command. ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command. Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim --- include/configs/socfpga_soc64_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index f0b7884ebc..347620e1b5 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -82,7 +82,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Environment variable */ -#ifdef CONFIG_FIT +#if IS_ENABLED(CONFIG_SPL_ATF) #define CONFIG_BOOTFILE "kernel.itb" #else #define CONFIG_BOOTFILE "Image" -- 2.19.0
[v2 00/17] Add Intel N5X SoC support
This is the 2nd version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 1, 4, 5, 7, 11, 12, 13, 15, 17
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 1:
- New patch in n5x series, the change is needed to execute
'linux_qspi_enable' correctly in ATF boot flow
Patch 4:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow
Patch 5:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
Patch 7:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
Patch 11:
- Renamed local variable “total_size” to “remaining_size”
Patch 12:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x
Patch 13:
- No change on the file. Need review again for this patch.
common.h need to be included before clock_manager.h.
Patch 15:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
Patch 17:
- Move linux_qspi_enable from bootcommand
Siew Chin Lim (16):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
arm: socfpga: Add handoff data support for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
ddr: altera: Add SDRAM driver for Intel N5X device
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (1):
ddr: socfpga: Enable memory test on memory size less than 1GB
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 101 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +
arch/arm/dts/socfpga_n5x_socdk.dts| 243 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../{base_addr_s10.h => base_addr_soc64.h}| 11 +-
.../mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h |2 -
.../include/mach/clock_manager_arria10.h |1 -
.../include/mach/clock_manager_gen5.h |1 -
.../include/mach/clock_manager_n5x.h | 12 +
.../include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h | 10 +-
arch/arm/mach-socfpga/misc.c |3 +
.../mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c | 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile|7 +
board/intel/n5x-socdk/socfpga.c |7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...tf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
...ex_atf_defconfig => socfpga_n5x_defconfig} | 29 +-
...tf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig |2 +-
drivers/clk/altera/Makefile |4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 +
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2299 +
[v2 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 5afdb10454..f0b7884ebc 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.19.0
[v2 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
v2:
- New patch in n5x series, the change is needed to execute
'linux_qspi_enable' correctly in ATF boot flow
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122fcd4..f5a3f2ad62 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -115,17 +115,18 @@ void board_fit_image_post_process(void **p_image, size_t
*p_size)
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 0de65a22a0..e0a8714e3d 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index c187987dd8..d0bc5e7909 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.19.0
[v2 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.19.0
[v2 04/17] arm: socfpga: Add handoff data support for Intel N5X device
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow
---
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +-
3 files changed, 136 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux :
SOC64_HANDOFF_MUX_LEN;
- socfpga_handoff_r
[v2 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.19.0
[v2 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
include/dt-bindings/clock/n5x-clock.h | 71
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPI
[v2 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84 +++
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x",
+ .id = UCLASS_CLK,
+
[v2 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...k_manager_agilex.c => clock_manager_n5x.c} | 32 +--
.../mach-socfpga/include/mach/clock_manager.h | 2 ++
.../include/mach/clock_manager_n5x.h | 12 +++
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.19.0
[v2 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.19.0
[v2 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.19.0
[v2 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
v2:
- Renamed local variable “total_size” to “remaining_size”
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.19.0
[v2 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
.../mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.19.0
[v2 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
...ex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++-
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +++
...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 110 +-
4 files changed, 182 insertions(+), 9 deletions(-)
copy arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%)
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (57%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020a0f..2e13277816 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -381,6 +381,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
similarity index 85%
copy from arch/arm/dts/socfpga_agilex-u-boot.dtsi
copy to arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 08f7cf7f7a..2f63f4a4e6 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019-2020 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
@@ -53,6 +53,10 @@
reset-names = "i2c";
};
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
&mmc {
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
};
@@ -76,11 +80,10 @@
};
&sdr {
- compatible = "intel,sdr-ctl-agilex";
- reg = <0xf8000400 0x80>,
- <0xf801 0x190>,
- <0xf8011000 0x500>;
+ compatible = "intel,sdr-ctl-n5x";
resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
new file mode 100644
index 00..57509f083e
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_n5x-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ i2c0 = &i2c1;
+ };
+
+ memory {
+ /*
+* Memory type: DDR4
+* 16GB
+* <0 0x 0 0x8000>,
+* <4 0x8000 3 0x8000>;
+*
+* 8GB
+* <0 0x 0 0x8000>,
+* <2 0x8000 1 0x8000>;
+*
+* 4GB
+* <0 0x 0 0x8000>,
+* <1 0x8000 0 0x8000>;
+*
+* Memory type: LPDDR4 (non-interleaving mode)
+* Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for
secure
+* region.
+*/
+ reg = <0 0x 0 0x6000>,
+ <0x10 0x0010 0 0x4000>;
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&nand {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ drvsel = <3>;
+ smplsel = <0>;
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts
b/arch/arm/dts/socfpga_n5x_socdk.dts
similarity index 57%
copy from arch/arm/dts/socfpga_agilex_socdk.dts
copy to arch/arm/dts/socfpga_n5x_socdk.dts
index bcdeecc0e0..30130bb910 100644
--- a/arch/arm/dts/socfpga_agilex_socdk.dts
+++ b/arch/arm/dts/socfpga_n5x_socdk.dts
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2020-2021, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
+#include
/ {
- model = "SoCFPGA Agilex SoCDK";
+ model = "eASIC N5X SoC
[v2 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
.../{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.19.0
[v2 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h | 10 +-
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2299 +
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2387 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..f86342e4ef
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2299 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
[v2 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.19.0
[v2 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
v2:
- Move linux_qspi_enable from bootcommand
---
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 28 +++
...ab_defconfig => socfpga_n5x_atf_defconfig} | 12
...agilex_defconfig => socfpga_n5x_defconfig} | 14 --
...ab_defconfig => socfpga_n5x_vab_defconfig} | 11
5 files changed, 61 insertions(+), 25 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (82%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..a4d733c756 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -183,6 +199,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -221,6 +239,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl
[v5 00/18] Enable ARM Trusted Firmware for U-Boot
This is the 5th version of patchset to enable ARM Trusted Firmware for U-Boot for Intel Stratix10 and Agilex platform. New U-boot flow with ARM Trusted Firmware (ATF) support: SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1) SPL loads the u-boot.itb which consist of: 1) u-boot-nodtb.bin (U-Boot Proper image) 2) u-boot.dtb (U-Boot Proper DTB) 3) bl31.bin (ATF-BL31 image) Patch status: Have changes: Patch 7, 8, 9, 10, 16, 17 Other patches unchanged. Detail changelog can find in commit message. v4->v5: Patch 7: - Change secure register access helper functions to return error code instead of hang the system if fail to access the secure register. Patch 8: - Change designware MMC driver 'clksel' callback function to return the status. This patch is a preparation for enabling Arm-Trusted-Firmware (ATF) in Intel SoC FPGA. This patch does not change functionality. Patch 9: - Report error if secure register access helper function failed to write SDMMC's DRVSEL and SMPLSEL via SMC call. Patch 10: - Report error if secure register access helper function failed to write PHY register via SMC call. patch 16: - Change 'blob' to 'blob-ext' entry in binman dts node for all input files. patch 17: - Revert all changes about BINMAN in Makefile. History: [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200817043431.28718-1-chee.hong@intel.com/ [v2]: https://patchwork.ozlabs.org/project/uboot/cover/20201001091614.184612-1-elly.siew.chin@intel.com/ [v3]: https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/ [v4]: https://patchwork.ozlabs.org/project/uboot/cover/20201218032853.46839-1-elly.siew.chin@intel.com/ These patchsets have dependency on: arm: socfpga: soc64: Add timeout waiting for NOC idle ACK https://lists.denx.de/pipermail/u-boot/2020-August/423029.html Rename Stratix10 FPGA driver and support Agilex https://lists.denx.de/pipermail/u-boot/2020-August/422798.html SoCFPGA mailbox driver fixes and enhancements https://lists.denx.de/pipermail/u-boot/2020-August/423140.html arm: socfpga: soc64: Initialize timer in SPL only https://lists.denx.de/pipermail/u-boot/2020-July/419692.html arm: socfpga: soc64: Remove PHY interface setup from misc arch init https://lists.denx.de/pipermail/u-boot/2020-July/419690.html Enable sysreset support for SoCFPGA SoC64 platforms https://lists.denx.de/pipermail/u-boot/2020-August/422509.html arm: socfpga: soc64: Disable CONFIG_PSCI_RESET https://lists.denx.de/pipermail/u-boot/2020-August/423373.html *** BLURB HERE *** Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim (4): arm: socfpga: Add secure register access helper functions for SoC 64bits mmc: dwmmc: Change designware MMC 'clksel' callback function to return status arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman arch/arm/dts/socfpga_agilex-u-boot.dtsi| 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 + arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 + arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 + arch/arm/mach-socfpga/board.c | 12 +- .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 + arch/arm/mach-socfpga/lowlevel_init_soc64.S| 76 +++ arch/arm/mach-socfpga/mailbox_s10.c| 5 + arch/arm/mach-socfpga/reset_manager_s10.c | 13 + arch/arm/mach-socfpga/secure_reg_helper.c | 97 arch/arm/mach-socfpga/smc_api.c| 56 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c| 3 +- configs/socfpga_agilex_atf_defconfig | 72 +++ co
[v5 01/18] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.13.0
[v5 02/18] arm: socfpga: soc64: Load FIT image with ATF support
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* CONFIG_BOOTARGS goes into the environment value "bootargs".
* Do note the value will override also the chosen node in FDT blob.
*/
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "kernel.itb"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run
linux_qspi_enable;" \
+ "run mmcfitboot"
+#else
+#define CONFIG_BOOTFILE "Image"
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;"
\
"run mmcboot"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "bootfile=Image\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
"fdt_addr=800\0" \
"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mmcroot=/dev/mmcblk0p2\0" \
@@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootfile};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
"linux_qspi_enable=if sf probe; then " \
"echo Enabling QSPI at Linux DTB...;" \
"fdt addr ${fdt_addr}; fdt resize;" \
@@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.13.0
[v5 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 ++ .../arm/mach-socfpga/lowlevel_init_soc64.S | 41 -- 2 files changed, 17 insertions(+), 26 deletions(-) copy board/cortina/presidio-asic/lowlevel_init.S => arch/arm/mach-socfpga/lowlevel_init_soc64.S (66%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S similarity index 66% copy from board/cortina/presidio-asic/lowlevel_init.S copy to arch/arm/mach-socfpga/lowlevel_init_soc64.S index 4450a5df79..612ea8a037 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -1,43 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2020 Cortina-Access + * Copyright (C) 2020 Intel Corporation. All rights reserved * + * SPDX-License-Identifier:GPL-2.0 */ - #include #include #include #include -#include - .globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) mov x29, lr /* Save LR */ -#if defined(CONFIG_SOC_CA7774) - /* Enable SMPEN in CPUECTLR */ - mrs x0, s3_1_c15_c2_1 - tst x0, #0x40 -b.neskip_smp_setup - orr x0, x0, #0x40 - msr s3_1_c15_c2_1, x0 -skip_smp_setup: -#endif - -#if defined(CONFIG_SOC_CA8277B) - /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE - mov x1, #1 - str w1, [x0] -#endif - #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else branch_if_slave x0, 1f -#ifndef CONFIG_TARGET_VENUS +#endif ldr x0, =GICD_BASE bl gic_init_secure -#endif 1: #if defined(CONFIG_GICV3) ldr x0, =GICR_BASE @@ -54,7 +42,7 @@ skip_smp_setup: /* * Slave should wait for master clearing spin table. -* This sync prevent salves observing incorrect +* This sync prevent slaves observing incorrect * value of spin table and jumping to wrong place. */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) @@ -85,3 +73,4 @@ lowlevel_in_el1: 2: mov lr, x29 /* Restore LR */ ret +ENDPROC(lowlevel_init) -- 2.13.0
[v5 04/18] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v5 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.13.0
[v5 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..cacb410691 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any
[v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a
status.
This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.
When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.
Signed-off-by: Siew Chin Lim
---
drivers/mmc/ca_dw_mmc.c | 4 +++-
drivers/mmc/dw_mmc.c | 9 +++--
drivers/mmc/exynos_dw_mmc.c | 4 +++-
drivers/mmc/nexell_dw_mmc.c | 4 +++-
drivers/mmc/socfpga_dw_mmc.c | 4 +++-
include/dwmmc.h | 2 +-
6 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
index 198c41f451..d0cf1b7248 100644
--- a/drivers/mmc/ca_dw_mmc.c
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data {
u8 ds;
};
-static void ca_dwmci_clksel(struct dwmci_host *host)
+static int ca_dwmci_clksel(struct dwmci_host *host)
{
struct ca_dwmmc_priv_data *priv = host->priv;
u32 val = readl(priv->sd_dll_reg);
@@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
val |= SD_CLK_SEL_100MHZ;
writel(val, priv->sd_dll_reg);
+
+ return 0;
}
static void ca_dwmci_board_init(struct dwmci_host *host)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7702f4be3f..7c8a312fa7 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_UHS_REG, regs);
- if (host->clksel)
- host->clksel(host);
+ if (host->clksel) {
+ int ret;
+
+ ret = host->clksel(host);
+ if (ret)
+ return ret;
+ }
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vqmmc_supply) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 435ccac594..7a25dac841 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data {
* Function used as callback function to initialise the
* CLKSEL register for every mmc channel.
*/
-static void exynos_dwmci_clksel(struct dwmci_host *host)
+static int exynos_dwmci_clksel(struct dwmci_host *host)
{
#ifdef CONFIG_DM_MMC
struct dwmci_exynos_priv_data *priv =
@@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
struct dwmci_exynos_priv_data *priv = host->priv;
#endif
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
+
+ return 0;
}
unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
index 0462759444..fe00189fe1 100644
--- a/drivers/mmc/nexell_dw_mmc.c
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -51,7 +51,7 @@ struct nexell_dwmmc_priv {
struct clk *clk_get(const char *id);
-static void nx_dw_mmc_clksel(struct dwmci_host *host)
+static int nx_dw_mmc_clksel(struct dwmci_host *host)
{
/* host->priv is pointer to "struct udevice" */
struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
@@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host)
DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
dwmci_writel(host, DWMCI_CLKSEL, val);
+
+ return 0;
}
static void nx_dw_mmc_reset(int ch)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..0a2845bcc2 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -46,7 +46,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
+static int socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
@@ -66,6 +66,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+
+ return 0;
}
static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index d8a8355a0a..f8aeda7697 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -174,7 +174,7 @@ struct dwmci_host {
struct mmc *mmc;
void *priv;
- void (*clksel)(struct dwmci_host *host);
+ int
[v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).
Signed-off-by: Siew Chin Lim
---
v5
---
Return error code instead of hang the system if fail to access
the secure register.
---
arch/arm/mach-socfpga/Makefile | 1 +
.../mach-socfpga/include/mach/secure_reg_helper.h | 19 +
arch/arm/mach-socfpga/secure_reg_helper.c | 97 ++
3 files changed, 117 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..82b681d870 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -73,6 +73,7 @@ obj-y += firewall.o
obj-y += spl_agilex.o
endif
else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 00..d5a11122c7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef_SECURE_REG_HELPER_H_
+#define_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+int socfpga_secure_reg_read32(u32 id, u32 *val);
+int socfpga_secure_reg_write32(u32 id, u32 val);
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c
b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 00..d9be45cc97
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
+{
+ switch (id) {
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+ break;
+ default:
+ return -EADDRNOTAVAIL;
+ }
+ return 0;
+}
+
+int socfpga_secure_reg_read32(u32 id, u32 *val)
+{
+ int ret;
+ u64 ret_arg;
+ u64 args[1];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+ if (ret)
+ return ret;
+
+ *val = (u32)ret_arg;
+
+ return 0;
+}
+
+int socfpga_secure_reg_write32(u32 id, u32 val)
+{
+ int ret;
+ u64 args[2];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+ int ret;
+ u64 args[3];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = mask;
+ args[2] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
--
2.13.0
[v5 10/18] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the PHY related secure register.
---
drivers/net/dwmac_socfpga.c | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..8efb88c8fb 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -6,6 +6,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -17,8 +19,6 @@
#include
#include
-#include
-
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
void*phy_intf;
@@ -64,6 +64,33 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u32 val = (readl(pdata->phy_intf) & ~modemask) |
+ (modereg << pdata->reg_shift);
+
+ u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+SYSMGR_SOC64_EMAC0) >> 2;
+
+ u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
+
+ int ret = socfpga_secure_reg_write32(id, val);
+ if (ret) {
+ dev_err(dev, "Failed to set PHY register via SMC call\n");
+ return ret;
+ }
+#else
+ clrsetbits_le32(pdata->phy_intf, modemask,
+ modereg << pdata->reg_shift);
+#endif
+
+ return 0;
+}
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +98,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +123,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ ret = dwmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
reset_release_bulk(&reset_bulk);
--
2.13.0
[v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the secure register.
---
drivers/mmc/socfpga_dw_mmc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0a2845bcc2..7a485b492d 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -58,10 +60,22 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ int ret;
+
+ ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
+sdmmc_mask);
+ if (ret) {
+ printf("DWMMC: Failed to set clksel via SMC call");
+ return ret;
+ }
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
[v5 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+ if (ret) {
+ printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ return;
+ }
+#else
u32 reg;
if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.13.0
[v5 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA recon
[v5 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.13.0
[v5 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
From: Chee Hong Ang Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 990f879b07..fdcd7d3e9a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.13.0
[v5 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.13.0
[v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim
---
v5
---
Change 'blob' to 'blob-ext' entry in binman dts node for all input files.
The input files (u-boot proper, Linux image files) that required to
build FIT images may not yet ready during u-boot compilation.
By using 'blob-ext', binman will report warning instead of error
during u-boot compilation when the input files doesn't exist.
It wouldn't fail the u-boot compilation. Then, user can prepare the
input files later, and use binman command to generate the FIT images.
---
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +-
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +-
4 files changed, 134 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index f0528a9ad9..08f7cf7f7a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,11 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2020 Intel Corporation
*/
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
/{
memory {
#address-cells = <2>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
new file mode 100644
index 00..cf365590a8
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot {
+ filename = "u-boot.itb";
+ fit {
+ fit,external-offset = ;
+ description = "FIT with firmware and bootloader";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat
device-tree";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+
[v5 17/18] arm: socfpga: soc64: Enable FIT image generation using binman
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim --- v4 --- Adjust BINMAN sequence in code, sorted by alphabetical order. v5 --- Revert all changes in Makefile for BINMAN: (1) Remove target "fit-itb", directly use binman command to generate fit (2) Do not skip binman for ARCH_SOCFPGA in default Makefile flow. Use "blob-ext" entry instead of "blob" in binman node in device tree, binman will report warning instead of error in default Makefile flow. So, it wouldn't fail the default compilation process. --- arch/arm/mach-socfpga/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 01f5a1fc41..4d4ff16337 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,6 +33,7 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -78,6 +79,7 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v5 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
From: Chee Hong Ang
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
...ilex_defconfig => socfpga_agilex_atf_defconfig} | 22
...0_defconfig => socfpga_stratix10_atf_defconfig} | 24 +-
2 files changed, 28 insertions(+), 18 deletions(-)
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (80%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
diff --git a/configs/socfpga_agilex_defconfig
b/configs/socfpga_agilex_atf_defconfig
similarity index 80%
copy from configs/socfpga_agilex_defconfig
copy to configs/socfpga_agilex_atf_defconfig
index 230d3c2ce5..ad87a8098f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -1,25 +1,29 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_CMD_MEMTEST=y
@@ -35,6 +39,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -44,6 +49,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_atf_defconfig
similarity index 80%
copy from configs/socfpga_stratix10_defconfig
copy to configs/socfpga_stratix10_atf_defconfig
index 3df44bb88d..1005ba979e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -1,26 +1,28 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_OPTIMIZE_INLINING=y
-CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_MEMTEST=y
@@ -37,11 +39,13 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.13.0
[v6 00/18] Enable ARM Trusted Firmware for U-Boot
This is the 6th version of patchset to enable ARM Trusted Firmware for U-Boot for Intel Stratix10 and Agilex platform. New U-boot flow with ARM Trusted Firmware (ATF) support: SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1) SPL loads the u-boot.itb which consist of: 1) u-boot-nodtb.bin (U-Boot Proper image) 2) u-boot.dtb (U-Boot Proper DTB) 3) bl31.bin (ATF-BL31 image) Patch status: Have changes: Patch 7, 10 Other patches unchanged. Detail changelog can find in commit message. v5->v6: Patch 7: - Direct return 'ret' after SMC call in write and update function. Patch 10: - Clean up the code and use socfpga_secure_reg_update32 to update PHY related secure registers. History: [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200817043431.28718-1-chee.hong@intel.com/ [v2]: https://patchwork.ozlabs.org/project/uboot/cover/20201001091614.184612-1-elly.siew.chin@intel.com/ [v3]: https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/ [v4]: https://patchwork.ozlabs.org/project/uboot/cover/20201218032853.46839-1-elly.siew.chin@intel.com/ [v5]: https://patchwork.ozlabs.org/project/uboot/cover/20201221164942.11640-1-elly.siew.chin@intel.com/ These patchsets have dependency on: arm: socfpga: soc64: Add timeout waiting for NOC idle ACK https://lists.denx.de/pipermail/u-boot/2020-August/423029.html Rename Stratix10 FPGA driver and support Agilex https://lists.denx.de/pipermail/u-boot/2020-August/422798.html SoCFPGA mailbox driver fixes and enhancements https://lists.denx.de/pipermail/u-boot/2020-August/423140.html arm: socfpga: soc64: Initialize timer in SPL only https://lists.denx.de/pipermail/u-boot/2020-July/419692.html arm: socfpga: soc64: Remove PHY interface setup from misc arch init https://lists.denx.de/pipermail/u-boot/2020-July/419690.html Enable sysreset support for SoCFPGA SoC64 platforms https://lists.denx.de/pipermail/u-boot/2020-August/422509.html arm: socfpga: soc64: Disable CONFIG_PSCI_RESET https://lists.denx.de/pipermail/u-boot/2020-August/423373.html Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim (4): arm: socfpga: Add secure register access helper functions for SoC 64bits mmc: dwmmc: Change designware MMC 'clksel' callback function to return status arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman arch/arm/dts/socfpga_agilex-u-boot.dtsi| 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 + arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 + arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 + arch/arm/mach-socfpga/board.c | 12 +- .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 + arch/arm/mach-socfpga/lowlevel_init_soc64.S| 76 +++ arch/arm/mach-socfpga/mailbox_s10.c| 5 + arch/arm/mach-socfpga/reset_manager_s10.c | 13 + arch/arm/mach-socfpga/secure_reg_helper.c | 91 arch/arm/mach-socfpga/smc_api.c| 56 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c| 3 +- configs/socfpga_agilex_atf_defconfig | 72 +++ configs/socfpga_stratix10_atf_defconfig| 74 +++ drivers/fpga/intel_sdm_mb.c| 139 + drivers/mmc/ca_dw_mmc.c| 4 +- drivers/mmc/dw_mmc.c | 9 +- drivers/mmc/exynos_dw_mmc.c| 4 +- drivers/mmc/nexell_dw_mmc.c| 4 +- drivers/mmc/socfpga_dw_mmc.c | 18 +- drivers/net/dwmac_socfpga.c| 37 +- include/configs/socfpga_soc64_common.h | 24 +- includ
[v6 01/18] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.13.0
[v6 02/18] arm: socfpga: soc64: Load FIT image with ATF support
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* CONFIG_BOOTARGS goes into the environment value "bootargs".
* Do note the value will override also the chosen node in FDT blob.
*/
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "kernel.itb"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run
linux_qspi_enable;" \
+ "run mmcfitboot"
+#else
+#define CONFIG_BOOTFILE "Image"
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;"
\
"run mmcboot"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "bootfile=Image\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
"fdt_addr=800\0" \
"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mmcroot=/dev/mmcblk0p2\0" \
@@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootfile};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
"linux_qspi_enable=if sf probe; then " \
"echo Enabling QSPI at Linux DTB...;" \
"fdt addr ${fdt_addr}; fdt resize;" \
@@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.13.0
[v6 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 ++ .../arm/mach-socfpga/lowlevel_init_soc64.S | 41 -- 2 files changed, 17 insertions(+), 26 deletions(-) copy board/cortina/presidio-asic/lowlevel_init.S => arch/arm/mach-socfpga/lowlevel_init_soc64.S (66%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S similarity index 66% copy from board/cortina/presidio-asic/lowlevel_init.S copy to arch/arm/mach-socfpga/lowlevel_init_soc64.S index 4450a5df79..612ea8a037 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -1,43 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2020 Cortina-Access + * Copyright (C) 2020 Intel Corporation. All rights reserved * + * SPDX-License-Identifier:GPL-2.0 */ - #include #include #include #include -#include - .globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) mov x29, lr /* Save LR */ -#if defined(CONFIG_SOC_CA7774) - /* Enable SMPEN in CPUECTLR */ - mrs x0, s3_1_c15_c2_1 - tst x0, #0x40 -b.neskip_smp_setup - orr x0, x0, #0x40 - msr s3_1_c15_c2_1, x0 -skip_smp_setup: -#endif - -#if defined(CONFIG_SOC_CA8277B) - /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE - mov x1, #1 - str w1, [x0] -#endif - #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else branch_if_slave x0, 1f -#ifndef CONFIG_TARGET_VENUS +#endif ldr x0, =GICD_BASE bl gic_init_secure -#endif 1: #if defined(CONFIG_GICV3) ldr x0, =GICR_BASE @@ -54,7 +42,7 @@ skip_smp_setup: /* * Slave should wait for master clearing spin table. -* This sync prevent salves observing incorrect +* This sync prevent slaves observing incorrect * value of spin table and jumping to wrong place. */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) @@ -85,3 +73,4 @@ lowlevel_in_el1: 2: mov lr, x29 /* Restore LR */ ret +ENDPROC(lowlevel_init) -- 2.13.0
[v6 04/18] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v6 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.13.0
[v6 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).
Signed-off-by: Siew Chin Lim
---
v5
---
Return error code instead of hang the system if fail to access
the secure register.
---
v6
---
Directly return 'ret' after SMC call in write and update function.
---
arch/arm/mach-socfpga/Makefile | 1 +
.../mach-socfpga/include/mach/secure_reg_helper.h | 19 +
arch/arm/mach-socfpga/secure_reg_helper.c | 91 ++
3 files changed, 111 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..82b681d870 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -73,6 +73,7 @@ obj-y += firewall.o
obj-y += spl_agilex.o
endif
else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 00..d5a11122c7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef_SECURE_REG_HELPER_H_
+#define_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+int socfpga_secure_reg_read32(u32 id, u32 *val);
+int socfpga_secure_reg_write32(u32 id, u32 val);
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c
b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 00..816006cb5a
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
+{
+ switch (id) {
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+ break;
+ default:
+ return -EADDRNOTAVAIL;
+ }
+ return 0;
+}
+
+int socfpga_secure_reg_read32(u32 id, u32 *val)
+{
+ int ret;
+ u64 ret_arg;
+ u64 args[1];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+ if (ret)
+ return ret;
+
+ *val = (u32)ret_arg;
+
+ return 0;
+}
+
+int socfpga_secure_reg_write32(u32 id, u32 val)
+{
+ int ret;
+ u64 args[2];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+ return ret;
+}
+
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+ int ret;
+ u64 args[3];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = mask;
+ args[2] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+ return ret;
+}
--
2.13.0
[v6 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..cacb410691 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any
[v6 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a
status.
This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.
When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.
Signed-off-by: Siew Chin Lim
---
drivers/mmc/ca_dw_mmc.c | 4 +++-
drivers/mmc/dw_mmc.c | 9 +++--
drivers/mmc/exynos_dw_mmc.c | 4 +++-
drivers/mmc/nexell_dw_mmc.c | 4 +++-
drivers/mmc/socfpga_dw_mmc.c | 4 +++-
include/dwmmc.h | 2 +-
6 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
index 198c41f451..d0cf1b7248 100644
--- a/drivers/mmc/ca_dw_mmc.c
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data {
u8 ds;
};
-static void ca_dwmci_clksel(struct dwmci_host *host)
+static int ca_dwmci_clksel(struct dwmci_host *host)
{
struct ca_dwmmc_priv_data *priv = host->priv;
u32 val = readl(priv->sd_dll_reg);
@@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
val |= SD_CLK_SEL_100MHZ;
writel(val, priv->sd_dll_reg);
+
+ return 0;
}
static void ca_dwmci_board_init(struct dwmci_host *host)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7702f4be3f..7c8a312fa7 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_UHS_REG, regs);
- if (host->clksel)
- host->clksel(host);
+ if (host->clksel) {
+ int ret;
+
+ ret = host->clksel(host);
+ if (ret)
+ return ret;
+ }
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vqmmc_supply) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 435ccac594..7a25dac841 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data {
* Function used as callback function to initialise the
* CLKSEL register for every mmc channel.
*/
-static void exynos_dwmci_clksel(struct dwmci_host *host)
+static int exynos_dwmci_clksel(struct dwmci_host *host)
{
#ifdef CONFIG_DM_MMC
struct dwmci_exynos_priv_data *priv =
@@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
struct dwmci_exynos_priv_data *priv = host->priv;
#endif
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
+
+ return 0;
}
unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
index 0462759444..fe00189fe1 100644
--- a/drivers/mmc/nexell_dw_mmc.c
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -51,7 +51,7 @@ struct nexell_dwmmc_priv {
struct clk *clk_get(const char *id);
-static void nx_dw_mmc_clksel(struct dwmci_host *host)
+static int nx_dw_mmc_clksel(struct dwmci_host *host)
{
/* host->priv is pointer to "struct udevice" */
struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
@@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host)
DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
dwmci_writel(host, DWMCI_CLKSEL, val);
+
+ return 0;
}
static void nx_dw_mmc_reset(int ch)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..0a2845bcc2 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -46,7 +46,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
+static int socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
@@ -66,6 +66,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+
+ return 0;
}
static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index d8a8355a0a..f8aeda7697 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -174,7 +174,7 @@ struct dwmci_host {
struct mmc *mmc;
void *priv;
- void (*clksel)(struct dwmci_host *host);
+ int
[v6 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the secure register.
---
drivers/mmc/socfpga_dw_mmc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0a2845bcc2..7a485b492d 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -58,10 +60,22 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ int ret;
+
+ ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
+sdmmc_mask);
+ if (ret) {
+ printf("DWMMC: Failed to set clksel via SMC call");
+ return ret;
+ }
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
[v6 10/18] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the PHY related secure register.
---
v6
---
Clean up the code and use socfpga_secure_reg_update32 to update
PHY related secure registers.
---
drivers/net/dwmac_socfpga.c | 37 +++--
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..26f647c778 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -6,6 +6,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -17,8 +19,6 @@
#include
#include
-#include
-
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
void*phy_intf;
@@ -64,6 +64,32 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+SYSMGR_SOC64_EMAC0) >> 2;
+
+ u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
+
+ int ret = socfpga_secure_reg_update32(id,
+modemask,
+modereg << pdata->reg_shift);
+ if (ret) {
+ dev_err(dev, "Failed to set PHY register via SMC call\n");
+ return ret;
+ }
+#else
+ clrsetbits_le32(pdata->phy_intf, modemask,
+ modereg << pdata->reg_shift);
+#endif
+
+ return 0;
+}
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +97,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +122,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ ret = dwmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
reset_release_bulk(&reset_bulk);
--
2.13.0
[v6 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+ if (ret) {
+ printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ return;
+ }
+#else
u32 reg;
if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.13.0
[v6 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA recon
[v6 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.13.0
[v6 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
From: Chee Hong Ang Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 990f879b07..fdcd7d3e9a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.13.0
[v6 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.13.0
[v6 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim
---
v5
---
Change 'blob' to 'blob-ext' entry in binman dts node for all input files.
The input files (u-boot proper, Linux image files) that required to
build FIT images may not yet ready during u-boot compilation.
By using 'blob-ext', binman will report warning instead of error
during u-boot compilation when the input files doesn't exist.
It wouldn't fail the u-boot compilation. Then, user can prepare the
input files later, and use binman command to generate the FIT images.
---
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +-
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +-
4 files changed, 134 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index f0528a9ad9..08f7cf7f7a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,11 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2020 Intel Corporation
*/
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
/{
memory {
#address-cells = <2>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
new file mode 100644
index 00..cf365590a8
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot {
+ filename = "u-boot.itb";
+ fit {
+ fit,external-offset = ;
+ description = "FIT with firmware and bootloader";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat
device-tree";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+
[v6 17/18] arm: socfpga: soc64: Enable FIT image generation using binman
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim --- v4 --- Adjust BINMAN sequence in code, sorted by alphabetical order. v5 --- Revert all changes in Makefile for BINMAN: (1) Remove target "fit-itb", directly use binman command to generate fit (2) Do not skip binman for ARCH_SOCFPGA in default Makefile flow. Use "blob-ext" entry instead of "blob" in binman node in device tree, binman will report warning instead of error in default Makefile flow. So, it wouldn't fail the default compilation process. --- arch/arm/mach-socfpga/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 01f5a1fc41..4d4ff16337 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,6 +33,7 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -78,6 +79,7 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v6 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
From: Chee Hong Ang
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
...ilex_defconfig => socfpga_agilex_atf_defconfig} | 22
...0_defconfig => socfpga_stratix10_atf_defconfig} | 24 +-
2 files changed, 28 insertions(+), 18 deletions(-)
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (80%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
diff --git a/configs/socfpga_agilex_defconfig
b/configs/socfpga_agilex_atf_defconfig
similarity index 80%
copy from configs/socfpga_agilex_defconfig
copy to configs/socfpga_agilex_atf_defconfig
index 230d3c2ce5..ad87a8098f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -1,25 +1,29 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_CMD_MEMTEST=y
@@ -35,6 +39,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -44,6 +49,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_atf_defconfig
similarity index 80%
copy from configs/socfpga_stratix10_defconfig
copy to configs/socfpga_stratix10_atf_defconfig
index 3df44bb88d..1005ba979e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -1,26 +1,28 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_OPTIMIZE_INLINING=y
-CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_MEMTEST=y
@@ -37,11 +39,13 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.13.0
[v7 00/18] Enable ARM Trusted Firmware for U-Boot
This is the 7th version of patchset to enable ARM Trusted Firmware for U-Boot for Intel Stratix10 and Agilex platform. New U-boot flow with ARM Trusted Firmware (ATF) support: SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1) SPL loads the u-boot.itb which consist of: 1) u-boot-nodtb.bin (U-Boot Proper image) 2) u-boot.dtb (U-Boot Proper DTB) 3) bl31.bin (ATF-BL31 image) Patch status: Have changes: Patch 7 Other patches unchanged. Detail changelog can find in commit message. v6->v7: Patch 7: - Simplify the code to "return invoke_smc(..." in write and update function. History: [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200817043431.28718-1-chee.hong@intel.com/ [v2]: https://patchwork.ozlabs.org/project/uboot/cover/20201001091614.184612-1-elly.siew.chin@intel.com/ [v3]: https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/ [v4]: https://patchwork.ozlabs.org/project/uboot/cover/20201218032853.46839-1-elly.siew.chin@intel.com/ [v5]: https://patchwork.ozlabs.org/project/uboot/cover/20201221164942.11640-1-elly.siew.chin@intel.com/ [v6]: https://patchwork.ozlabs.org/project/uboot/cover/20201223145626.25206-1-elly.siew.chin@intel.com/ These patchsets have dependency on: arm: socfpga: soc64: Add timeout waiting for NOC idle ACK https://lists.denx.de/pipermail/u-boot/2020-August/423029.html Rename Stratix10 FPGA driver and support Agilex https://lists.denx.de/pipermail/u-boot/2020-August/422798.html SoCFPGA mailbox driver fixes and enhancements https://lists.denx.de/pipermail/u-boot/2020-August/423140.html arm: socfpga: soc64: Initialize timer in SPL only https://lists.denx.de/pipermail/u-boot/2020-July/419692.html arm: socfpga: soc64: Remove PHY interface setup from misc arch init https://lists.denx.de/pipermail/u-boot/2020-July/419690.html Enable sysreset support for SoCFPGA SoC64 platforms https://lists.denx.de/pipermail/u-boot/2020-August/422509.html arm: socfpga: soc64: Disable CONFIG_PSCI_RESET https://lists.denx.de/pipermail/u-boot/2020-August/423373.html Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim (4): arm: socfpga: Add secure register access helper functions for SoC 64bits mmc: dwmmc: Change designware MMC 'clksel' callback function to return status arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman arch/arm/dts/socfpga_agilex-u-boot.dtsi| 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 + arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 + arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 + arch/arm/mach-socfpga/board.c | 12 +- .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 + arch/arm/mach-socfpga/lowlevel_init_soc64.S| 76 +++ arch/arm/mach-socfpga/mailbox_s10.c| 5 + arch/arm/mach-socfpga/reset_manager_s10.c | 13 + arch/arm/mach-socfpga/secure_reg_helper.c | 89 arch/arm/mach-socfpga/smc_api.c| 56 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c| 3 +- configs/socfpga_agilex_atf_defconfig | 72 +++ configs/socfpga_stratix10_atf_defconfig| 74 +++ drivers/fpga/intel_sdm_mb.c| 139 + drivers/mmc/ca_dw_mmc.c| 4 +- drivers/mmc/dw_mmc.c | 9 +- drivers/mmc/exynos_dw_mmc.c| 4 +- drivers/mmc/nexell_dw_mmc.c| 4 +- drivers/mmc/socfpga_dw_mmc.c | 18 +- drivers/net/dwmac_socfpga.c| 37 +- include/configs/socfpga_soc64_common.h | 2
[v7 01/18] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.13.0
[v7 02/18] arm: socfpga: soc64: Load FIT image with ATF support
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* CONFIG_BOOTARGS goes into the environment value "bootargs".
* Do note the value will override also the chosen node in FDT blob.
*/
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "kernel.itb"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run
linux_qspi_enable;" \
+ "run mmcfitboot"
+#else
+#define CONFIG_BOOTFILE "Image"
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;"
\
"run mmcboot"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "bootfile=Image\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
"fdt_addr=800\0" \
"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mmcroot=/dev/mmcblk0p2\0" \
@@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootfile};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
"linux_qspi_enable=if sf probe; then " \
"echo Enabling QSPI at Linux DTB...;" \
"fdt addr ${fdt_addr}; fdt resize;" \
@@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.13.0
[v7 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 ++ .../arm/mach-socfpga/lowlevel_init_soc64.S | 41 -- 2 files changed, 17 insertions(+), 26 deletions(-) copy board/cortina/presidio-asic/lowlevel_init.S => arch/arm/mach-socfpga/lowlevel_init_soc64.S (66%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S similarity index 66% copy from board/cortina/presidio-asic/lowlevel_init.S copy to arch/arm/mach-socfpga/lowlevel_init_soc64.S index 4450a5df79..612ea8a037 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -1,43 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2020 Cortina-Access + * Copyright (C) 2020 Intel Corporation. All rights reserved * + * SPDX-License-Identifier:GPL-2.0 */ - #include #include #include #include -#include - .globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) mov x29, lr /* Save LR */ -#if defined(CONFIG_SOC_CA7774) - /* Enable SMPEN in CPUECTLR */ - mrs x0, s3_1_c15_c2_1 - tst x0, #0x40 -b.neskip_smp_setup - orr x0, x0, #0x40 - msr s3_1_c15_c2_1, x0 -skip_smp_setup: -#endif - -#if defined(CONFIG_SOC_CA8277B) - /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE - mov x1, #1 - str w1, [x0] -#endif - #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else branch_if_slave x0, 1f -#ifndef CONFIG_TARGET_VENUS +#endif ldr x0, =GICD_BASE bl gic_init_secure -#endif 1: #if defined(CONFIG_GICV3) ldr x0, =GICR_BASE @@ -54,7 +42,7 @@ skip_smp_setup: /* * Slave should wait for master clearing spin table. -* This sync prevent salves observing incorrect +* This sync prevent slaves observing incorrect * value of spin table and jumping to wrong place. */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) @@ -85,3 +73,4 @@ lowlevel_in_el1: 2: mov lr, x29 /* Restore LR */ ret +ENDPROC(lowlevel_init) -- 2.13.0
[v7 04/18] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v7 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.13.0
[v7 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..cacb410691 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any
[v7 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the secure register.
---
drivers/mmc/socfpga_dw_mmc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0a2845bcc2..7a485b492d 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -58,10 +60,22 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ int ret;
+
+ ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
+sdmmc_mask);
+ if (ret) {
+ printf("DWMMC: Failed to set clksel via SMC call");
+ return ret;
+ }
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
[v7 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a
status.
This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.
When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.
Signed-off-by: Siew Chin Lim
---
drivers/mmc/ca_dw_mmc.c | 4 +++-
drivers/mmc/dw_mmc.c | 9 +++--
drivers/mmc/exynos_dw_mmc.c | 4 +++-
drivers/mmc/nexell_dw_mmc.c | 4 +++-
drivers/mmc/socfpga_dw_mmc.c | 4 +++-
include/dwmmc.h | 2 +-
6 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
index 198c41f451..d0cf1b7248 100644
--- a/drivers/mmc/ca_dw_mmc.c
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data {
u8 ds;
};
-static void ca_dwmci_clksel(struct dwmci_host *host)
+static int ca_dwmci_clksel(struct dwmci_host *host)
{
struct ca_dwmmc_priv_data *priv = host->priv;
u32 val = readl(priv->sd_dll_reg);
@@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
val |= SD_CLK_SEL_100MHZ;
writel(val, priv->sd_dll_reg);
+
+ return 0;
}
static void ca_dwmci_board_init(struct dwmci_host *host)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7702f4be3f..7c8a312fa7 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_UHS_REG, regs);
- if (host->clksel)
- host->clksel(host);
+ if (host->clksel) {
+ int ret;
+
+ ret = host->clksel(host);
+ if (ret)
+ return ret;
+ }
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vqmmc_supply) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 435ccac594..7a25dac841 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data {
* Function used as callback function to initialise the
* CLKSEL register for every mmc channel.
*/
-static void exynos_dwmci_clksel(struct dwmci_host *host)
+static int exynos_dwmci_clksel(struct dwmci_host *host)
{
#ifdef CONFIG_DM_MMC
struct dwmci_exynos_priv_data *priv =
@@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
struct dwmci_exynos_priv_data *priv = host->priv;
#endif
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
+
+ return 0;
}
unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
index 0462759444..fe00189fe1 100644
--- a/drivers/mmc/nexell_dw_mmc.c
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -51,7 +51,7 @@ struct nexell_dwmmc_priv {
struct clk *clk_get(const char *id);
-static void nx_dw_mmc_clksel(struct dwmci_host *host)
+static int nx_dw_mmc_clksel(struct dwmci_host *host)
{
/* host->priv is pointer to "struct udevice" */
struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
@@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host)
DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
dwmci_writel(host, DWMCI_CLKSEL, val);
+
+ return 0;
}
static void nx_dw_mmc_reset(int ch)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..0a2845bcc2 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -46,7 +46,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
+static int socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
@@ -66,6 +66,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+
+ return 0;
}
static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index d8a8355a0a..f8aeda7697 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -174,7 +174,7 @@ struct dwmci_host {
struct mmc *mmc;
void *priv;
- void (*clksel)(struct dwmci_host *host);
+ int
[v7 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).
Signed-off-by: Siew Chin Lim
---
v5
---
Return error code instead of hang the system if fail to access
the secure register.
---
v6
---
Directly return 'ret' after SMC call in write and update function.
---
v7
---
Simplify the code to "return invoke_smc(..." in write and update function.
---
arch/arm/mach-socfpga/Makefile | 1 +
.../mach-socfpga/include/mach/secure_reg_helper.h | 19 +
arch/arm/mach-socfpga/secure_reg_helper.c | 89 ++
3 files changed, 109 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..82b681d870 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -73,6 +73,7 @@ obj-y += firewall.o
obj-y += spl_agilex.o
endif
else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 00..d5a11122c7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef_SECURE_REG_HELPER_H_
+#define_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+int socfpga_secure_reg_read32(u32 id, u32 *val);
+int socfpga_secure_reg_write32(u32 id, u32 val);
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c
b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 00..0d4f45f33d
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
+{
+ switch (id) {
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+ break;
+ case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+ *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+ break;
+ default:
+ return -EADDRNOTAVAIL;
+ }
+ return 0;
+}
+
+int socfpga_secure_reg_read32(u32 id, u32 *val)
+{
+ int ret;
+ u64 ret_arg;
+ u64 args[1];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+ if (ret)
+ return ret;
+
+ *val = (u32)ret_arg;
+
+ return 0;
+}
+
+int socfpga_secure_reg_write32(u32 id, u32 val)
+{
+ int ret;
+ u64 args[2];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = val;
+ return invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+}
+
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+ int ret;
+ u64 args[3];
+
+ phys_addr_t reg_addr;
+ ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
+ if (ret)
+ return ret;
+
+ args[0] = (u64)reg_addr;
+ args[1] = mask;
+ args[2] = val;
+ return invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+}
--
2.13.0
[v7 10/18] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v5
---
Call secure register access helper function to write the secure register.
Return error if fail to write the PHY related secure register.
---
v6
---
Clean up the code and use socfpga_secure_reg_update32 to update
PHY related secure registers.
---
drivers/net/dwmac_socfpga.c | 37 +++--
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..26f647c778 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -6,6 +6,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -17,8 +19,6 @@
#include
#include
-#include
-
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
void*phy_intf;
@@ -64,6 +64,32 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+SYSMGR_SOC64_EMAC0) >> 2;
+
+ u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
+
+ int ret = socfpga_secure_reg_update32(id,
+modemask,
+modereg << pdata->reg_shift);
+ if (ret) {
+ dev_err(dev, "Failed to set PHY register via SMC call\n");
+ return ret;
+ }
+#else
+ clrsetbits_le32(pdata->phy_intf, modemask,
+ modereg << pdata->reg_shift);
+#endif
+
+ return 0;
+}
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +97,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +122,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ ret = dwmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
reset_release_bulk(&reset_bulk);
--
2.13.0
[v7 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+ if (ret) {
+ printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ return;
+ }
+#else
u32 reg;
if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.13.0
[v7 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA recon
[v7 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.13.0
[v7 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
From: Chee Hong Ang Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 990f879b07..fdcd7d3e9a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.13.0
[v7 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.13.0
[v7 17/18] arm: socfpga: soc64: Enable FIT image generation using binman
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim --- v4 --- Adjust BINMAN sequence in code, sorted by alphabetical order. v5 --- Revert all changes in Makefile for BINMAN: (1) Remove target "fit-itb", directly use binman command to generate fit (2) Do not skip binman for ARCH_SOCFPGA in default Makefile flow. Use "blob-ext" entry instead of "blob" in binman node in device tree, binman will report warning instead of error in default Makefile flow. So, it wouldn't fail the default compilation process. --- arch/arm/mach-socfpga/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 01f5a1fc41..4d4ff16337 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,6 +33,7 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -78,6 +79,7 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v7 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim
---
v5
---
Change 'blob' to 'blob-ext' entry in binman dts node for all input files.
The input files (u-boot proper, Linux image files) that required to
build FIT images may not yet ready during u-boot compilation.
By using 'blob-ext', binman will report warning instead of error
during u-boot compilation when the input files doesn't exist.
It wouldn't fail the u-boot compilation. Then, user can prepare the
input files later, and use binman command to generate the FIT images.
---
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +-
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +-
4 files changed, 134 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index f0528a9ad9..08f7cf7f7a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,11 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2020 Intel Corporation
*/
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
/{
memory {
#address-cells = <2>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
new file mode 100644
index 00..cf365590a8
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot {
+ filename = "u-boot.itb";
+ fit {
+ fit,external-offset = ;
+ description = "FIT with firmware and bootloader";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat
device-tree";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+
[v7 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
From: Chee Hong Ang
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
...ilex_defconfig => socfpga_agilex_atf_defconfig} | 22
...0_defconfig => socfpga_stratix10_atf_defconfig} | 24 +-
2 files changed, 28 insertions(+), 18 deletions(-)
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (80%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
diff --git a/configs/socfpga_agilex_defconfig
b/configs/socfpga_agilex_atf_defconfig
similarity index 80%
copy from configs/socfpga_agilex_defconfig
copy to configs/socfpga_agilex_atf_defconfig
index 230d3c2ce5..ad87a8098f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -1,25 +1,29 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_CMD_MEMTEST=y
@@ -35,6 +39,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -44,6 +49,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_atf_defconfig
similarity index 80%
copy from configs/socfpga_stratix10_defconfig
copy to configs/socfpga_stratix10_atf_defconfig
index 3df44bb88d..1005ba979e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -1,26 +1,28 @@
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x
-CONFIG_SYS_MEMTEST_END=0x3fe0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_OPTIMIZE_INLINING=y
-CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_MEMTEST=y
@@ -37,11 +39,13 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.13.0
[v2 0/6] Add Vendor Authorized Boot (VAB) support
This is the 2nd version of patchset to add Vendor Authorized Boot (VAB)
support for Intel Agilex SoC device.
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Patch status:
Have changes: Patch 1, 2, 5, 6
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 1:
- Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
This is new patch in 2nd version of VAB series. This is code clean up
without functionality change.
Patch 2:
- Renamed CONFIG_SECURE_VAB_AUTH* to CONFIG_SOCFPGA_SECURE_VAB_AUTH*
- Changes in secure_vab.c
- Changed to use SZ_1K for 1024
- Updated comment in secure_vab.c of "... the certificate for T"
- The code will report error before end of the function if reach
maximum retry.
- In board_prep_linux function, only execute linux_qspi_enable
command if it exists in enviroment variable. It is optional.
Patch 5:
- Move CONFIG_BOOTCOMMAND to defconfig.
This is new patch in 2nd version of VAB series. This is code clean up
without functionality change.
Patch 6:
- Renamed CONFIG_SECURE_VAB_AUTH to CONFIG_SOCFPGA_SECURE_VAB_AUTH
- Add CONFIG_BOOTCOMMAND in defconfig
History:
[v1]:
https://patchwork.ozlabs.org/project/uboot/cover/20201110070505.26935-1-elly.siew.chin@intel.com/
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot
https://patchwork.ozlabs.org/project/uboot/cover/20201224102113.32972-1-elly.siew.chin@intel.com/
Siew Chin Lim (6):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
arm: socfpga: cmd: Support 'vab' command
arm: socfpga: dts: soc64: Update filename in binman node of FIT image
with VAB support
configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
configs: socfpga: Add defconfig for Agilex with VAB support
arch/arm/Kconfig | 6 +-
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 +++
arch/arm/mach-socfpga/Kconfig | 20 +++
arch/arm/mach-socfpga/Makefile | 3 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +-
arch/arm/mach-socfpga/include/mach/secure_vab.h| 63 +++
.../arm/mach-socfpga/include/mach/system_manager.h | 3 +-
arch/arm/mach-socfpga/secure_vab.c | 193 +
arch/arm/mach-socfpga/vab.c| 37
common/Kconfig.boot| 2 +-
configs/socfpga_agilex_atf_defconfig | 2 +
configs/socfpga_agilex_defconfig | 2 +
..._atf_defconfig => socfpga_agilex_vab_defconfig} | 5 +-
configs/socfpga_stratix10_atf_defconfig| 2 +
configs/socfpga_stratix10_defconfig| 2 +
drivers/ddr/altera/Kconfig | 6 +-
drivers/fpga/Kconfig | 2 +-
drivers/sysreset/Kconfig | 2 +-
include/configs/socfpga_soc64_common.h | 9 +-
20 files changed, 363 insertions(+), 22 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h
create mode 100644 arch/arm/mach-socfpga/secure_vab.c
create mode 100644 arch/arm/mach-socfpga/vab.c
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(91%)
--
2.13.0
[v2 1/6] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim --- v2 --- - This is new patch in 2nd version of VAB series. This is code clean up without functional change. --- arch/arm/Kconfig| 6 +++--- arch/arm/mach-socfpga/Kconfig | 5 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +-- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- drivers/ddr/altera/Kconfig | 6 +++--- drivers/fpga/Kconfig| 2 +- drivers/sysreset/Kconfig| 2 +- 7 files changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe90875ae..7eea261fe9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -974,7 +974,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select ARM64 if TARGET_SOCFPGA_SOC64 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -986,7 +986,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT @@ -995,7 +995,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 4d4ff16337..9b1abdaabd 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -38,6 +38,7 @@ config TARGET_SOCFPGA_AGILEX select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 config TARGET_SOCFPGA_ARRIA5 bool @@ -75,12 +76,16 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF +config TARGET_SOCFPGA_SOC64 + bool + config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX + select TARGET_SOCFPGA_SOC64 choice prompt "Altera SOCFPGA board select" diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7844ad14cb..8c25325e45 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -43,8 +43,7 @@ void socfpga_per_reset_all(void); #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#elif defined(CONFIG_TARGET_SOCFPGA_SOC64) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index f816954717..5603eaa3d0 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -8,8 +8,7 @@ phys_addr_t socfpga_get_sysmgr_addr(void); -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#if defined(CONFIG_TARGET_SOCFPGA_SOC64) #include #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0) diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 8f590dc5f6..4660d20def 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/fpga/Kconfi
[v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
v2
---
- Renamed SECURE_VAB_AUTH* to SOCFPGA_SECURE_VAB_AUTH*
- Changes in secure_vab.c
- Changed to use SZ_1K for 1024
- Updated comment in secure_vab.c of "... the certificate for T"
- The code will report error before end of the function if reach
maximum retry.
- In board_prep_linux function, only execute linux_qspi_enable
command if it exists in enviroment variable. It is optional.
---
arch/arm/mach-socfpga/Kconfig| 15 ++
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
arch/arm/mach-socfpga/secure_vab.c | 193 +++
common/Kconfig.boot | 2 +-
6 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h
create mode 100644 arch/arm/mach-socfpga/secure_vab.c
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9b1abdaabd..0c35406232 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
config NR_DRAM_BANKS
default 1
+config SOCFPGA_SECURE_VAB_AUTH
+ bool "Enable boot image authentication with Secure Device Manager"
+ depends on TARGET_SOCFPGA_AGILEX
+ select FIT_IMAGE_POST_PROCESS
+ select SHA384
+ select SHA512_ALGO
+ select SPL_FIT_IMAGE_POST_PROCESS
+ help
+All images loaded from FIT will be authenticated by Secure Device
+Manager.
+
+config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
+ bool "Allow non-FIT VAB signed images"
+ depends on SOCFPGA_SECURE_VAB_AUTH
+
config SPL_SIZE_LIMIT
default 0x1 if TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 82b681d870..1f1e21766d 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
+# Copyright (C) 2017-2020 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -47,6 +48,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 4d783119ea..fbaf11597e 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -118,6 +118,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_RECONFIG_MSEL 7
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
+#define MBOX_VAB_SRC_CERT 11
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE51
#define MBOX_QSPI_DIRECT 59
diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h
b/arch/arm/mach-socfpga/include/mach/secure_vab.h
new file mode 100644
index 00..42588588e8
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef_SECURE_VAB_H_
+#define_SECURE_VAB_H_
+
+#include
+#include
+#include
+
+#define VAB_DATA_SZ64
+
+#define SDM_CERT_MAGIC_NUM 0x25D04E7F
+#define FCS_HPS_VAB_MAGIC_NUM 0xD0564142
+
+#define MAX_CERT_SIZE (SZ_4K)
+
+/*
+ * struct fcs_hps_vab_certificate_data
+ * @vab_cert_magic_num: VAB Certificate Magic Word (0xD0564142)
+ * @flags: TBD
+ * @fcs_data: Data words being certificate signed.
+ * @cert_sign_keychain: Certificate Signing Keychain
+ */
+struct fcs_hps_vab_certificate_data {
+ u32 vab_cert_magic_num; /* offset 0x10 */
+ u32 flags;
+ u8 rsvd0_1[8];
+ u8 fcs_sha384[SHA384_SUM_LEN]; /* offset 0x20 */
+};
+
+/*
+ * struct fcs_hps_vab_certificate_header
+ * @cert_magic_num: Certificate Magic Word (0x25D04E7F)
+ * @cert_data_sz: size of this certificate header (0x80)
+ * Includes magic number all the way to the certificate
+ * signing keychain (excludes cert. signing keychain)
+ *
[v2 3/6] arm: socfpga: cmd: Support 'vab' command
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/vab.c| 37 +
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/mach-socfpga/vab.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 1f1e21766d..9e63296b38 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -51,6 +51,7 @@ obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c
new file mode 100644
index 00..4c592a87cf
--- /dev/null
+++ b/arch/arm/mach-socfpga/vab.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned long addr, len;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ len = simple_strtoul(argv[2], NULL, 16);
+
+ if (socfpga_vendor_authentication((void *)&addr, (size_t *)&len) == 0)
+ printf("%s 0x%016lx (%ld bytes)\n",
+ "Image Authentication passed at address", addr, len);
+ else
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vab,3, 2, do_vab,
+ "perform vendor authorization",
+ "addr len - authorize 'len' bytes starting at\n"
+ " 'addr' via vendor public key"
+);
--
2.13.0
[v2 4/6] arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index cf365590a8..4b30473743 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -117,4 +117,26 @@
};
};
+#if defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&uboot_blob {
+ filename = "signed-u-boot-nodtb.bin";
+};
+
+&atf_blob {
+ filename = "signed-bl31.bin";
+};
+
+&uboot_fdt_blob {
+ filename = "signed-u-boot.dtb";
+};
+
+&kernel_blob {
+ filename = "signed-Image";
+};
+
+&kernel_fdt_blob {
+ filename = "signed-linux.dtb";
+};
+#endif
+
#endif
--
2.13.0
[v2 5/6] configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to *_defconfig file for both Stratix 10 and Agilex. Signed-off-by: Siew Chin Lim --- v2 --- - This is new patch in 2nd version of VAB series. This is code clean up without functionality change. --- configs/socfpga_agilex_atf_defconfig| 2 ++ configs/socfpga_agilex_defconfig| 2 ++ configs/socfpga_stratix10_atf_defconfig | 2 ++ configs/socfpga_stratix10_defconfig | 2 ++ include/configs/socfpga_soc64_common.h | 9 + 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index ad87a8098f..704a9d56b9 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -19,6 +19,8 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot" CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 230d3c2ce5..3d5d39fe0f 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -18,6 +18,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 1005ba979e..344277a6cc 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -19,6 +19,8 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot" CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 CONFIG_SPL_ATF=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 3df44bb88d..2d145e1a5f 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_OPTIMIZE_INLINING=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fdcd7d3e9a..35200833f1 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -79,19 +79,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* CONFIG_CADENCE_QSPI */ /* - * Boot arguments passed to the boot command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will override also the chosen node in FDT blob. + * Enviroment variable */ - #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "kernel.itb" -#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \ - "run mmcfitboot" #else #define CONFIG_BOOTFILE "Image" -#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ - "run mmcboot" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.13.0
[v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
Booting Agilex with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
v2
---
- Renamed CONFIG_SECURE_VAB_AUTH to CONFIG_SOCFPGA_SECURE_VAB_AUTH
- Add BOOTCOMMAND macro in defconfig
---
.../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(92%)
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_vab_defconfig
similarity index 92%
copy from configs/socfpga_agilex_atf_defconfig
copy to configs/socfpga_agilex_vab_defconfig
index 704a9d56b9..1e28efea5e 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARM_SMCCC=y
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x20
@@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
@@ -15,12 +15,13 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200
--
2.13.0
[PATCH] arm: socfpga: smc: Remove unused SMC function ID
Remove unused SMC function ID 61 and 62. Signed-off-by: Siew Chin Lim --- include/linux/intel-smc.h | 52 --- 1 file changed, 52 deletions(-) diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index cacb410691..68d62be417 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -518,56 +518,4 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_MBOX_SEND_CMD \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) -/* - * Request INTEL_SIP_SMC_HPS_SET_PHYINTF - * - * Select EMACx PHY interface - * - * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF - * a1 EMAC number: - * 0 - EMAC0 - * 1 - EMAC1 - * 2 - EMAC2 - * a2 Type of PHY interface: - * 0 - GMII_MII - * 1 - RGMII - * 2 - RMII - * 3 - RESET - * a3-7 not used - * - * Return status - * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR - */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 -#define INTEL_SIP_SMC_HPS_SET_PHYINTF \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) - -/* - * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * - * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC - * - * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): - * 0 - 0 degree - * 1 - 45 degrees - * 2 - 90 degrees - * 3 - 135 degrees - * 4 - 180 degrees - * 5 - 225 degrees - * 6 - 270 degrees - * 7 - 315 degrees - * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): - * (Same as above) - * a3-7 not used - * - * Return status - * a0 INTEL_SIP_SMC_STATUS_OK - */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK62 -#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) - #endif -- 2.13.0
[PATCH] arm: socfpga: Move Stratix10 and Agilex SPL common code
Move Stratix10 and Agilex SPL common code to spl_soc64.c.
We are in preparation for new n5x device support.
No functional change in this patch.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/spl_agilex.c | 16
arch/arm/mach-socfpga/spl_s10.c| 17 -
arch/arm/mach-socfpga/spl_soc64.c | 25 +
4 files changed, 27 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/mach-socfpga/spl_soc64.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 9e63296b38..e4c2da93d5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -70,10 +70,12 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += firewall.o
obj-y += spl_s10.o
+obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
+obj-y += spl_soc64.o
endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex.c
index 71b17ce3a5..ee5a9dc1e2 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -25,22 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
int ret;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 955a1161e8..c20e87cdbe 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -26,23 +26,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- /* TODO: Get from SDM or handoff */
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
diff --git a/arch/arm/mach-socfpga/spl_soc64.c
b/arch/arm/mach-socfpga/spl_soc64.c
new file mode 100644
index 00..cb98ab39e4
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ */
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT)
+u32 spl_boot_mode(const u32 boot_device)
+{
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
+ else
+ return MMCSD_MODE_RAW;
+}
+#endif
--
2.13.0
[v1 0/5] Restructure Stratix10 and Agilex handoff code
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
This patchset restructure Stratix10 and Agilex handoff code to be
generic and to be used by all SOC64 devices.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Rename all handoff macro prefix from S10_* to SOC64* and change
all corresponding file name from *_s10 to *_soc64. Last,
change the code to use generic fundtion from wrap_handoff_soc64.c.
History:
The first version of this patchset is extracted from "Add Intel Diamond Mesa
SoC support" series.
https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin@intel.com/
This patchset has dependency on:
1. arm: socfpga: Move Stratix10 and Agilex SPL common code
https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin....@intel.com/
Siew Chin Lim (5):
arm: socfpga: Rename Stratix10 and Agilex handoff common macros
arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
arm: socfpga: Restructure Stratix10 and Agilex handoff code
arch/arm/mach-socfpga/Makefile | 12 ++--
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 62 ++
.../include/mach/system_manager_soc64.h| 4 --
...system_manager_s10.c => system_manager_soc64.c} | 53 ++--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 -
...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 16 ++---
include/configs/socfpga_soc64_common.h | 4 +-
10 files changed, 187 insertions(+), 134 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(57%)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (74%)
--
2.13.0
[v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 39 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 +-
arch/arm/mach-socfpga/wrap_pll_config_s10.c| 16 -
include/configs/socfpga_soc64_common.h | 4 +--
6 files changed, 59 insertions(+), 59 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 642dcbb0ac..e060e5754e 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
deleted file mode 100644
index 3e9b606ce2..00
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation
- *
- */
-
-#ifndef _HANDOFF_S10_H_
-#define _HANDOFF_S10_H_
-
-/*
- * Offset for HW handoff from Quartus tools
- */
-#define S10_HANDOFF_BASE 0xFFE3F000
-#define S10_HANDOFF_MUX(S10_HANDOFF_BASE + 0x10)
-#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
-#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
-#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
-#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
-#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
-#define S10_HANDOFF_MAGIC_MUX 0x504D5558
-#define S10_HANDOFF_MAGIC_IOCTL0x494F4354
-#define S10_HANDOFF_MAGIC_FPGA 0x46504741
-#define S10_HANDOFF_MAGIC_DELAY0x444C4159
-#define S10_HANDOFF_MAGIC_CLOCK0x434C4B53
-#define S10_HANDOFF_MAGIC_MISC 0x4D495343
-#define S10_HANDOFF_OFFSET_LENGTH 0x4
-#define S10_HANDOFF_OFFSET_DATA0x10
-
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
-#else
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
-#endif
-
-#define S10_HANDOFF_SIZE 4096
-
-#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
new file mode 100644
index 00..804715b13d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation
+ *
+ */
+
+#ifndef _HANDOFF_SOC64_H_
+#define _HANDOFF_SOC64_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define SOC64_HANDOFF_BASE 0xFFE3F000
+#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580)
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MAGIC_MUX0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+#define SOC64_HANDOFF_OFFSET_LENGTH0x4
+#define SOC64_HANDOFF_OFFSET_DATA 0x10
+
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#else
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
+#endif
+
+#define SOC64_HANDOFF_SIZE 4096
+
+#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
index 0b497ec30c..d10fb5e454 100644
--- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -7,23 +7,23 @@
#include
#include
#include
-#include
+#include
static void sysmgr_pinmux_handoff_read(void *handoff_address,
const u32 **table,
unsigned int *table_len)
{
unsigned int
[v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e4c2da93d5..eca6fd173f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -38,7 +38,7 @@ obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
@@ -53,7 +53,7 @@ obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/wrap_pll_config_s10.c
rename to arch/arm/mach-socfpga/wrap_pll_config_soc64.c
--
2.13.0
[v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index eca6fd173f..f9dd166ab3 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -35,7 +35,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_soc64.o
@@ -49,7 +49,7 @@ obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/system_manager_s10.c
rename to arch/arm/mach-socfpga/system_manager_soc64.c
--
2.13.0
[v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 804715b13d..2561255712 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2020 Intel Corporation * */ @@ -10,21 +10,25 @@ /* * Offset for HW handoff from Quartus tools */ -#define SOC64_HANDOFF_BASE 0xFFE3F000 -#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) -#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) -#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) -#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) -#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) -#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +/* HPS handoff */ #define SOC64_HANDOFF_MAGIC_MUX0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 + #define SOC64_HANDOFF_OFFSET_LENGTH0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 +#define SOC64_HANDOFF_SIZE 4096 + +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608) @@ -34,6 +38,4 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif -#define SOC64_HANDOFF_SIZE 4096 - #endif /* _HANDOFF_SOC64_H_ */ -- 2.13.0
[v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Update system_manager_soc64.c to use generic handoff
function in wrap_handoff_soc64.c.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 +-
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++
.../include/mach/system_manager_soc64.h| 4 --
arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 -
6 files changed, 131 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f9dd166ab3..5779c55621 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -37,7 +37,7 @@ obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
@@ -52,7 +52,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 2561255712..f4c03688d6 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -11,6 +11,7 @@
* Offset for HW handoff from Quartus tools
*/
/* HPS handoff */
+#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
#define SOC64_HANDOFF_MAGIC_MUX0x504D5558
#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
@@ -38,4 +39,24 @@
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
+#define SOC64_HANDOFF_MUX_LEN 96
+#define SOC64_HANDOFF_IOCTL_LEN96
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_FPGA_LEN 42
+#else
+#define SOC64_HANDOFF_FPGA_LEN 40
+#endif
+#define SOC64_HANDOFF_DELAY_LEN96
+
+#ifndef __ASSEMBLY__
+#include
+enum endianness {
+ little_endian,
+ big_endian
+};
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+enum endianness big_endian);
+#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 4949cae97a..1eb8e7a904 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -10,10 +10,6 @@
void sysmgr_pinmux_init(void);
void populate_sysmgr_fpgaintf_module(void);
void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_WDDBG 0x08
#define SYSMGR_SOC64_DMA 0x20
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index c123cc9644..a19d3c2de9 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -5,9 +5,10 @@
*/
#include
+#include
+#include
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -64,39 +65,55 @@ void populate_sysmgr_fpgaintf_module(void)
*/
void populate_sysmgr_pinmux(void)
{
- const u32 *sys_mgr_table_u32;
- unsigned int len, i;
+ u32 len, i;
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
big_endian);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
big_endian);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
big_endian);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
big_endian);
+
+ len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
+ len = (len > len_fpga) ? len : len_fpga;
+ len = (len > len_delay) ? len : len_delay;
+
+ u32 handoff_
[v1 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series. We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device and we would like to clean up some code before enable N5X device. This patchset move duplicated function 'cm_get_qspi_controller_clk_hz' to clock_manager.c and change to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. History: The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series. https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin@intel.com/ This patchset has dependency on: 1. arm: socfpga: Move Stratix10 and Agilex SPL common code https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin@intel.com/ 2. Restructure Stratix10 and Agilex handoff code https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin@intel.com/ Siew Chin Lim (2): arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Changed to store QSPI reference clock in kHz arch/arm/mach-socfpga/clock_manager.c | 16 +++-- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 arch/arm/mach-socfpga/clock_manager_s10.c | 6 arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +++ .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - .../include/mach/system_manager_soc64.h| 16 - arch/arm/mach-socfpga/mailbox_s10.c| 40 +++--- include/configs/socfpga_soc64_common.h | 1 + 8 files changed, 69 insertions(+), 21 deletions(-) -- 2.13.0
[v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 5 +--
.../include/mach/system_manager_soc64.h| 16 -
arch/arm/mach-socfpga/mailbox_s10.c| 40 +++---
include/configs/socfpga_soc64_common.h | 1 +
4 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index be426a5cfb..2783b9d18d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -67,8 +67,9 @@ int set_cpu_clk_info(void)
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+ return (readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
+SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * CLOCK_1K;
}
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 1eb8e7a904..fc4e17821b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
-/* store qspi ref clock */
+/*
+ * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC
64-bit
+ * storing qspi ref clock (kHz)
+ */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD00x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD10x204
@@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
#define SYSMGR_SOC64_IODELAY0 0x1400
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC
64-bit
+ * storing qspi ref clock (kHz)
+ */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASKBIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
+
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 7dcdae8136..2a13fbb506 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -356,6 +356,38 @@ int mbox_qspi_close(void)
0, NULL, 0, 0, NULL);
}
+int mbox_qspi_set_controller_clk_hz(int clk_hz)
+{
+ u32 reg;
+ u32 clk_khz;
+
+ /* We are getting QSPI ref clock and set into sysmgr boot register */
+ /*
+* Only clock freq in kHz degree is accepted due to limited bits[27:0]
+* is reserved for storing the QSPI clock freq into boot scratch cold0
+* register
+*/
+ if (clk_hz < CLOCK_1K)
+ return -EINVAL;
+
+ clk_khz = clk_hz / CLOCK_1K;
+ printf("QSPI: Reference clock at %d kHz\n", clk_khz);
+
+ /*
+* DDR retention bit, SHA comparison bit and reset type bits sharing the
+* same scratch register in N5X, ensure the content inside register is
+* not overwritten by QSPI ref clock (kHz)
+*/
+ reg = (readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
+~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
+
+ writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
+ socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+ return 0;
+}
+
int mbox_qspi_open(void)
{
int ret;
@@ -384,10 +416,10 @@ int mbox_qspi_open(void)
if (ret)
goto error;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0],
- socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+ /* Store QSPI controller ref clock frequency*/
+ ret = mbox_qspi_set_controller_clk_hz(resp_buf[0]);
+
[v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 15 ---
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mach-socfpga/clock_manager_s10.c | 6 --
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index f0b15f770c..be426a5cfb 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -4,12 +4,13 @@
*/
#include
+#include
+#include
+#include
+#include
#include
#include
#include
-#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -63,6 +64,14 @@ int set_cpu_clk_info(void)
return 0;
}
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+#endif
+
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_agilex.c
index 6377f2ce3b..e035c09aae 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
-u32 cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index e060e5754e..4b4f0749db 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 1f734bcd65..0f0cb230fa 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index cb7923baef..98c3bf1b03 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {
--
2.13.0
[PATCH] arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabled
Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted from FIT'
checking in board_prep_linux function. And, fix typo of
CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE.
CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus,
board_prep_linux function will always be called by both ATF and
VAB boot flow.
board_pre_linux function will do 'is OS booted from FIT' checking,
and it will be called before board_fit_image_post_process function.
VAB boot flow expects the OS is always booted from FIT and with VAB
signed cerfiticate because the VAB authentication is implemented in
board_fit_image_post_process function. So, VAB needs the 'is OS booted
from FIT' checking in board_pre_linux function.
However, for ATF boot flow, it is not a requirement that the OS must
always booted from FIT. The OS can be booted from individual Image and
kernel dtb file. Thus, we should not do 'if OS is booted from FIT'
checking in board_prep_linux function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 81aa07c902..650122fcd4 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -115,7 +115,8 @@ void board_fit_image_post_process(void **p_image, size_t
*p_size)
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (!IS_ENABLED(CONFIG_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+ !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
/*
* Ensure the OS is always booted from FIT and with
* VAB signed certificate
--
2.13.0
[v2 0/5] Restructure Stratix10 and Agilex handoff code
This is the 2cd version of patchset to restructure Stratix10 and Agilex
handoff code to be generic and to be used by all SOC64 devices.
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
Patch status:
Have changes: Patch 5
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 5:
- Change "#ifdef" to "#if IS_ENABLED()"
- Change to use captial letter for enum macros (LITTLE_ENDIAN, BIG_ENDIAN)
- Soft include files by alphabetical order in system_manager_soc64.c
and wrap_handoff_soc64.c
- Simplify and clean up socfpga_get_handoff_size function
History:
[v1]:
https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin@intel.com/
The first version of this patchset is extracted from "Add Intel Diamond Mesa
SoC support" series.
https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin@intel.com/
This patchset has dependency on:
1. arm: socfpga: Move Stratix10 and Agilex SPL common code
https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin@intel.com/
Siew Chin Lim (5):
arm: socfpga: Rename Stratix10 and Agilex handoff common macros
arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
arm: socfpga: Restructure Stratix10 and Agilex handoff code
arch/arm/mach-socfpga/Makefile | 12 ++--
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 -
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 62
.../include/mach/system_manager_soc64.h| 4 --
...system_manager_s10.c => system_manager_soc64.c} | 55 +++---
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 66 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 --
...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 16 +++---
include/configs/socfpga_soc64_common.h | 4 +-
10 files changed, 181 insertions(+), 135 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(57%)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (74%)
--
2.13.0
[v2 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 39 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 +-
arch/arm/mach-socfpga/wrap_pll_config_s10.c| 16 -
include/configs/socfpga_soc64_common.h | 4 +--
6 files changed, 59 insertions(+), 59 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 642dcbb0ac..e060e5754e 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
deleted file mode 100644
index 3e9b606ce2..00
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation
- *
- */
-
-#ifndef _HANDOFF_S10_H_
-#define _HANDOFF_S10_H_
-
-/*
- * Offset for HW handoff from Quartus tools
- */
-#define S10_HANDOFF_BASE 0xFFE3F000
-#define S10_HANDOFF_MUX(S10_HANDOFF_BASE + 0x10)
-#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
-#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
-#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
-#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
-#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
-#define S10_HANDOFF_MAGIC_MUX 0x504D5558
-#define S10_HANDOFF_MAGIC_IOCTL0x494F4354
-#define S10_HANDOFF_MAGIC_FPGA 0x46504741
-#define S10_HANDOFF_MAGIC_DELAY0x444C4159
-#define S10_HANDOFF_MAGIC_CLOCK0x434C4B53
-#define S10_HANDOFF_MAGIC_MISC 0x4D495343
-#define S10_HANDOFF_OFFSET_LENGTH 0x4
-#define S10_HANDOFF_OFFSET_DATA0x10
-
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
-#else
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
-#endif
-
-#define S10_HANDOFF_SIZE 4096
-
-#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
new file mode 100644
index 00..804715b13d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation
+ *
+ */
+
+#ifndef _HANDOFF_SOC64_H_
+#define _HANDOFF_SOC64_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define SOC64_HANDOFF_BASE 0xFFE3F000
+#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580)
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MAGIC_MUX0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+#define SOC64_HANDOFF_OFFSET_LENGTH0x4
+#define SOC64_HANDOFF_OFFSET_DATA 0x10
+
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#else
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
+#endif
+
+#define SOC64_HANDOFF_SIZE 4096
+
+#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
index 0b497ec30c..d10fb5e454 100644
--- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -7,23 +7,23 @@
#include
#include
#include
-#include
+#include
static void sysmgr_pinmux_handoff_read(void *handoff_address,
const u32 **table,
unsigned int *table_len)
{
unsigned int
[v2 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e4c2da93d5..eca6fd173f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -38,7 +38,7 @@ obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
@@ -53,7 +53,7 @@ obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/wrap_pll_config_s10.c
rename to arch/arm/mach-socfpga/wrap_pll_config_soc64.c
--
2.13.0
[v2 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index eca6fd173f..f9dd166ab3 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -35,7 +35,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_soc64.o
@@ -49,7 +49,7 @@ obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/system_manager_s10.c
rename to arch/arm/mach-socfpga/system_manager_soc64.c
--
2.13.0
[v2 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 804715b13d..2561255712 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2020 Intel Corporation * */ @@ -10,21 +10,25 @@ /* * Offset for HW handoff from Quartus tools */ -#define SOC64_HANDOFF_BASE 0xFFE3F000 -#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) -#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) -#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) -#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) -#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) -#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +/* HPS handoff */ #define SOC64_HANDOFF_MAGIC_MUX0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 + #define SOC64_HANDOFF_OFFSET_LENGTH0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 +#define SOC64_HANDOFF_SIZE 4096 + +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608) @@ -34,6 +38,4 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif -#define SOC64_HANDOFF_SIZE 4096 - #endif /* _HANDOFF_SOC64_H_ */ -- 2.13.0
