Re: [PATCH 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox
Hello Tom, Thank you for your comment! 2021年4月14日(水) 2:47 Tom Rini : > > On Wed, Apr 14, 2021 at 12:30:15AM +0900, Masami Hiramatsu wrote: > > > Add device trees for 96boards EE DeveloperBox and basement SynQuacer > > SoC dtsi. These files are imported from EDK2 with cosmetic change > > and modified for accessing SPI NOR flash. > > > > Signed-off-by: Masami Hiramatsu > > --- > > arch/arm/dts/DeveloperBox.dts | 146 + > > arch/arm/dts/Makefile |2 > > arch/arm/dts/SynQuacer.dtsi | 590 > > + > > arch/arm/dts/SynQuacerCaches.dtsi | 72 + > > This poses a bit of a naming challenge. I assume, but please correct me > if I'm wrong, that you don't intend to push these dts files to the Linux > kernel. So that means EDK2 is the primary source of the files, yes? Yes, those are originally written for the EDK2 and I ported it. > We > want to keep them as-is from the upstream project, and note that > relevant git hash/tag/etc that matches where we pulled from, to make > future syncs easier, in the commit message. Let me confirm what you mean, is the git hash/tag/etc what the commit I copied from? and note it in commit message or in the devicetree file? BTW, I made some changes on it for U-Boot drivers. - Enabled OP-TEE node by default (EDK2 checks OP-TEE existance and enables it) - Add SPI node information for accessing SPI-NOR from U-Boot (EDK2 embedded such information inside) Thus the DeveloperBox.dts may not be kept as-is. > I assume this is not part of the uniphier family, so we should start by > naming these as arch/arm/dts/synquacer-... to fit with the general > scheme. Perhaps -developerbox, -core and -caches ? OK. BTW, I'm not sure what is the best way to use SYS_CPU and SYS_SOC. This SoC family name is SynQuacer and the SoC itself is SC2A11. In this case, CONFIG_SYS_CPU=synquacer CONFIG_SYS_SOC=sc2a11 or CONFIG_SYS_SOC=synquacer-sc2a11 ? > And for any changes > we do need, they go in a -u-boot.dtsi file and then potentially > automatically included (if it fits in the logic we have today for that) > or specifically #included otherwise. It seems that (CONFIG_SYS_SOC)-u-boot.dtsi is automatically included, am I correct? Thank you, -- Masami Hiramatsu
Re: [PATCH 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Hello Tom,
2021年4月14日(水) 2:47 Tom Rini :
>
> On Wed, Apr 14, 2021 at 12:31:21AM +0900, Masami Hiramatsu wrote:
>
> > Add the DeveloperBox 96boards EE support. This board is also
> > known as Socionext SynQuacer E-Series. It contians one "SC2A11"
> > SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
> > 3 PCIe slots (1 4x port and 2 1x ports which are expanded via
> > PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
> > ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
> > MicroATX Form Factor.
> >
> > For more information, see this page;
> > https://www.96boards.org/product/developerbox/
> >
> > Signed-off-by: Masami Hiramatsu
> [snip]
> > diff --git a/arch/arm/include/asm/arch-sc2a11/gpio.h
> > b/arch/arm/include/asm/arch-sc2a11/gpio.h
> > new file mode 100644
> > index 00..6779803080
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-sc2a11/gpio.h
> > @@ -0,0 +1,9 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2021 (C) Linaro Ltd.
> > + */
> > +
> > +#ifndef __ASM_ARCH_SC2A11_GPIO_H
> > +#define __ASM_ARCH_SC2A11_GPIO_H
> > +
> > +#endif
>
> Please update the list in arch/arm/include/asm/gpio.h to not look for
> asm/arch/gpio.h on this SoC, thanks.
Ah, I missed that. OK, I'll change arch/arm/include/asm/gpio.h.
BTW, isn't it better to introduce CONFIG_ARCH_GENERIC_GPIO
instead of updating the header?
> > diff --git a/board/socionext/developerbox/README
> > b/board/socionext/developerbox/README
> > new file mode 100644
> > index 00..bb121002dd
> > --- /dev/null
> > +++ b/board/socionext/developerbox/README
>
> This needs to be in rST form and under doc/board/ now.
>
> [snip]
> > +/*
> > + * arguments for booti command
> > + */
> > +#define LINUX_BASIC_BOOTARGS "basic_bootargs='"
> > \
> > + "console=ttyAMA0,"
> > __stringify(CONFIG_BAUDRATE) " " \
> > + "rootwait verbose'\0"
> > +
> > +/* kernel:mmcblk0p1(ext2), rootfs:mmcblk0p1(ext2), devtree:mmcblk0p1(ext2)
> > */
> > +#define LINUX_MMCBOOTCOMMAND1
> > \
> > + "mmcboot1=echo 'Boot from MMC (ext2 single rootfs)' ; "
> > \
> > + "mmc dev 0 &&"
> > \
> > + "ext2load mmc 0:1 ${kernel_addr} /boot/Image && "
> > \
> > + "ext2load mmc 0:1 ${fdt_addr_base} /boot/DeveloperBox.dtb &&
> > " \
> > + "setenv fdt_addr ${fdt_addr_base} &&"
> > \
> > + "setenv fdt_size ${filesize} &&"
> > \
> > + "setenv bootargs ${mmc_bootargs1} && "
> > \
> > + "booti ${kernel_addr} - ${fdt_addr}\0"
> > \
> > + "mmc_bootargs1="
> > \
> > + "root=/dev/mmcblk0p1 rw dtb=0x${fdt_addr},0x${fdt_size} "
> > \
> > + "${basic_bootargs} \0"
>
> You are strongly encouraged to use the generic distro boot features
> instead. This may require a little work to handle the device tree.
OK, anyway I can just drop it, because this platform is expected to use
UEFI boot (the DeveloperBox is shipped with EDK2).
I left this just for reference.
Thank you,
--
Masami Hiramatsu
Re: [PATCH 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Hi Takahiro,
2021年4月14日(水) 10:27 Takahiro Akashi :
>
> On Wed, Apr 14, 2021 at 10:12:42AM +0900, Masami Hiramatsu wrote:
> > Hello Tom,
> >
> > 2021年4月14日(水) 2:47 Tom Rini :
> > >
> > > On Wed, Apr 14, 2021 at 12:31:21AM +0900, Masami Hiramatsu wrote:
> > >
> > > > Add the DeveloperBox 96boards EE support. This board is also
> > > > known as Socionext SynQuacer E-Series. It contians one "SC2A11"
> > > > SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
> > > > 3 PCIe slots (1 4x port and 2 1x ports which are expanded via
> > > > PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
> > > > ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
> > > > MicroATX Form Factor.
> > > >
> > > > For more information, see this page;
> > > > https://www.96boards.org/product/developerbox/
> > > >
> > > > Signed-off-by: Masami Hiramatsu
> > > [snip]
> > > > diff --git a/arch/arm/include/asm/arch-sc2a11/gpio.h
> > > > b/arch/arm/include/asm/arch-sc2a11/gpio.h
> > > > new file mode 100644
> > > > index 00..6779803080
> > > > --- /dev/null
> > > > +++ b/arch/arm/include/asm/arch-sc2a11/gpio.h
> > > > @@ -0,0 +1,9 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +/*
> > > > + * Copyright 2021 (C) Linaro Ltd.
> > > > + */
> > > > +
> > > > +#ifndef __ASM_ARCH_SC2A11_GPIO_H
> > > > +#define __ASM_ARCH_SC2A11_GPIO_H
> > > > +
> > > > +#endif
> > >
> > > Please update the list in arch/arm/include/asm/gpio.h to not look for
> > > asm/arch/gpio.h on this SoC, thanks.
> >
> > Ah, I missed that. OK, I'll change arch/arm/include/asm/gpio.h.
> >
> > BTW, isn't it better to introduce CONFIG_ARCH_GENERIC_GPIO
> > instead of updating the header?
> >
> > > > diff --git a/board/socionext/developerbox/README
> > > > b/board/socionext/developerbox/README
> > > > new file mode 100644
> > > > index 00..bb121002dd
> > > > --- /dev/null
> > > > +++ b/board/socionext/developerbox/README
> > >
> > > This needs to be in rST form and under doc/board/ now.
> > >
> > > [snip]
> > > > +/*
> > > > + * arguments for booti command
> > > > + */
> > > > +#define LINUX_BASIC_BOOTARGS "basic_bootargs='"
> > > > \
> > > > + "console=ttyAMA0,"
> > > > __stringify(CONFIG_BAUDRATE) " " \
> > > > + "rootwait verbose'\0"
> > > > +
> > > > +/* kernel:mmcblk0p1(ext2), rootfs:mmcblk0p1(ext2),
> > > > devtree:mmcblk0p1(ext2) */
> > > > +#define LINUX_MMCBOOTCOMMAND1
> > > > \
> > > > + "mmcboot1=echo 'Boot from MMC (ext2 single rootfs)' ; "
> > > > \
> > > > + "mmc dev 0 &&"
> > > > \
> > > > + "ext2load mmc 0:1 ${kernel_addr} /boot/Image && "
> > > > \
> > > > + "ext2load mmc 0:1 ${fdt_addr_base} /boot/DeveloperBox.dtb
> > > > && " \
> > > > + "setenv fdt_addr ${fdt_addr_base} &&"
> > > > \
> > > > + "setenv fdt_size ${filesize} &&"
> > > > \
> > > > + "setenv bootargs ${mmc_bootargs1} && "
> > > > \
> > > > + "booti ${kernel_addr} - ${fdt_addr}\0"
> > > > \
> > > > + "mmc_bootargs1="
> > > > \
> > > > + "root=/dev/mmcblk0p1 rw dtb=0x${fdt_addr},0x${fdt_size} "
> > > > \
> > > > + "${basic_bootargs} \0"
> > >
> > > You are strongly encouraged to use the generic distro boot features
> > > instead. This may require a little work to handle the device tree.
> >
> > OK, anyway I can just drop it, because this platform is expected to use
> > UEFI boot (the DeveloperBox is shipped with EDK2).
> > I left this just for reference.
>
> So why not define UEFI load options (BOOT) and use UEFI boot manager
> ("bootefi bootmgr")?
> That is the way how UEFI (at least boot manager) boots the kernel.
Good point! Actually, I'm not sure how to define the BOOT in
config.h (I only
know how to include efivars file when build). Could you tell me how to do it?
I would like to rewrite the default boot commands.
Thank you,
--
Masami Hiramatsu
Re: [PATCH 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Hi Takahiro,
2021年4月14日(水) 13:48 Takahiro Akashi :
>
> > > So why not define UEFI load options (BOOT) and use UEFI boot manager
> > > ("bootefi bootmgr")?
> > > That is the way how UEFI (at least boot manager) boots the kernel.
> >
> > Good point! Actually, I'm not sure how to define the BOOT in
> > config.h (I only
> > know how to include efivars file when build). Could you tell me how to do
> > it?
> > I would like to rewrite the default boot commands.
>
> For example,
> => efidebug boot add 1 USBBOOT usb 0:1 /EFI/BOOT/bootaa64.efi
> => efidebug boot add 2 MMCBOOT mmc 0:1 /EFI/BOOT/bootaa64.efi
> => efidebug boot order 1 2
> => bootefi bootmgr
Hmm, but this can not be embedded in the build process, can this?
>
> Since "BOOTxxx" are non-volatile variables, we don't have to
> set them again once those commands are run.
What is the default behavior of "bootefi bootmgr" if there is no
BOOT is set?
If it just do nothing and exit, I think I can add it to the top of
CONFIG_BOOTCOMMAND
so that U-Boot can try it first.
(BOOT will be set by user after boot)
> But distro_bootcmd can also detect and try to boot "bootaa64.efi" anyway.
> (I'm not sure about the order of devices to detect though.)
Hmm, interesting. OK, I'll try to enable distro_bootcmd.
Thank you,
>
> -Takahiro Akashi
>
> > Thank you,
> >
> > --
> > Masami Hiramatsu
--
Masami Hiramatsu
Re: [PATCH 03/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Hi Bin,
On Thu, 15 Apr 2021 06:30:27 +0800
Bin Meng wrote:
> Hi,
>
> On Thu, Apr 15, 2021 at 3:39 AM Simon Glass wrote:
> >
> > On Tue, 13 Apr 2021 at 16:23, Masami Hiramatsu
> > wrote:
> > >
> > > Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
> > > sets the VGA bridge bits by checking pplat->class, but if the parent
> > > device is the pci host bus device, it can be skipped. Moreover, it
> > > shouldn't access the pplat because the parent has different plat data.
> > >
> > > Without this fix, "pci enum" command cause a synchronous abort.
> > >
> > > pci_auto_config_devices: start
> > > PCI Autoconfig: Bus Memory region: [7800-7fff],
> > > Physical Memory [7800-7fffx]
> > > PCI Autoconfig: Bus I/O region: [0-],
> > > Physical Memory [77f0-77f0x]
> > > pci_auto_config_devices: device pci_6:0.0
> > > PCI Autoconfig: BAR 0, Mem, size=0x100, address=0x7800
> > > bus_lower=0x7900
> > >
> > > PCI Autoconfig: BAR 1, Mem, size=0x800, No room in resource, avail
> > > start=7900 / size=800, need=800
> > > PCI: Failed autoconfig bar 14
> > >
> > > PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
> > >
> > > PCI Autoconfig: BAR 3, Mem, size=0x200, address=0x7a00
> > > bus_lower=0x7c00
> > >
> > > PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
> > >
> > > PCI Autoconfig: ROM, size=0x8, address=0x7c00 bus_lower=0x7c08
> > >
> > > "Synchronous Abort" handler, esr 0x9606
> > > elr: e002bd28 lr : e002bce8 (reloc)
> > > elr: fff6fd28 lr : fff6fce8
> > > x0 : 1041 x1 : 003e
> > > x2 : ffb0f8c8 x3 : 0001
> > > x4 : 0080 x5 :
> > > x6 : fff718fc x7 : 000f
> > > x8 : ffb0f238 x9 : 0008
> > > x10: x11: 0010
> > > x12: 0006 x13: 0001869f
> > > x14: ffb0fcd0 x15: 0020
> > > x16: fff71cc4 x17: 0000
> > > x18: ffb13d90 x19: ffb14320
> > > x20: x21: ffb14090
> > > x22: ffb0f8c8 x23: 0001
> > > x24: ffb14c10 x25:
> > > x26: x27:
> > > x28: ffb14c70 x29: ffb0f830
> > >
> > > Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
> > > Resetting CPU ...
> > >
> > > Signed-off-by: Masami Hiramatsu
> > > ---
> > > drivers/pci/pci-uclass.c |3 +++
> > > 1 file changed, 3 insertions(+)
> >
> > Reviewed-by: Simon Glass
>
> I can't find this patch in my inbox, nor in the patchwork.
Hmm, it is strange... I set up gitconfig but it seems not working well.
Let me send patch via my MUA next time.
> Could you please resend?
OK, I attached it to this mail. (maybe it is safer in this case)
Thank you,
--
Linaro
dm-pci-skip-setting-vga-bridge
Description: Binary data
Re: [PATCH 01/13] pci: Update the highest subordinate bus number for bridge setup
Hi Tim,
Sorry for confusion. It may be my git configuration issue.
It seems not to correctly send the series to the SMTP server.
Here is the patch.
Thank you,
2021年4月16日(金) 0:07 Tim Harvey :
>
> On Wed, Apr 14, 2021 at 12:38 PM Simon Glass wrote:
> >
> > On Tue, 13 Apr 2021 at 16:21, Masami Hiramatsu
> > wrote:
> > >
> > > Update the highest subordinate bus number after probing the devices
> > > under the bus for setting up the bridge correctly.
> > > The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > removed this but it is required if a PCIe bridge is under the bus.
> > >
> > > Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > Signed-off-by: Masami Hiramatsu
> > > ---
> > > drivers/pci/pci-uclass.c |3 +++
> > > 1 file changed, 3 insertions(+)
> >
> > Reviewed-by: Simon Glass
> >
> > Can we add a test for this?
>
> Simon / Masami,
>
> I ran into this regression as well and likely need the same patch. My
> mailer did not receive the original patch and I can't seem to find it
> anywhere, can you please resend this?
>
> Best regards,
>
> Tim
--
Masami Hiramatsu
pci-update-the-highest
Description: Binary data
Re: [PATCH 01/13] pci: Update the highest subordinate bus number for bridge setup
Hi Tim,
2021年4月16日(金) 9:21 Tim Harvey :
>
> On Thu, Apr 15, 2021 at 5:15 PM Masami Hiramatsu
> wrote:
> >
> > Hi Tim,
> >
> > Sorry for confusion. It may be my git configuration issue.
> > It seems not to correctly send the series to the SMTP server.
> > Here is the patch.
> >
> > Thank you,
> >
> > 2021年4月16日(金) 0:07 Tim Harvey :
> > >
> > > On Wed, Apr 14, 2021 at 12:38 PM Simon Glass wrote:
> > > >
> > > > On Tue, 13 Apr 2021 at 16:21, Masami Hiramatsu
> > > > wrote:
> > > > >
> > > > > Update the highest subordinate bus number after probing the devices
> > > > > under the bus for setting up the bridge correctly.
> > > > > The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > > > removed this but it is required if a PCIe bridge is under the bus.
> > > > >
> > > > > Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > > > Signed-off-by: Masami Hiramatsu
> > > > > ---
> > > > > drivers/pci/pci-uclass.c |3 +++
> > > > > 1 file changed, 3 insertions(+)
> > > >
> > > > Reviewed-by: Simon Glass
> > > >
> > > > Can we add a test for this?
> > >
> > > Simon / Masami,
> > >
> > > I ran into this regression as well and likely need the same patch. My
> > > mailer did not receive the original patch and I can't seem to find it
> > > anywhere, can you please resend this?
> > >
> > > Best regards,
> > >
> > > Tim
> >
>
> Masami,
>
> Thanks - yes, this is the patch I have also which is required for
> dm-pci with a bridge which I have on Gateworks Ventana boards.
>
> Tested-by: Tim Harvey
Thanks for testing!
>
> Tim
--
Masami Hiramatsu
Re: [PATCH 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox
Hi Tom, 2021年4月15日(木) 2:33 Tom Rini : > > BTW, I made some changes on it for U-Boot drivers. > > - Enabled OP-TEE node by default (EDK2 checks OP-TEE existance > > and enables it) > > - Add SPI node information for accessing SPI-NOR from U-Boot (EDK2 > > embedded such information inside) > > Thus the DeveloperBox.dts may not be kept as-is. > > These kinds of changes can be done in something such as > DeveloperBox-u-boot.dtsi. Check out the logic in scripts/Makefile.lib > around automatic inclusion of a "-u-boot.dtsi" file. OK, I confirmed adding "CONFIG_DEFAULT_DEVICE_TREE-u-boot.dtsi" works. > > > I assume this is not part of the uniphier family, so we should start by > > > naming these as arch/arm/dts/synquacer-... to fit with the general > > > scheme. Perhaps -developerbox, -core and -caches ? > > > > OK. BTW, I'm not sure what is the best way to use SYS_CPU and SYS_SOC. > > This SoC family name is SynQuacer and the SoC itself is SC2A11. > > In this case, > > CONFIG_SYS_CPU=synquacer > > CONFIG_SYS_SOC=sc2a11 > > or > > CONFIG_SYS_SOC=synquacer-sc2a11 > > I think the first example you list is likely the best. I found that SYS_CPU is already set to "armv8" and it is used in the build process. So I will not change it. Thank you, -- Masami Hiramatsu
Re: [PATCH 1/3] pci: Update the highest subordinate bus number for bridge setup
Hi Tim,
Thanks for picking it up. I'll drop this patch from the next version.
Thank you,
2021年4月17日(土) 6:53 Tim Harvey :
>
> From: Masami Hiramatsu
>
> Update the highest subordinate bus number after probing the devices
> under the bus for setting up the bridge correctly.
> The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
> removed this but it is required if a PCIe bridge is under the bus.
>
> Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
> Signed-off-by: Masami Hiramatsu
> ---
> drivers/pci/pci-uclass.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> index dfd54b339f..f463ef3550 100644
> --- a/drivers/pci/pci-uclass.c
> +++ b/drivers/pci/pci-uclass.c
> @@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
> return log_msg_ret("probe", ret);
> }
>
> + if (!ea_pos)
> + sub_bus = pci_get_bus_max();
> +
> dm_pciauto_postscan_setup_bridge(bus, sub_bus);
>
> return sub_bus;
> --
> 2.17.1
>
--
Masami Hiramatsu
Re: [PATCH 1/3] pci: Update the highest subordinate bus number for bridge setup
Hi Tim,
2021年4月17日(土) 7:35 Tim Harvey :
>
> On Fri, Apr 16, 2021 at 3:30 PM Masami Hiramatsu
> wrote:
> >
> > Hi Tim,
> >
> > Thanks for picking it up. I'll drop this patch from the next version.
> >
> > Thank you,
> >
> > 2021年4月17日(土) 6:53 Tim Harvey :
> > >
> > > From: Masami Hiramatsu
> > >
> > > Update the highest subordinate bus number after probing the devices
> > > under the bus for setting up the bridge correctly.
> > > The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > removed this but it is required if a PCIe bridge is under the bus.
> > >
> > > Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
> > > Signed-off-by: Masami Hiramatsu
> > > ---
> > > drivers/pci/pci-uclass.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> > > index dfd54b339f..f463ef3550 100644
> > > --- a/drivers/pci/pci-uclass.c
> > > +++ b/drivers/pci/pci-uclass.c
> > > @@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
> > > return log_msg_ret("probe", ret);
> > > }
> > >
> > > + if (!ea_pos)
> > > + sub_bus = pci_get_bus_max();
> > > +
> > > dm_pciauto_postscan_setup_bridge(bus, sub_bus);
> > >
> > > return sub_bus;
> > > --
> > > 2.17.1
> > >
>
> Masami,
>
> I'm not a maintainer, I just re-posted it. I do need this fix for my
> Gateworks Ventana driver-model conversion completion however so I put
> it in my series as well. Hopefully 'someone' will pick it up :)
I got it. Anyway I can refer to this on the ML archive, so I'll point
to this from the next version.
Mine was not sent to ML because of my poor typo :(
Thank you!
>
> Tim
--
Masami Hiramatsu
[PATCH v2 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hello, Here is the 2nd version of the series (including some fixes for build errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. Because of my poor typo, the previous version was not sent to the ML. Anyway I have fixed it. This series includes not only DeveloperBox support but also some fixes for the issues which I faced while porting U-Boot on the DeveloperBox. First 3 patches are fixes, next 1 patch is a code cleanup for generic gpio for arm. The next 7 patches adding DeveloperBox devices and board support. The last 2 patches are related to the UEFI capsule update. Changes in v2 - Previous [1/13] was re-sent to the ML by Tim Harvey, so I dropped it. So this series needs the following patch. https://lists.denx.de/pipermail/u-boot/2021-April/447519.html And I had some comments on the v1 patch, so I updated: [10/13] - Add reference commit id of original EDK2 to the comment - Just copy the EDK2 dts files as-is (change #include path) - Split out the u-boot specific changes in -u-boot.dtsi. - Removed unneeded spi-nor flash partition information. [11/13] - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. DeveloperBox DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots (1x slots are connected via PCIe bridge chip) * 4 USB-3.0 ports * 2 SATA ports * 1 GbE network port * 1 USB-UART serial port (micro USB) * 64MB SPI NOR Flash * 8GB eMMC Flash Storage * 96boards LS connector The DeveloperBox schematic can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf And the other documents can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/ Currently, the U-Boot port supports: - * USB * eMMC * SPI-NOR * SATA * GbE The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as BL33, but no need to combine with it. Thank you, --- Jassi Brar (4): mtd: spi-nor-ids: add support for Macronix mx25u51245g and mx66u1g45g flash mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver spi: synquacer: Add HSSPI SPI controller driver for SynQuacer net: synquacer: Add netsec driver Masami Hiramatsu (9): ata: ahci-pci: Use scsi_ops to initialize ops dm: pci: Skip setting VGA bridge bits if parent device is the host bus efi: Fix to use null handle to create new handle for efi_fmp_raw gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs pci: synquacer: Add SynQuacer ECAM based PCIe driver ARM: dts: synquacer: Add device trees for DeveloperBox board: synquacer: Add DeveloperBox 96boards EE support doc: qemu: arm64: Fix the documentation of capsule update configs: synquacer: Enable EFI capsule update support arch/arm/Kconfig | 32 + arch/arm/dts/Makefile |2 arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 + .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 57 + arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 + arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++ arch/arm/include/asm/gpio.h|8 board/cortina/common/Kconfig |1 board/socionext/developerbox/Kconfig | 36 + board/socionext/developerbox/MAINTAINERS | 13 board/socionext/developerbox/Makefile |9 board/socionext/developerbox/developerbox.c| 145 +++ configs/synquacer_developerbox_defconfig | 108 ++ doc/board/emulation/qemu_capsule_update.rst| 11 doc/board/index.rst|1 doc/board/socionext/developerbox.rst | 87 ++ doc/board/socionext/index.rst |9 drivers/ata/ahci-pci.c |2 drivers/mmc/Kconfig| 10 drivers/mmc/Makefile |1 drivers/mmc/f_sdh30.c | 81 + drivers/mmc/sdhci.c|9 drivers/mtd/spi/spi-nor-ids.c |2 drivers/net/Kconfig|8 drivers/net/Makefile |1
[PATCH v2 01/13] ata: ahci-pci: Use scsi_ops to initialize ops
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/ata/ahci-pci.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f..b1d231e0f9 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops= &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
[PATCH v2 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [7800-7fff],
Physical Memory [7800-7fffx]
PCI Autoconfig: Bus I/O region: [0-],
Physical Memory [77f0-77f0x]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x100, address=0x7800
bus_lower=0x7900
PCI Autoconfig: BAR 1, Mem, size=0x800, No room in resource, avail
start=7900 / size=800, need=800
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x200, address=0x7a00
bus_lower=0x7c00
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x8, address=0x7c00 bus_lower=0x7c08
"Synchronous Abort" handler, esr 0x9606
elr: e002bd28 lr : e002bce8 (reloc)
elr: fff6fd28 lr : fff6fce8
x0 : 1041 x1 : 003e
x2 : ffb0f8c8 x3 : 0001
x4 : 0080 x5 :
x6 : fff718fc x7 : 000f
x8 : ffb0f238 x9 : 0008
x10: x11: 0010
x12: 0006 x13: 0001869f
x14: ffb0fcd0 x15: 0020
x16: fff71cc4 x17:
x18: ffb13d90 x19: ffb14320
x20: x21: ffb14090
x22: ffb0f8c8 x23: 0001
x24: ffb14c10 x25:
x26: x27:
x28: ffb14c70 x29: ffb0f830
Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/pci/pci-uclass.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index f463ef3550..e9baa34e74 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
[PATCH v2 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw
When running the efidebug capsule disk-update command, the efi_fmp_raw
protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
below. This is because the code passes efi_root instaed of handle.
=> efidebug capsule disk-update
EFI: Call: efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbaf5988)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbaf5988,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6ee8)
EFI: new handle fbb37520
EFI: Exit: efi_install_protocol_interface: 0
EFI: 0 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 0
EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbfec648)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbfec648,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6f18)
EFI: handle fbaf8520
EFI: Exit: efi_install_protocol_interface: 2
EFI: 2 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 2
EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
Command failed, result=1
To fix this issue, pass the handle variable as same as the efi_fmp_fit
installation.
Signed-off-by: Masami Hiramatsu
---
lib/efi_loader/efi_capsule.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 7ba1ced0a0..ebb0725484 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -938,7 +938,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
handle = NULL;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &efi_root,
+ &handle,
&efi_guid_firmware_management_protocol,
&efi_fmp_raw, NULL));
}
[PATCH v2 04/13] gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs
Many architecture do not have specific asm/arch/gpio.h, so instead of adding !defined(CONFIG_ARCH_xxx), introduce CONFIG_ONLY_GENERIC_GPIO and select it. Signed-off-by: Masami Hiramatsu --- arch/arm/Kconfig | 17 + arch/arm/include/asm/gpio.h |8 +--- board/cortina/common/Kconfig |1 + 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3307f2b3fc..fba28323cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -89,6 +89,11 @@ config HAS_VBAR config HAS_THUMB2 bool +config ONLY_GENERIC_GPIO + bool + help + The target has no arch-/gpio.h and use only asm-generic/gpio.h. + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -634,18 +639,21 @@ config ARCH_BCM283X config ARCH_BCM63158 bool "Broadcom BCM63158 family" + select ONLY_GENERIC_GPIO select DM select OF_CONTROL imply CMD_DM config ARCH_BCM68360 bool "Broadcom BCM68360 family" + select ONLY_GENERIC_GPIO select DM select OF_CONTROL imply CMD_DM config ARCH_BCM6858 bool "Broadcom BCM6858 family" + select ONLY_GENERIC_GPIO select DM select OF_CONTROL imply CMD_DM @@ -716,6 +724,7 @@ config TARGET_BCMNS2 config TARGET_BCMNS3 bool "Support Broadcom NS3" select ARM64 + select ONLY_GENERIC_GPIO select BOARD_LATE_INIT help Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit @@ -784,6 +793,7 @@ config ARCH_KEYSTONE config ARCH_K3 bool "Texas Instruments' K3 Architecture" + select ONLY_GENERIC_GPIO select SPL select SUPPORT_SPL select FIT @@ -929,6 +939,7 @@ config ARCH_OWL config ARCH_QEMU bool "QEMU Virtual Platform" + select ONLY_GENERIC_GPIO select DM select DM_SERIAL select OF_CONTROL @@ -1061,6 +1072,7 @@ config ARCH_SUNXI config ARCH_U8500 bool "ST-Ericsson U8500 Series" select CPU_V7A + select ONLY_GENERIC_GPIO select DM select DM_GPIO select DM_MMC if MMC @@ -1203,6 +1215,7 @@ config TARGET_VEXPRESS64_JUNO config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" select ARM64 + select ONLY_GENERIC_GPIO select PL01X_SERIAL select DM select DM_SERIAL @@ -1633,6 +1646,7 @@ config TARGET_COLIBRI_PXA270 config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" + select ONLY_GENERIC_GPIO select BOARD_LATE_INIT select DM select DM_ETH @@ -1670,6 +1684,7 @@ config ARCH_STM32 config ARCH_STI bool "Support STMicrolectronics SoCs" + select ONLY_GENERIC_GPIO select BLK select CPU_V7A select DM @@ -1717,6 +1732,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" + select ONLY_GENERIC_GPIO select BLK select BINMAN if SPL_OPTEE select DM @@ -1778,6 +1794,7 @@ config TARGET_THUNDERX_88XX config ARCH_ASPEED bool "Support Aspeed SoCs" + select ONLY_GENERIC_GPIO select DM select OF_CONTROL imply CMD_DM diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 7609367884..bf1f239f81 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,10 +1,4 @@ -#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ - !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ - !defined(CONFIG_ARCH_QEMU) +#if !defined(CONFIG_ONLY_GENERIC_GPIO) #include #endif #include diff --git a/board/cortina/common/Kconfig b/board/cortina/common/Kconfig index 00c709e70f..3f1be84d21 100644 --- a/board/cortina/common/Kconfig +++ b/board/cortina/common/Kconfig @@ -1,6 +1,7 @@ config CORTINA_PLATFORM bool "Cortina-Access Platform" default y + select ONLY_GENERIC_GPIO help Select this option for Cortina-Access platforms to enables selection of CA drivers
[PATCH v2 05/13] mtd: spi-nor-ids: add support for Macronix mx25u51245g and mx66u1g45g flash
From: Jassi Brar
Signed-off-by: Jassi Brar
---
drivers/mtd/spi/spi-nor-ids.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 2b57797954..30a18b4140 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -160,9 +160,11 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_4B_OPCODES) },
+ { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
[PATCH v2 06/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile |1 drivers/pci/pcie_ecam_synquacer.c | 600 + 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index ba41787f64..e36551a771 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 5ed94bc95c..6338c595af 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 00..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOPBIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REGBIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_10x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +
[PATCH v2 07/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
From: Jassi Brar
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile |1 +
drivers/mmc/f_sdh30.c | 81 +
drivers/mmc/sdhci.c |9 +
4 files changed, 101 insertions(+)
create mode 100644 drivers/mmc/f_sdh30.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f8ca52efb6..a9ae419e41 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -549,6 +549,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config F_SDH30_SDHCI
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db3..b48a76ba94 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER)+= tmio-common.o
uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_F_SDH30_SDHCI)+= f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 00..44c6521bfe
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 2, 40);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops= &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index d9ab6a0a83..f038debc6c 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -708,6 +708,15 @@ static int sdhci_init(struct mmc *mmc)
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
+ if (IS_ENABLED(CONFIG_F_SDH30_SDHCI)) {
+ /*
+* Reference to Part1 Physical Layer Simplified Specification
+* Ver 3.01, 6.4.1 Power Up
+* This delay must be at least 74 clock sizes, or 1 ms.
+*/
+ udelay(1000);
+ }
+
if (host->ops && host->ops->get_cd)
host->ops->get_cd(host);
[PATCH v2 08/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
From: Jassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
drivers/spi/Kconfig |8 +
drivers/spi/Makefile|1
drivers/spi/spi-synquacer.c | 491 +++
3 files changed, 500 insertions(+)
create mode 100644 drivers/spi/spi-synquacer.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..62d9676550 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -481,4 +481,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..98c95323d1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 00..ce558c4bc0
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MCTRL 0x0
+#define MEN0
+#define CSEN 1
+#define IPCLK 3
+#define MES4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF0x14
+#define TXE0x18
+#define TXC0x1c
+#define RXF0x20
+#define RXE0x24
+#define RXC0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART0x38
+#define TRIGGER0
+#define DMSTOP 8
+#define CS_MASK3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX1
+#define DATA_TX2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
[PATCH v2 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu
---
Changes in v2:
- Add reference commit id of original EDK2 to the comment
- Just copy the EDK2 dts files as-is (change #include path)
- Split out the u-boot specific changes in -u-boot.dtsi.
- Removed unneeded spi-nor flash partition information.
---
arch/arm/dts/Makefile |2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 57 ++
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++
arch/arm/dts/synquacer-sc2a11.dtsi | 595
5 files changed, 783 insertions(+)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c6710826a0..127fdb75a2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1032,6 +1032,8 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi
b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 00..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref {\
+i-cache-size = <0x8000>;\
+i-cache-line-size = <64>; \
+i-cache-sets = <256>; \
+d-cache-size = <0x8000>;\
+d-cache-line-size = <64>; \
+d-cache-sets = <128>; \
+l2-cache = ; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+cache-size = <0x4>; \
+cache-line-size = <64>; \
+cache-sets = <256>; \
+cache-unified; \
+next-level-cache = <&L3>; \
+};
+
+/ {
+__L2(0)
+__L2(1)
+__L2(2)
+__L2(3)
+__L2(4)
+__L2(5)
+__L2(6)
+__L2(7)
+__L2(8)
+__L2(9)
+__L2(10)
+__L2(11)
+
+L3: l3-cache {
+cache-level = <3>;
+cache-size = <0x40>;
+cache-line-size = <64>;
+cache-sets = <4096>;
+cache-unified;
+};
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 00..9f20d12bfc
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ };
+
+ spi_nor: spi@5480 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x5480 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ active_clk_edges;
+ chipselect_num = <1>;
+
+
[PATCH v2 09/13] net: synquacer: Add netsec driver
From: Jassi Brar Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar --- drivers/net/Kconfig |8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 ++ 3 files changed, 1143 insertions(+) create mode 100644 drivers/net/sni_netsec.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0e84c22b50..e7c6814c31 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -649,6 +649,14 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config SNI_NETSEC + bool "Socionext NETSEC Ethernet support" + depends on DM_ETH && SYNQUACER_SPI + select PHYLIB + help + This driver implements support for the Socionext SynQuacer NETSEC + ethernet controller, as found on the Socionext SynQuacer family. + source "drivers/net/mscc_eswitch/Kconfig" config ETHER_ON_FEC1 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a19511aaa7..30e1c9baab 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-y += mscc_eswitch/ diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c new file mode 100644 index 00..a9ebf6af9c --- /dev/null +++ b/drivers/net/sni_netsec.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * netsec.c - Socionext Synquacer Netsec driver + * Copyright 2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NETSEC_REG_SOFT_RST0x104 +#define NETSEC_REG_COM_INIT0x120 + +#define NETSEC_REG_TOP_STATUS 0x200 +#define NETSEC_IRQ_RX BIT(1) +#define NETSEC_IRQ_TX BIT(0) + +#define NETSEC_REG_TOP_INTEN 0x204 +#define NETSEC_REG_INTEN_SET 0x234 +#define NETSEC_REG_INTEN_CLR 0x238 + +#define NETSEC_REG_NRM_TX_STATUS 0x400 +#define NETSEC_REG_NRM_TX_INTEN0x404 +#define NETSEC_REG_NRM_TX_INTEN_SET0x428 +#define NETSEC_REG_NRM_TX_INTEN_CLR0x42c +#define NRM_TX_ST_NTOWNR BIT(17) +#define NRM_TX_ST_TR_ERR BIT(16) +#define NRM_TX_ST_TXDONE BIT(15) +#define NRM_TX_ST_TMREXP BIT(14) + +#define NETSEC_REG_NRM_RX_STATUS 0x440 +#define NETSEC_REG_NRM_RX_INTEN0x444 +#define NETSEC_REG_NRM_RX_INTEN_SET0x468 +#define NETSEC_REG_NRM_RX_INTEN_CLR0x46c +#define NRM_RX_ST_RC_ERR BIT(16) +#define NRM_RX_ST_PKTCNT BIT(15) +#define NRM_RX_ST_TMREXP BIT(14) + +#define NETSEC_REG_PKT_CMD_BUF 0xd0 + +#define NETSEC_REG_CLK_EN 0x100 + +#define NETSEC_REG_PKT_CTRL0x140 + +#define NETSEC_REG_DMA_TMR_CTRL0x20c +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c +#define NETSEC_REG_F_TAIKI_VER 0x230 +#define NETSEC_REG_DMA_HM_CTRL 0x214 +#define NETSEC_REG_DMA_MH_CTRL 0x220 +#define NETSEC_REG_ADDR_DIS_CORE 0x218 +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c + +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 + +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT0x418 + +#define NETSEC_REG_NRM_TX_TMR 0x41c + +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 +#define NETSEC_REG_NRM_TX_TXINT_TMR0x420 +#define NETSEC_REG_NRM_RX_RXINT_TMR0x460 + +#define NETSEC_REG_NRM_RX_TMR 0x45c + +#define NETSEC_REG_NRM_TX_DESC_START_UP0x434 +#define NETSEC_REG_NRM_TX_DESC_START_LW0x408 +#define NETSEC_REG_NRM_RX_DESC_START_UP0x474 +#define NETSEC_REG_NRM_RX_DESC_START_LW0x448 + +#define NETSEC_REG_NRM_TX_CONFIG 0x430 +#define NETSEC_REG_NRM_RX_CONFIG 0x470 + +#define MAC_REG_STATUS 0x1024 +#define MAC_REG_DATA 0x11c0 +#define MAC_REG_CMD0x11c4 +#define MAC_REG_FLOW_TH0x11cc +#define MAC_REG_INTF_SEL 0x11d4 +#define M
[PATCH v2 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig| 15 +++ board/socionext/developerbox/Kconfig| 36 +++ board/socionext/developerbox/MAINTAINERS| 13 ++ board/socionext/developerbox/Makefile |9 ++ board/socionext/developerbox/developerbox.c | 145 +++ configs/synquacer_developerbox_defconfig| 93 + doc/board/index.rst |1 doc/board/socionext/developerbox.rst| 87 doc/board/socionext/index.rst |9 ++ include/configs/synquacer.h | 106 10 files changed, 514 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fba28323cd..1caea3ac58 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1675,6 +1675,20 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select ONLY_GENERIC_GPIO + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2022,6 +2036,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 00..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help +Choose this option if you build the U-Boot for the DeveloperBox +96boards Enterprise Edition. +This board will booted from SCP firmware and it enables SMMU, thus +the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 00..d10ad3b8f7 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,13 @@ +DEVELOPER BOX +M: Masami Hiramatsu +M: Jassi Brar +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F:
[PATCH v2 12/13] doc: qemu: arm64: Fix the documentation of capsule update
Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 9fec75f8f1..e2a9f0db71 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - -$ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ -e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. +$ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The
[PATCH v2 13/13] configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig | 15 +++ include/configs/synquacer.h |6 ++ 2 files changed, 21 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index c0d6fa49c0..a0bbbfdd0f 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -91,3 +91,18 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index b2dd6d0f0f..5eeb16ce1c 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -58,6 +58,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info='" \ + "mtd nor1=u-boot.bin raw 20 10;"\ + "fip.bin raw 18 78000;" \ + "optee.bin raw 50 10'\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -101,6 +106,7 @@ "ramdisk_addr_r=0xa000\0" \ "scriptaddr=0x8800\0" \ "pxefile_addr_r=0x8810\0" \ + DEFAULT_DFU_ALT_INFO\ BOOTENV #endif /* __CONFIG_H */
Re: [PATCH v2 12/13] doc: qemu: arm64: Fix the documentation of capsule update
Hi, 2021年4月19日(月) 9:37 Takahiro Akashi : > > Sughosh, > > On Sun, Apr 18, 2021 at 01:37:58PM +0530, Sughosh Ganu wrote: > > On Sat, 17 Apr 2021 at 23:51, Heinrich Schuchardt > > wrote: > > > > > On 4/17/21 1:39 AM, Masami Hiramatsu wrote: > > > > Since the EDK2 GenerateCapsule script is out of date and it > > > > doesn't generate the supported version capsule file, the document > > > > should refer the mkeficapsule in tools. > > > > > > > > Signed-off-by: Masami Hiramatsu > > > > --- > > > > doc/board/emulation/qemu_capsule_update.rst | 11 ++- > > > > 1 file changed, 2 insertions(+), 9 deletions(-) > > > > > > > > diff --git a/doc/board/emulation/qemu_capsule_update.rst > > > b/doc/board/emulation/qemu_capsule_update.rst > > > > index 9fec75f8f1..e2a9f0db71 100644 > > > > --- a/c > > > > +++ b/doc/board/emulation/qemu_capsule_update.rst > > > > @@ -39,16 +39,9 @@ In addition, the following config needs to be > > > disabled(QEMU ARM specific):: > > > > > > > > CONFIG_TFABOOT > > > > > > > > -The capsule file can be generated by using the GenerateCapsule.py > > > > -script in EDKII:: > > > > - > > > > -$ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ > > > > - --fw-version --lsv --guid \ > > > > -e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index > > > \ > > > > - --verbose > > > > +The capsule file can be generated by using the tools/mkeficapsule:: > > > > > > > > -The above is a wrapper script(GenerateCapsule) which eventually calls > > > > -the actual GenerateCapsule.py script. > > > > +$ mkeficapsule --raw --index 1 > > > > > > Thanks for the change. > > > > > > Could you, please, adjust the same in chapter "Enabling Capsule > > > Authentication" below. So as Sughosh said, since currently mkeficapsule doesn't support authentication, I only changed it for the normal capsule update. Without this change, the capsule update just failed. > > Currently, we do not have support for adding authentication header to the > > capsule. This is because I have been using the GenerateCapsule script in > > edk2 for generation of a capsule with authentication header. I think adding > > the signature to the capsule is easier when done through a python script > > rather than C code. > > Why do you think so? > At a quick glance at the script, it internally uses openssl command like: > openssl smime -sign -binary -outform DER -md sha256 \ > -signer <...> -certfile <...> > (See PayloadDescriptor.Encode in the script.) > > The output from the standard output is exactly what you want > to use to build a capsule file, that is "AuthInfo". > Then you can naturally extend mkeficapsule to insert this signature > between the header and the image itself in a capsule file. Hmm, if it can be done by just calling openssl, I think it is easier for me to run the tools/mkeficapsule, because I don't need to build EDK2 for U-Boot. If GenerateCapsule becomes a standard implementation and independent from the EDK2 project, from the interoperability point of view, it is better to use that. But it is a part of EDK2 and the GenerateCapsule seems out-of-date and not maintained well (why doesn't it support the latest version yet??) Thank you, > Furthermore, I believe, it is fairly straightforward to add a native > 'signing' feature to mkeficapsule if you use openssl library. > > -Takahiro Akashi > > > > I am working on adding support for the latest version > > of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER in the GenerateCapsule > > script in edk2. Meanwhile, would it be possible to have support for the > > version 2 of this header in the capsule driver -- it is a minor change and > > I already have a patch for it. If you are fine, I can submit a patch for > > the same. > > > > -sughosh > > > > > > > > > > Best regards > > > > > > Heinrich > > > > > > > > > > > As per the UEFI specification, the capsule file needs to be placed on > > > > the EFI System Partition, under the \EFI\UpdateCapsule directory. The > > > > > > > > > > -- Masami Hiramatsu
Re: [PATCH v2 07/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
Hi Jaehoon,
Thanks for your comments.
2021年4月20日(火) 7:05 Jaehoon Chung :
>
> Hi Masami,
>
> On 4/17/21 8:38 AM, Masami Hiramatsu wrote:
> > From: Jassi Brar
> >
> > Signed-off-by: Jassi Brar
> > Signed-off-by: Masami Hiramatsu
> > ---
> > drivers/mmc/Kconfig | 10 ++
> > drivers/mmc/Makefile |1 +
> > drivers/mmc/f_sdh30.c | 81
> > +
> > drivers/mmc/sdhci.c |9 +
> > 4 files changed, 101 insertions(+)
> > create mode 100644 drivers/mmc/f_sdh30.c
> >
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> > index f8ca52efb6..a9ae419e41 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -549,6 +549,16 @@ config MMC_SDHCI_IPROC
> >
> > If unsure, say N.
> >
> > +config F_SDH30_SDHCI
>
> MMS_SDHCI_F_SDH30 or MMC_SDHCI_xxx.
OK. I'll change it.
>
> > + bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
> > + depends on BLK && DM_MMC
> > + depends on MMC_SDHCI
> > + help
> > + This selects the Secure Digital Host Controller Interface (SDHCI)
> > + Needed by some Fujitsu SoC for MMC / SD / SDIO support.
> > + If you have a controller with this interface, say Y or M here.
> > + If unsure, say N.
> > +
> > config MMC_SDHCI_KONA
> > bool "SDHCI support on Broadcom KONA platform"
> > depends on MMC_SDHCI
> > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> > index 89d6af3db3..b48a76ba94 100644
> > --- a/drivers/mmc/Makefile
> > +++ b/drivers/mmc/Makefile
> > @@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o
> > uniphier-sd.o
> > obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
> > obj-$(CONFIG_MMC_BCM2835)+= bcm2835_sdhost.o
> > obj-$(CONFIG_MMC_MTK)+= mtk-sd.o
> > +obj-$(CONFIG_F_SDH30_SDHCI) += f_sdh30.o
> > diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
> > new file mode 100644
> > index 00..44c6521bfe
> > --- /dev/null
> > +++ b/drivers/mmc/f_sdh30.c
> > @@ -0,0 +1,81 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Socionext F_SDH30 eMMC driver
> > + * Copyright 2021 Linaro Ltd.
> > + * Copyright 2021 Socionext, Inc.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +struct f_sdh30_plat {
> > + struct mmc_config cfg;
> > + struct mmc mmc;
> > +};
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static int f_sdh30_probe(struct udevice *dev)
>
> xxx_sdhci_probe().
Let me confirm. The controller name is F_SDH30, so it is better to be
f_sdh30_sdhci_probe(), correct?
> > +{
> > + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> > + struct f_sdh30_plat *plat = dev_get_plat(dev);
> > + struct sdhci_host *host = dev_get_priv(dev);
> > + int ret;
> > +
> > + ret = mmc_of_parse(dev, &plat->cfg);
> > + if (ret)
> > + return ret;
> > +
> > + host->mmc = &plat->mmc;
> > + host->mmc->dev = dev;
> > + host->mmc->priv = host;
> > +
> > + ret = sdhci_setup_cfg(&plat->cfg, host, 2, 40);
> > + if (ret)
> > + return ret;
> > +
> > + upriv->mmc = host->mmc;
> > +
> > + mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
> > +
> > + return sdhci_probe(dev);
> > +}
> > +
> > +static int f_sdh30_of_to_plat(struct udevice *dev)
> > +{
> > + struct sdhci_host *host = dev_get_priv(dev);
> > +
> > + host->name = strdup(dev->name);
> > + host->ioaddr = dev_read_addr_ptr(dev);
> > + host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
> > + host->index = dev_read_u32_default(dev, "index", 0);
> > +
> > + return 0;
> > +}
> > +
> > +static int f_sdh30_bind(struct udevice *dev)
> > +{
> > + struct f_sdh30_plat *plat = dev_get_plat(dev);
> > +
> > + return sdhci_bind(dev, &plat->mmc, &plat->cfg);
> > +}
> > +
> > +static const struct udevice_id f_sdh30_mmc_ids[] = {
> > + { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
> > + { }
> > +};
> > +
>
Re: [PATCH v2 05/13] mtd: spi-nor-ids: add support for Macronix mx25u51245g and mx66u1g45g flash
Hello Pratyush,
2021年4月19日(月) 17:41 Pratyush Yadav :
>
> On 17/04/21 08:38AM, Masami Hiramatsu wrote:
> > From: Jassi Brar
> >
> > Signed-off-by: Jassi Brar
> > ---
> > drivers/mtd/spi/spi-nor-ids.c |2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > index 2b57797954..30a18b4140 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -160,9 +160,11 @@ const struct flash_info spi_nor_ids[] = {
> > { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
> > { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ
> > | SPI_NOR_QUAD_READ) },
> > { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K |
> > SPI_NOR_4B_OPCODES) },
> > + { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>
> The flash ID is the same as that of mx66u51235f. Because the ID matching
> function searches through this array in linear fashion, mx66u51235f can
> never be detected. This is a regression.
OK
>
> I am seeing a lot of ID collisions on Macronix flashes recently [0]. Not
> sure how to handle them though. At least in this case both flashes use
> the same set of flags so it should just change the name of the flash
> detected.
Would you mean rename the entry as below?
{ INFO("mx66u51235f/mx25u51245g",...
Thank you,
>
> [0]
> https://lore.kernel.org/linux-mtd/caeymn7zep9f1sue6umrdwkr8bvt5hdri-4f3+g-gp9anugg...@mail.gmail.com/T/#u
>
> > { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
> > { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ
> > | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ
> > | SPI_NOR_4B_OPCODES | SECT_4K) },
> >
>
> --
> Regards,
> Pratyush Yadav
> Texas Instruments Inc.
--
Masami Hiramatsu
Re: [PATCH v2 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Hi, I found that I need to enable CONFIG_CMD_FS_GENERIC for enabling distroboot support. I'll fix it in the next version. Thank you, 2021年4月17日(土) 8:39 Masami Hiramatsu : > > Add the DeveloperBox 96boards EE support. This board is also > known as Socionext SynQuacer E-Series. It contians one "SC2A11" > SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, > 3 PCIe slots (1 4x port and 2 1x ports which are expanded via > PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA > ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard > MicroATX Form Factor. > > For more information, see this page; > https://www.96boards.org/product/developerbox/ > > Signed-off-by: Masami Hiramatsu > --- > Changes in v2: > - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. > - Remove non-UEFI boot commands. > - Use Distro boot. > - Remove NOR-connected SPI node by path instead of alias. > - Rename configs/SynQuacer_defconfig to > configs/synquacer_developerbox_defconfig. > - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. > - Move README under doc/board/socionext/ and make it .rst text. > --- > arch/arm/Kconfig| 15 +++ > board/socionext/developerbox/Kconfig| 36 +++ > board/socionext/developerbox/MAINTAINERS| 13 ++ > board/socionext/developerbox/Makefile |9 ++ > board/socionext/developerbox/developerbox.c | 145 > +++ > configs/synquacer_developerbox_defconfig| 93 + > doc/board/index.rst |1 > doc/board/socionext/developerbox.rst| 87 > doc/board/socionext/index.rst |9 ++ > include/configs/synquacer.h | 106 > 10 files changed, 514 insertions(+) > create mode 100644 board/socionext/developerbox/Kconfig > create mode 100644 board/socionext/developerbox/MAINTAINERS > create mode 100644 board/socionext/developerbox/Makefile > create mode 100644 board/socionext/developerbox/developerbox.c > create mode 100644 configs/synquacer_developerbox_defconfig > create mode 100644 doc/board/socionext/developerbox.rst > create mode 100644 doc/board/socionext/index.rst > create mode 100644 include/configs/synquacer.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index fba28323cd..1caea3ac58 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1675,6 +1675,20 @@ config ARCH_UNIPHIER > Support for UniPhier SoC family developed by Socionext Inc. > (formerly, System LSI Business Division of Panasonic Corporation) > > +config ARCH_SYNQUACER > + bool "Socionext SynQuacer SoCs" > + select ARM64 > + select ONLY_GENERIC_GPIO > + select DM > + select GIC_V3 > + select PSCI_RESET > + select SYSRESET > + select SYSRESET_PSCI > + select OF_CONTROL > + help > + Support for SynQuacer SoC family developed by Socionext Inc. > + This SoC is used on 96boards EE DeveloperBox. > + > config ARCH_STM32 > bool "Support STMicroelectronics STM32 MCU with cortex M" > select CPU_V7M > @@ -2022,6 +2036,7 @@ source "board/hisilicon/poplar/Kconfig" > source "board/isee/igep003x/Kconfig" > source "board/kontron/sl28/Kconfig" > source "board/myir/mys_6ulx/Kconfig" > +source "board/socionext/developerbox/Kconfig" > source "board/spear/spear300/Kconfig" > source "board/spear/spear310/Kconfig" > source "board/spear/spear320/Kconfig" > diff --git a/board/socionext/developerbox/Kconfig > b/board/socionext/developerbox/Kconfig > new file mode 100644 > index 00..706b8dc0f1 > --- /dev/null > +++ b/board/socionext/developerbox/Kconfig > @@ -0,0 +1,36 @@ > +if ARCH_SYNQUACER > + > +choice > + prompt "SC2A11 Cortex-A53 MPCore 24cores" > + optional > + > +config TARGET_DEVELOPERBOX > + bool "Socionext DeveloperBox" > + select PCI > + select DM_PCI > + select PCIE_ECAM_SYNQUACER > + select SYS_DISABLE_DCACHE_OPS > + select OF_BOARD_SETUP > + help > +Choose this option if you build the U-Boot for the DeveloperBox > +96boards Enterprise Edition. > +This board will booted from SCP firmware and it enables SMMU, thus > +the dcache is updated automatically when DMA operation is executed. > +endchoice > + > +config SYS_SOC > + default "sc2a11" > + > +if TARGET_DEVELOPERBOX > + > +config SYS_BOA
Re: [PATCH 5/5] Makefile: Add provision for embedding public key in platform's dtb
2021年4月28日(水) 14:44 AKASHI Takahiro :
>
> On Thu, Apr 08, 2021 at 09:58:17PM +0200, Heinrich Schuchardt wrote:
> > On 4/7/21 1:53 PM, Sughosh Ganu wrote:
> > > Add provision for embedding the public key used for capsule
> > > authentication in the platform's dtb. This is done by invoking the
> > > mkeficapsule utility which puts the public key in the efi signature
> > > list(esl) format into the dtb.
> > >
> > > Signed-off-by: Sughosh Ganu
> > > ---
> > > Makefile | 10 ++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/Makefile b/Makefile
> > > index 193aa4d1c9..0d50c6a805 100644
> > > --- a/Makefile
> > > +++ b/Makefile
> > > @@ -1010,6 +1010,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm
> > > -f $@; false; }
> > > quiet_cmd_lzma = LZMA$@
> > > cmd_lzma = lzma -c -z -k -9 $< > $@
> > >
> > > +quiet_cmd_mkeficapsule = MKEFICAPSULE $@
> > > +cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K
> > > $(CONFIG_EFI_PKEY_FILE) \
> > > + -D $@
> > > +
> >
> > tools/mkeficapsule --help does neither show a parameter -K nor a
> > parameter -D.
>
> This clearly shows that the feature with -K/-D has nothing to do with
> creating a capsule file.
> Two totally different things in one place (command).
> And the dtb overlay operation can be achieved by using standard commands.
If I understand correctly, we need the following steps,
1. prepare the key for signing
2. make dtb overlay from that key
3. sign the capsule with the key
And Sughosh's implementation is using mkeficapsule for 2 and 3.
Takahiro pointed that mkeficapsule is only for 3 because of its name
and avoid confusion.
Is that correct?
What would you think about changing the tool name?
E.g.
For step 2.
capsuletool dtb --public-key pubkey [--overlay] target.dtb
For step 3.
capsuletool capsule --raw u-boot.bin --index 1 --public-key pubkey u-boot.cap
Then we can expand it for inspection, verify etc.
Thank you,
>
> I believe that the feature should be removed from mkeficapsule.
>
> -Takahiro Akashi
>
>
> > Please, update tools/mkeficapsule.c before using these. A
> > man-page for mkeficapsule in doc/usage/ would be helpful.
> >
> > $ tools/mkeficapsule --help
> > Usage: mkeficapsule [options]
> > Options:
> > --fitnew FIT image file
> > --rawnew raw image file
> > --index update image index
> > --instanceupdate hardware instance
> > --public-key public key esl file
> > --dtb dtb file
> > --overlay the dtb file is an overlay
> > --help print a help message
> >
> > Best regards
> >
> > Heinrich
> >
> > > cfg: u-boot.cfg
> > >
> > > quiet_cmd_cfgcheck = CFGCHK $2
> > > @@ -1104,8 +1108,14 @@ endif
> > > PHONY += dtbs
> > > dtbs: dts/dt.dtb
> > > @:
> > > +ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
> > > +dts/dt.dtb: u-boot tools
> > > + $(Q)$(MAKE) $(build)=dts dtbs
> > > + $(call cmd,mkeficapsule)
> > > +else
> > > dts/dt.dtb: u-boot
> > > $(Q)$(MAKE) $(build)=dts dtbs
> > > +endif
> > >
> > > quiet_cmd_copy = COPY$@
> > > cmd_copy = cp $< $@
> > >
> >
--
Masami Hiramatsu
Re: [PATCH v2 04/13] gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs
Hi Simon, 2021年4月30日(金) 1:10 Simon Glass : > > Hi Masami, > > On Fri, 16 Apr 2021 at 16:38, Masami Hiramatsu > wrote: > > > > Many architecture do not have specific asm/arch/gpio.h, so instead > > of adding !defined(CONFIG_ARCH_xxx), introduce CONFIG_ONLY_GENERIC_GPIO > > This seems OK, but I think GPIO_GENERIC_ONLY is a better name, since > it uses the GPIO prefix. > > I would also prefer to have a 'positive' option, but I suspect that > might be a pain to do? Would you mean making it something like CONFIG_GPIO_EXTRA_HEADER ? I think it is also possible. My concern is if I missed any arch which should say y that :P. Thank you, > > > and select it. > > > > Signed-off-by: Masami Hiramatsu > > --- > > arch/arm/Kconfig | 17 + > > arch/arm/include/asm/gpio.h |8 +--- > > board/cortina/common/Kconfig | 1 + > > 3 files changed, 19 insertions(+), 7 deletions(-) > > > > [..] > > Regards, > Simon -- Masami Hiramatsu
Re: [PATCH v2 04/13] gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs
Hi Tom, 2021年5月3日(月) 20:51 Tom Rini : > > On Fri, Apr 30, 2021 at 11:13:45AM -0700, Simon Glass wrote: > > Hi Masami, > > > > On Thu, 29 Apr 2021 at 20:03, Masami Hiramatsu > > wrote: > > > > > > Hi Simon, > > > > > > 2021年4月30日(金) 1:10 Simon Glass : > > > > > > > > Hi Masami, > > > > > > > > On Fri, 16 Apr 2021 at 16:38, Masami Hiramatsu > > > > wrote: > > > > > > > > > > Many architecture do not have specific asm/arch/gpio.h, so instead > > > > > of adding !defined(CONFIG_ARCH_xxx), introduce > > > > > CONFIG_ONLY_GENERIC_GPIO > > > > > > > > This seems OK, but I think GPIO_GENERIC_ONLY is a better name, since > > > > it uses the GPIO prefix. > > > > > > > > I would also prefer to have a 'positive' option, but I suspect that > > > > might be a pain to do? > > > > > > Would you mean making it something like CONFIG_GPIO_EXTRA_HEADER ? > > > > > > I think it is also possible. My concern is if I missed any arch which > > > should say y that :P. > > > > Yes...it's just that negative configs generally cause us pain at some point. > > And in terms of catching all of the platforms, you can submit a pull > request in GitHub which will trigger a CI world build and tell you > what's broken :) OK, let me try it. Thank you! > > -- > Tom -- Masami Hiramatsu
Re: [PATCH 5/5] Makefile: Add provision for embedding public key in platform's dtb
Hi,
2021年5月7日(金) 17:15 AKASHI Takahiro :
>
> On Wed, Apr 28, 2021 at 03:31:36PM +0900, Masami Hiramatsu wrote:
> > 2021年4月28日(水) 14:44 AKASHI Takahiro :
> > >
> > > On Thu, Apr 08, 2021 at 09:58:17PM +0200, Heinrich Schuchardt wrote:
> > > > On 4/7/21 1:53 PM, Sughosh Ganu wrote:
> > > > > Add provision for embedding the public key used for capsule
> > > > > authentication in the platform's dtb. This is done by invoking the
> > > > > mkeficapsule utility which puts the public key in the efi signature
> > > > > list(esl) format into the dtb.
> > > > >
> > > > > Signed-off-by: Sughosh Ganu
> > > > > ---
> > > > > Makefile | 10 ++
> > > > > 1 file changed, 10 insertions(+)
> > > > >
> > > > > diff --git a/Makefile b/Makefile
> > > > > index 193aa4d1c9..0d50c6a805 100644
> > > > > --- a/Makefile
> > > > > +++ b/Makefile
> > > > > @@ -1010,6 +1010,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || {
> > > > > rm -f $@; false; }
> > > > > quiet_cmd_lzma = LZMA$@
> > > > > cmd_lzma = lzma -c -z -k -9 $< > $@
> > > > >
> > > > > +quiet_cmd_mkeficapsule = MKEFICAPSULE $@
> > > > > +cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K
> > > > > $(CONFIG_EFI_PKEY_FILE) \
> > > > > + -D $@
> > > > > +
> > > >
> > > > tools/mkeficapsule --help does neither show a parameter -K nor a
> > > > parameter -D.
> > >
> > > This clearly shows that the feature with -K/-D has nothing to do with
> > > creating a capsule file.
> > > Two totally different things in one place (command).
> > > And the dtb overlay operation can be achieved by using standard commands.
> >
> > If I understand correctly, we need the following steps,
> > 1. prepare the key for signing
> > 2. make dtb overlay from that key
> > 3. sign the capsule with the key
> >
> > And Sughosh's implementation is using mkeficapsule for 2 and 3.
> > Takahiro pointed that mkeficapsule is only for 3 because of its name
> > and avoid confusion.
> >
> > Is that correct?
> >
> > What would you think about changing the tool name?
> > E.g.
> >
> > For step 2.
> > capsuletool dtb --public-key pubkey [--overlay] target.dtb
>
> My point is: as this command line shows, it has nothing to do
> with a capsule file. It simply deals with dtb blob for overlaying.
> (So 'capsuletool' is not appropriate.)
But if the capsuletool provide the devicetree template for the capsule
something like test/py/tests/test_efi_capsule/pubkey.dts, we can say
it is related to the capsule, because the dts is obviously for capsule.
What would you think?
Thank you,
>
> -Takahiro Akashi
>
>
> > For step 3.
> > capsuletool capsule --raw u-boot.bin --index 1 --public-key pubkey
> > u-boot.cap
> >
> > Then we can expand it for inspection, verify etc.
> >
> > Thank you,
> >
> > >
> > > I believe that the feature should be removed from mkeficapsule.
> > >
> > > -Takahiro Akashi
> > >
> > >
> > > > Please, update tools/mkeficapsule.c before using these. A
> > > > man-page for mkeficapsule in doc/usage/ would be helpful.
> > > >
> > > > $ tools/mkeficapsule --help
> > > > Usage: mkeficapsule [options]
> > > > Options:
> > > > --fitnew FIT image file
> > > > --rawnew raw image file
> > > > --index update image index
> > > > --instanceupdate hardware instance
> > > > --public-key public key esl file
> > > > --dtb dtb file
> > > > --overlay the dtb file is an overlay
> > > > --help print a help message
> > > >
> > > > Best regards
> > > >
> > > > Heinrich
> > > >
> > > > > cfg: u-boot.cfg
> > > > >
> > > > > quiet_cmd_cfgcheck = CFGCHK $2
> > > > > @@ -1104,8 +1108,14 @@ endif
> > > > > PHONY += dtbs
> > > > > dtbs: dts/dt.dtb
> > > > > @:
> > > > > +ifeq
> > > > > ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
> > > > > +dts/dt.dtb: u-boot tools
> > > > > + $(Q)$(MAKE) $(build)=dts dtbs
> > > > > + $(call cmd,mkeficapsule)
> > > > > +else
> > > > > dts/dt.dtb: u-boot
> > > > > $(Q)$(MAKE) $(build)=dts dtbs
> > > > > +endif
> > > > >
> > > > > quiet_cmd_copy = COPY$@
> > > > > cmd_copy = cp $< $@
> > > > >
> > > >
> >
> >
> >
> > --
> > Masami Hiramatsu
--
Masami Hiramatsu
Re: [PATCH 5/5] Makefile: Add provision for embedding public key in platform's dtb
2021年5月7日(金) 18:57 Masami Hiramatsu :
>
> Hi,
>
> 2021年5月7日(金) 17:15 AKASHI Takahiro :
> >
> > On Wed, Apr 28, 2021 at 03:31:36PM +0900, Masami Hiramatsu wrote:
> > > 2021年4月28日(水) 14:44 AKASHI Takahiro :
> > > >
> > > > On Thu, Apr 08, 2021 at 09:58:17PM +0200, Heinrich Schuchardt wrote:
> > > > > On 4/7/21 1:53 PM, Sughosh Ganu wrote:
> > > > > > Add provision for embedding the public key used for capsule
> > > > > > authentication in the platform's dtb. This is done by invoking the
> > > > > > mkeficapsule utility which puts the public key in the efi signature
> > > > > > list(esl) format into the dtb.
> > > > > >
> > > > > > Signed-off-by: Sughosh Ganu
> > > > > > ---
> > > > > > Makefile | 10 ++
> > > > > > 1 file changed, 10 insertions(+)
> > > > > >
> > > > > > diff --git a/Makefile b/Makefile
> > > > > > index 193aa4d1c9..0d50c6a805 100644
> > > > > > --- a/Makefile
> > > > > > +++ b/Makefile
> > > > > > @@ -1010,6 +1010,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) ||
> > > > > > { rm -f $@; false; }
> > > > > > quiet_cmd_lzma = LZMA$@
> > > > > > cmd_lzma = lzma -c -z -k -9 $< > $@
> > > > > >
> > > > > > +quiet_cmd_mkeficapsule = MKEFICAPSULE $@
> > > > > > +cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K
> > > > > > $(CONFIG_EFI_PKEY_FILE) \
> > > > > > + -D $@
> > > > > > +
> > > > >
> > > > > tools/mkeficapsule --help does neither show a parameter -K nor a
> > > > > parameter -D.
> > > >
> > > > This clearly shows that the feature with -K/-D has nothing to do with
> > > > creating a capsule file.
> > > > Two totally different things in one place (command).
> > > > And the dtb overlay operation can be achieved by using standard
> > > > commands.
> > >
> > > If I understand correctly, we need the following steps,
> > > 1. prepare the key for signing
> > > 2. make dtb overlay from that key
> > > 3. sign the capsule with the key
> > >
> > > And Sughosh's implementation is using mkeficapsule for 2 and 3.
> > > Takahiro pointed that mkeficapsule is only for 3 because of its name
> > > and avoid confusion.
> > >
> > > Is that correct?
> > >
> > > What would you think about changing the tool name?
> > > E.g.
> > >
> > > For step 2.
> > > capsuletool dtb --public-key pubkey [--overlay] target.dtb
> >
> > My point is: as this command line shows, it has nothing to do
> > with a capsule file. It simply deals with dtb blob for overlaying.
> > (So 'capsuletool' is not appropriate.)
>
> But if the capsuletool provide the devicetree template for the capsule
> something like test/py/tests/test_efi_capsule/pubkey.dts, we can say
> it is related to the capsule, because the dts is obviously for capsule.
> What would you think?
Ah, wait. I misunderstood. It seems that the efi_get_public_key_data() is
platform dependent. Thus isn't it hard to provide a unified tool to embed
the key data into the dtb because it is usable for some platform but
not usable for others?
Thank you,
--
Masami Hiramatsu
[PATCH v3 00/14] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hello, Here is the 3rd version of the series (including some fixes for build errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. This series includes not only DeveloperBox support but also some fixes for the issues which I faced while porting U-Boot on the DeveloperBox. First 3 patches are fixes, next 1 patch is a code cleanup for generic gpio for arm. The next 7 patches adding DeveloperBox devices and board support. The last 2 patches are related to the UEFI capsule update. Previous version is here: https://lists.denx.de/pipermail/u-boot/2021-April/447529.html Changes in v3 - I've dropped the spi-nor-ids update patch because it causes a regression. [01/14]: - To enable USB XHCI support, I pick my pci patch again in this version. [05/14]: - Change the config name to positive and selected by the opposite CONFIG_ARCH_*. (Build checked by Github CI) [07/14]: - Rename config name to MMC_SDHCI_F_SDH30. - Remove unneeded wait in drivers/mmc/sdhci.c. - Rename probe function to f_sdh30_sdhci_probe. [10/14]: - Use generic nor flash instead of specific mx25u51245g. (chip parameters will be searched by the register value) [11/14]: - Enable CONFIG_MMC_SDHCI_F_SDH30. - Enable CONFIG_CMD_GENERIC (fstype command) for distro boot. - Remove unneeded CONFIG_ONLY_GENERIC_GPIO. [12/14]: New patch to fix DFU error on MTD (for Capsule update) [13/14]: - Fix a typo in dfu_alt_info. DeveloperBox DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots (1x slots are connected via PCIe bridge chip) * 4 USB-3.0 ports * 2 SATA ports * 1 GbE network port * 1 USB-UART serial port (micro USB) * 64MB SPI NOR Flash * 8GB eMMC Flash Storage * 96boards LS connector The DeveloperBox schematic can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf And the other documents can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/ Currently, the U-Boot port supports: - * USB * eMMC * SPI-NOR * SATA * GbE The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as BL33, but no need to combine with it. Thank you, --- Jassi Brar (3): mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver spi: synquacer: Add HSSPI SPI controller driver for SynQuacer net: synquacer: Add netsec driver Masami Hiramatsu (11): pci: Update the highest subordinate bus number for bridge setup ata: ahci-pci: Use scsi_ops to initialize ops dm: pci: Skip setting VGA bridge bits if parent device is the host bus efi: Fix to use null handle to create new handle for efi_fmp_raw gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs pci: synquacer: Add SynQuacer ECAM based PCIe driver ARM: dts: synquacer: Add device trees for DeveloperBox board: synquacer: Add DeveloperBox 96boards EE support dfu_mtd: Ignore non-implemented lock device failure doc: qemu: arm64: Fix the documentation of capsule update configs: synquacer: Enable EFI capsule update support arch/arm/Kconfig | 108 ++ arch/arm/dts/Makefile |2 arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 + .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 57 + arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 + arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++ arch/arm/include/asm/gpio.h|8 board/socionext/developerbox/Kconfig | 36 + board/socionext/developerbox/MAINTAINERS | 13 board/socionext/developerbox/Makefile |9 board/socionext/developerbox/developerbox.c| 145 +++ configs/synquacer_developerbox_defconfig | 109 ++ doc/board/emulation/qemu_capsule_update.rst| 11 doc/board/index.rst|1 doc/board/socionext/developerbox.rst | 87 ++ doc/board/socionext/index.rst |9 drivers/ata/ahci-pci.c |2 drivers/dfu/dfu_mtd.c |2 drivers/mmc/Kconfig| 10 drivers/mmc/Makefile |1 drivers/mmc/f_sdh30.c | 81 + drivers/net/Kconfig|8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 drivers/pci/Kc
[PATCH v3 01/14] pci: Update the highest subordinate bus number for bridge setup
Update the highest subordinate bus number after probing the devices
under the bus for setting up the bridge correctly.
The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
removed this but it is required if a PCIe bridge is under the bus.
Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
Tested-by: Tim Harvey
---
drivers/pci/pci-uclass.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index dfd54b339f..f463ef3550 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
return log_msg_ret("probe", ret);
}
+ if (!ea_pos)
+ sub_bus = pci_get_bus_max();
+
dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
[PATCH v3 02/14] ata: ahci-pci: Use scsi_ops to initialize ops
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/ata/ahci-pci.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f..b1d231e0f9 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops= &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
[PATCH v3 03/14] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [7800-7fff],
Physical Memory [7800-7fffx]
PCI Autoconfig: Bus I/O region: [0-],
Physical Memory [77f0-77f0x]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x100, address=0x7800
bus_lower=0x7900
PCI Autoconfig: BAR 1, Mem, size=0x800, No room in resource, avail
start=7900 / size=800, need=800
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x200, address=0x7a00
bus_lower=0x7c00
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x8, address=0x7c00 bus_lower=0x7c08
"Synchronous Abort" handler, esr 0x9606
elr: e002bd28 lr : e002bce8 (reloc)
elr: fff6fd28 lr : fff6fce8
x0 : 1041 x1 : 003e
x2 : ffb0f8c8 x3 : 0001
x4 : 0080 x5 :
x6 : fff718fc x7 : 000f
x8 : ffb0f238 x9 : 0008
x10: x11: 0010
x12: 0006 x13: 0001869f
x14: ffb0fcd0 x15: 0020
x16: fff71cc4 x17:
x18: ffb13d90 x19: ffb14320
x20: x21: ffb14090
x22: ffb0f8c8 x23: 0001
x24: ffb14c10 x25:
x26: x27:
x28: ffb14c70 x29: ffb0f830
Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/pci/pci-uclass.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index f463ef3550..e9baa34e74 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
[PATCH v3 04/14] efi: Fix to use null handle to create new handle for efi_fmp_raw
When running the efidebug capsule disk-update command, the efi_fmp_raw
protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
below. This is because the code passes efi_root instaed of handle.
=> efidebug capsule disk-update
EFI: Call: efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbaf5988)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbaf5988,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6ee8)
EFI: new handle fbb37520
EFI: Exit: efi_install_protocol_interface: 0
EFI: 0 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 0
EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbfec648)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbfec648,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6f18)
EFI: handle fbaf8520
EFI: Exit: efi_install_protocol_interface: 2
EFI: 2 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 2
EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
Command failed, result=1
To fix this issue, pass the handle variable as same as the efi_fmp_fit
installation.
Signed-off-by: Masami Hiramatsu
---
lib/efi_loader/efi_capsule.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 6ee883d5b1..f038245c93 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -949,7 +949,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
handle = NULL;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &efi_root,
+ &handle,
&efi_guid_firmware_management_protocol,
&efi_fmp_raw, NULL));
}
[PATCH v3 05/14] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Change the config name to positive and selected by the opposite CONFIG_ARCH_*. (Build checked by Github CI) --- arch/arm/Kconfig| 94 +++ arch/arm/include/asm/gpio.h |8 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..023824df77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select D
[PATCH v3 06/14] pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile |1 drivers/pci/pcie_ecam_synquacer.c | 600 + 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index d5b6018b3d..2e6393f25b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 1f741786a0..035e3d3088 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 00..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOPBIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REGBIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_10x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +
[PATCH v3 07/14] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
From: Jassi Brar
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Rename config name to MMC_SDHCI_F_SDH30.
- Remove unneeded wait in drivers/mmc/sdhci.c.
- Rename probe function to f_sdh30_sdhci_probe.
---
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile |1 +
drivers/mmc/f_sdh30.c | 81 +
3 files changed, 92 insertions(+)
create mode 100644 drivers/mmc/f_sdh30.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f4ad1db45d..026b6f7d24 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -559,6 +559,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config MMC_SDHCI_F_SDH30
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db3..f5fd59093e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER)+= tmio-common.o
uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30)+= f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 00..3a85d9e348
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 2, 40);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops= &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
[PATCH v3 08/14] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
From: Jassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
drivers/spi/Kconfig |8 +
drivers/spi/Makefile|1
drivers/spi/spi-synquacer.c | 491 +++
3 files changed, 500 insertions(+)
create mode 100644 drivers/spi/spi-synquacer.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..62d9676550 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -481,4 +481,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..98c95323d1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 00..ce558c4bc0
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MCTRL 0x0
+#define MEN0
+#define CSEN 1
+#define IPCLK 3
+#define MES4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF0x14
+#define TXE0x18
+#define TXC0x1c
+#define RXF0x20
+#define RXE0x24
+#define RXC0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART0x38
+#define TRIGGER0
+#define DMSTOP 8
+#define CS_MASK3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX1
+#define DATA_TX2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
[PATCH v3 09/14] net: synquacer: Add netsec driver
From: Jassi Brar Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar --- drivers/net/Kconfig |8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 ++ 3 files changed, 1143 insertions(+) create mode 100644 drivers/net/sni_netsec.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 382639044b..9fc28b149d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -673,6 +673,14 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config SNI_NETSEC + bool "Socionext NETSEC Ethernet support" + depends on DM_ETH && SYNQUACER_SPI + select PHYLIB + help + This driver implements support for the Socionext SynQuacer NETSEC + ethernet controller, as found on the Socionext SynQuacer family. + source "drivers/net/mscc_eswitch/Kconfig" config ETHER_ON_FEC1 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 2ce89f7e3c..c23e828edc 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-y += mscc_eswitch/ diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c new file mode 100644 index 00..a9ebf6af9c --- /dev/null +++ b/drivers/net/sni_netsec.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * netsec.c - Socionext Synquacer Netsec driver + * Copyright 2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NETSEC_REG_SOFT_RST0x104 +#define NETSEC_REG_COM_INIT0x120 + +#define NETSEC_REG_TOP_STATUS 0x200 +#define NETSEC_IRQ_RX BIT(1) +#define NETSEC_IRQ_TX BIT(0) + +#define NETSEC_REG_TOP_INTEN 0x204 +#define NETSEC_REG_INTEN_SET 0x234 +#define NETSEC_REG_INTEN_CLR 0x238 + +#define NETSEC_REG_NRM_TX_STATUS 0x400 +#define NETSEC_REG_NRM_TX_INTEN0x404 +#define NETSEC_REG_NRM_TX_INTEN_SET0x428 +#define NETSEC_REG_NRM_TX_INTEN_CLR0x42c +#define NRM_TX_ST_NTOWNR BIT(17) +#define NRM_TX_ST_TR_ERR BIT(16) +#define NRM_TX_ST_TXDONE BIT(15) +#define NRM_TX_ST_TMREXP BIT(14) + +#define NETSEC_REG_NRM_RX_STATUS 0x440 +#define NETSEC_REG_NRM_RX_INTEN0x444 +#define NETSEC_REG_NRM_RX_INTEN_SET0x468 +#define NETSEC_REG_NRM_RX_INTEN_CLR0x46c +#define NRM_RX_ST_RC_ERR BIT(16) +#define NRM_RX_ST_PKTCNT BIT(15) +#define NRM_RX_ST_TMREXP BIT(14) + +#define NETSEC_REG_PKT_CMD_BUF 0xd0 + +#define NETSEC_REG_CLK_EN 0x100 + +#define NETSEC_REG_PKT_CTRL0x140 + +#define NETSEC_REG_DMA_TMR_CTRL0x20c +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c +#define NETSEC_REG_F_TAIKI_VER 0x230 +#define NETSEC_REG_DMA_HM_CTRL 0x214 +#define NETSEC_REG_DMA_MH_CTRL 0x220 +#define NETSEC_REG_ADDR_DIS_CORE 0x218 +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c + +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 + +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT0x418 + +#define NETSEC_REG_NRM_TX_TMR 0x41c + +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 +#define NETSEC_REG_NRM_TX_TXINT_TMR0x420 +#define NETSEC_REG_NRM_RX_RXINT_TMR0x460 + +#define NETSEC_REG_NRM_RX_TMR 0x45c + +#define NETSEC_REG_NRM_TX_DESC_START_UP0x434 +#define NETSEC_REG_NRM_TX_DESC_START_LW0x408 +#define NETSEC_REG_NRM_RX_DESC_START_UP0x474 +#define NETSEC_REG_NRM_RX_DESC_START_LW0x448 + +#define NETSEC_REG_NRM_TX_CONFIG 0x430 +#define NETSEC_REG_NRM_RX_CONFIG 0x470 + +#define MAC_REG_STATUS 0x1024 +#define MAC_REG_DATA 0x11c0 +#define MAC_REG_CMD0x11c4 +#define MAC_REG_FLOW_TH0x11cc +#define MAC_REG_INTF_SEL 0x11d4 +#define M
[PATCH v3 10/14] ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Use generic nor flash instead of specific mx25u51245g.
(chip parameters will be searched by the register value)
Changes in v2:
- Add reference commit id of original EDK2 to the comment
- Just copy the EDK2 dts files as-is (change #include path)
- Split out the u-boot specific changes in -u-boot.dtsi.
- Removed unneeded spi-nor flash partition information.
---
arch/arm/dts/Makefile |2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 57 ++
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++
arch/arm/dts/synquacer-sc2a11.dtsi | 595
5 files changed, 783 insertions(+)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5cae010c2..92b48e7033 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1083,6 +1083,8 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi
b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 00..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref {\
+i-cache-size = <0x8000>;\
+i-cache-line-size = <64>; \
+i-cache-sets = <256>; \
+d-cache-size = <0x8000>;\
+d-cache-line-size = <64>; \
+d-cache-sets = <128>; \
+l2-cache = ; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+cache-size = <0x4>; \
+cache-line-size = <64>; \
+cache-sets = <256>; \
+cache-unified; \
+next-level-cache = <&L3>; \
+};
+
+/ {
+__L2(0)
+__L2(1)
+__L2(2)
+__L2(3)
+__L2(4)
+__L2(5)
+__L2(6)
+__L2(7)
+__L2(8)
+__L2(9)
+__L2(10)
+__L2(11)
+
+L3: l3-cache {
+cache-level = <3>;
+cache-size = <0x40>;
+cache-line-size = <64>;
+cache-sets = <4096>;
+cache-unified;
+};
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 00..2439997753
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ };
+
+ spi_nor: spi@5480 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x5480 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <
[PATCH v3 11/14] board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- Changes in v3: - Enable CONFIG_MMC_SDHCI_F_SDH30. - Enable CONFIG_CMD_GENERIC (fstype command) for distro boot. - Remove unneeded CONFIG_ONLY_GENERIC_GPIO. Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig| 14 +++ board/socionext/developerbox/Kconfig| 36 +++ board/socionext/developerbox/MAINTAINERS| 13 ++ board/socionext/developerbox/Makefile |9 ++ board/socionext/developerbox/developerbox.c | 145 +++ configs/synquacer_developerbox_defconfig| 94 ++ doc/board/index.rst |1 doc/board/socionext/developerbox.rst| 87 doc/board/socionext/index.rst |9 ++ include/configs/synquacer.h | 106 10 files changed, 514 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 023824df77..7ff24535cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1760,6 +1760,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2102,6 +2115,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 00..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help +Choose this option if you build the U-Boot for the DeveloperBox +96boards Enterprise Edition. +This board will booted from SCP firmware and it enables SMMU, thus +the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 00..d10ad3b8f7 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,13 @@ +DEVELOPER BOX +M: Masami Hiramatsu +M: Jassi Brar +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developer
[PATCH v3 13/14] doc: qemu: arm64: Fix the documentation of capsule update
Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 33ce4bcd32..0a2286d039 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - -$ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ -e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. +$ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The
[PATCH v3 12/14] dfu_mtd: Ignore non-implemented lock device failure
Ignore the non-implemented lock device failure on writing mtd
via DFU. Without this fix, DFU write shows an error on such device
even if it succeeded, because dfu->write_medium returns -EOPNOTSUPP.
Signed-off-by: Masami Hiramatsu
Cc: Lukasz Majewski
---
drivers/dfu/dfu_mtd.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
index ca67585a7e..e58302c32d 100644
--- a/drivers/dfu/dfu_mtd.c
+++ b/drivers/dfu/dfu_mtd.c
@@ -152,6 +152,8 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity
*dfu,
ret = mtd_lock(mtd, lock_ofs, lock_len);
if (ret && ret != -EOPNOTSUPP)
printf("MTD device lock failed\n");
+ if (ret == -EOPNOTSUPP)
+ ret = 0;
}
return ret;
}
[PATCH v3 14/14] configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Fix a typo in dfu_alt_info. --- configs/synquacer_developerbox_defconfig | 15 +++ include/configs/synquacer.h |6 ++ 2 files changed, 21 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index de12587775..428c66fa58 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -92,3 +92,18 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index b2dd6d0f0f..f88fa21eff 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -58,6 +58,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ + "mtd nor1=u-boot.bin raw 20 10;"\ + "fip.bin raw 18 78000;" \ + "optee.bin raw 50 10\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -101,6 +106,7 @@ "ramdisk_addr_r=0xa000\0" \ "scriptaddr=0x8800\0" \ "pxefile_addr_r=0x8810\0" \ + DEFAULT_DFU_ALT_INFO\ BOOTENV #endif /* __CONFIG_H */
Re: [PATCH 06/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver
Hi, Kojima-san found a stability issue on this driver. Let me fix that. Thank you, 2021年4月5日(月) 11:09 Masami Hiramatsu : > > Add ECAM based SynQuacer PCIe RC driver. This driver configures the > PCIe RC and filter out a ghost pcie config. > > Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device > is configured by firmware (EDK2), it doesn't re-configure in the kernel. > So as same as EDK2, U-Boot needs to configure it before boot the kernel. > > Signed-off-by: Masami Hiramatsu > --- > drivers/pci/Kconfig | 12 + > drivers/pci/Makefile |1 > drivers/pci/pcie_ecam_synquacer.c | 597 > + > 3 files changed, 610 insertions(+) > create mode 100644 drivers/pci/pcie_ecam_synquacer.c > > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index ba41787f64..e36551a771 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC > Say Y here if you want to enable support for generic ECAM-based > PCIe host controllers, such as the one emulated by QEMU. > > +config PCIE_ECAM_SYNQUACER > + bool "SynQuacer ECAM-based PCI host controller support" > + default n > + depends on DM_PCI > + select PCI_INIT_R > + select PCI_REGION_MULTI_ENTRY > + help > + Say Y here if you want to enable support for Socionext > + SynQuacer SoC's ECAM-based PCIe host controllers. > + Note that this must be configured when boot because Linux driver > + expects the PCIe RC has been configured in the bootloader. > + > config PCI_PHYTIUM > bool "Phytium PCIe support" > depends on DM_PCI > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > index 5ed94bc95c..6338c595af 100644 > --- a/drivers/pci/Makefile > +++ b/drivers/pci/Makefile > @@ -16,6 +16,7 @@ endif > obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o > > obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o > +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o > obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o > obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o > obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o > diff --git a/drivers/pci/pcie_ecam_synquacer.c > b/drivers/pci/pcie_ecam_synquacer.c > new file mode 100644 > index 00..582a4e3d50 > --- /dev/null > +++ b/drivers/pci/pcie_ecam_synquacer.c > @@ -0,0 +1,597 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * SynQuacer PCIE host driver > + * > + * Based on drivers/pci/pcie_ecam_generic.c > + * > + * Copyright (C) 2016 Imagination Technologies > + * Copyright (C) 2021 Linaro Ltd. > + */ > + > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +/* iATU registers */ > +#define IATU_VIEWPORT_OFF 0x900 > +#define IATU_VIEWPORT_INBOUND BIT(31) > +#define IATU_VIEWPORT_OUTBOUND 0 > +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) > + > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT(12) > + > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT(28) > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF > + > +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C > +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 > +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 > +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 > +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C > + > +/* Clock and resets */ > +#define CORE_CONTROL 0x000 > +#define APP_LTSSM_ENABLE BIT(4) > +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) > + > +#define AXI_CLK_STOP 0x004 > +#define DBI_ACLK_STOP BIT(8) > +#define SLV_ACLK_STOP BIT(4) > +#define MSTR_ACLK_STOPBIT(0) > +#define DBI_CSY
Re: [PATCH 2/4] tools: mkeficapsule: remove device-tree related operation
Hi Ilias,
2021年5月12日(水) 16:21 Ilias Apalodimas :
>
> Akashi-san,
>
> On Wed, May 12, 2021 at 01:57:51PM +0900, AKASHI Takahiro wrote:
> > As we discussed, "-K" and "-D" options have nothing to do with
> > creating a capsule file. The same result can be obtained by
> > using standard commands like:
> > === signature.dts ===
> > /dts-v1/;
> > /plugin/;
> >
> > &{/} {
> > signature {
> > capsule-key = /incbin/("SIGNER.esl");
> > };
> > };
> > ===
> > $ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
> > $ fdtoverlay -i test.dtb -o test_sig.dtb -v signature.dtbo
> >
> > So just remove this feature.
> > (Effectively revert the commit 322c813f4bec ("mkeficapsule: Add support
> > for embedding public key in a dtb").)
> >
> > The same feature is implemented by a shell script (tools/fdtsig.sh).
>
>
> The only reason I can see to keep this, is if mkeficapsule gets included
> intro distro packages in the future. That would make end users life a bit
> easier, since they would need a single binary to create the whole
> CapsuleUpdate sequence.
Hmm, I think it is better to write a manpage of mkeficapsule which
also describes
how to embed the key into dtb as in the above example if it is so short.
Or, distros can package the above shell script with mkeficapsule.
Embedding a key and signing a capsule are different operations but
using the same tool may confuse users (at least me).
Thank you,
--
Masami Hiramatsu
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
+ goto err_4;
> >>> }
> >>> offset = sizeof(capsule) + sizeof(u64);
> >>> size = fwrite(&offset, 1, sizeof(offset), f);
> >>> if (size < sizeof(offset)) {
> >>> printf("write failed (%zx)\n", size);
> >>> - goto err_3;
> >>> + goto err_4;
> >>> }
> >>>
> >>> image.version = 0x0003;
> >>> @@ -323,34 +542,61 @@ static int create_fwbin(char *path, char *bin,
> >>> efi_guid_t *guid,
> >>> image.reserved[1] = 0;
> >>> image.reserved[2] = 0;
> >>> image.update_image_size = bin_stat.st_size;
> >>> + if (auth_context.sig_size)
> >>> + image.update_image_size += sizeof(auth_context.auth)
> >>> + + auth_context.sig_size;
> >>> image.update_vendor_code_size = 0; /* none */
> >>> image.update_hardware_instance = instance;
> >>> image.image_capsule_support = 0;
> >>> + if (auth_context.sig_size)
> >>> + image.image_capsule_support |= CAPSULE_SUPPORT_AUTHENTICATION;
> >>>
> >>> size = fwrite(&image, 1, sizeof(image), f);
> >>> if (size < sizeof(image)) {
> >>> printf("write failed (%zx)\n", size);
> >>> - goto err_3;
> >>> + goto err_4;
> >>> }
> >>> - size = fread(data, 1, bin_stat.st_size, g);
> >>> - if (size < bin_stat.st_size) {
> >>> - printf("read failed (%zx)\n", size);
> >>> - goto err_3;
> >>> +
> >>> +#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
> >>
> >> We don't want to use #if if avoidable.
> >
> > For this specific chunk of code, we can remove #ifdef,
> > but we should not remove #ifdef elsewhere.
> >
> > -Takahiro Akashi
> >
> >
> >>> + if (auth_context.sig_size) {
> >>> + size = fwrite(&auth_context.auth, 1,
> >>> + sizeof(auth_context.auth), f);
> >>> + if (size < sizeof(auth_context.auth)) {
> >>> + printf("write failed (%zx)\n", size);
> >>> + goto err_4;
> >>> + }
> >>> + size = fwrite(auth_context.sig_data, 1,
> >>> + auth_context.sig_size, f);
> >>> + if (size < auth_context.sig_size) {
> >>> + printf("write failed (%zx)\n", size);
> >>> + goto err_4;
> >>> + }
> >>> }
> >>> +#endif
> >>> +
> >>> size = fwrite(data, 1, bin_stat.st_size, f);
> >>> if (size < bin_stat.st_size) {
> >>> printf("write failed (%zx)\n", size);
> >>> - goto err_3;
> >>> + goto err_4;
> >>> }
> >>>
> >>> fclose(f);
> >>> fclose(g);
> >>> free(data);
> >>> +#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
> >>> + if (auth_context.sig_size)
> >>> + OPENSSL_free(auth_context.sig_data);
> >>> +#endif
> >>>
> >>> return 0;
> >>>
> >>> -err_3:
> >>> +err_4:
> >>> fclose(f);
> >>> +err_3:
> >>> +#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
> >>> + if (auth_context.sig_size)
> >>> + OPENSSL_free(auth_context.sig_data);
> >>> +#endif
> >>> err_2:
> >>> free(data);
> >>> err_1:
> >>> @@ -359,10 +605,6 @@ err_1:
> >>> return -1;
> >>> }
> >>>
> >>> -/*
> >>> - * Usage:
> >>> - * $ mkeficapsule -f
> >>> - */
> >>> int main(int argc, char **argv)
> >>> {
> >>> char *file;
> >>> @@ -370,6 +612,8 @@ int main(int argc, char **argv)
> >>> char *dtb_file;
> >>> efi_guid_t *guid;
> >>> unsigned long index, instance;
> >>> + uint64_t mcount;
> >>> + char *privkey_file, *cert_file;
> >>> int c, idx;
> >>> int ret;
> >>> bool overlay = false;
> >>> @@ -380,8 +624,12 @@ int main(int argc, char **argv)
> >>> guid = NULL;
> >>> index = 0;
> >>> instance = 0;
> >>> + mcount = 0;
> >>> + privkey_file = NULL;
> >>> + cert_file = NULL;
> >>> + dump_sig = 0;
> >>> for (;;) {
> >>> - c = getopt_long(argc, argv, "f:r:i:I:v:D:K:Oh", options,
> >>> &idx);
> >>> + c = getopt_long(argc, argv, opts_short, options, &idx);
> >>> if (c == -1)
> >>> break;
> >>>
> >>> @@ -422,6 +670,28 @@ int main(int argc, char **argv)
> >>> }
> >>> dtb_file = optarg;
> >>> break;
> >>> +#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
> >>
> >> see above
> >>
> >> Best regards
> >>
> >> Heinrich
> >>
> >>> + case 'P':
> >>> + if (privkey_file) {
> >>> + printf("Private Key already specified\n");
> >>> + return -1;
> >>> + }
> >>> + privkey_file = optarg;
> >>> + break;
> >>> + case 'C':
> >>> + if (cert_file) {
> >>> + printf("Certificate file already
> >>> specified\n");
> >>> + return -1;
> >>> + }
> >>> + cert_file = optarg;
> >>> + break;
> >>> + case 'm':
> >>> + mcount = strtoul(optarg, NULL, 0);
> >>> + break;
> >>> + case 'd':
> >>> + dump_sig = 1;
> >>> + break;
> >>> +#endif
> >>> case 'O':
> >>> overlay = true;
> >>> break;
> >>> @@ -431,8 +701,12 @@ int main(int argc, char **argv)
> >>> }
> >>> }
> >>>
> >>> - /* need a fit image file or raw image file */
> >>> - if (!file && !pkey_file && !dtb_file) {
> >>> + /* check necessary parameters */
> >>> + if ((file && (!(optind < argc) ||
> >>> + (privkey_file && !cert_file) ||
> >>> + (!privkey_file && cert_file))) ||
> >>> + ((pkey_file && !dtb_file) ||
> >>> +(!pkey_file && dtb_file))) {
> >>> print_usage();
> >>> exit(EXIT_FAILURE);
> >>> }
> >>> @@ -442,12 +716,12 @@ int main(int argc, char **argv)
> >>> if (ret == -1) {
> >>> printf("Adding public key to the dtb failed\n");
> >>> exit(EXIT_FAILURE);
> >>> - } else {
> >>> - exit(EXIT_SUCCESS);
> >>> }
> >>> }
> >>>
> >>> - if (create_fwbin(argv[optind], file, guid, index, instance)
> >>> + if (optind < argc &&
> >>> + create_fwbin(argv[optind], file, guid, index, instance,
> >>> +mcount, privkey_file, cert_file)
> >>> < 0) {
> >>> printf("Creating firmware capsule failed\n");
> >>> exit(EXIT_FAILURE);
> >>>
> >>
>
--
Masami Hiramatsu
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
Hi Heinrich, 2021年5月13日(木) 14:50 Heinrich Schuchardt : > > On 5/13/21 7:12 AM, Masami Hiramatsu wrote: > > Hi Heinrich, > > > > 2021年5月13日(木) 13:22 Heinrich Schuchardt : > >> > >> On 5/13/21 5:08 AM, AKASHI Takahiro wrote: > >>> On Wed, May 12, 2021 at 10:56:41AM +0200, Heinrich Schuchardt wrote: > >>>> On 12.05.21 06:57, AKASHI Takahiro wrote: > >>>>> With this enhancement, mkeficapsule will be able to create a capsule > >>>>> file with a signature which will be verified later by FMP's SetImage(). > >>>>> > >>>>> We will have to specify addtional command parameters: > >>>>> -monotonic-cout : monotonic count > >>>>> -private-key : private key file > >>>>> -certificate : certificate file > >>>>> Only when those parameters are given, a signature will be added > >>>>> to a capsule file. > >>>>> > >>>>> Users are expected to maintain the monotonic count for each firmware > >>>>> image. > >>>>> > >>>>> Signed-off-by: AKASHI Takahiro > >>>>> --- > >>>>>tools/Makefile | 4 + > >>>>>tools/mkeficapsule.c | 324 > >>>>> +++ > >>>>>2 files changed, 303 insertions(+), 25 deletions(-) > >>>>> > >>>>> diff --git a/tools/Makefile b/tools/Makefile > >>>>> index d020c55d6644..02eae0286e20 100644 > >>>>> --- a/tools/Makefile > >>>>> +++ b/tools/Makefile > >>>>> @@ -231,6 +231,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs > >>>>>hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler > >>>>>HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include > >>>>> > >>>>> +ifneq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),) > >>>>> +HOSTLDLIBS_mkeficapsule += \ > >>>>> + $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo > >>>>> "-lssl -lcrypto") > >>>> > >>>> I don't expect any user wants to install two tool versions in parallel. > >>>> > >>>> The tool should always be able to add a signature. > >>>> Adding a signature must be optional. > >>> > >>> It seems to me that those two statements mutually contradict. > >>> Or do you intend to say that we should have a separate kconfig > >>> option to enable/disable signing feature in mkeficapsule? > >>> > >>> If so, I can agree. > >>> > >>> In either way, we should have an option to turn on/off this functionality > >>> as not all users use signed capsules. > >> > >> I want to have a single binary to distribute with Linux distros (e.g. > >> Debian/Ubuntu package u-boot-tools). > > > > I couldn't catch your point. If so, the distros can build u-boot with > > CONFIG_EFI_CAPSULE_AUTHENTICATE=y... > > Why should the tool depend on board configuration? Yeah, at this point I agreed. I think there should be a separated CONFIG for tools or forcibly link those libraries. (I think most people don't mind if it requires new libraries to be built, that usually happens.) > Who would want capsule updates without authentication? Hm, so you think even CONFIG_EFI_CAPSULE_AUTHENTICATE is only for development. Capsule must be signed, right? Then, all distro should build u-boot with CONFIG_EFI_CAPSULE_AUTHENTICATE=y, isn't it? > > BTW, IMHO, if u-boot.bin can not find the ESL in the device tree, > > it should skip authentication too. > > In this case the capsule should be rejected (if > CONFIG_EFI_CAPSULE_AUTHENTICATE=y). I meant U-Boot has NO key to authenticate the capsule. I think in that case U-Boot build process must require the key (ESL) and if user doesn't provide it, the build should fail (if it doesn't skip capsule authentication.) Or, we have no way to update U-Boot anymore. > > Then, user can choose whether enabling capsule authentication or not > > by embedding ESL into their devicetree. > > The user shall not be able to decide anything that might hamper > security. The U-Boot binary must dictate if a capsule is safe. Hmm, I think the root issue is that the ESL embedding process is not integrated into the build process yet. For the safe capsule update, we must enable capsule authentication with keys. (unsafe one is only for testing/development) M
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
2021年5月13日(木) 16:24 AKASHI Takahiro : > > >> > BTW, IMHO, if u-boot.bin can not find the ESL in the device tree, > > >> > it should skip authentication too. > > >> > > >> In this case the capsule should be rejected (if > > >> CONFIG_EFI_CAPSULE_AUTHENTICATE=y). > > > > > >That's basically right. > > >But as I mentioned in my comment against Sughosh's patch, > > >the authentication process will be enforced only if the capsule has > > >an attribute, IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. > > > > > > > That would be a security desaster. > > The requirement that I mentioned above is clearly described > in UEFI specification. > If you think that it is a disaster, please discuss the topic > in UEFI Forum first. I confirmed UEFI specification, version 2.7, Section.23.1 the last of EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() - If IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED is supported and clear, then authentication is not required to perform the firmware image operations. - Oh, this is really crazy because deciding whether to authenticate the suspicious package or not, depends on whether the package said "please authenticate me" or not. :D Anyway, since this behavior follows the specification, it should be kept by default, but also IMHO, there should be a CONFIG option to enforce capsule authentication always. Thank you, -- Masami Hiramatsu
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
2021年5月13日(木) 19:27 Ilias Apalodimas : > > On Thu, May 13, 2021 at 05:38:51PM +0900, AKASHI Takahiro wrote: > > On Thu, May 13, 2021 at 05:18:36PM +0900, Masami Hiramatsu wrote: > > > 2021年5月13日(木) 16:24 AKASHI Takahiro : > > > > > > > > >> > BTW, IMHO, if u-boot.bin can not find the ESL in the device tree, > > > > > >> > it should skip authentication too. > > > > > >> > > > > > >> In this case the capsule should be rejected (if > > > > > >> CONFIG_EFI_CAPSULE_AUTHENTICATE=y). > > > > > > > > > > > >That's basically right. > > > > > >But as I mentioned in my comment against Sughosh's patch, > > > > > >the authentication process will be enforced only if the capsule has > > > > > >an attribute, IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. > > > > > > > > > > > > > > > > That would be a security desaster. > > > > > > > > The requirement that I mentioned above is clearly described > > > > in UEFI specification. > > > > If you think that it is a disaster, please discuss the topic > > > > in UEFI Forum first. > > > > > > I confirmed UEFI specification, version 2.7, Section.23.1 > > > the last of EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() > > > > > > - > > > If IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED is supported and clear, then > > > authentication is not required to perform the firmware image operations. > > > - > > > > Thank you for citing this. > > > > > Oh, this is really crazy because deciding whether to authenticate the > > > suspicious > > > package or not, depends on whether the package said "please > > > authenticate me" or not. :D > > > > Well, the attributes can been fetched with GetInfo API, but > > how it is managed depends on the implementation of FMP drivers. > > > > As I proposed somewhere else, those attributes should be > > maintained in a separate place (maybe as part of system's policy), > > presumably ESRT or platform-specific internal database? > > FWIW I personally don't think we should even have a config option. But even > if we did it certainly must not be dictated by a hardware config. > > When you install distro packages you accept whatever dependencies the > package has. mkeficapsule is a capsule creation and signing tool. I don't > see any reason for keeping the creation and signing apart. My question is, since the U-Boot binary is heavily dependent on the target platform, can we split the u-boot.bin creation (may include embedding keys) and the capsule file creation (including signing)? Thank you, -- Masami Hiramatsu
Re: [PATCH 2/4] tools: mkeficapsule: remove device-tree related operation
Hi Heinrich,
2021年5月14日(金) 2:42 Heinrich Schuchardt :
>
> On 5/13/21 9:13 AM, AKASHI Takahiro wrote:
> > On Thu, May 13, 2021 at 07:08:12AM +0200, Heinrich Schuchardt wrote:
> >> On 5/13/21 4:33 AM, AKASHI Takahiro wrote:
> >>> On Wed, May 12, 2021 at 12:01:32PM +0200, Heinrich Schuchardt wrote:
> >>>> On 12.05.21 10:01, Ilias Apalodimas wrote:
> >>>>> On Wed, May 12, 2021 at 04:49:02PM +0900, Masami Hiramatsu wrote:
> >>>>>> Hi Ilias,
> >>>>>>
> >>>>>> 2021年5月12日(水) 16:21 Ilias Apalodimas :
> >>>>>>>
> >>>>>>> Akashi-san,
> >>>>>>>
> >>>>>>> On Wed, May 12, 2021 at 01:57:51PM +0900, AKASHI Takahiro wrote:
> >>>>>>>> As we discussed, "-K" and "-D" options have nothing to do with
> >>>>>>>> creating a capsule file. The same result can be obtained by
> >>>>>>>> using standard commands like:
> >>>>>>>> === signature.dts ===
> >>>>>>>> /dts-v1/;
> >>>>>>>> /plugin/;
> >>>>>>>>
> >>>>>>>> &{/} {
> >>>>>>>> signature {
> >>>>>>>> capsule-key = /incbin/("SIGNER.esl");
> >>>>>>>> };
> >>>>>>>> };
> >>>>>>>> ===
> >>>>>>>> $ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
> >>>>>>>> $ fdtoverlay -i test.dtb -o test_sig.dtb -v signature.dtbo
> >>>>>>>>
> >>>>>>>> So just remove this feature.
> >>>>>>>> (Effectively revert the commit 322c813f4bec ("mkeficapsule: Add
> >>>>>>>> support
> >>>>>>>> for embedding public key in a dtb").)
> >>>>>>>>
> >>>>>>>> The same feature is implemented by a shell script (tools/fdtsig.sh).
> >>>>>>>
> >>>>>>>
> >>>>>>> The only reason I can see to keep this, is if mkeficapsule gets
> >>>>>>> included
> >>>>>>> intro distro packages in the future. That would make end users life
> >>>>>>> a bit
> >>>>>>> easier, since they would need a single binary to create the whole
> >>>>>>> CapsuleUpdate sequence.
> >>>>>>
> >>>>>> Hmm, I think it is better to write a manpage of mkeficapsule which
> >>>>>> also describes
> >>>>>> how to embed the key into dtb as in the above example if it is so
> >>>>>> short.
> >>>>>> Or, distros can package the above shell script with mkeficapsule.
> >>>>>>
> >>>>>> Embedding a key and signing a capsule are different operations but
> >>>>>> using the same tool may confuse users (at least me).
> >>>>>
> >>>>> Sure fair enough. I am merely pointing out we need a way to explain
> >>>>> all of
> >>>>> those to users.
> >>>>
> >>>> This is currently our only documentation:
> >>>>
> >>>> https://u-boot.readthedocs.io/en/latest/board/emulation/qemu_capsule_update.html?highlight=mkeficapsule
> >>>
> >>> As I mentioned several times (and TODO in the cover letter),
> >>> this text must be reviewed, revised and generalized
> >>> as a platform-independent document.
> >>> It contains a couple of errors.
> >>>
> >>>> For mkimage we have a man-page ./doc/mkimage.1 that is packaged with
> >>>> Debians u-boot-tools package. Please, provide a similar man-page as
> >>>> ./doc/mkeficapsule.1.
> >>>
> >>> So after all do you agree to removing "-K/-D"?
> >>
> >> I see no need to replicate in U-Boot what is already in the device tree
> >> compiler package.
> >
> > This is another reason that we should remove Sughosh's change.
> >
> >> In the current workflow the fdt command is used to load the public key.
> >> This is insecure and not usable for production.
> >
> > I totally disagree.
> > Why is using fdt command (what do
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
Hi all, I think it's time to summarize the topics on this thread. 1. tools/mkeficapsule, config options dependency - The tools, especially useful and distributable tools like mkeficapsule should not be changed by the target board configuration. - Since there are target boards which don't need capsule authentication, it should be configurable. That also can optimize the library dependency. 2. tools/mkeficapsule, revert -K/-D options - Since these options are for embedding a public key in the devicetree, that is not related to the capsule file. Also, the same feature can be provided by a simple shell script. 3. capsule authentication, key embedding method - Embedding key in the devicetree is too fragile, especially, the document says overwriting new device tree including key with fdt command. That is not for the product, only for proof of concept. - Such a key should be embedded in the U-Boot, or hardware secure storage so that the user can not change it. (BTW, I think there are more options, like embedding keys in SCP firmware, TF-A, or OP-TEE, outside of U-Boot) 4. capsule authentication, authentication enablement - The UEFI spec said IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED can be supported but cleared (for the current running firmware). This means it is possible that the authentication feature is supported, but not enabled. - For ensuring security, if U-Boot is compiled with CONFIG_EFI_CAPSULE_AUTHETICATE=y, IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED must always be set. Are there any other topics on this thread? and any other comments on these topics? Thank you, 2021年5月14日(金) 18:51 AKASHI Takahiro : > > Heinrich, > > Can you please reply to each of my replies? > Otherwise, I don't know which one of my comments/opinions you agree to > and which one not. > > On Fri, May 14, 2021 at 10:45:48AM +0200, Heinrich Schuchardt wrote: > > On 5/14/21 9:13 AM, AKASHI Takahiro wrote: > > > > E.g for IMAGE_ATTRIBUTE_IN_USE > > > > > > > > AttributesSupported | AttributesSetting | Meaning > > > > +---+ > > > > 0 | 0 | state is unknown > > > > 0 | 1 | state is unknown > > > > 1 | 0 | image is not in use > > > > 1 | 1 | image is in use > > > We are discussing *_REQUIRED. > > > Can you give me the same table for *_REQUIRED? > > > > > > -Takahiro Akashi > > > > > > > > > > IMAGE_ATTRIBUTE_RESET_REQUIRED > > > > AttributesSupported | AttributesSetting | Meaning > > +---+ > > 0 | 0 | state is unknown > > 0 | 1 | state is unknown > > 1 | 0 | reset is not needed > > | | to complete upgrade > > 1 | 1 | reset is needed > > | | to complete upgrade > > > > > > IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED > > > > AttributesSupported | AttributesSetting | Meaning > > +---+ > > 0 | 0 | state is unknown > > 0 | 1 | state is unknown > > 1 | 0 | signed and unsigned > > | | capsules are accepted > > 1 | 1 | capsules are only > > | | accepted after > > | | checking the signature > > So what? > This table shows there is a case where the authentication will be > skipped even if CONFIG_EFI_CAPSULE_AUTHETICATE is on and > it is completely compliant with UEFI specification. > > That is what I and Masami was discussing. > > > > > > > But as I mentioned in my comment against Sughosh's patch, > > > > > > the authentication process will be enforced only if the capsule has > > > > > > an attribute, IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. > > > > > > > > > > > > > > > > That would be a security desaster. > > So I said that you should discuss the topic in UEFI forum first > if you think so. > > -Takahiro Akashi > > > > For both bits AttributesSupported=0 does not make much sense. > > > > IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED is a property of the current > > image and should only be deleted by installing a new capsule. > > > > A vendor might send you a special firmware image for unlocking your > > device after registering as a developer. Xiaomi handled it like this for > > one of my routers. > > > > Best regards > > > > Heinrich -- Masami Hiramatsu
Re: [PATCH 1/4] tools: mkeficapsule: add firmwware image signing
Hi Heinrich, 2021年5月15日(土) 11:03 Heinrich Schuchardt : > > On 5/14/21 3:09 PM, Masami Hiramatsu wrote: > > Hi all, > > > > I think it's time to summarize the topics on this thread. > > > > 1. tools/mkeficapsule, config options dependency > >- The tools, especially useful and distributable tools like > > mkeficapsule should not be changed by the target board configuration. > >- Since there are target boards which don't need capsule > > authentication, it should be configurable. That also can optimize the > > library dependency. > > Thank you for providing this summary. > > You described that the tool shall not depend on the target board > configuration. Your sentence starting with "Since" contradicts this. Ah, sorry for the confusion. Each bullet shows a different opinion on the topic. > As Ilias pointed out all Linux distributions come with an OpenSSL > package. The library dependency is nothing to worry about. OK, so this is for topic #1. > > Capsule updates without authentication don't not make much sense in a > world full of attacks. and this is for topic #1 and maybe related to #4? > > Hence, a configuration switch for the tool is not needed. Thanks for clarifying your opinion! > > Best regards > > Heinrich > > > > > 2. tools/mkeficapsule, revert -K/-D options > >- Since these options are for embedding a public key in the > > devicetree, that is not related to the capsule file. Also, the same > > feature can be provided by a simple shell script. > > > > 3. capsule authentication, key embedding method > >- Embedding key in the devicetree is too fragile, especially, the > > document says overwriting new device tree including key with fdt > > command. That is not for the product, only for proof of concept. > >- Such a key should be embedded in the U-Boot, or hardware secure > > storage so that the user can not change it. > > (BTW, I think there are more options, like embedding keys in SCP > > firmware, TF-A, or OP-TEE, outside of U-Boot) > > > > 4. capsule authentication, authentication enablement > >- The UEFI spec said IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED can be > > supported but cleared (for the current running firmware). This means > > it is possible that the authentication feature is supported, but not > > enabled. > >- For ensuring security, if U-Boot is compiled with > > CONFIG_EFI_CAPSULE_AUTHETICATE=y, > > IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED must always be set. > > > > Are there any other topics on this thread? and any other comments on > > these topics? > > > > Thank you, -- Masami Hiramatsu
[PATCH v4 00/14] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hi, Here is the 4th version of the series (including some fixes for build errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. This series includes not only DeveloperBox support but also some fixes for the issues which I faced while porting U-Boot on the DeveloperBox. First 3 patches are fixes, next 1 patch is a code cleanup for generic gpio for arm. The next 7 patches adding DeveloperBox devices and board support. The last 3 patches are related to the UEFI capsule update (including bugfixes). Previous version is here: https://lists.denx.de/pipermail/u-boot/2021-May/449305.html Changes in v4 - I dropped a PCI bugfix because it has been merged. And add I2C driver and enable RTC and EBBR support on the configuration. [06/14]: - Add Jaehoon's reviewed-by (Thanks!) [09/14]: - Add a new i2c driver. [10/14]: - Add i2c0 and RTC node. [11/14]: - Add I2C and RTC configuration. - Enable RTC and Date command. - Remove I2C0 node before booting linux to hide it same as EDK2 does. - Add some configurations to make it EBBR compliant. [14/14]: - Add some config options for EBBR. BTW, should I split fixes from this series? (since I didn't expect this took so long...) DeveloperBox DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots (1x slots are connected via PCIe bridge chip) * 4 USB-3.0 ports * 2 SATA ports * 1 GbE network port * 1 USB-UART serial port (micro USB) * 64MB SPI NOR Flash * 8GB eMMC Flash Storage * 96boards LS connector The DeveloperBox schematic can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf And the other documents can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/ Currently, the U-Boot port supports: - * USB * eMMC * SPI-NOR * SATA * GbE The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as BL33, but no need to combine with it. Thank you, --- Jassi Brar (4): mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver spi: synquacer: Add HSSPI SPI controller driver for SynQuacer net: synquacer: Add netsec driver i2c: synquacer: SNI Synquacer I2C controller Masami Hiramatsu (10): ata: ahci-pci: Use scsi_ops to initialize ops dm: pci: Skip setting VGA bridge bits if parent device is the host bus efi: Fix to use null handle to create new handle for efi_fmp_raw gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs pci: synquacer: Add SynQuacer ECAM based PCIe driver ARM: dts: synquacer: Add device trees for DeveloperBox board: synquacer: Add DeveloperBox 96boards EE support dfu_mtd: Ignore non-implemented lock device failure doc: qemu: arm64: Fix the documentation of capsule update configs: synquacer: Enable EFI capsule update support arch/arm/Kconfig | 108 ++ arch/arm/dts/Makefile |2 arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 + .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 + arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 + arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++ arch/arm/include/asm/gpio.h|8 board/socionext/developerbox/Kconfig | 36 + board/socionext/developerbox/MAINTAINERS | 14 board/socionext/developerbox/Makefile |9 board/socionext/developerbox/developerbox.c| 146 +++ configs/synquacer_developerbox_defconfig | 131 ++ doc/board/emulation/qemu_capsule_update.rst| 11 doc/board/index.rst|1 doc/board/socionext/developerbox.rst | 87 ++ doc/board/socionext/index.rst |9 drivers/ata/ahci-pci.c |2 drivers/dfu/dfu_mtd.c |2 drivers/i2c/Kconfig|7 drivers/i2c/Makefile |1 drivers/i2c/synquacer_i2c.c| 338 ++ drivers/mmc/Kconfig| 10 drivers/mmc/Makefile |1 drivers/mmc/f_sdh30.c | 81 + drivers/net/Kconfig|8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 drivers/pci/Kconfig| 12 drivers/pci/Makefile |1 d
[PATCH v4 01/14] ata: ahci-pci: Use scsi_ops to initialize ops
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/ata/ahci-pci.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f..b1d231e0f9 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops= &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
[PATCH v4 02/14] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [7800-7fff],
Physical Memory [7800-7fffx]
PCI Autoconfig: Bus I/O region: [0-],
Physical Memory [77f0-77f0x]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x100, address=0x7800
bus_lower=0x7900
PCI Autoconfig: BAR 1, Mem, size=0x800, No room in resource, avail
start=7900 / size=800, need=800
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x200, address=0x7a00
bus_lower=0x7c00
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x8, address=0x7c00 bus_lower=0x7c08
"Synchronous Abort" handler, esr 0x9606
elr: e002bd28 lr : e002bce8 (reloc)
elr: fff6fd28 lr : fff6fce8
x0 : 1041 x1 : 003e
x2 : ffb0f8c8 x3 : 0001
x4 : 0080 x5 :
x6 : fff718fc x7 : 000f
x8 : ffb0f238 x9 : 0008
x10: x11: 0010
x12: 0006 x13: 0001869f
x14: ffb0fcd0 x15: 0020
x16: fff71cc4 x17:
x18: ffb13d90 x19: ffb14320
x20: x21: ffb14090
x22: ffb0f8c8 x23: 0001
x24: ffb14c10 x25:
x26: x27:
x28: ffb14c70 x29: ffb0f830
Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/pci/pci-uclass.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e632..afe4f1974a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
[PATCH v4 03/14] efi: Fix to use null handle to create new handle for efi_fmp_raw
When running the efidebug capsule disk-update command, the efi_fmp_raw
protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
below. This is because the code passes efi_root instaed of handle.
=> efidebug capsule disk-update
EFI: Call: efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbaf5988)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbaf5988,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6ee8)
EFI: new handle fbb37520
EFI: Exit: efi_install_protocol_interface: 0
EFI: 0 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 0
EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbfec648)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbfec648,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6f18)
EFI: handle fbaf8520
EFI: Exit: efi_install_protocol_interface: 2
EFI: 2 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 2
EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
Command failed, result=1
To fix this issue, pass the handle variable as same as the efi_fmp_fit
installation.
Signed-off-by: Masami Hiramatsu
---
lib/efi_loader/efi_capsule.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 6ee883d5b1..f038245c93 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -949,7 +949,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
handle = NULL;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &efi_root,
+ &handle,
&efi_guid_firmware_management_protocol,
&efi_fmp_raw, NULL));
}
[PATCH v4 04/14] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Change the config name to positive and selected by the opposite CONFIG_ARCH_*. (Build checked by Github CI) --- arch/arm/Kconfig| 94 +++ arch/arm/include/asm/gpio.h |8 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..023824df77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select D
[PATCH v4 05/14] pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile |1 drivers/pci/pcie_ecam_synquacer.c | 600 + 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index d5b6018b3d..2e6393f25b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 1f741786a0..035e3d3088 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 00..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOPBIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REGBIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_10x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +
[PATCH v4 07/14] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
From: Jassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
drivers/spi/Kconfig |8 +
drivers/spi/Makefile|1
drivers/spi/spi-synquacer.c | 491 +++
3 files changed, 500 insertions(+)
create mode 100644 drivers/spi/spi-synquacer.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..62d9676550 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -481,4 +481,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..98c95323d1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 00..ce558c4bc0
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MCTRL 0x0
+#define MEN0
+#define CSEN 1
+#define IPCLK 3
+#define MES4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF0x14
+#define TXE0x18
+#define TXC0x1c
+#define RXF0x20
+#define RXE0x24
+#define RXC0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART0x38
+#define TRIGGER0
+#define DMSTOP 8
+#define CS_MASK3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX1
+#define DATA_TX2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
[PATCH v4 06/14] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
From: Jassi Brar
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
Reviewed-by: Jaehoon Chung
---
Changes in v4:
- Add Jaehoon's reviewed-by.
Changes in v3:
- Rename config name to MMC_SDHCI_F_SDH30.
- Remove unneeded wait in drivers/mmc/sdhci.c.
- Rename probe function to f_sdh30_sdhci_probe.
---
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile |1 +
drivers/mmc/f_sdh30.c | 81 +
3 files changed, 92 insertions(+)
create mode 100644 drivers/mmc/f_sdh30.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8901456967..1c5aecfa5c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -561,6 +561,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config MMC_SDHCI_F_SDH30
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db3..f5fd59093e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER)+= tmio-common.o
uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30)+= f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 00..3a85d9e348
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 2, 40);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops= &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
[PATCH v4 08/14] net: synquacer: Add netsec driver
From: Jassi Brar Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar --- drivers/net/Kconfig |8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 ++ 3 files changed, 1143 insertions(+) create mode 100644 drivers/net/sni_netsec.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 382639044b..9fc28b149d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -673,6 +673,14 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config SNI_NETSEC + bool "Socionext NETSEC Ethernet support" + depends on DM_ETH && SYNQUACER_SPI + select PHYLIB + help + This driver implements support for the Socionext SynQuacer NETSEC + ethernet controller, as found on the Socionext SynQuacer family. + source "drivers/net/mscc_eswitch/Kconfig" config ETHER_ON_FEC1 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 2ce89f7e3c..c23e828edc 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-y += mscc_eswitch/ diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c new file mode 100644 index 00..a9ebf6af9c --- /dev/null +++ b/drivers/net/sni_netsec.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * netsec.c - Socionext Synquacer Netsec driver + * Copyright 2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NETSEC_REG_SOFT_RST0x104 +#define NETSEC_REG_COM_INIT0x120 + +#define NETSEC_REG_TOP_STATUS 0x200 +#define NETSEC_IRQ_RX BIT(1) +#define NETSEC_IRQ_TX BIT(0) + +#define NETSEC_REG_TOP_INTEN 0x204 +#define NETSEC_REG_INTEN_SET 0x234 +#define NETSEC_REG_INTEN_CLR 0x238 + +#define NETSEC_REG_NRM_TX_STATUS 0x400 +#define NETSEC_REG_NRM_TX_INTEN0x404 +#define NETSEC_REG_NRM_TX_INTEN_SET0x428 +#define NETSEC_REG_NRM_TX_INTEN_CLR0x42c +#define NRM_TX_ST_NTOWNR BIT(17) +#define NRM_TX_ST_TR_ERR BIT(16) +#define NRM_TX_ST_TXDONE BIT(15) +#define NRM_TX_ST_TMREXP BIT(14) + +#define NETSEC_REG_NRM_RX_STATUS 0x440 +#define NETSEC_REG_NRM_RX_INTEN0x444 +#define NETSEC_REG_NRM_RX_INTEN_SET0x468 +#define NETSEC_REG_NRM_RX_INTEN_CLR0x46c +#define NRM_RX_ST_RC_ERR BIT(16) +#define NRM_RX_ST_PKTCNT BIT(15) +#define NRM_RX_ST_TMREXP BIT(14) + +#define NETSEC_REG_PKT_CMD_BUF 0xd0 + +#define NETSEC_REG_CLK_EN 0x100 + +#define NETSEC_REG_PKT_CTRL0x140 + +#define NETSEC_REG_DMA_TMR_CTRL0x20c +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c +#define NETSEC_REG_F_TAIKI_VER 0x230 +#define NETSEC_REG_DMA_HM_CTRL 0x214 +#define NETSEC_REG_DMA_MH_CTRL 0x220 +#define NETSEC_REG_ADDR_DIS_CORE 0x218 +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c + +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 + +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT0x418 + +#define NETSEC_REG_NRM_TX_TMR 0x41c + +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 +#define NETSEC_REG_NRM_TX_TXINT_TMR0x420 +#define NETSEC_REG_NRM_RX_RXINT_TMR0x460 + +#define NETSEC_REG_NRM_RX_TMR 0x45c + +#define NETSEC_REG_NRM_TX_DESC_START_UP0x434 +#define NETSEC_REG_NRM_TX_DESC_START_LW0x408 +#define NETSEC_REG_NRM_RX_DESC_START_UP0x474 +#define NETSEC_REG_NRM_RX_DESC_START_LW0x448 + +#define NETSEC_REG_NRM_TX_CONFIG 0x430 +#define NETSEC_REG_NRM_RX_CONFIG 0x470 + +#define MAC_REG_STATUS 0x1024 +#define MAC_REG_DATA 0x11c0 +#define MAC_REG_CMD0x11c4 +#define MAC_REG_FLOW_TH0x11cc +#define MAC_REG_INTF_SEL 0x11d4 +#define M
[PATCH v4 09/14] i2c: synquacer: SNI Synquacer I2C controller
From: Jassi Brar Add driver for class of I2C controllers found on Socionext Synquacer platform. Signed-off-by: Jassi Brar --- drivers/i2c/Kconfig |7 + drivers/i2c/Makefile|1 drivers/i2c/synquacer_i2c.c | 338 +++ 3 files changed, 346 insertions(+) create mode 100644 drivers/i2c/synquacer_i2c.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 57a4efb88e..ce0d796d09 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -455,6 +455,13 @@ config SYS_I2C_STM32F7 _ Optional clock stretching _ Software reset +config SYS_I2C_SYNQUACER + bool "Socionext SynQuacer I2C controller" + depends on ARCH_SYNQUACER && DM_I2C + help + Support for Socionext Synquacer I2C controller. This I2C controller + will be used for RTC and LS-connector on DeveloperBox. + config SYS_I2C_TEGRA bool "NVIDIA Tegra internal I2C controller" depends on ARCH_TEGRA diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 8c9f1fcd8b..06a1150f03 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o +obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c new file mode 100644 index 00..6672d9435e --- /dev/null +++ b/drivers/i2c/synquacer_i2c.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_BSR0x0 +#define REG_BCR0x4 +#define REG_CCR0x8 +#define REG_ADR0xc +#define REG_DAR0x10 +#define REG_CSR0x14 +#define REG_FSR0x18 +#define REG_BC2R 0x1c + +/* I2C register bit definitions */ +#define BSR_FBTBIT(0) // First Byte Transfer +#define BSR_GCABIT(1) // General Call Address +#define BSR_AASBIT(2) // Address as Slave +#define BSR_TRXBIT(3) // Transfer/Receive +#define BSR_LRBBIT(4) // Last Received Bit +#define BSR_AL BIT(5) // Arbitration Lost +#define BSR_RSCBIT(6) // Repeated Start Cond. +#define BSR_BB BIT(7) // Bus Busy + +#define BCR_INTBIT(0) // Interrupt +#define BCR_INTE BIT(1) // Interrupt Enable +#define BCR_GCAA BIT(2) // Gen. Call Access Ack. +#define BCR_ACKBIT(3) // Acknowledge +#define BCR_MSSBIT(4) // Master Slave Select +#define BCR_SCCBIT(5) // Start Condition Cont. +#define BCR_BEIE BIT(6) // Bus Error Int Enable +#define BCR_BERBIT(7) // Bus Error + +#define CCR_CS_MASK(0x1f) // CCR Clock Period Sel. +#define CCR_EN BIT(5) // Enable +#define CCR_FM BIT(6) // Speed Mode Select + +#define CSR_CS_MASK(0x3f) // CSR Clock Period Sel. + +#define BC2R_SCLL BIT(0) // SCL Low Drive +#define BC2R_SDAL BIT(1) // SDA Low Drive +#define BC2R_SCLS BIT(4) // SCL Status +#define BC2R_SDAS BIT(5) // SDA Status + +/* PCLK frequency */ +#define BUS_CLK_FR(rate) (((rate) / 2000) + 1) + +#define I2C_CLK_DEF6250 + +/* STANDARD MODE frequency */ +#define CLK_MASTER_STD(rate) \ + DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2) +/* FAST MODE frequency */ +#define CLK_MASTER_FAST(rate) \ + DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3) + +/* (clkrate <= 1800) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MAX_18M(rate) \ + ((CLK_MASTER_STD(rate) - 65) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define CSR_CS_STD_MAX_18M(rate) 0x00 + +/* calculate the value of CS bits in CCR register on fast mode */ +#define CCR_CS_FAST_MAX_18M(rate) \ + ((CLK_MASTER_FAST(rate) - 1) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define CSR_CS_FAST_MAX_18M(rate) 0x00 + +/* (clkrate > 1800) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MIN_18M(rate) \ + ((CLK_MASTER_STD(rate) -
[PATCH v4 10/14] ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu
---
Changes in v4:
- Add i2c0 and RTC node.
Changes in v3:
- Use generic nor flash instead of specific mx25u51245g.
(chip parameters will be searched by the register value)
Changes in v2:
- Add reference commit id of original EDK2 to the comment
- Just copy the EDK2 dts files as-is (change #include path)
- Split out the u-boot specific changes in -u-boot.dtsi.
- Removed unneeded spi-nor flash partition information.
---
arch/arm/dts/Makefile |2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +++
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++
arch/arm/dts/synquacer-sc2a11.dtsi | 595
5 files changed, 801 insertions(+)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c601a5c98..2195729d7c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1099,6 +1099,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) +=
ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi
b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 00..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref {\
+i-cache-size = <0x8000>;\
+i-cache-line-size = <64>; \
+i-cache-sets = <256>; \
+d-cache-size = <0x8000>;\
+d-cache-line-size = <64>; \
+d-cache-sets = <128>; \
+l2-cache = ; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+cache-size = <0x4>; \
+cache-line-size = <64>; \
+cache-sets = <256>; \
+cache-unified; \
+next-level-cache = <&L3>; \
+};
+
+/ {
+__L2(0)
+__L2(1)
+__L2(2)
+__L2(3)
+__L2(4)
+__L2(5)
+__L2(6)
+__L2(7)
+__L2(8)
+__L2(9)
+__L2(10)
+__L2(11)
+
+L3: l3-cache {
+cache-level = <3>;
+cache-size = <0x40>;
+cache-line-size = <64>;
+cache-sets = <4096>;
+cache-unified;
+};
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 00..2f13a42235
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ i2c0 = &i2c0;
+ };
+
+ spi_nor: spi@5480 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x5480 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+
[PATCH v4 11/14] board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- Changes in v4: - Add I2C and RTC configuration. - Enable RTC and Date command. - Remove I2C0 node before booting linux to hide it same as EDK2 does. - Add some configurations to make it EBBR compliant. Changes in v3: - Enable CONFIG_MMC_SDHCI_F_SDH30. - Enable CONFIG_CMD_GENERIC (fstype command) for distro boot. - Remove unneeded CONFIG_ONLY_GENERIC_GPIO. Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig| 14 +++ board/socionext/developerbox/Kconfig| 36 +++ board/socionext/developerbox/MAINTAINERS| 14 +++ board/socionext/developerbox/Makefile |9 ++ board/socionext/developerbox/developerbox.c | 146 +++ configs/synquacer_developerbox_defconfig| 114 + doc/board/index.rst |1 doc/board/socionext/developerbox.rst| 87 doc/board/socionext/index.rst |9 ++ include/configs/synquacer.h | 109 10 files changed, 539 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 023824df77..7ff24535cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1760,6 +1760,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2102,6 +2115,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 00..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help +Choose this option if you build the U-Boot for the DeveloperBox +96boards Enterprise Edition. +This board will booted from SCP firmware and it enables SMMU, thus +the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 00..aa672b6e05 --- /dev/null +++ b/board/socionext/develope
[PATCH v4 12/14] dfu_mtd: Ignore non-implemented lock device failure
Ignore the non-implemented lock device failure on writing mtd
via DFU. Without this fix, DFU write shows an error on such device
even if it succeeded, because dfu->write_medium returns -EOPNOTSUPP.
Signed-off-by: Masami Hiramatsu
Cc: Lukasz Majewski
---
drivers/dfu/dfu_mtd.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
index ca67585a7e..e58302c32d 100644
--- a/drivers/dfu/dfu_mtd.c
+++ b/drivers/dfu/dfu_mtd.c
@@ -152,6 +152,8 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity
*dfu,
ret = mtd_lock(mtd, lock_ofs, lock_len);
if (ret && ret != -EOPNOTSUPP)
printf("MTD device lock failed\n");
+ if (ret == -EOPNOTSUPP)
+ ret = 0;
}
return ret;
}
[PATCH v4 13/14] doc: qemu: arm64: Fix the documentation of capsule update
Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 33ce4bcd32..0a2286d039 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - -$ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ -e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. +$ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The
[PATCH v4 14/14] configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- Changes in v4: - Add some config options for EBBR. Changes in v3: - Fix a typo in dfu_alt_info. --- configs/synquacer_developerbox_defconfig | 17 + include/configs/synquacer.h |6 ++ 2 files changed, 23 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 2875fcd794..487755f444 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -112,3 +112,20 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y +CONFIG_EFI_CAPSULE_FIRMWARE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FMP_HEADER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 0dab4de1f1..8fe10d7485 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -61,6 +61,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ + "mtd nor1=u-boot.bin raw 20 10;"\ + "fip.bin raw 18 78000;" \ + "optee.bin raw 50 10\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -104,6 +109,7 @@ "ramdisk_addr_r=0xa000\0" \ "scriptaddr=0x8800\0" \ "pxefile_addr_r=0x8810\0" \ + DEFAULT_DFU_ALT_INFO\ BOOTENV #endif /* __CONFIG_H */
Re: [PATCH v4 12/14] dfu_mtd: Ignore non-implemented lock device failure
Hi Sughosh,
2021年5月19日(水) 15:07 Sughosh Ganu :
>
>
>
> On Wed, 19 May 2021 at 11:16, Masami Hiramatsu
> wrote:
>>
>> Ignore the non-implemented lock device failure on writing mtd
>> via DFU. Without this fix, DFU write shows an error on such device
>> even if it succeeded, because dfu->write_medium returns -EOPNOTSUPP.
>>
>> Signed-off-by: Masami Hiramatsu
>> Cc: Lukasz Majewski
>> ---
>> drivers/dfu/dfu_mtd.c |2 ++
>> 1 file changed, 2 insertions(+)
>
>
> A patch has already been submitted for this[1].
Ah, thanks for pointing! If that is merged, I can drop this patch.
Thank you,
>
> Patrick, can you please apply this in your tree and send it as part of the
> next PR. Thanks.
>
> -sughosh
>
> [1] - https://lists.denx.de/pipermail/u-boot/2021-March/443896.html
>
>
>>
>> diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
>> index ca67585a7e..e58302c32d 100644
>> --- a/drivers/dfu/dfu_mtd.c
>> +++ b/drivers/dfu/dfu_mtd.c
>> @@ -152,6 +152,8 @@ static int mtd_block_op(enum dfu_op op, struct
>> dfu_entity *dfu,
>> ret = mtd_lock(mtd, lock_ofs, lock_len);
>> if (ret && ret != -EOPNOTSUPP)
>> printf("MTD device lock failed\n");
>> + if (ret == -EOPNOTSUPP)
>> + ret = 0;
>> }
>> return ret;
>> }
>>
--
Masami Hiramatsu
Re: [PATCH v4 00/14] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hello Ilias, 2021年5月23日(日) 17:07 Ilias Apalodimas : > > Hi Masami, > > On Wed, May 19, 2021 at 02:44:21PM +0900, Masami Hiramatsu wrote: > > Hi, > > > > Here is the 4th version of the series (including some fixes for build > > errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. > > > > This series includes not only DeveloperBox support but also some fixes > > for the issues which I faced while porting U-Boot on the DeveloperBox. > > First 3 patches are fixes, next 1 patch is a code cleanup for generic > > gpio for arm. The next 7 patches adding DeveloperBox devices > > and board support. The last 3 patches are related to the UEFI capsule > > update (including bugfixes). > > > > Previous version is here: > > > > https://lists.denx.de/pipermail/u-boot/2021-May/449305.html > > > > > > The default debug level is set to 7. I think it would be better to set it > to something more reasonable for the final commit. Yes, it was for the development value. It should be removed from defconfig at last, because it depends on the builder's choice. > Unfortunately I don't > have time for a more detailed review, but I did manage to run this on my > Synquacer and managed to run a full linux distro with EFI. > > Tested-by: Ilias Apalodimas Thanks for testing! Thank you, > > > Changes in v4 > > - > > > > I dropped a PCI bugfix because it has been merged. And add I2C driver > > and enable RTC and EBBR support on the configuration. > > > > [06/14]: > > - Add Jaehoon's reviewed-by (Thanks!) > > [09/14]: > > - Add a new i2c driver. > > [10/14]: > > - Add i2c0 and RTC node. > > [11/14]: > > - Add I2C and RTC configuration. > > - Enable RTC and Date command. > > - Remove I2C0 node before booting linux to hide it same as EDK2 does. > > - Add some configurations to make it EBBR compliant. > > [14/14]: > > - Add some config options for EBBR. > > > > > > BTW, should I split fixes from this series? (since I didn't expect this took > > so long...) > > > > > > DeveloperBox > > > > > > DeveloperBox is a certified 96boards Enterprise Edition board. The > > board/SoC has: - > > * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor > > motherboard > > * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) > > * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots > > (1x slots are connected via PCIe bridge chip) > > * 4 USB-3.0 ports > > * 2 SATA ports > > * 1 GbE network port > > * 1 USB-UART serial port (micro USB) > > * 64MB SPI NOR Flash > > * 8GB eMMC Flash Storage > > * 96boards LS connector > > > > The DeveloperBox schematic can be found here: - > > https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf > > > > And the other documents can be found here: - > > https://www.96boards.org/documentation/enterprise/developerbox/ > > > > > > Currently, the U-Boot port supports: - > > * USB > > * eMMC > > * SPI-NOR > > * SATA > > * GbE > > > > The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. > > The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as > > BL33, but no need to combine with it. > > > > > > Thank you, > > > > --- > > > > Jassi Brar (4): > > mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver > > spi: synquacer: Add HSSPI SPI controller driver for SynQuacer > > net: synquacer: Add netsec driver > > i2c: synquacer: SNI Synquacer I2C controller > > > > Masami Hiramatsu (10): > > ata: ahci-pci: Use scsi_ops to initialize ops > > dm: pci: Skip setting VGA bridge bits if parent device is the host bus > > efi: Fix to use null handle to create new handle for efi_fmp_raw > > gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs > > pci: synquacer: Add SynQuacer ECAM based PCIe driver > > ARM: dts: synquacer: Add device trees for DeveloperBox > > board: synquacer: Add DeveloperBox 96boards EE support > > dfu_mtd: Ignore non-implemented lock device failure > > doc: qemu: arm64: Fix the documentation of capsule update > > configs: synquacer: Enable EFI capsule update support > > > > > > arch/arm/Kconfig | 108 ++ > > arch/arm/dts/Makefile
[PATCH] efi: Restrict the simple file system protocol to support only FAT
Because UEFI specification v2.9, 13.3 File System Format said "The
file system supported by the Extensible Firmware Interface is based
on the FAT file system.", the simple file system protocol might be
better to support only FAT filesystem.
There must be no problem from UEFI application to access only FAT
because ESP must be formatted by FAT32 and the removable media is
FAT12 or FAT16, according to the UEFI spec.
Reported-by: Kazuhiko Sakamoto
Signed-off-by: Masami Hiramatsu
---
lib/efi_loader/efi_disk.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 307d5d759b..f69ae6587f 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -318,19 +318,25 @@ efi_fs_from_path(struct efi_device_path *full_path)
}
/**
- * efi_fs_exists() - check if a partition bears a file system
+ * efi_supported_fs_exists() - check if a partition bears a supported file
system
*
* @desc: block device descriptor
* @part: partition number
- * Return: 1 if a file system exists on the partition
+ * Return: 1 if a supported file system exists on the partition
* 0 otherwise
*/
-static int efi_fs_exists(struct blk_desc *desc, int part)
+static int efi_supported_fs_exists(struct blk_desc *desc, int part)
{
if (fs_set_blk_dev_with_part(desc, part))
return 0;
- if (fs_get_type() == FS_TYPE_ANY)
+ /*
+* Because UEFI specification v2.9, 13.3 File System Format said
+* "The file system supported by the Extensible Firmware Interface
+* is based on the FAT file system.", the simple file system protocol
+* should support only FAT filesystem.
+*/
+ if (fs_get_type() != FS_TYPE_FAT)
return 0;
fs_close();
@@ -428,10 +434,10 @@ static efi_status_t efi_disk_add_dev(
/*
* On partitions or whole disks without partitions install the
-* simple file system protocol if a file system is available.
+* simple file system protocol if a supported file system exists.
*/
if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
- efi_fs_exists(desc, part)) {
+ efi_supported_fs_exists(desc, part)) {
diskobj->volume = efi_simple_file_system(desc, part,
diskobj->dp);
ret = efi_add_protocol(&diskobj->header,
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
+Cc: Grant and Vincent
This will fix some EBBR certification test errors if the target
machine has any partition which is partially (e.g. read only)
supported by U-Boot. UEFI spec doesn't require accessing such
filesystems, but U-Boot provides.
Of course, we can also drop filesystem configs except for FAT
filesystem support for UEFI only platforms. But it doesn't help hybrid
platforms.
Thank you,
2021年6月3日(木) 11:17 Masami Hiramatsu :
>
> Because UEFI specification v2.9, 13.3 File System Format said "The
> file system supported by the Extensible Firmware Interface is based
> on the FAT file system.", the simple file system protocol might be
> better to support only FAT filesystem.
>
> There must be no problem from UEFI application to access only FAT
> because ESP must be formatted by FAT32 and the removable media is
> FAT12 or FAT16, according to the UEFI spec.
>
> Reported-by: Kazuhiko Sakamoto
> Signed-off-by: Masami Hiramatsu
> ---
> lib/efi_loader/efi_disk.c | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> index 307d5d759b..f69ae6587f 100644
> --- a/lib/efi_loader/efi_disk.c
> +++ b/lib/efi_loader/efi_disk.c
> @@ -318,19 +318,25 @@ efi_fs_from_path(struct efi_device_path *full_path)
> }
>
> /**
> - * efi_fs_exists() - check if a partition bears a file system
> + * efi_supported_fs_exists() - check if a partition bears a supported file
> system
> *
> * @desc: block device descriptor
> * @part: partition number
> - * Return: 1 if a file system exists on the partition
> + * Return: 1 if a supported file system exists on the partition
> * 0 otherwise
> */
> -static int efi_fs_exists(struct blk_desc *desc, int part)
> +static int efi_supported_fs_exists(struct blk_desc *desc, int part)
> {
> if (fs_set_blk_dev_with_part(desc, part))
> return 0;
>
> - if (fs_get_type() == FS_TYPE_ANY)
> + /*
> +* Because UEFI specification v2.9, 13.3 File System Format said
> +* "The file system supported by the Extensible Firmware Interface
> +* is based on the FAT file system.", the simple file system protocol
> +* should support only FAT filesystem.
> +*/
> + if (fs_get_type() != FS_TYPE_FAT)
> return 0;
>
> fs_close();
> @@ -428,10 +434,10 @@ static efi_status_t efi_disk_add_dev(
>
> /*
> * On partitions or whole disks without partitions install the
> -* simple file system protocol if a file system is available.
> +* simple file system protocol if a supported file system exists.
> */
> if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
> - efi_fs_exists(desc, part)) {
> + efi_supported_fs_exists(desc, part)) {
> diskobj->volume = efi_simple_file_system(desc, part,
> diskobj->dp);
> ret = efi_add_protocol(&diskobj->header,
>
--
Masami Hiramatsu
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
Hi Akashi-san,
2021年6月3日(木) 11:50 AKASHI Takahiro :
>
> On Thu, Jun 03, 2021 at 11:17:56AM +0900, Masami Hiramatsu wrote:
> > Because UEFI specification v2.9, 13.3 File System Format said "The
> > file system supported by the Extensible Firmware Interface is based
> > on the FAT file system.", the simple file system protocol might be
> > better to support only FAT filesystem.
>
> If I remember correctly, Heinrich rejected the idea a long time ago.
>
> When I posted the commit 867400677cda ("efi_loader: disk: install
> FILE_SYSTEM_PROTOCOL only if available"), he insisted that the UEFI
> specification does require FAT support but that it doesn't deny
> any support for other file systems.
> So I had to change the code, allowing FS_TYPE_ANY.
Thanks for the good information.
Indeed, the specification doesn't deny any other filesystems.
I think the problem is that the simple file system protocol doesn't
provide any filesystem format information.
EFI_FILE_PROTOCOL.GetInfo() will get the EFI_FILE_SYSTEM_INFO, but it
doesn't include the filesystem format information. Thus, UEFI
application can not know why it can write the file on this volume but
cannot on another volume.
Maybe we can set the ReadOnly field of EFI_FILE_SYSTEM_INFO correctly
if the filesystem doesn't support write operation, and make
EFI_FILE_PROTOCOL.Write() returns EFI_WRITE_PROTECTED. In that case it
may help UEFI application understands what happen.
Thank you,
>
> -Takahiro Akashi
>
> > There must be no problem from UEFI application to access only FAT
> > because ESP must be formatted by FAT32 and the removable media is
> > FAT12 or FAT16, according to the UEFI spec.
> >
> > Reported-by: Kazuhiko Sakamoto
> > Signed-off-by: Masami Hiramatsu
> > ---
> > lib/efi_loader/efi_disk.c | 18 --
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> > index 307d5d759b..f69ae6587f 100644
> > --- a/lib/efi_loader/efi_disk.c
> > +++ b/lib/efi_loader/efi_disk.c
> > @@ -318,19 +318,25 @@ efi_fs_from_path(struct efi_device_path *full_path)
> > }
> >
> > /**
> > - * efi_fs_exists() - check if a partition bears a file system
> > + * efi_supported_fs_exists() - check if a partition bears a supported file
> > system
> > *
> > * @desc:block device descriptor
> > * @part:partition number
> > - * Return: 1 if a file system exists on the partition
> > + * Return: 1 if a supported file system exists on the partition
> > * 0 otherwise
> > */
> > -static int efi_fs_exists(struct blk_desc *desc, int part)
> > +static int efi_supported_fs_exists(struct blk_desc *desc, int part)
> > {
> > if (fs_set_blk_dev_with_part(desc, part))
> > return 0;
> >
> > - if (fs_get_type() == FS_TYPE_ANY)
> > + /*
> > + * Because UEFI specification v2.9, 13.3 File System Format said
> > + * "The file system supported by the Extensible Firmware Interface
> > + * is based on the FAT file system.", the simple file system protocol
> > + * should support only FAT filesystem.
> > + */
> > + if (fs_get_type() != FS_TYPE_FAT)
> > return 0;
> >
> > fs_close();
> > @@ -428,10 +434,10 @@ static efi_status_t efi_disk_add_dev(
> >
> > /*
> >* On partitions or whole disks without partitions install the
> > - * simple file system protocol if a file system is available.
> > + * simple file system protocol if a supported file system exists.
> >*/
> > if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
> > - efi_fs_exists(desc, part)) {
> > + efi_supported_fs_exists(desc, part)) {
> > diskobj->volume = efi_simple_file_system(desc, part,
> >diskobj->dp);
> > ret = efi_add_protocol(&diskobj->header,
> >
--
Masami Hiramatsu
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
Hi Heinrich,
2021年6月3日(木) 13:08 Heinrich Schuchardt :
>
> Am 3. Juni 2021 04:17:56 MESZ schrieb Masami Hiramatsu
> :
> >Because UEFI specification v2.9, 13.3 File System Format said "The
> >file system supported by the Extensible Firmware Interface is based
> >on the FAT file system.", the simple file system protocol might be
> >better to support only FAT filesystem.
> >
> >There must be no problem from UEFI application to access only FAT
> >because ESP must be formatted by FAT32 and the removable media is
> >FAT12 or FAT16, according to the UEFI spec.
> >
>
> Does the UEFI spec forbid to access to other file systems?
No, it does not forbid.
>
> Which problems were observed?
My problem was observed by UEFI SCT (
https://github.com/tianocore/edk2-test/tree/master/uefi-sct ), which
reported errors while testing some volumes formatted by Ext4.
I can fix that with dropping Ext4 support from the U-Boot too. Or
maybe fixed by enabling Ext4 write support. But I thought that is not
a fundamental solution because there are other filesystems which
support read-only (e.g. Btrfs). And UEFI
configuration(CONFIG_EFI_LOADER) doesn't depend on write support.
Of course, the test program itself should check whether the filesystem
is FAT (because UEFI spec only specifies FAT full support, other
filesystems are out-of-spec), but there is no way to determine that
the volume is formatted by FAT (at least in the simple filesystem
protocol). This is reasonable, because UEFI spec expects only FAT.
Thus, I have some ideas except for this fix.
- Check the filesystem driver and only if it supports full operations
(read/write, mkdir etc.), makes it available from UEFI simple file
system protocol (this also checks CONFIG_*_WRITE).
- Set the volume read only if the filesystem driver doesn't support
write and return correct error code. This will give a consistent
filesystem model to the application. (maybe SCT needs to check volume
ReadOnly flag before test it.)
What would you think?
Thank you,
>
> Best regards
>
> Heinrich
>
>
> >Reported-by: Kazuhiko Sakamoto
> >Signed-off-by: Masami Hiramatsu
> >---
> > lib/efi_loader/efi_disk.c | 18 --
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> >diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> >index 307d5d759b..f69ae6587f 100644
> >--- a/lib/efi_loader/efi_disk.c
> >+++ b/lib/efi_loader/efi_disk.c
> >@@ -318,19 +318,25 @@ efi_fs_from_path(struct efi_device_path
> >*full_path)
> > }
> >
> > /**
> >- * efi_fs_exists() - check if a partition bears a file system
> >+ * efi_supported_fs_exists() - check if a partition bears a supported
> >file system
> > *
> > * @desc: block device descriptor
> > * @part: partition number
> >- * Return:1 if a file system exists on the partition
> >+ * Return:1 if a supported file system exists on the partition
> > *0 otherwise
> > */
> >-static int efi_fs_exists(struct blk_desc *desc, int part)
> >+static int efi_supported_fs_exists(struct blk_desc *desc, int part)
> > {
> > if (fs_set_blk_dev_with_part(desc, part))
> > return 0;
> >
> >- if (fs_get_type() == FS_TYPE_ANY)
> >+ /*
> >+ * Because UEFI specification v2.9, 13.3 File System Format said
> >+ * "The file system supported by the Extensible Firmware Interface
> >+ * is based on the FAT file system.", the simple file system protocol
> >+ * should support only FAT filesystem.
> >+ */
> >+ if (fs_get_type() != FS_TYPE_FAT)
> > return 0;
> >
> > fs_close();
> >@@ -428,10 +434,10 @@ static efi_status_t efi_disk_add_dev(
> >
> > /*
> >* On partitions or whole disks without partitions install the
> >- * simple file system protocol if a file system is available.
> >+ * simple file system protocol if a supported file system exists.
> >*/
> > if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
> >- efi_fs_exists(desc, part)) {
> >+ efi_supported_fs_exists(desc, part)) {
> > diskobj->volume = efi_simple_file_system(desc, part,
> >diskobj->dp);
> > ret = efi_add_protocol(&diskobj->header,
>
--
Masami Hiramatsu
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
Hi Heinrich, 2021年6月3日(木) 14:15 Heinrich Schuchardt : > > Am 3. Juni 2021 06:57:16 MESZ schrieb Masami Hiramatsu > : > >Hi Heinrich, > > > >2021年6月3日(木) 13:08 Heinrich Schuchardt : > >> > >> Am 3. Juni 2021 04:17:56 MESZ schrieb Masami Hiramatsu > >: > >> >Because UEFI specification v2.9, 13.3 File System Format said "The > >> >file system supported by the Extensible Firmware Interface is based > >> >on the FAT file system.", the simple file system protocol might be > >> >better to support only FAT filesystem. > >> > > >> >There must be no problem from UEFI application to access only FAT > >> >because ESP must be formatted by FAT32 and the removable media is > >> >FAT12 or FAT16, according to the UEFI spec. > >> > > >> > >> Does the UEFI spec forbid to access to other file systems? > > > >No, it does not forbid. > > > >> > >> Which problems were observed? > > > >My problem was observed by UEFI SCT ( > >https://github.com/tianocore/edk2-test/tree/master/uefi-sct ), which > >reported errors while testing some volumes formatted by Ext4. > > > >I can fix that with dropping Ext4 support from the U-Boot too. Or > >maybe fixed by enabling Ext4 write support. But I thought that is not > >a fundamental solution because there are other filesystems which > >support read-only (e.g. Btrfs). And UEFI > >configuration(CONFIG_EFI_LOADER) doesn't depend on write support. > > > >Of course, the test program itself should check whether the filesystem > >is FAT (because UEFI spec only specifies FAT full support, other > >filesystems are out-of-spec), but there is no way to determine that > >the volume is formatted by FAT (at least in the simple filesystem > >protocol). This is reasonable, because UEFI spec expects only FAT. > > > >Thus, I have some ideas except for this fix. > >- Check the filesystem driver and only if it supports full operations > >(read/write, mkdir etc.), makes it available from UEFI simple file > >system protocol (this also checks CONFIG_*_WRITE). > >- Set the volume read only if the filesystem driver doesn't support > >write and return correct error code. This will give a consistent > >filesystem model to the application. (maybe SCT needs to check volume > >ReadOnly flag before test it.) > > > >What would you think? > > > >Thank you, > > For running the SCT I use an image which has only a FAT partition. That depends on the device configuration. My platform (DeveloperBox) is something like PC, which has not only USB, but eMMC, SATA, NVMe. Of course I can just disable CONFIG_EXT4 from U-Boot for SCT, but I don't like erasing all the partitions on which I have installed debian... > > At least Debian and Ubuntu do not allow /boot to be on a FAT file system. If > we want to boot Linux via the EFI stub without GRUB, we need ext4 support > exposed to the EFI sub-system. See Ilias' recent contributions for the > EFI_LOAD_FILE2_PROTOCOL for initrd and efidebug. This came in handy for > booting via EFI on RISC-V where the initrd= command line parameter is not > supported by Linux. IMHO, such dependency is out of UEFI spec. That means Debian/Ubuntu doesn't follow the UEFI spec. (but as far as I know, those install ESP on the disk and install GRUB efi application for boot) And yes, EFI_LOAD_FILE2_PROTOCOL needs to load initrd from somewhere (I'm usually put it on the ESP). But, if the EFI_LOAD_FILE2_PROTOCOL *requires* to access ext4 partition, I think that is not supported by UEFI spec. Anyway, I agree that denying access to non-FAT partitions is too restricted. What about my other ideas? If the volume is set to ReadOnly, that is good for both of the SCT and the EFI_LOAD_FILE2_PROTOCOL. Thank you, > > Best regards > > Heinrich > > > > > > > >> > >> Best regards > >> > >> Heinrich > >> > >> > >> >Reported-by: Kazuhiko Sakamoto > >> >Signed-off-by: Masami Hiramatsu > >> >--- > >> > lib/efi_loader/efi_disk.c | 18 -- > >> > 1 file changed, 12 insertions(+), 6 deletions(-) > >> > > >> >diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c > >> >index 307d5d759b..f69ae6587f 100644 > >> >--- a/lib/efi_loader/efi_disk.c > >> >+++ b/lib/efi_loader/efi_disk.c > >> >@@ -318,19 +318,25 @@ efi_fs_from_path(struct efi_device_path > >> >*full_path) > >> > } > >> > > >> >
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
Hi Ilias, 2021年6月3日(木) 15:25 Ilias Apalodimas : > > [...] > > > > > > At least Debian and Ubuntu do not allow /boot to be on a FAT file system. > > > If we want to boot Linux via the EFI stub without GRUB, we need ext4 > > > support exposed to the EFI sub-system. See Ilias' recent contributions > > > for the EFI_LOAD_FILE2_PROTOCOL for initrd and efidebug. This came in > > > handy for booting via EFI on RISC-V where the initrd= command line > > > parameter is not supported by Linux. > > > > IMHO, such dependency is out of UEFI spec. That means Debian/Ubuntu > > doesn't follow the UEFI spec. (but as far as I know, those install ESP > > on the disk and install GRUB efi application for boot) > > And yes, EFI_LOAD_FILE2_PROTOCOL needs to load initrd from somewhere > > (I'm usually put it on the ESP). But, if the EFI_LOAD_FILE2_PROTOCOL > > *requires* to access ext4 partition, I think that is not supported by > > UEFI spec. > > One of the advantages in using EFI_LOAD_FILE2_PROTOCOL is that you can load > it from *any* file system the firmware has access to. The only thing the > kernel does is provide a buffer big enough to fit in the initrd. The > firmware is free to locate the file and copy it in that memory however it > sees fit. Ah, I got it. Yes, EFI_LOAD_FILE2_PROTOCOL doesn't depend on the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. Thus it should be able to load the file from where the U-Boot can access. However, since current implementation depends on the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, my patch limits the ability... Thank you, > > Cheers > /Ilias > > > > Anyway, I agree that denying access to non-FAT partitions is too > > restricted. What about my other ideas? If the volume is set to > > ReadOnly, that is good for both of the SCT and the > > EFI_LOAD_FILE2_PROTOCOL. > > > > > > Thank you, > > > > > > > > Best regards > > > > > > Heinrich > > > > > > -- Masami Hiramatsu
Re: [PATCH] efi: Restrict the simple file system protocol to support only FAT
Hi Heinrich, 2021年6月3日(木) 15:14 Heinrich Schuchardt : [..] > > If a volume or file is read only the UEFI spec requires to report this > in EFI_FILE_PROTOCOL.GetInfo(). Yes. > > On partition level we have the following deficiencies in U-Boot: > > * we cannot (re-)mount a partition read-only > * we cannot determine if a partition is read-only Hmm, but I think the filesystem driver itself defined it in fstype_info. Thus we can check it as below. fsinfo = fs_get_info(fs_get_type()); if (fsinfo->write == fs_write_unsupported) // then set the volume readonly BTW, it seems fsinfo->opendir and readdir are also required for EFI_FILE_PROTOCOL, unless it, UEFI application can not follow the directory tree. Hmm. > * we can neither read nor write the volume label > * we cannot determine the free space. > > The current implementation of the FAT driver does not support reading > attributes and dates. I have started looking into what is needed in the > FAT driver. > https://github.com/xypron/u-boot-patches/blob/bfe483ed97978678b124f8fe579682aab6e3e9d8/patch-efi-next.sh#L91 > But it is not ready for submission. Ah, that's great! I would like to test it. Thank you, -- Masami Hiramatsu
[PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hi, Here is the 5th version of the series (including some fixes for build errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. This series includes not only DeveloperBox support but also some fixes for the issues which I faced while porting U-Boot on the DeveloperBox. First 3 patches are fixes, next 1 patch is a code cleanup for generic gpio for arm. The next 7 patches adding DeveloperBox devices and board support. The last 2 patches are related to the UEFI capsule update. Previous version is here: https://lists.denx.de/pipermail/u-boot/2021-May/449305.html Changes in v5 - I dripped dfu_mtd bugfix patch (previous [12/14]) from this, because Sughosh already fixed it. [11/13]: - Remove log level from config. DeveloperBox DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots (1x slots are connected via PCIe bridge chip) * 4 USB-3.0 ports * 2 SATA ports * 1 GbE network port * 1 USB-UART serial port (micro USB) * 64MB SPI NOR Flash * 8GB eMMC Flash Storage * 96boards LS connector The DeveloperBox schematic can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf And the other documents can be found here: - https://www.96boards.org/documentation/enterprise/developerbox/ Currently, the U-Boot port supports: - * USB * eMMC * SPI-NOR * SATA * GbE The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as BL33, but no need to combine with it. Thank you, --- Jassi Brar (4): mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver spi: synquacer: Add HSSPI SPI controller driver for SynQuacer net: synquacer: Add netsec driver i2c: synquacer: SNI Synquacer I2C controller Masami Hiramatsu (9): ata: ahci-pci: Use scsi_ops to initialize ops dm: pci: Skip setting VGA bridge bits if parent device is the host bus efi: Fix to use null handle to create new handle for efi_fmp_raw gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs pci: synquacer: Add SynQuacer ECAM based PCIe driver ARM: dts: synquacer: Add device trees for DeveloperBox board: synquacer: Add DeveloperBox 96boards EE support doc: qemu: arm64: Fix the documentation of capsule update configs: synquacer: Enable EFI capsule update support arch/arm/Kconfig | 108 ++ arch/arm/dts/Makefile |2 arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 + .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 + arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 + arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++ arch/arm/include/asm/gpio.h|8 board/socionext/developerbox/Kconfig | 36 + board/socionext/developerbox/MAINTAINERS | 14 board/socionext/developerbox/Makefile |9 board/socionext/developerbox/developerbox.c| 146 +++ configs/synquacer_developerbox_defconfig | 129 ++ doc/board/emulation/qemu_capsule_update.rst| 11 doc/board/index.rst|1 doc/board/socionext/developerbox.rst | 87 ++ doc/board/socionext/index.rst |9 drivers/ata/ahci-pci.c |2 drivers/i2c/Kconfig|7 drivers/i2c/Makefile |1 drivers/i2c/synquacer_i2c.c| 338 ++ drivers/mmc/Kconfig| 10 drivers/mmc/Makefile |1 drivers/mmc/f_sdh30.c | 81 + drivers/net/Kconfig|8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 drivers/pci/Kconfig| 12 drivers/pci/Makefile |1 drivers/pci/pci-uclass.c |3 drivers/pci/pcie_ecam_synquacer.c | 600 +++ drivers/spi/Kconfig|8 drivers/spi/Makefile |1 drivers/spi/spi-synquacer.c| 491 + include/configs/synquacer.h| 115 ++ lib/efi_loader/efi_capsule.c |2 35 files changed, 4158 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
[PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/ata/ahci-pci.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f..b1d231e0f9 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops= &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
[PATCH v5 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [7800-7fff],
Physical Memory [7800-7fffx]
PCI Autoconfig: Bus I/O region: [0-],
Physical Memory [77f0-77f0x]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x100, address=0x7800
bus_lower=0x7900
PCI Autoconfig: BAR 1, Mem, size=0x800, No room in resource, avail
start=7900 / size=800, need=800
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x200, address=0x7a00
bus_lower=0x7c00
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x8, address=0x7c00 bus_lower=0x7c08
"Synchronous Abort" handler, esr 0x9606
elr: e002bd28 lr : e002bce8 (reloc)
elr: fff6fd28 lr : fff6fce8
x0 : 1041 x1 : 003e
x2 : ffb0f8c8 x3 : 0001
x4 : 0080 x5 :
x6 : fff718fc x7 : 000f
x8 : ffb0f238 x9 : 0008
x10: x11: 0010
x12: 0006 x13: 0001869f
x14: ffb0fcd0 x15: 0020
x16: fff71cc4 x17:
x18: ffb13d90 x19: ffb14320
x20: x21: ffb14090
x22: ffb0f8c8 x23: 0001
x24: ffb14c10 x25:
x26: x27:
x28: ffb14c70 x29: ffb0f830
Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu
Reviewed-by: Simon Glass
---
drivers/pci/pci-uclass.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e632..afe4f1974a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
[PATCH v5 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw
When running the efidebug capsule disk-update command, the efi_fmp_raw
protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
below. This is because the code passes efi_root instaed of handle.
=> efidebug capsule disk-update
EFI: Call: efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbaf5988)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbaf5988,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6ee8)
EFI: new handle fbb37520
EFI: Exit: efi_install_protocol_interface: 0
EFI: 0 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 0
EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle,
&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(fbfec648)
EFI: Call: efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(fbfec648,
86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6f18)
EFI: handle fbaf8520
EFI: Exit: efi_install_protocol_interface: 2
EFI: 2 returned by efi_install_protocol_interface( handle, protocol,
EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 2
EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root,
&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
Command failed, result=1
To fix this issue, pass the handle variable as same as the efi_fmp_fit
installation.
Signed-off-by: Masami Hiramatsu
---
lib/efi_loader/efi_capsule.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 9ead0d2c78..71d3d1e523 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -939,7 +939,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
handle = NULL;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &efi_root,
+ &handle,
&efi_guid_firmware_management_protocol,
&efi_fmp_raw, NULL));
}
[PATCH v5 04/13] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Change the config name to positive and selected by the opposite CONFIG_ARCH_*. (Build checked by Github CI) --- arch/arm/Kconfig| 94 +++ arch/arm/include/asm/gpio.h |8 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..023824df77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select D
[PATCH v5 05/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile |1 drivers/pci/pcie_ecam_synquacer.c | 600 + 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b2b7b253f8..782179eb0f 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c742bb2c94..6568dc9a08 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 00..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOPBIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REGBIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_10x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +
[PATCH v5 06/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
From: Jassi Brar
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
Reviewed-by: Jaehoon Chung
---
Changes in v4:
- Add Jaehoon's reviewed-by.
Changes in v3:
- Rename config name to MMC_SDHCI_F_SDH30.
- Remove unneeded wait in drivers/mmc/sdhci.c.
- Rename probe function to f_sdh30_sdhci_probe.
---
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile |1 +
drivers/mmc/f_sdh30.c | 81 +
3 files changed, 92 insertions(+)
create mode 100644 drivers/mmc/f_sdh30.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8901456967..1c5aecfa5c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -561,6 +561,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config MMC_SDHCI_F_SDH30
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db3..f5fd59093e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER)+= tmio-common.o
uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30)+= f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 00..3a85d9e348
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 2, 40);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops= &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
[PATCH v5 07/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
From: Jassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
drivers/spi/Kconfig |8 +
drivers/spi/Makefile|1
drivers/spi/spi-synquacer.c | 491 +++
3 files changed, 500 insertions(+)
create mode 100644 drivers/spi/spi-synquacer.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..62d9676550 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -481,4 +481,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..98c95323d1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 00..ce558c4bc0
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MCTRL 0x0
+#define MEN0
+#define CSEN 1
+#define IPCLK 3
+#define MES4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF0x14
+#define TXE0x18
+#define TXC0x1c
+#define RXF0x20
+#define RXE0x24
+#define RXC0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART0x38
+#define TRIGGER0
+#define DMSTOP 8
+#define CS_MASK3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX1
+#define DATA_TX2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
[PATCH v5 08/13] net: synquacer: Add netsec driver
From: Jassi Brar Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar --- drivers/net/Kconfig |8 drivers/net/Makefile |1 drivers/net/sni_netsec.c | 1134 ++ 3 files changed, 1143 insertions(+) create mode 100644 drivers/net/sni_netsec.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 382639044b..9fc28b149d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -673,6 +673,14 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config SNI_NETSEC + bool "Socionext NETSEC Ethernet support" + depends on DM_ETH && SYNQUACER_SPI + select PHYLIB + help + This driver implements support for the Socionext SynQuacer NETSEC + ethernet controller, as found on the Socionext SynQuacer family. + source "drivers/net/mscc_eswitch/Kconfig" config ETHER_ON_FEC1 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a44a7d3f56..d56baa65b2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-y += mscc_eswitch/ diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c new file mode 100644 index 00..a9ebf6af9c --- /dev/null +++ b/drivers/net/sni_netsec.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * netsec.c - Socionext Synquacer Netsec driver + * Copyright 2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NETSEC_REG_SOFT_RST0x104 +#define NETSEC_REG_COM_INIT0x120 + +#define NETSEC_REG_TOP_STATUS 0x200 +#define NETSEC_IRQ_RX BIT(1) +#define NETSEC_IRQ_TX BIT(0) + +#define NETSEC_REG_TOP_INTEN 0x204 +#define NETSEC_REG_INTEN_SET 0x234 +#define NETSEC_REG_INTEN_CLR 0x238 + +#define NETSEC_REG_NRM_TX_STATUS 0x400 +#define NETSEC_REG_NRM_TX_INTEN0x404 +#define NETSEC_REG_NRM_TX_INTEN_SET0x428 +#define NETSEC_REG_NRM_TX_INTEN_CLR0x42c +#define NRM_TX_ST_NTOWNR BIT(17) +#define NRM_TX_ST_TR_ERR BIT(16) +#define NRM_TX_ST_TXDONE BIT(15) +#define NRM_TX_ST_TMREXP BIT(14) + +#define NETSEC_REG_NRM_RX_STATUS 0x440 +#define NETSEC_REG_NRM_RX_INTEN0x444 +#define NETSEC_REG_NRM_RX_INTEN_SET0x468 +#define NETSEC_REG_NRM_RX_INTEN_CLR0x46c +#define NRM_RX_ST_RC_ERR BIT(16) +#define NRM_RX_ST_PKTCNT BIT(15) +#define NRM_RX_ST_TMREXP BIT(14) + +#define NETSEC_REG_PKT_CMD_BUF 0xd0 + +#define NETSEC_REG_CLK_EN 0x100 + +#define NETSEC_REG_PKT_CTRL0x140 + +#define NETSEC_REG_DMA_TMR_CTRL0x20c +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c +#define NETSEC_REG_F_TAIKI_VER 0x230 +#define NETSEC_REG_DMA_HM_CTRL 0x214 +#define NETSEC_REG_DMA_MH_CTRL 0x220 +#define NETSEC_REG_ADDR_DIS_CORE 0x218 +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c + +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 + +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT0x418 + +#define NETSEC_REG_NRM_TX_TMR 0x41c + +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 +#define NETSEC_REG_NRM_TX_TXINT_TMR0x420 +#define NETSEC_REG_NRM_RX_RXINT_TMR0x460 + +#define NETSEC_REG_NRM_RX_TMR 0x45c + +#define NETSEC_REG_NRM_TX_DESC_START_UP0x434 +#define NETSEC_REG_NRM_TX_DESC_START_LW0x408 +#define NETSEC_REG_NRM_RX_DESC_START_UP0x474 +#define NETSEC_REG_NRM_RX_DESC_START_LW0x448 + +#define NETSEC_REG_NRM_TX_CONFIG 0x430 +#define NETSEC_REG_NRM_RX_CONFIG 0x470 + +#define MAC_REG_STATUS 0x1024 +#define MAC_REG_DATA 0x11c0 +#define MAC_REG_CMD0x11c4 +#define MAC_REG_FLOW_TH0x11cc +#define MAC_REG_INTF_SEL 0x11d4 +#define M
[PATCH v5 09/13] i2c: synquacer: SNI Synquacer I2C controller
From: Jassi Brar Add driver for class of I2C controllers found on Socionext Synquacer platform. Signed-off-by: Jassi Brar --- drivers/i2c/Kconfig |7 + drivers/i2c/Makefile|1 drivers/i2c/synquacer_i2c.c | 338 +++ 3 files changed, 346 insertions(+) create mode 100644 drivers/i2c/synquacer_i2c.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 57a4efb88e..ce0d796d09 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -455,6 +455,13 @@ config SYS_I2C_STM32F7 _ Optional clock stretching _ Software reset +config SYS_I2C_SYNQUACER + bool "Socionext SynQuacer I2C controller" + depends on ARCH_SYNQUACER && DM_I2C + help + Support for Socionext Synquacer I2C controller. This I2C controller + will be used for RTC and LS-connector on DeveloperBox. + config SYS_I2C_TEGRA bool "NVIDIA Tegra internal I2C controller" depends on ARCH_TEGRA diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 8c9f1fcd8b..06a1150f03 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o +obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c new file mode 100644 index 00..6672d9435e --- /dev/null +++ b/drivers/i2c/synquacer_i2c.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_BSR0x0 +#define REG_BCR0x4 +#define REG_CCR0x8 +#define REG_ADR0xc +#define REG_DAR0x10 +#define REG_CSR0x14 +#define REG_FSR0x18 +#define REG_BC2R 0x1c + +/* I2C register bit definitions */ +#define BSR_FBTBIT(0) // First Byte Transfer +#define BSR_GCABIT(1) // General Call Address +#define BSR_AASBIT(2) // Address as Slave +#define BSR_TRXBIT(3) // Transfer/Receive +#define BSR_LRBBIT(4) // Last Received Bit +#define BSR_AL BIT(5) // Arbitration Lost +#define BSR_RSCBIT(6) // Repeated Start Cond. +#define BSR_BB BIT(7) // Bus Busy + +#define BCR_INTBIT(0) // Interrupt +#define BCR_INTE BIT(1) // Interrupt Enable +#define BCR_GCAA BIT(2) // Gen. Call Access Ack. +#define BCR_ACKBIT(3) // Acknowledge +#define BCR_MSSBIT(4) // Master Slave Select +#define BCR_SCCBIT(5) // Start Condition Cont. +#define BCR_BEIE BIT(6) // Bus Error Int Enable +#define BCR_BERBIT(7) // Bus Error + +#define CCR_CS_MASK(0x1f) // CCR Clock Period Sel. +#define CCR_EN BIT(5) // Enable +#define CCR_FM BIT(6) // Speed Mode Select + +#define CSR_CS_MASK(0x3f) // CSR Clock Period Sel. + +#define BC2R_SCLL BIT(0) // SCL Low Drive +#define BC2R_SDAL BIT(1) // SDA Low Drive +#define BC2R_SCLS BIT(4) // SCL Status +#define BC2R_SDAS BIT(5) // SDA Status + +/* PCLK frequency */ +#define BUS_CLK_FR(rate) (((rate) / 2000) + 1) + +#define I2C_CLK_DEF6250 + +/* STANDARD MODE frequency */ +#define CLK_MASTER_STD(rate) \ + DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2) +/* FAST MODE frequency */ +#define CLK_MASTER_FAST(rate) \ + DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3) + +/* (clkrate <= 1800) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MAX_18M(rate) \ + ((CLK_MASTER_STD(rate) - 65) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define CSR_CS_STD_MAX_18M(rate) 0x00 + +/* calculate the value of CS bits in CCR register on fast mode */ +#define CCR_CS_FAST_MAX_18M(rate) \ + ((CLK_MASTER_FAST(rate) - 1) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define CSR_CS_FAST_MAX_18M(rate) 0x00 + +/* (clkrate > 1800) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MIN_18M(rate) \ + ((CLK_MASTER_STD(rate) -
[PATCH v5 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu
---
Changes in v4:
- Add i2c0 and RTC node.
Changes in v3:
- Use generic nor flash instead of specific mx25u51245g.
(chip parameters will be searched by the register value)
Changes in v2:
- Add reference commit id of original EDK2 to the comment
- Just copy the EDK2 dts files as-is (change #include path)
- Split out the u-boot specific changes in -u-boot.dtsi.
- Removed unneeded spi-nor flash partition information.
---
arch/arm/dts/Makefile |2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +++
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++
arch/arm/dts/synquacer-sc2a11.dtsi | 595
5 files changed, 801 insertions(+)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..167dbbc056 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1103,6 +1103,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) +=
ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi
b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 00..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref {\
+i-cache-size = <0x8000>;\
+i-cache-line-size = <64>; \
+i-cache-sets = <256>; \
+d-cache-size = <0x8000>;\
+d-cache-line-size = <64>; \
+d-cache-sets = <128>; \
+l2-cache = ; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+cache-size = <0x4>; \
+cache-line-size = <64>; \
+cache-sets = <256>; \
+cache-unified; \
+next-level-cache = <&L3>; \
+};
+
+/ {
+__L2(0)
+__L2(1)
+__L2(2)
+__L2(3)
+__L2(4)
+__L2(5)
+__L2(6)
+__L2(7)
+__L2(8)
+__L2(9)
+__L2(10)
+__L2(11)
+
+L3: l3-cache {
+cache-level = <3>;
+cache-size = <0x40>;
+cache-line-size = <64>;
+cache-sets = <4096>;
+cache-unified;
+};
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 00..2f13a42235
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ i2c0 = &i2c0;
+ };
+
+ spi_nor: spi@5480 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x5480 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+
[PATCH v5 11/13] board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- Changes in v5: - Remove log level from config. Changes in v4: - Add I2C and RTC configuration. - Enable RTC and Date command. - Remove I2C0 node before booting linux to hide it same as EDK2 does. - Add some configurations to make it EBBR compliant. Changes in v3: - Enable CONFIG_MMC_SDHCI_F_SDH30. - Enable CONFIG_CMD_GENERIC (fstype command) for distro boot. - Remove unneeded CONFIG_ONLY_GENERIC_GPIO. Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig| 14 +++ board/socionext/developerbox/Kconfig| 36 +++ board/socionext/developerbox/MAINTAINERS| 14 +++ board/socionext/developerbox/Makefile |9 ++ board/socionext/developerbox/developerbox.c | 146 +++ configs/synquacer_developerbox_defconfig| 112 + doc/board/index.rst |1 doc/board/socionext/developerbox.rst| 87 doc/board/socionext/index.rst |9 ++ include/configs/synquacer.h | 109 10 files changed, 537 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 023824df77..7ff24535cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1760,6 +1760,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2102,6 +2115,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 00..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help +Choose this option if you build the U-Boot for the DeveloperBox +96boards Enterprise Edition. +This board will booted from SCP firmware and it enables SMMU, thus +the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 00..aa672b6e05
[PATCH v5 12/13] doc: qemu: arm64: Fix the documentation of capsule update
Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 33ce4bcd32..0a2286d039 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - -$ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ -e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. +$ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The
[PATCH v5 13/13] configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- Changes in v4: - Add some config options for EBBR. Changes in v3: - Fix a typo in dfu_alt_info. --- configs/synquacer_developerbox_defconfig | 17 + include/configs/synquacer.h |6 ++ 2 files changed, 23 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index cbc09d3225..d42db9a1d6 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -110,3 +110,20 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y +CONFIG_EFI_CAPSULE_FIRMWARE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FMP_HEADER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 0dab4de1f1..8fe10d7485 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -61,6 +61,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ + "mtd nor1=u-boot.bin raw 20 10;"\ + "fip.bin raw 18 78000;" \ + "optee.bin raw 50 10\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -104,6 +109,7 @@ "ramdisk_addr_r=0xa000\0" \ "scriptaddr=0x8800\0" \ "pxefile_addr_r=0x8810\0" \ + DEFAULT_DFU_ALT_INFO\ BOOTENV #endif /* __CONFIG_H */
Re: [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
Hello, Would anyone have any comments on this series? Thank you, 2021年6月4日(金) 18:43 Masami Hiramatsu : > > Hi, > > Here is the 5th version of the series (including some fixes for build > errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot. > > This series includes not only DeveloperBox support but also some fixes > for the issues which I faced while porting U-Boot on the DeveloperBox. > First 3 patches are fixes, next 1 patch is a code cleanup for generic > gpio for arm. The next 7 patches adding DeveloperBox devices > and board support. The last 2 patches are related to the UEFI capsule > update. > > Previous version is here: > > https://lists.denx.de/pipermail/u-boot/2021-May/449305.html > > > Changes in v5 > - > > I dripped dfu_mtd bugfix patch (previous [12/14]) from this, > because Sughosh already fixed it. > > [11/13]: > - Remove log level from config. > > > DeveloperBox > > > DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC > has: - > * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor > motherboard > * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) > * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots > (1x slots are connected via PCIe bridge chip) > * 4 USB-3.0 ports > * 2 SATA ports > * 1 GbE network port > * 1 USB-UART serial port (micro USB) > * 64MB SPI NOR Flash > * 8GB eMMC Flash Storage > * 96boards LS connector > > The DeveloperBox schematic can be found here: - > https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf > > And the other documents can be found here: - > https://www.96boards.org/documentation/enterprise/developerbox/ > > > Currently, the U-Boot port supports: - > * USB > * eMMC > * SPI-NOR > * SATA > * GbE > > The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. > The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as > BL33, but no need to combine with it. > > > Thank you, > > --- > > Jassi Brar (4): > mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver > spi: synquacer: Add HSSPI SPI controller driver for SynQuacer > net: synquacer: Add netsec driver > i2c: synquacer: SNI Synquacer I2C controller > > Masami Hiramatsu (9): > ata: ahci-pci: Use scsi_ops to initialize ops > dm: pci: Skip setting VGA bridge bits if parent device is the host bus > efi: Fix to use null handle to create new handle for efi_fmp_raw > gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs > pci: synquacer: Add SynQuacer ECAM based PCIe driver > ARM: dts: synquacer: Add device trees for DeveloperBox > board: synquacer: Add DeveloperBox 96boards EE support > doc: qemu: arm64: Fix the documentation of capsule update > configs: synquacer: Enable EFI capsule update support > > > arch/arm/Kconfig | 108 ++ > arch/arm/dts/Makefile |2 > arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 + > .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 + > arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 + > arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++ > arch/arm/include/asm/gpio.h|8 > board/socionext/developerbox/Kconfig | 36 + > board/socionext/developerbox/MAINTAINERS | 14 > board/socionext/developerbox/Makefile |9 > board/socionext/developerbox/developerbox.c| 146 +++ > configs/synquacer_developerbox_defconfig | 129 ++ > doc/board/emulation/qemu_capsule_update.rst| 11 > doc/board/index.rst|1 > doc/board/socionext/developerbox.rst | 87 ++ > doc/board/socionext/index.rst |9 > drivers/ata/ahci-pci.c |2 > drivers/i2c/Kconfig|7 > drivers/i2c/Makefile |1 > drivers/i2c/synquacer_i2c.c| 338 ++ > drivers/mmc/Kconfig| 10 > drivers/mmc/Makefile |1 > drivers/mmc/f_sdh30.c | 81 + > drivers/net/Kconfig|8 > drivers/net/Makefile |1 > drivers/net/sni_netsec.c | 1134 > > drivers/pci/Kconfig| 12 > drivers/pci/Makefile
Re: [PATCH] efi_loader: FMP cleanups
2021年6月15日(火) 0:10 Ilias Apalodimas :
>
> Right now we allow both of the FMPs (RAW and FIT based) to be installed at
> the same time. Moreover we only install those if a CapsuleUpdate is
> requested. Since we now have an ESRT table, it makes more sense to
> unconditionally install the FMP, so any userspace applications (e.g fwupd)
> can make use of them and trigger an update.
>
> While at it clean up the FMP installation as well. Chapter 23 of the EFI
> spec (rev 2.9) says:
> "A specific updatable hardware firmware store must be represented by
> exactly one FMP instance".
> This is not the case for us, since both of our FMP protocols can be
> installed at the same time and are controlled by a single 'dfu_alt_info'
> env variable.
> So make the config option a choice and allow the user to install one
> of them at any given time.
>
> The overall changes show up in fwupd
>
> pre-patch:
> fwupdmgr get-devices
> No detected devices
>
> post-patch (with FIT FMP installed):
> fwupdmgr get-devices
> WARNING: Required efivarfs filesystem was not found
> See https://github.com/fwupd/fwupd/wiki/PluginFlag:efivar-not-mounted for
> more information.
> Unknown Product
> │
> └─Unknown Firmware:
> Device ID: 605080e08f71dabb86d0781c28f7d923edabf7d6
> Current version:0
> Vendor: DMI:U-Boot
> Update Error: Not updatable as efivarfs was not found
> GUIDs: ae13ff2d-9ad4-4e25-9ac8-6d80b3b22147
> 230c8b18-8d9b-53ec-838b-6cfc0383493a ←
> main-system-firmware
> 1a1da7d4-0a24-51b5-8a1a-1e3274328094 ←
> UEFI\RES_{AE13FF2D-9AD4-4E25-9AC8-6D80B3B22147}
> Device Flags: • Internal device
> • System requires external power source
> • Needs a reboot after installation
> • Device is usable for the duration of the update
>
This looks good to me, and this covers one patch which I sent before.
https://lists.denx.de/pipermail/u-boot/2021-June/451401.html
Reviewed-by: Masami Hiramatsu
Thank you!
> Signed-off-by: Ilias Apalodimas
> ---
> configs/sandbox64_defconfig | 1 -
> configs/sandbox_defconfig| 1 -
> configs/xilinx_zynqmp_virt_defconfig | 1 -
> include/efi_loader.h | 1 +
> lib/efi_loader/Kconfig | 48 +++-
> lib/efi_loader/efi_capsule.c | 22 -
> lib/efi_loader/efi_setup.c | 4 +++
> 7 files changed, 37 insertions(+), 41 deletions(-)
>
> diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
> index 9a373bab6fe3..af18b6c7826e 100644
> --- a/configs/sandbox64_defconfig
> +++ b/configs/sandbox64_defconfig
> @@ -233,7 +233,6 @@ CONFIG_LZ4=y
> CONFIG_ERRNO_STR=y
> CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
> CONFIG_EFI_CAPSULE_ON_DISK=y
> -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
> CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
> CONFIG_EFI_SECURE_BOOT=y
> CONFIG_TEST_FDTDEC=y
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index bdbf714e2bd9..24313fdfa53d 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -280,7 +280,6 @@ CONFIG_LZ4=y
> CONFIG_ERRNO_STR=y
> CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
> CONFIG_EFI_CAPSULE_ON_DISK=y
> -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
> CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
> CONFIG_EFI_SECURE_BOOT=y
> CONFIG_TEST_FDTDEC=y
> diff --git a/configs/xilinx_zynqmp_virt_defconfig
> b/configs/xilinx_zynqmp_virt_defconfig
> index e939b04ef6a5..0c2d1a70a5a1 100644
> --- a/configs/xilinx_zynqmp_virt_defconfig
> +++ b/configs/xilinx_zynqmp_virt_defconfig
> @@ -188,5 +188,4 @@ CONFIG_EFI_SET_TIME=y
> CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
> CONFIG_EFI_CAPSULE_ON_DISK=y
> CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
> -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
> CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 0a9c82a257e1..b81180cfda8b 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -972,4 +972,5 @@ efi_status_t efi_esrt_register(void);
> * - error code otherwise.
> */
> efi_status_t efi_esrt_populate(void);
> +efi_status_t efi_load_capsule_drivers(void);
> #endif /* _EFI_LOADER_H */
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index 6242caceb7f9..da6f5faf5adb 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -161,6 +161,31 @@ config EFI_CAPSULE_FIRMWARE_MANAGEMENT
> Select this option if you want to enable capsule-based
> firmware update using Firmware Managemen
Re: [PATCH 2/3 v2] efi_loader: Force a sinlge FMP instance per hardware store
Hi Ilias,
2021年6月18日(金) 19:51 Ilias Apalodimas :
>
> Chapter 23 of the EFI spec (rev 2.9) says:
> "A specific updatable hardware firmware store must be represented by
> exactly one FMP instance".
> This is not the case for us, since both of our FMP protocols can be
> installed at the same time because they are controlled by a single
> 'dfu_alt_info' env variable.
> So make the config options depend on each other and allow the user to
> install one of them at any given time. If we fix the meta-data provided
> by the 'dfu_alt_info' in the future, to hint about the capsule type
> (fit or raw) we can revise this and enable both FMPs to be installed, as
> long as they target different firmware hardware stores
>
> Note that we are not using a Kconfig 'choice' on purpose, since we
> want to allow both of those to be installed and tested in sandbox
This sounds like changing the Kconfig, thus...
[...]
> --- a/lib/efi_loader/efi_capsule.c
> +++ b/lib/efi_loader/efi_capsule.c
> @@ -918,15 +918,15 @@ static void efi_capsule_scan_done(void)
> }
>
> /**
> - * arch_efi_load_capsule_drivers - initialize capsule drivers
> + * efi_load_capsule_drivers - initialize capsule drivers
> *
> - * Architecture or board specific initialization routine
> + * Generic FMP drivers backed by DFU
> *
> * Return: status code
> */
> -efi_status_t __weak arch_efi_load_capsule_drivers(void)
> +efi_status_t __weak efi_load_capsule_drivers(void)
> {
> - __maybe_unused efi_handle_t handle;
> + __maybe_unused efi_handle_t handle = NULL;
> efi_status_t ret = EFI_SUCCESS;
>
> if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) {
> @@ -975,10 +975,6 @@ efi_status_t efi_launch_capsules(void)
>
> index = get_last_capsule();
>
> - /* Load capsule drivers */
> - ret = arch_efi_load_capsule_drivers();
> - if (ret != EFI_SUCCESS)
> - return ret;
I think this part of the change should be included in the next patch.
Thank you,
>
> /*
> * Find capsules on disk.
> --
> 2.32.0.rc0
>
--
Masami Hiramatsu
Re: [PATCH 1/3 v2] efi: Fix to use null handle to create new handle for efi_fmp_raw
Hi,
2021年6月19日(土) 4:22 Heinrich Schuchardt :
>
> Am 18. Juni 2021 12:51:12 MESZ schrieb Ilias Apalodimas
> :
> >From: Masami Hiramatsu
> >
> >When running the efidebug capsule disk-update command, the efi_fmp_raw
> >protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
> >below. This is because the code passes efi_root instaed of handle.
>
> instead
Oops, it's my typo.
>
> Is the problem that two protocols with the same GUID are installed on the
> same handle?
Actually, the returned handle is ignored in both cases. That "handle"
is the local variable, and the handle is set to NULL before installing
FMP in both cases.
>
>
> >
> >=> efidebug capsule disk-update
> >EFI: Call: efi_install_multiple_protocol_interfaces( &handle,
> >&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
> > EFI: Entry efi_install_multiple_protocol_interfaces(fbaf5988)
> >EFI: Call: efi_install_protocol_interface( handle, protocol,
> >EFI_NATIVE_INTERFACE, protocol_interface)
> >EFI: Entry efi_install_protocol_interface(fbaf5988,
> >86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6ee8)
> >EFI: new handle fbb37520
> > EFI: Exit: efi_install_protocol_interface: 0
> >EFI: 0 returned by efi_install_protocol_interface( handle, protocol,
> >EFI_NATIVE_INTERFACE, protocol_interface)
> > EFI: Exit: efi_install_multiple_protocol_interfaces: 0
> >EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle,
> >&efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
> >EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root,
> >&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
> > EFI: Entry efi_install_multiple_protocol_interfaces(fbfec648)
> >EFI: Call: efi_install_protocol_interface( handle, protocol,
> >EFI_NATIVE_INTERFACE, protocol_interface)
> >EFI: Entry efi_install_protocol_interface(fbfec648,
> >86c77a67-0b97-4633-a187-49104d0685c7, 0, fbfa6f18)
> >EFI: handle fbaf8520
> > EFI: Exit: efi_install_protocol_interface: 2
> >EFI: 2 returned by efi_install_protocol_interface( handle, protocol,
> >EFI_NATIVE_INTERFACE, protocol_interface)
> > EFI: Exit: efi_install_multiple_protocol_interfaces: 2
> >EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root,
> >&efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
> >Command failed, result=1
> >
> >To fix this issue, pass the handle variable as same as the efi_fmp_fit
> >installation.
>
>
> You can not install twice protocols with the same GUID one one handle
> What do you mean by same variable?
Ah, yes. The description might not be correct. The handle is
initialized right before installing a new protocol with the same GUID
(previous one is discarded at that point).
>
> >
> >Signed-off-by: Masami Hiramatsu
> >Signed-off-by: Ilias Apalodimas
> >---
> >v1 is at https://lists.denx.de/pipermail/u-boot/2021-June/452097.html
> >changes since v1:
> >- split patches
> >- pick up Masami's patch fixing the efi_root issue
> >- Don't use 'choice' on Kconfig sicne we need both of the FMPs
> >installed for sandbox testing
> > instead just make them mutually exclusive with 'depends on'
>
> I can't see ''depends on" in this patch.
Aha, I think that comment is for the 2nd patch in the series.
Thank you,
>
> Best regards
>
> Heinrich
>
>
> >- Only install the FMPs if CONFIG_EFI_HAVE_CAPSULE_SUPPORT is selected
> > lib/efi_loader/efi_capsule.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/lib/efi_loader/efi_capsule.c
> >b/lib/efi_loader/efi_capsule.c
> >index 9ead0d2c7816..71d3d1e523ce 100644
> >--- a/lib/efi_loader/efi_capsule.c
> >+++ b/lib/efi_loader/efi_capsule.c
> >@@ -939,7 +939,7 @@ efi_status_t __weak
> >arch_efi_load_capsule_drivers(void)
> > if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
> > handle = NULL;
> > ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
> >- &efi_root,
> >+ &handle,
> > &efi_guid_firmware_management_protocol,
> > &efi_fmp_raw, NULL));
> > }
>
--
Masami Hiramatsu
Re: [PATCH 2/3 v3] efi_loader: Force a sinlge FMP instance per hardware store
Hi, 2021年6月22日(火) 23:39 Ilias Apalodimas : > > Chapter 23 of the EFI spec (rev 2.9) says: > "A specific updatable hardware firmware store must be represented by > exactly one FMP instance". > This is not the case for us, since both of our FMP protocols can be > installed at the same time because they are controlled by a single > 'dfu_alt_info' env variable. > So make the config options depend on each other and allow the user to > install one of them at any given time. If we fix the meta-data provided > by the 'dfu_alt_info' in the future, to hint about the capsule type > (fit or raw) we can revise this and enable both FMPs to be installed, as > long as they target different firmware hardware stores > > Note that we are not using a Kconfig 'choice' on purpose, since we > want to allow both of those to be installed and tested in sandbox > > Signed-off-by: Ilias Apalodimas This looks good to me. Reviewed-by: Masami Hiramatsu > --- > Changes since v2: > - BTW, you might need to describe the change (fix to move the FMP installation part to the next patch, etc.). But I think this is a minor issue. Thank you, > Changes since v1: > - Don't use 'choice' on Kconfig sicne we need both of the FMPs installed for > sandbox testing > instead just make them mutually exclusive with 'depends on' > > configs/xilinx_zynqmp_virt_defconfig | 1 - > lib/efi_loader/Kconfig | 45 ++-- > 2 files changed, 22 insertions(+), 24 deletions(-) > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index 6adbe987cb7f..4d34e6c4cba5 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -187,5 +187,4 @@ CONFIG_OF_LIBFDT_OVERLAY=y > CONFIG_EFI_SET_TIME=y > CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y > CONFIG_EFI_CAPSULE_ON_DISK=y > -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y > CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > index 6242caceb7f9..684adfb62379 100644 > --- a/lib/efi_loader/Kconfig > +++ b/lib/efi_loader/Kconfig > @@ -161,6 +161,28 @@ config EFI_CAPSULE_FIRMWARE_MANAGEMENT > Select this option if you want to enable capsule-based > firmware update using Firmware Management Protocol. > > +config EFI_CAPSULE_FIRMWARE_FIT > + bool "FMP driver for FIT images" > + depends on FIT > + depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT > + select UPDATE_FIT > + select DFU > + select EFI_CAPSULE_FIRMWARE > + help > + Select this option if you want to enable firmware management > protocol > + driver for FIT image > + > +config EFI_CAPSULE_FIRMWARE_RAW > + bool "FMP driver for raw images" > + depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT > + depends on SANDBOX || (!SANDBOX && !EFI_CAPSULE_FIRMWARE_FIT) > + select DFU_WRITE_ALT > + select DFU > + select EFI_CAPSULE_FIRMWARE > + help > + Select this option if you want to enable firmware management > protocol > + driver for raw image > + > config EFI_CAPSULE_AUTHENTICATE > bool "Update Capsule authentication" > depends on EFI_CAPSULE_FIRMWARE > @@ -181,29 +203,6 @@ config EFI_CAPSULE_AUTHENTICATE > Select this option if you want to enable capsule > authentication > > -config EFI_CAPSULE_FIRMWARE_FIT > - bool "FMP driver for FIT image" > - depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT > - depends on FIT > - select UPDATE_FIT > - select DFU > - select EFI_CAPSULE_FIRMWARE > - default n > - help > - Select this option if you want to enable firmware management > protocol > - driver for FIT image > - > -config EFI_CAPSULE_FIRMWARE_RAW > - bool "FMP driver for raw image" > - depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT > - select DFU > - select DFU_WRITE_ALT > - select EFI_CAPSULE_FIRMWARE > - default n > - help > - Select this option if you want to enable firmware management > protocol > - driver for raw image > - > config EFI_DEVICE_PATH_TO_TEXT > bool "Device path to text protocol" > default y > -- > 2.32.0.rc0 > -- Masami Hiramatsu
