[U-Boot] [PATCH] sunxi: Add H6 SPI SPL support
Add H6 SPI addresses and masks
(since H6 memory map is totally different).
Tested on Pine H64 rev B with Winbond W25Q128FW,
Signed-off-by: Marek Kraus
---
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c | 123
configs/pine_h64_defconfig | 1 +
3 files changed, 98 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 74e234cded..81b5948454 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -972,7 +972,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 043d9f6ead..cdf6d53ec5 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -28,7 +28,7 @@
* A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
* Both of them are supported.
*
- * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
+ * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64/H6 are
* supported at the moment.
*/
@@ -70,6 +70,25 @@
#define SUN6I_TCR_XCH BIT(31)
/*/
+/* SUN50I_H6 variant of the SPI controller */
+/*/
+
+#define SUN50I_H6_SPI0_CCTL (0x0501 + 0x24)
+#define SUN50I_H6_SPI0_GCR (0x0501 + 0x04)
+#define SUN50I_H6_SPI0_TCR (0x0501 + 0x08)
+#define SUN50I_H6_SPI0_FIFO_STA (0x0501 + 0x1C)
+#define SUN50I_H6_SPI0_MBC (0x0501 + 0x30)
+#define SUN50I_H6_SPI0_MTC (0x0501 + 0x34)
+#define SUN50I_H6_SPI0_BCC (0x0501 + 0x38)
+#define SUN50I_H6_SPI0_TXD (0x0501 + 0x200)
+#define SUN50I_H6_SPI0_RXD (0x0501 + 0x300)
+
+#define SUN50I_H6_SPI_GATING_REG(0x03001000 + 0x96C)
+#define SUN50I_H6_SPI0_RST BIT(16)
+#define SUN50I_H6_SPI0_GATING_CLK BIT(0)
+#define SUN50I_H6_CCU_SPI0_CLK (0x03001000 + 0x940)
+
+/*/
#define CCM_AHB_GATING0 (0x01C2 + 0x60)
#define CCM_SPI0_CLK(0x01C2 + 0xA0)
@@ -85,19 +104,29 @@
/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
- * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
+ * from SPI Flash, H6 using PC0,PC2,PC3,PC5 , everything else is using
+ * pins PC0,PC1,PC2,PC3.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
unsigned int pin;
- for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
- sunxi_gpio_set_cfgpin(pin, pin_function);
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
- sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
- else
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
+ } else {
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
+ sunxi_gpio_set_cfgpin(pin, pin_function);
+
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) ||
+ IS_ENABLED(CONFIG_MACH_SUN7I))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
+ else
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
+ }
}
/*
@@ -106,26 +135,43 @@ static void spi0_pinmux_setup(unsigned int pin_function)
static void spi0_enable_clock(void)
{
/* Deassert SPI0 reset on SUN6I */
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ setbits_le32(SUN50I_H6_SPI_GATING_REG,
+SUN50I_H6_SPI0_RST);
+ else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
/* Open the SPI0 gate */
- setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ setbits_le32(SUN50I_H6_SPI_GATING_REG,
+
[U-Boot] [PATCH v2] sunxi: Add H6 SPI SPL support
Add H6 SPI addresses and masks
(since H6 memory map is totally different).
Tested on Pine H64 rev B with Winbond W25Q128FW,
Signed-off-by: Marek Kraus
Cc: Jagan Teki
---
Changes for v2:
- Macros for sun6i offsets, when different base address
---
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c | 154 +---
configs/pine_h64_defconfig | 1 +
3 files changed, 109 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 74e234cded..81b5948454 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -972,7 +972,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 043d9f6ead..b4c082340e 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -28,7 +28,7 @@
* A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
* Both of them are supported.
*
- * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
+ * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64/H6 are
* supported at the moment.
*/
@@ -54,15 +54,16 @@
/* SUN6I variant of the SPI controller */
/*/
-#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
-#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
-#define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
-#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
-#define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
-#define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
-#define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
-#define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
-#define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
+#define SUN6I_SPI0 0x01C68000
+#define SUN6I_SPI_CCTL 0x24
+#define SUN6I_SPI_GCR 0x04
+#define SUN6I_SPI_TCR 0x08
+#define SUN6I_SPI_FIFO_STA 0x1C
+#define SUN6I_SPI_MBC 0x30
+#define SUN6I_SPI_MTC 0x34
+#define SUN6I_SPI_BCC 0x38
+#define SUN6I_SPI_TXD 0x200
+#define SUN6I_SPI_RXD 0x300
#define SUN6I_CTL_ENABLEBIT(0)
#define SUN6I_CTL_MASTERBIT(1)
@@ -70,6 +71,17 @@
#define SUN6I_TCR_XCH BIT(31)
/*/
+/* SUN50I_H6 variant of the SPI controller */
+/*/
+
+#define SUN50I_H6_SPI0 0x0501
+
+#define SUN50I_H6_SPI_GATING_REG(0x03001000 + 0x96C)
+#define SUN50I_H6_SPI0_RST BIT(16)
+#define SUN50I_H6_SPI0_GATING_CLK BIT(0)
+#define SUN50I_H6_CCU_SPI0_CLK (0x03001000 + 0x940)
+
+/*/
#define CCM_AHB_GATING0 (0x01C2 + 0x60)
#define CCM_SPI0_CLK(0x01C2 + 0xA0)
@@ -85,19 +97,28 @@
/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
- * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
+ * from SPI Flash, H6 using PC0,PC2,PC3,PC5 , everything else is using
+ * pins PC0,PC1,PC2,PC3.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
unsigned int pin;
- for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
- sunxi_gpio_set_cfgpin(pin, pin_function);
-
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
- sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
- else
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
+ } else {
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
+ sunxi_gpio_set_cfgpin(pin, pin_function);
+
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) ||
+ IS_ENABLED(CONFIG_MACH_SUN7I))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
+
