Re: [PATCH 1/2] ram: ast2600: Keep MPLL power on

[Joel Stanley]

On Tue, 21 Feb 2023 at 13:01, Dylan Hung  wrote:
>
> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
>
> Signed-off-by: Dylan Hung 

Reviewed-by: Joel Stanley 

> ---
>  drivers/ram/aspeed/sdram_ast2600.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/ram/aspeed/sdram_ast2600.c 
> b/drivers/ram/aspeed/sdram_ast2600.c
> index 18767554123f..d463933363ee 100644
> --- a/drivers/ram/aspeed/sdram_ast2600.c
> +++ b/drivers/ram/aspeed/sdram_ast2600.c
> @@ -1089,13 +1089,13 @@ static int ast2600_sdrammc_probe(struct udevice *dev)
> }
>
> reg = readl(&priv->scu->mpll);
> -   reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK |
> +   reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK |
>  SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK);
> -   reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG);
> +   reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG);
> writel(reg, &priv->scu->mpll);
> writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext);
> udelay(100);
> -   reg &= ~(SCU_PLL_RST | SCU_PLL_OFF);
> +   reg &= ~SCU_PLL_RST;
> writel(reg, &priv->scu->mpll);
>
> while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0)
> --
> 2.25.1
>

Re: [PATCH 2/2] clk: ast2600: Keep PLL power on

[Joel Stanley]

On Tue, 21 Feb 2023 at 13:01, Dylan Hung  wrote:
>
> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
>
> Signed-off-by: Dylan Hung 

Reviewed-by: Joel Stanley 

> ---
>  drivers/clk/aspeed/clk_ast2600.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/clk/aspeed/clk_ast2600.c 
> b/drivers/clk/aspeed/clk_ast2600.c
> index 0df1dc3718d3..e5ada5b6d49c 100644
> --- a/drivers/clk/aspeed/clk_ast2600.c
> +++ b/drivers/clk/aspeed/clk_ast2600.c
> @@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu 
> *scu,
> }
>
> p_cfg->reg.b.bypass = 0;
> -   p_cfg->reg.b.off = 1;
> +   p_cfg->reg.b.off = 0;
> p_cfg->reg.b.reset = 1;
>
> reg = readl(addr);
> @@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu 
> *scu,
> /* write extend parameter */
> writel(p_cfg->ext_reg, addr_ext);
> udelay(100);
> -   p_cfg->reg.b.off = 0;
> p_cfg->reg.b.reset = 0;
> reg &= ~GENMASK(25, 0);
> reg |= p_cfg->reg.w;
> --
> 2.25.1
>

Re: [PATCH v5 0/6] tpm: Support boot measurements

[Joel Stanley]

On Thu, 2 Feb 2023 at 17:08, Eddie James  wrote:
>
> This series adds support for measuring the boot images more generically
> than the existing EFI support. Several EFI functions have been moved to
> the TPM layer. The series includes optional measurement from the bootm
> command.
> A new test case has been added for the bootm measurement to test the new
> path, and the sandbox TPM2 driver has been updated to support this use
> case.
> This series is based on Ilias' auto-startup series:
> https://lore.kernel.org/u-boot/20230126081844.591148-1-ilias.apalodi...@linaro.org/

Nice work Eddie. It looks like you're closing in on the issues Ilias
and Simon have.

I did some testing and found some missing dependencies from running
'make check':

sandbox_spl: +make O=/home/joel/dev/u-boot/upstream/build-sandbox_spl
-s sandbox_spl_defconfig
+make O=/home/joel/dev/u-boot/upstream/build-sandbox_spl -s -j8
/usr/bin/ld: warning: test/overlay/test-fdt-overlay-stacked.dtb.o:
missing .note.GNU-stack section implies executable stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in
a future version of the linker
/usr/bin/ld: /tmp/cc8cNroX.ltrans22.ltrans.o:(.data.rel+0x440):
undefined reference to `do_ut_measurement'
collect2: error: ld returned 1 exit status
make[2]: *** [/home/joel/dev/u-boot/upstream/Makefile:1752: u-boot] Error 1

There's a few variants of the sandbox defconfig. I'm not sure if we
want to exclude the measurement code from those configs, or add it to
the configs.

When fixing them up to add CONFIG_MEASURED_BOOT=y we still fail to link:

sandbox_spl: +make O=/home/joel/dev/u-boot/upstream/build-sandbox_spl
-s sandbox_spl_defconfig
+make O=/home/joel/dev/u-boot/upstream/build-sandbox_spl -s -j8
/usr/bin/ld: warning: test/overlay/test-fdt-overlay-stacked.dtb.o:
missing .note.GNU-stack section implies executable stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in
a future version of the linker
/usr/bin/ld: /tmp/ccRuOSFi.ltrans17.ltrans.o: in function `tcg2_create_digest':
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:112:
undefined reference to `sha512_starts'
/usr/bin/ld: 
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:113:
undefined reference to `sha512_update'
/usr/bin/ld: 
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:114:
undefined reference to `sha512_finish'
/usr/bin/ld: 
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:106:
undefined reference to `sha384_starts'
/usr/bin/ld: 
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:107:
undefined reference to `sha384_update'
/usr/bin/ld: 
/home/joel/dev/u-boot/upstream/build-sandbox_spl/../lib/tpm-v2.c:108:
undefined reference to `sha384_finish'
collect2: error: ld returned 1 exit status

This sorted that out for me:

--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -411,6 +411,8 @@ config TPM
bool "Trusted Platform Module (TPM) Support"
depends on DM
imply DM_RNG
+   select SHA512
+   select SHA384

The tree I tested with is here:
https://github.com/shenki/u-boot/commits/measured-boot

Cheers,

Joel

>
> Changes since v4:
>  - Remove tcg2_measure_event function and check for NULL data in
>tcg2_measure_data
>  - Use tpm_auto_startup
>  - Fix efi_tcg2.c compilation for removing tcg2_pcr_read function
>  - Change PCR indexes for initrd and dtb
>  - Drop u8 casting in measurement test
>  - Use bullets in documentation
>
> Changes since v3:
>  - Reordered headers
>  - Refactored more of EFI code into common code
> Removed digest_info structure and instead used the common alg_to_mask
>   and alg_to_len
> Improved event log parsing in common code to get it equivalent to EFI
>   Common code now extends PCR if previous bootloader stage couldn't
>   No need to allocate memory in the common code, so EFI copies the
>   discovered buffer like it did before
> Rename efi measure_event function
>
> Changes since v2:
>  - Add documentation.
>  - Changed reserved memory address to the top of the RAM for sandbox dts.
>  - Add measure state to booti and bootz.
>  - Skip measurement for EFI images that should be measured
>
> Changes since v1:
>  - Refactor TPM layer functions to allow EFI system to use them, and
>remove duplicate EFI functions.
>  - Add test case
>  - Drop #ifdefs for bootm
>  - Add devicetree measurement config option
>  - Update sandbox TPM driver
>
> Eddie James (6):
>   tpm: Fix spelling for tpmu_ha union
>   tpm: Support boot measurements
>   bootm: Support boot measurement
>   tpm: sandbox: Update for needed TPM2 capabilities
>   test: Add sandbox TPM boot measurement
>   doc: Add measured boot documentation
>
>  arch/sandbox/dts/sandbox.dtsi  |   14 +
>  arch/sandbox/dts/test.dts  |   13 +
>  boot/Kconfig   |   23 +
>  boot/bootm.c   |   70 +++
>  cmd/booti.c|1 +
>  cmd/bootm.c|2 +

Re: [PATCH v4 0/4] net: Enable NC-SI support

[Joel Stanley]

On Tue, 23 Aug 2022 at 04:54, Joel Stanley  wrote:
>
> On Mon, 8 Aug 2022 at 12:16, Joel Stanley  wrote:
> >
> > Back in 2019 Sam submitted NC-SI support. The NC-SI PHY driver was
> > merged (patches 1 and 2), but we never got around to merging patches 3
> > and 4:
> >
> >  https://lore.kernel.org/u-boot/20190618013720.2823-1-...@mendozajonas.com/
> >
> > Sam as long since moved on from working on the Aspeed BMCs, but the code
> > has been in use in the vendor fork for some time.
> >
> > This refreshes his patches and enables support in the Aspeed defconfigs,
> > giving compile coverage to the NC-SI phy.
> >
> > v4 splits the ncsi integration and cmd code into separate patches, and
> > adds r-b from Ramon and Cédric to patches 3 and 4.
>
> We have review on these patches now. Can we get them merged?

ping

>
> >
> > Joel Stanley (1):
> >   config/aspeed: Enable NC-SI support
> >
> > Samuel Mendoza-Jonas (3):
> >   net: NC-SI setup and handling
> >   cmd: Add ncsi command
> >   net/ftgmac100: Add NC-SI mode support
> >
> >  include/net.h |  2 +-
> >  include/phy.h |  2 ++
> >  cmd/net.c | 22 ++
> >  drivers/net/ftgmac100.c   | 14 ++
> >  drivers/net/phy/ncsi.c|  1 +
> >  drivers/net/phy/phy.c |  9 -
> >  net/net.c | 27 ++-
> >  cmd/Kconfig   |  8 
> >  configs/evb-ast2500_defconfig |  2 ++
> >  configs/evb-ast2600_defconfig |  2 ++
> >  10 files changed, 82 insertions(+), 7 deletions(-)
> >
> > --
> > 2.35.1
> >

Re: [PATCH] liteeth: LiteX Ethernet device

[Joel Stanley]

On Sun, 18 Sept 2022 at 15:50, Sean Anderson  wrote:
>
> On 8/10/22 00:29, Joel Stanley wrote:
> > LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
> > network device that is commonly used in LiteX designs.

> > +static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp)
> > +{
> > + struct liteeth *priv = dev_get_priv(dev);
> > + u8 rx_slot;
> > + int len;
> > +
> > + if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
> > + debug("liteeth: No packet ready\n");
> > + return -EPERM;
>
> Shouldn't this be -EAGAIN?

Your suggestion makes more sense. I think I copied another driver with
these return codes, perhaps ftgmac100.

I'll respin with EAGAIN and EMSGSIZE.

Cheers,

Joel

bootelf unable to boot

[Joel Stanley]

Hello Simon,

In 78398652723b ("bootm: Tidy up use of autostart env var") you
rationalised the checking of autoboot in the bootelf command handling.
This changed the bootelf default behaviour from "autostart by default"
to "autostart only when autostart=on".

The issue is with boards that have a flow where they dhcp or tftp an
image and then load it with bootelf. If they set autostart=on, the
dhcp command will try to use the bootm flow to load the elf, which
fails. If they set autostart=off, there's no way to reach
do_bootelf_exec.

There seems to be two use cases for bootelf in the tree: an
ELF-loading version of bootm (x86/sebios testing, and a way to load an
arbitrary ELF into memory for another processor to run (Zynq). I was
using it for the former, for a powerpc platform.

The following change would restore the existing behaviour, and fix my use case:

diff --git a/cmd/elf.c b/cmd/elf.c
index 2b33c50bd026..d3beb818e53f 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -68,7 +68,7 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
else
addr = load_elf_image_shdr(addr);

-   if (!env_get_autostart())
+   if (env_get_no("autostart") == 1)
return rcode;

printf("## Starting application at 0x%08lx ...\n", addr);
diff --git a/env/common.c b/env/common.c
index f9226e0690d0..7d6e4386e08d 100644
--- a/env/common.c
+++ b/env/common.c
@@ -235,6 +235,16 @@ int env_get_yesno(const char *var)
1 : 0;
 }

+int env_get_no(const char *var)
+{
+   char *s = env_get(var);
+
+   if (s == NULL)
+   return -1;
+   return (*s == '0' || *s == 'n' || *s == 'N' || *s == 'f' || *s == 'F') ?
+   1 : 0;
+}
+

Do you have any alternative suggestions?

Cheers,

Joel

[PATCH v2] liteeth: LiteX Ethernet device

[Joel Stanley]

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.

Signed-off-by: Joel Stanley 
Reviewed-by: Ramon Fried 
---
v2:
 Fixed some return values
 Add asm/byteorder.h to fix building
v1:
 https://lore.kernel.org/r/20220810042954.153280-1-j...@jms.id.au
---
 include/linux/litex.h |  84 +
 drivers/net/liteeth.c | 214 ++
 drivers/net/Kconfig   |   5 +
 drivers/net/Makefile  |   1 +
 4 files changed, 304 insertions(+)
 create mode 100644 include/linux/litex.h
 create mode 100644 drivers/net/liteeth.c

diff --git a/include/linux/litex.h b/include/linux/litex.h
new file mode 100644
index ..5e91db41fdcb
--- /dev/null
+++ b/include/linux/litex.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Common LiteX header providing
+ * helper functions for accessing CSRs.
+ *
+ * Copyright (C) 2019-2020 Antmicro 
+ */
+
+#ifndef _LINUX_LITEX_H
+#define _LINUX_LITEX_H
+
+#include 
+#include 
+
+static inline void _write_litex_subregister(u32 val, void __iomem *addr)
+{
+   writel((u32 __force)cpu_to_le32(val), addr);
+}
+
+static inline u32 _read_litex_subregister(void __iomem *addr)
+{
+   return le32_to_cpu((__le32 __force)readl(addr));
+}
+
+/*
+ * LiteX SoC Generator, depending on the configuration, can split a single
+ * logical CSR (Control&Status Register) into a series of consecutive physical
+ * registers.
+ *
+ * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
+ * 32-bit wide logical CSR will be laid out as four 32-bit physical
+ * subregisters, each one containing one byte of meaningful data.
+ *
+ * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
+ * means that only larger-than-32-bit CSRs will be split across multiple
+ * subregisters (e.g., a 64-bit CSR will be spread across two consecutive
+ * 32-bit subregisters).
+ *
+ * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
+ */
+
+static inline void litex_write8(void __iomem *reg, u8 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write16(void __iomem *reg, u16 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write32(void __iomem *reg, u32 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write64(void __iomem *reg, u64 val)
+{
+   _write_litex_subregister(val >> 32, reg);
+   _write_litex_subregister(val, reg + 4);
+}
+
+static inline u8 litex_read8(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u16 litex_read16(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u32 litex_read32(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u64 litex_read64(void __iomem *reg)
+{
+   return ((u64)_read_litex_subregister(reg) << 32) |
+   _read_litex_subregister(reg + 4);
+}
+
+#endif /* _LINUX_LITEX_H */
diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c
new file mode 100644
index ..84d3852723e2
--- /dev/null
+++ b/drivers/net/liteeth.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LiteX Liteeth Ethernet
+ *
+ * Copyright 2021 Joel Stanley , IBM Corp.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#define LITEETH_WRITER_SLOT   0x00
+#define LITEETH_WRITER_LENGTH 0x04
+#define LITEETH_WRITER_ERRORS 0x08
+#define LITEETH_WRITER_EV_STATUS  0x0C
+#define LITEETH_WRITER_EV_PENDING 0x10
+#define LITEETH_WRITER_EV_ENABLE  0x14
+#define LITEETH_READER_START  0x18
+#define LITEETH_READER_READY  0x1C
+#define LITEETH_READER_LEVEL  0x20
+#define LITEETH_READER_SLOT   0x24
+#define LITEETH_READER_LENGTH 0x28
+#define LITEETH_READER_EV_STATUS  0x2C
+#define LITEETH_READER_EV_PENDING 0x30
+#define LITEETH_READER_EV_ENABLE  0x34
+#define LITEETH_PREAMBLE_CRC  0x38
+#define LITEETH_PREAMBLE_ERRORS   0x3C
+#define LITEETH_CRC_ERRORS0x40
+
+struct liteeth {
+   struct udevice *dev;
+
+   void __iomem *base;
+   u32 slot_size;
+
+   /* Tx */
+   u32 tx_slot;
+   u32 num_tx_slots;
+   void __iomem *tx_base;
+
+   /* Rx */
+   u32 rx_slot;
+   u32 num_rx_slots;
+   void __iomem *rx_base;
+};
+
+static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct liteeth *priv = dev_get_priv(dev);
+   u8 rx_slot;
+   int len;
+
+   if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
+   debug("liteeth: No packet ready\n");
+   return -EAGAIN;
+   }
+
+   rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
+   len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
+
+   debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len);
+
+   *packetp = priv->rx_base +

[PATCH] liteeth: LiteX Ethernet device

[Joel Stanley]

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.

Signed-off-by: Joel Stanley 
---
 include/linux/litex.h |  83 
 drivers/net/liteeth.c | 214 ++
 drivers/net/Kconfig   |   5 +
 drivers/net/Makefile  |   1 +
 4 files changed, 303 insertions(+)
 create mode 100644 include/linux/litex.h
 create mode 100644 drivers/net/liteeth.c

diff --git a/include/linux/litex.h b/include/linux/litex.h
new file mode 100644
index ..f2edb86d5f44
--- /dev/null
+++ b/include/linux/litex.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Common LiteX header providing
+ * helper functions for accessing CSRs.
+ *
+ * Copyright (C) 2019-2020 Antmicro 
+ */
+
+#ifndef _LINUX_LITEX_H
+#define _LINUX_LITEX_H
+
+#include 
+
+static inline void _write_litex_subregister(u32 val, void __iomem *addr)
+{
+   writel((u32 __force)cpu_to_le32(val), addr);
+}
+
+static inline u32 _read_litex_subregister(void __iomem *addr)
+{
+   return le32_to_cpu((__le32 __force)readl(addr));
+}
+
+/*
+ * LiteX SoC Generator, depending on the configuration, can split a single
+ * logical CSR (Control&Status Register) into a series of consecutive physical
+ * registers.
+ *
+ * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
+ * 32-bit wide logical CSR will be laid out as four 32-bit physical
+ * subregisters, each one containing one byte of meaningful data.
+ *
+ * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
+ * means that only larger-than-32-bit CSRs will be split across multiple
+ * subregisters (e.g., a 64-bit CSR will be spread across two consecutive
+ * 32-bit subregisters).
+ *
+ * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
+ */
+
+static inline void litex_write8(void __iomem *reg, u8 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write16(void __iomem *reg, u16 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write32(void __iomem *reg, u32 val)
+{
+   _write_litex_subregister(val, reg);
+}
+
+static inline void litex_write64(void __iomem *reg, u64 val)
+{
+   _write_litex_subregister(val >> 32, reg);
+   _write_litex_subregister(val, reg + 4);
+}
+
+static inline u8 litex_read8(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u16 litex_read16(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u32 litex_read32(void __iomem *reg)
+{
+   return _read_litex_subregister(reg);
+}
+
+static inline u64 litex_read64(void __iomem *reg)
+{
+   return ((u64)_read_litex_subregister(reg) << 32) |
+   _read_litex_subregister(reg + 4);
+}
+
+#endif /* _LINUX_LITEX_H */
diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c
new file mode 100644
index ..5da713a9c7a1
--- /dev/null
+++ b/drivers/net/liteeth.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LiteX Liteeth Ethernet
+ *
+ * Copyright 2021 Joel Stanley , IBM Corp.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#define LITEETH_WRITER_SLOT   0x00
+#define LITEETH_WRITER_LENGTH 0x04
+#define LITEETH_WRITER_ERRORS 0x08
+#define LITEETH_WRITER_EV_STATUS  0x0C
+#define LITEETH_WRITER_EV_PENDING 0x10
+#define LITEETH_WRITER_EV_ENABLE  0x14
+#define LITEETH_READER_START  0x18
+#define LITEETH_READER_READY  0x1C
+#define LITEETH_READER_LEVEL  0x20
+#define LITEETH_READER_SLOT   0x24
+#define LITEETH_READER_LENGTH 0x28
+#define LITEETH_READER_EV_STATUS  0x2C
+#define LITEETH_READER_EV_PENDING 0x30
+#define LITEETH_READER_EV_ENABLE  0x34
+#define LITEETH_PREAMBLE_CRC  0x38
+#define LITEETH_PREAMBLE_ERRORS   0x3C
+#define LITEETH_CRC_ERRORS0x40
+
+struct liteeth {
+   struct udevice *dev;
+
+   void __iomem *base;
+   u32 slot_size;
+
+   /* Tx */
+   u32 tx_slot;
+   u32 num_tx_slots;
+   void __iomem *tx_base;
+
+   /* Rx */
+   u32 rx_slot;
+   u32 num_rx_slots;
+   void __iomem *rx_base;
+};
+
+static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct liteeth *priv = dev_get_priv(dev);
+   u8 rx_slot;
+   int len;
+
+   if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
+   debug("liteeth: No packet ready\n");
+   return -EPERM;
+   }
+
+   rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
+   len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
+
+   debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len);
+
+   *packetp = priv->rx_base + rx_slot * priv->slot_size;
+
+   return len;
+}
+
+static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+   struct liteeth *priv = d

Re: [PATCH v4 0/4] net: Enable NC-SI support

[Joel Stanley]

On Mon, 8 Aug 2022 at 12:16, Joel Stanley  wrote:
>
> Back in 2019 Sam submitted NC-SI support. The NC-SI PHY driver was
> merged (patches 1 and 2), but we never got around to merging patches 3
> and 4:
>
>  https://lore.kernel.org/u-boot/20190618013720.2823-1-...@mendozajonas.com/
>
> Sam as long since moved on from working on the Aspeed BMCs, but the code
> has been in use in the vendor fork for some time.
>
> This refreshes his patches and enables support in the Aspeed defconfigs,
> giving compile coverage to the NC-SI phy.
>
> v4 splits the ncsi integration and cmd code into separate patches, and
> adds r-b from Ramon and Cédric to patches 3 and 4.

We have review on these patches now. Can we get them merged?

>
> Joel Stanley (1):
>   config/aspeed: Enable NC-SI support
>
> Samuel Mendoza-Jonas (3):
>   net: NC-SI setup and handling
>   cmd: Add ncsi command
>   net/ftgmac100: Add NC-SI mode support
>
>  include/net.h |  2 +-
>  include/phy.h |  2 ++
>  cmd/net.c | 22 ++
>  drivers/net/ftgmac100.c   | 14 ++
>  drivers/net/phy/ncsi.c|  1 +
>  drivers/net/phy/phy.c |  9 -
>  net/net.c | 27 ++-
>  cmd/Kconfig   |  8 
>  configs/evb-ast2500_defconfig |  2 ++
>  configs/evb-ast2600_defconfig |  2 ++
>  10 files changed, 82 insertions(+), 7 deletions(-)
>
> --
> 2.35.1
>

[PATCH] lib/rsa: Sanity check db_len

[Joel Stanley]

When building with GCC 12:

../tools/../lib/rsa/rsa-verify.c:275:11: warning: ‘*db’ may be used 
uninitialized [-Wmaybe-uninitialized]
  275 | db[0] &= 0xff >> leftmost_bits;
  | ~~^~~

If msg_len or hash_len were nonsense values, db_len would end up invalid
and the rest of the function wil not work, so detect this case and
return early. If this was host code we could assert, but as this is
target code print an error and return.

Fixes: 061daa0b61f0 ("rsa: add support of padding pss")
Signed-off-by: Joel Stanley 
---
 lib/rsa/rsa-verify.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 1d95cfbdee0c..a7c87e40afa2 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -234,6 +234,11 @@ int padding_pss_verify(struct image_sign_info *info,
uint8_t leftmost_mask;
struct checksum_algo *checksum = info->checksum;
 
+   if (db_len <= 0) {
+   printf("%s: invalid db length\n", __func__);
+   return -EINVAL;
+   }
+
/* first, allocate everything */
db_mask = malloc(db_len);
db = malloc(db_len);
-- 
2.35.1

[PATCH] image: Ensure image header name is null terminated

[Joel Stanley]

When building with GCC 12:

../include/image.h:779:9: warning: ‘strncpy’ specified bound 32 equals 
destination size [-Wstringop-truncation]
  779 | strncpy(image_get_name(hdr), name, IH_NMLEN);
  | ^~~~

Ensure the copied string is null terminated by always setting the final
byte to 0. Shorten the strncpy to IH_NMLEN-1 as we will always overwrite
the last byte.

We can't use strlcpy as this is code is built on the host as well as the
target.

Fixes: b97a2a0a21f2 ("[new uImage] Define a API for image handling operations")
Signed-off-by: Joel Stanley 
---
 include/image.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/image.h b/include/image.h
index e4c6a50b885f..665b2278b7fb 100644
--- a/include/image.h
+++ b/include/image.h
@@ -776,7 +776,10 @@ image_set_hdr_b(comp)  /* image_set_comp */
 
 static inline void image_set_name(image_header_t *hdr, const char *name)
 {
-   strncpy(image_get_name(hdr), name, IH_NMLEN);
+   char *hdr_name = image_get_name(hdr);
+
+   strncpy(hdr_name, name, IH_NMLEN - 1);
+   hdr_name[IH_NMLEN - 1] = '\0';
 }
 
 int image_check_hcrc(const image_header_t *hdr);
-- 
2.35.1

[PATCH] gitlab-ci: Update comment about the Dockerfile

[Joel Stanley]

It's found in the u-boot tree now.

Signed-off-by: Joel Stanley 
---
 .gitlab-ci.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 5592862f74b8..cebd76d050b6 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-# Grab our configured image.  The source for this is found at:
-# https://source.denx.de/u-boot/gitlab-ci-runner
+# Grab our configured image.  The source for this is found
+# in the u-boot tree at tools/docker/Dockerfile
 image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022
 
 # We run some tests in different order, to catch some failures quicker.
-- 
2.35.1

Re: [RFC PATCH 8/8] WIP: .azure-pipelines.yml: Remove evb-ast2600

[Joel Stanley]

On Mon, 29 Aug 2022 at 06:23, Stefan Roese  wrote:
>
> The evb-ast2600 target always runs into an timeout error when run via
> Azure CI. For test purpose only, this patch removes this CI build
> target so that the world build can be run.
>
> Joel, Chia-Wei, could you perhaps take a look at this and help to fix
> the problems that I'm seeing with this build target here?

Where does it hang? Can you attach the logs?

What kind of debugging have you tried to date?

Cheers,

Joel

>
> Signed-off-by: Stefan Roese 
> Cc: Joel Stanley 
> Cc: Chia-Wei Wang 
> ---
>  .azure-pipelines.yml | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
> index 0fa92479b4c4..e48f1667f8de 100644
> --- a/.azure-pipelines.yml
> +++ b/.azure-pipelines.yml
> @@ -261,9 +261,6 @@ stages:
>  evb_ast2500:
>TEST_PY_BD: "evb-ast2500"
>TEST_PY_ID: "--id qemu"
> -evb_ast2600:
> -  TEST_PY_BD: "evb-ast2600"
> -  TEST_PY_ID: "--id qemu"
>  vexpress_ca9x4:
>TEST_PY_BD: "vexpress_ca9x4"
>TEST_PY_ID: "--id qemu"
> --
> 2.37.2
>

Re: [RFC PATCH 8/8] WIP: .azure-pipelines.yml: Remove evb-ast2600

[Joel Stanley]

On Fri, 2 Sept 2022 at 04:09, Joel Stanley  wrote:
>
> On Mon, 29 Aug 2022 at 06:23, Stefan Roese  wrote:
> >
> > The evb-ast2600 target always runs into an timeout error when run via
> > Azure CI. For test purpose only, this patch removes this CI build
> > target so that the world build can be run.
> >
> > Joel, Chia-Wei, could you perhaps take a look at this and help to fix
> > the problems that I'm seeing with this build target here?
>
> Where does it hang? Can you attach the logs?

The hang appears to be in the timer code, where the spl hangs due to a
div by zero. When inspecting, gd->arch.timer_rate_hz is zero at this
point.

However I also noticed the cycling code introduces a symbol that ends
up in BSS. If I give cyclic_running a non-zero value it moves back
into the data section, and the SPL and u-boot proper make it all the
way through.

This suggests there's still something wrong with the BSS handling for
the 2600 SPL (not resolved by f6810b749f2e ("aspeed/ast2600: Fix SPL
linker script") or the follow up fix). If I use the common arm spl
linker script, the system boots.

Chai Wei, I think we need a different solution for placing the BSS
outside of the flash.

Cheers,

Joel

>
> What kind of debugging have you tried to date?
>
> Cheers,
>
> Joel
>
> >
> > Signed-off-by: Stefan Roese 
> > Cc: Joel Stanley 
> > Cc: Chia-Wei Wang 
> > ---
> >  .azure-pipelines.yml | 3 ---
> >  1 file changed, 3 deletions(-)
> >
> > diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
> > index 0fa92479b4c4..e48f1667f8de 100644
> > --- a/.azure-pipelines.yml
> > +++ b/.azure-pipelines.yml
> > @@ -261,9 +261,6 @@ stages:
> >  evb_ast2500:
> >TEST_PY_BD: "evb-ast2500"
> >TEST_PY_ID: "--id qemu"
> > -evb_ast2600:
> > -  TEST_PY_BD: "evb-ast2600"
> > -  TEST_PY_ID: "--id qemu"
> >  vexpress_ca9x4:
> >TEST_PY_BD: "vexpress_ca9x4"
> >TEST_PY_ID: "--id qemu"
> > --
> > 2.37.2
> >

Re: [PATCH 0/3] Improvements to FIT hashing

[Joel Stanley]

Helli Simon,

On Wed, 17 Feb 2021 at 03:20, Joel Stanley  wrote:
>
> Here are some small changes to the FIT hashing code in order to use
> more code from common/, which in turns allows hw implementations of SHA.
>
> This was motivated by a need to reduce the SPL size for the Aspeed
> platforms by using the hardware engine. I have a driver for the Aspeed
> SoC that I will submit.

Do you have any thoughts on this series?

Cheers,

Joel

>
> Joel Stanley (3):
>   hw_sha: Fix coding style errors
>   fit: Use hash.c to call SHA code
>   hash: Allow for SHA512 hardware implementations
>
>  common/hash.c  | 24 ++--
>  common/image-fit.c | 34 --
>  include/hw_sha.h   | 38 --
>  lib/Kconfig| 15 +++
>  4 files changed, 69 insertions(+), 42 deletions(-)
>
> --
> 2.30.0
>

Re: [PATCH 2/3] fit: Use hash.c to call SHA code

[Joel Stanley]

On Wed, 17 Feb 2021 at 05:04, AKASHI Takahiro
 wrote:
>
> Simon,
>
> # This is not a direct comment on this patch.
>
> On Wed, Feb 17, 2021 at 01:50:41PM +1030, Joel Stanley wrote:
> > Currently the FIT hashing will call directly into the SHA algorithms to
> > get a hash.
> >
> > This moves the fit code to use hash_lookup_algo, giving a common
> > entrypoint into the hashing code and removing the duplicated algorithm
> > look up. It also allows the use of hardware acceleration if configured.
> >
> > Signed-off-by: Joel Stanley 
> > ---
> >  common/image-fit.c | 34 --
> >  1 file changed, 8 insertions(+), 26 deletions(-)
> >
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 28b3d2b19111..3451cdecc95b 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -1210,37 +1210,19 @@ int fit_set_timestamp(void *fit, int noffset, 
> > time_t timestamp)
> >   * 0, on success
> >   *-1, when algo is unsupported
> >   */
> > -int calculate_hash(const void *data, int data_len, const char *algo,
> > +int calculate_hash(const void *data, int data_len, const char *algo_name,
> >   uint8_t *value, int *value_len)
> >  {
> > - if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
> > - *((uint32_t *)value) = crc32_wd(0, data, data_len,
> > - CHUNKSZ_CRC32);
> > - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
> > - *value_len = 4;
> > - } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
> > - sha1_csum_wd((unsigned char *)data, data_len,
> > -  (unsigned char *)value, CHUNKSZ_SHA1);
> > - *value_len = 20;
> > - } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
> > - sha256_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA256);
> > - *value_len = SHA256_SUM_LEN;
> > - } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
> > - sha384_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA384);
> > - *value_len = SHA384_SUM_LEN;
> > - } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
> > - sha512_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA512);
> > - *value_len = SHA512_SUM_LEN;
> > - } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
> > - md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
> > - *value_len = 16;
> > - } else {
> > + struct hash_algo *algo;
> > +
> > + if (hash_lookup_algo(algo_name, &algo)) {
> >   debug("Unsupported hash alogrithm\n");
> >   return -1;
> >   }
> > +
> > + algo->hash_func_ws(data, data_len, value, algo->chunk_size);
> > + *value_len = algo->digest_size;
>
> With this patch applied, there co-exists a very similar, hence
> confusing function, hash_calculate(), in rsa-checksum.c (now checksum.c?).
> If there is no particular reason for those two functions,
> we'd better unify them?

hash_calculate is doing a progressive hash over a count of regions.
This code is hashing a single chunk of data.

I agree the naming could be improved to make this clearer.

Cheers,

Joel


>
> -Takahiro Akashi
>
>
> >   return 0;
> >  }
> >
> > --
> > 2.30.0
> >

Re: [PATCH] hash: Kconfig option for SHA512 hardware acceleration

[Joel Stanley]

On Fri, 14 May 2021 at 09:12, Heinrich Schuchardt  wrote:
>
> Commit a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
> defined function definitions for hardware accelerated SHA384 and SHA512.
> If CONFIG_SHA_HW_ACCEL=y, these functions are used.
>
> We already have boards using CONFIG_SHA_HW_ACCEL=y but none implements the
> new functions hw_sha384() and hw_sha512().
>
> For implementing the EFI TCG2 protocol we need SHA384 and SHA512. The
> missing hardware acceleration functions lead to build errors on boards like
> peach-pi_defconfig.
>
> Introduce a new Kconfig symbol CONFIG_SHA512_HW_ACCEL to control if the
> functions hw_sha384() and hw_sha512() shall be used to implement the SHA384
> and SHA512 algorithms.
>
> Fixes: a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
> Signed-off-by: Heinrich Schuchardt 
> ---
> This patch replaces
> hash: revert Allow for SHA512 hardware implementations
> https://lists.denx.de/pipermail/u-boot/2021-May/449648.html
> https://patchwork.ozlabs.org/project/uboot/patch/20210512170040.137058-1-xypron.g...@gmx.de/

This looks to be a good compromise. Thanks for fixing it.

Reviewed-by: Joel Stanley 

The CONFIG maze that is the hash acceleration code could do with some
overarching cleanup at some point.


> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -389,21 +389,32 @@ config SHA384
>   (digest).
>
>  config SHA_HW_ACCEL
> -   bool "Enable hashing using hardware"
> +   bool "Enable hardware acceleration for SHA hash functions"
> help
> - This option enables hardware acceleration for SHA hashing.
> - This affects the 'hash' command and also the hash_lookup_algo()
> - function.
> + This option enables hardware acceleration for the SHA1 and SHA256
> + hashing algorithms. This affects the 'hash' command and also the
> + hash_lookup_algo() function.
> +
> +if SHA_HW_ACCEL
> +
> +config SHA512_HW_ACCEL
> +   bool "Enable hardware acceleration for SHA512"
> +   depends on SHA512_ALGO

This dependency is new, does it make sense? We don't have an
equivalent one for SHA_HW_ACCEL, but perhaps we should introduce one?

> +   help
> + This option enables hardware acceleration for the SHA384 andSHA512

Nit: there's a missing space after "and" here.

Perhaps you could add to the help text that this option should be
disabled if the platform requires SHA512 support but does not have
hardware acceleration.

> + hashing algorithms. This affects the 'hash' command and also the
> + hash_lookup_algo() function.
>
>  config SHA_PROG_HW_ACCEL
> bool "Enable Progressive hashing support using hardware"
> -   depends on SHA_HW_ACCEL
> help
>   This option enables hardware-acceleration for SHA progressive
>   hashing.
>   Data can be streamed in a block at a time and the hashing is
>   performed in hardware.
>
> +endif
> +
>  config MD5
> bool "Support MD5 algorithm"
> help
> --
> 2.30.2
>

[PATCH] crypto: Add driver for Aspeed HACE

[Joel Stanley]

The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
uses it in a polling mode to perform hash calculations over buffers
placed in DRAM.

It registers a driver to allow the hardware's clocking to be enabled
using the clock framework.

Co-developed-by: Klaus Heinrich Kiwi 
Signed-off-by: Klaus Heinrich Kiwi 
Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig |   1 +
 drivers/crypto/Kconfig|  19 +++
 drivers/crypto/Makefile   |   1 +
 drivers/crypto/aspeed_hace.c  | 256 ++
 4 files changed, 277 insertions(+)
 create mode 100644 drivers/crypto/aspeed_hace.c

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 91518dbe3589..52ae8e423bfd 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -45,6 +45,7 @@ CONFIG_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
+CONFIG_ASPEED_HACE=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_SPL_MISC=y
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 1ea116be7503..e92037d88906 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -2,4 +2,23 @@ menu "Hardware crypto devices"
 
 source drivers/crypto/fsl/Kconfig
 
+config ASPEED_HACE
+   bool "ASPEED Hash and Crypto Engine"
+   depends on ASPEED_AST2600
+   imply SHA_HW_ACCEL
+   imply SHA_PROG_HW_ACCEL
+   imply SHA512
+   imply SHA512_ALGO
+   imply CMD_HASH
+   help
+Select this option to enable a driver for using the SHA engine in
+the ASPEED BMC SoCs.
+
+Enabling this allows the use of SHA operations in hardware without 
requiring the
+SHA software implementations, saving code size.
+
+Due to hardware limitations it cannot be used with a FIT placed in SPI
+FLASH. Data can only be hashed if it is in SDRAM, making this relevant
+for MMC and network boot only.
+
 endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index efbd1d3fca05..ac93b1295954 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -4,5 +4,6 @@
 #  http://www.samsung.com
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)   += ace_sha.o
+obj-$(CONFIG_ASPEED_HACE)  += aspeed_hace.o
 obj-y += rsa_mod_exp/
 obj-y += fsl/
diff --git a/drivers/crypto/aspeed_hace.c b/drivers/crypto/aspeed_hace.c
new file mode 100644
index ..941c1555fe5c
--- /dev/null
+++ b/drivers/crypto/aspeed_hace.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+//
+// (C) Copyright ASPEED Technology Inc.
+// Copyright 2021 IBM Corp.
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define ASPEED_HACE_STS0x1C
+#define  HACE_RSA_ISR  BIT(13)
+#define  HACE_CRYPTO_ISR   BIT(12)
+#define  HACE_HASH_ISR BIT(9)
+#define  HACE_RSA_BUSY BIT(2)
+#define  HACE_CRYPTO_BUSY  BIT(1)
+#define  HACE_HASH_BUSYBIT(0)
+#define ASPEED_HACE_HASH_SRC   0x20
+#define ASPEED_HACE_HASH_DIGEST_BUFF   0x24
+#define ASPEED_HACE_HASH_KEY_BUFF  0x28
+#define ASPEED_HACE_HASH_DATA_LEN  0x2C
+#define  HACE_SG_LAST  BIT(31)
+#define ASPEED_HACE_HASH_CMD   0x30
+#define  HACE_SHA_BE_ENBIT(3)
+#define  HACE_MD5_LE_ENBIT(2)
+#define  HACE_ALGO_MD5 0
+#define  HACE_ALGO_SHA1BIT(5)
+#define  HACE_ALGO_SHA224  BIT(6)
+#define  HACE_ALGO_SHA256  (BIT(4) | BIT(6))
+#define  HACE_ALGO_SHA512  (BIT(5) | BIT(6))
+#define  HACE_ALGO_SHA384  (BIT(5) | BIT(6) | BIT(10))
+#define  HACE_SG_ENBIT(18)
+
+#define ASPEED_MAX_SG  32
+
+struct aspeed_sg {
+   u32 len;
+   u32 addr;
+};
+
+struct aspeed_hash_ctx {
+   u32 method;
+   u32 digest_size;
+   u32 len;
+   u32 count;
+   struct aspeed_sg list[ASPEED_MAX_SG]; /* Must be 8 byte aligned */
+};
+
+struct aspeed_hace {
+   struct clk clk;
+};
+
+static phys_addr_t base;
+
+static int aspeed_hace_wait_completion(u32 reg, u32 flag, int timeout_us)
+{
+   u32 val;
+
+   return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us);
+}
+
+static int digest_object(const void *src, unsigned int length, void *digest, 
u32 method)
+{
+   if (!((u32)src & BIT(31))) {
+   debug("HACE src out of bounds: can only copy from SDRAM\n");
+   return -EINVAL;
+   }
+
+   if ((u32)digest & 0x7) {
+   debug("HACE dest alignment incorrect: %p\n", digest);
+   return -EINVAL;
+   }
+
+   if (readl(base + ASPEED_HACE_STS) & HACE_HASH_BUSY) {
+   debug("HACE error: engine busy\n");
+  

[PATCH] Makefile: Conditionally add defaultenv_h to envtools target

[Joel Stanley]

When building the envtools target with CONFIG_USE_DEFAULT_ENV_FILE=y,
the tools require generated/defaultenv_autogenerated.h.

 In file included from tools/env/fw_env.c:126:
 include/env_default.h:115:10: fatal error: 
generated/defaultenv_autogenerated.h: No such file or directory
   115 | #include "generated/defaultenv_autogenerated.h"
   |  ^~

Signed-off-by: Joel Stanley 
---
This is the minimal patch to fix the issue I was having building under
Yocto, which explicitly builds the envtools target separate to the rest
of u-boot. A similar change is probably required by the 'tools' target.

Alternatively, the tools and envtools could depend on a prepare
target, such as prepare1, which includes all of the prerequisites that
are listed.

 Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Makefile b/Makefile
index a73481d18c14..e096dc999c42 100644
--- a/Makefile
+++ b/Makefile
@@ -1871,6 +1871,8 @@ endif
 
 ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y)
 prepare1: $(defaultenv_h)
+
+envtools: $(defaultenv_h)
 endif
 
 archprepare: prepare1 scripts_basic
-- 
2.32.0

[PATCH 0/3] Improvements to FIT hashing

[Joel Stanley]

Here are some small changes to the FIT hashing code in order to use
more code from common/, which in turns allows hw implementations of SHA.

This was motivated by a need to reduce the SPL size for the Aspeed
platforms by using the hardware engine. I have a driver for the Aspeed
SoC that I will submit.

Joel Stanley (3):
  hw_sha: Fix coding style errors
  fit: Use hash.c to call SHA code
  hash: Allow for SHA512 hardware implementations

 common/hash.c  | 24 ++--
 common/image-fit.c | 34 --
 include/hw_sha.h   | 38 --
 lib/Kconfig| 15 +++
 4 files changed, 69 insertions(+), 42 deletions(-)

-- 
2.30.0

[PATCH 1/3] hw_sha: Fix coding style errors

[Joel Stanley]

Checkpatch complains about:

 ERROR: "foo * bar" should be "foo *bar"

and

 CHECK: Alignment should match open parenthesis

Signed-off-by: Joel Stanley 
---
 include/hw_sha.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/hw_sha.h b/include/hw_sha.h
index 991e496a3cb2..15b1a1c79836 100644
--- a/include/hw_sha.h
+++ b/include/hw_sha.h
@@ -18,8 +18,8 @@
  * should allocate at least 32 bytes at pOut in advance.
  * @param chunk_size   chunk size for sha256
  */
-void hw_sha256(const uchar * in_addr, uint buflen,
-   uchar * out_addr, uint chunk_size);
+void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr,
+  uint chunk_size);
 
 /**
  * Computes hash value of input pbuf using h/w acceleration
@@ -31,8 +31,8 @@ void hw_sha256(const uchar * in_addr, uint buflen,
  * should allocate at least 32 bytes at pOut in advance.
  * @param chunk_size   chunk_size for sha1
  */
-void hw_sha1(const uchar * in_addr, uint buflen,
-   uchar * out_addr, uint chunk_size);
+void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr,
+uint chunk_size);
 
 /*
  * Create the context for sha progressive hashing using h/w acceleration
@@ -56,7 +56,7 @@ int hw_sha_init(struct hash_algo *algo, void **ctxp);
  * @return 0 if ok, -ve on error
  */
 int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
-unsigned int size, int is_last);
+ unsigned int size, int is_last);
 
 /*
  * Copy sha hash result at destination location
@@ -70,6 +70,6 @@ int hw_sha_update(struct hash_algo *algo, void *ctx, const 
void *buf,
  * @return 0 if ok, -ve on error
  */
 int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
-int size);
+ int size);
 
 #endif
-- 
2.30.0

[PATCH 2/3] fit: Use hash.c to call SHA code

[Joel Stanley]

Currently the FIT hashing will call directly into the SHA algorithms to
get a hash.

This moves the fit code to use hash_lookup_algo, giving a common
entrypoint into the hashing code and removing the duplicated algorithm
look up. It also allows the use of hardware acceleration if configured.

Signed-off-by: Joel Stanley 
---
 common/image-fit.c | 34 --
 1 file changed, 8 insertions(+), 26 deletions(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 28b3d2b19111..3451cdecc95b 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1210,37 +1210,19 @@ int fit_set_timestamp(void *fit, int noffset, time_t 
timestamp)
  * 0, on success
  *-1, when algo is unsupported
  */
-int calculate_hash(const void *data, int data_len, const char *algo,
+int calculate_hash(const void *data, int data_len, const char *algo_name,
uint8_t *value, int *value_len)
 {
-   if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
-   *((uint32_t *)value) = crc32_wd(0, data, data_len,
-   CHUNKSZ_CRC32);
-   *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
-   *value_len = 4;
-   } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
-   sha1_csum_wd((unsigned char *)data, data_len,
-(unsigned char *)value, CHUNKSZ_SHA1);
-   *value_len = 20;
-   } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
-   sha256_csum_wd((unsigned char *)data, data_len,
-  (unsigned char *)value, CHUNKSZ_SHA256);
-   *value_len = SHA256_SUM_LEN;
-   } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
-   sha384_csum_wd((unsigned char *)data, data_len,
-  (unsigned char *)value, CHUNKSZ_SHA384);
-   *value_len = SHA384_SUM_LEN;
-   } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
-   sha512_csum_wd((unsigned char *)data, data_len,
-  (unsigned char *)value, CHUNKSZ_SHA512);
-   *value_len = SHA512_SUM_LEN;
-   } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
-   md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
-   *value_len = 16;
-   } else {
+   struct hash_algo *algo;
+
+   if (hash_lookup_algo(algo_name, &algo)) {
debug("Unsupported hash alogrithm\n");
return -1;
}
+
+   algo->hash_func_ws(data, data_len, value, algo->chunk_size);
+   *value_len = algo->digest_size;
+
return 0;
 }
 
-- 
2.30.0

[PATCH 3/3] hash: Allow for SHA512 hardware implementations

[Joel Stanley]

Similar to support for SHA1 and SHA256, allow the use of hardware hashing
engine by enabling the algorithm and setting  CONFIG_SHA_HW_ACCEL /
CONFIG_SHA_PROG_HW_ACCEL.

Signed-off-by: Joel Stanley 
---
 common/hash.c| 24 ++--
 include/hw_sha.h | 26 ++
 lib/Kconfig  | 15 +++
 3 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/common/hash.c b/common/hash.c
index fc64002f736a..10dff7ddb0e7 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -97,7 +97,7 @@ static int hash_finish_sha256(struct hash_algo *algo, void 
*ctx, void
 }
 #endif
 
-#if defined(CONFIG_SHA384)
+#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
 static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
 {
sha512_context *ctx = malloc(sizeof(sha512_context));
@@ -125,7 +125,7 @@ static int hash_finish_sha384(struct hash_algo *algo, void 
*ctx, void
 }
 #endif
 
-#if defined(CONFIG_SHA512)
+#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
 static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
 {
sha512_context *ctx = malloc(sizeof(sha512_context));
@@ -260,10 +260,20 @@ static struct hash_algo hash_algo[] = {
.name   = "sha384",
.digest_size= SHA384_SUM_LEN,
.chunk_size = CHUNKSZ_SHA384,
+#ifdef CONFIG_SHA_HW_ACCEL
+   .hash_func_ws   = hw_sha384,
+#else
.hash_func_ws   = sha384_csum_wd,
+#endif
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+   .hash_init  = hw_sha_init,
+   .hash_update= hw_sha_update,
+   .hash_finish= hw_sha_finish,
+#else
.hash_init  = hash_init_sha384,
.hash_update= hash_update_sha384,
.hash_finish= hash_finish_sha384,
+#endif
},
 #endif
 #ifdef CONFIG_SHA512
@@ -271,10 +281,20 @@ static struct hash_algo hash_algo[] = {
.name   = "sha512",
.digest_size= SHA512_SUM_LEN,
.chunk_size = CHUNKSZ_SHA512,
+#ifdef CONFIG_SHA_HW_ACCEL
+   .hash_func_ws   = hw_sha512,
+#else
.hash_func_ws   = sha512_csum_wd,
+#endif
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+   .hash_init  = hw_sha_init,
+   .hash_update= hw_sha_update,
+   .hash_finish= hw_sha_finish,
+#else
.hash_init  = hash_init_sha512,
.hash_update= hash_update_sha512,
.hash_finish= hash_finish_sha512,
+#endif
},
 #endif
{
diff --git a/include/hw_sha.h b/include/hw_sha.h
index 15b1a1c79836..d4f3471c4308 100644
--- a/include/hw_sha.h
+++ b/include/hw_sha.h
@@ -8,6 +8,32 @@
 #define __HW_SHA_H
 #include 
 
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr  A pointer to the input buffer
+ * @param bufleni  Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 64 bytes are copied to pout[0]...pout[63]. Thus, a user
+ * should allocate at least 64 bytes at pOut in advance.
+ * @param chunk_size   chunk size for sha512
+ */
+void hw_sha512(const uchar *in_addr, uint buflen, uchar *out_addr,
+  uint chunk_size);
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr  A pointer to the input buffer
+ * @param bufleni  Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 48 bytes are copied to pout[0]...pout[47]. Thus, a user
+ * should allocate at least 48 bytes at pOut in advance.
+ * @param chunk_size   chunk size for sha384
+ */
+void hw_sha384(const uchar *in_addr, uint buflen, uchar *out_addr,
+  uint chunk_size);
+
 /**
  * Computes hash value of input pbuf using h/w acceleration
  *
diff --git a/lib/Kconfig b/lib/Kconfig
index b35a71ac368b..0d753eedeced 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -389,19 +389,18 @@ config SHA384
 config SHA_HW_ACCEL
bool "Enable hashing using hardware"
help
- This option enables hardware acceleration
- for SHA1/SHA256 hashing.
- This affects the 'hash' command and also the
- hash_lookup_algo() function.
+ This option enables hardware acceleration for SHA hashing.
+ This affects the 'hash' command and also the hash_lookup_algo()
+ function.
 
 config SHA_PROG_HW_ACCEL
bool "Enable Progressive hashing support using hardware"
depends on SHA_HW_ACCEL
help
- This option enables hardware-acceleration for
- SHA1/SHA256 progressive hashing.
- Data can be streamed in a block at a time and the hashing
- is performed in hardw

[PATCH] image: fit: Use stack allocation macro

[Joel Stanley]

The documentation above the DEFINE_ALIGN_BUFFER says it's for use
outside functions, but we're inside one.

Instead use ALLOC_CACHE_ALIGN_BUFFER, the stack based macro, which also
includes the cache alignment.

Fixes: b583348ca8c8 ("image: fit: Align hash output buffers")
Signed-off-by: Joel Stanley 
---
This fixes booting the ast2600-evb image in qemu, which was getting all
zeroes for the output of the FIT hash check.

The 'static' buffer was in BSS but the output image didn't contain a BSS
section. The pointer was left pointing to the text, so the code was
trying to write to the (read only?) text area in SPI NOR memory space.

 tools/mkimage.h  | 3 +--
 boot/image-fit.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/tools/mkimage.h b/tools/mkimage.h
index 7652c8b001c3..f5ca65e2edfd 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -41,8 +41,7 @@ static inline ulong map_to_sysmem(void *ptr)
return (ulong)(uintptr_t)ptr;
 }
 
-#define ARCH_DMA_MINALIGN 1
-#define DEFINE_ALIGN_BUFFER(type, name, size, alugn) type name[size]
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) type name[size]
 
 #define MKIMAGE_TMPFILE_SUFFIX ".tmp"
 #define MKIMAGE_MAX_TMPFILE_LEN256
diff --git a/boot/image-fit.c b/boot/image-fit.c
index f57d97f55229..df3e5df8836a 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -1264,8 +1264,7 @@ int calculate_hash(const void *data, int data_len, const 
char *name,
 static int fit_image_check_hash(const void *fit, int noffset, const void *data,
size_t size, char **err_msgp)
 {
-   DEFINE_ALIGN_BUFFER(uint8_t, value, FIT_MAX_HASH_LEN,
-   ARCH_DMA_MINALIGN);
+   ALLOC_CACHE_ALIGN_BUFFER(uint8_t, value, FIT_MAX_HASH_LEN);
int value_len;
const char *algo;
uint8_t *fit_value;
-- 
2.35.1

[PATCH 00/10] i2c: Improvements for aspeed boards

[Joel Stanley]

This set of patches clean up the aspeed i2c support for the ast2500 and
enable the ast2600.

It has been tested in qemu and on the ast2600-evb.

Eddie James (1):
  ARM: dts: ast2600: Add I2C pinctrl

Joel Stanley (9):
  ARM: dts: ast2600: Add I2C reset properties
  ARM: dts: ast2600: Dsiable I2C nodes by default
  ARM: dts: ast2500-evb: Add I2C devices
  ARM: dts: ast2600-evb: Add I2C devices
  reset/aspeed: Implement status callback
  i2c/aspeed: Fix reset control
  i2c/aspeed: Add AST2600 compatible
  config/ast2600: Enable I2C driver
  config/aspeed: Enable EEPROM options

 drivers/i2c/ast_i2c.c | 23 +-
 drivers/reset/reset-ast2500.c | 19 
 drivers/reset/reset-ast2600.c | 17 +++
 arch/arm/dts/ast2500-evb.dts  | 19 
 arch/arm/dts/ast2600-evb.dts  | 11 +++
 arch/arm/dts/ast2600.dtsi | 56 +++
 configs/evb-ast2500_defconfig |  3 ++
 configs/evb-ast2600_defconfig |  3 ++
 8 files changed, 144 insertions(+), 7 deletions(-)

-- 
2.35.1

[PATCH 01/10] ARM: dts: ast2600: Add I2C pinctrl

[Joel Stanley]

From: Eddie James 

Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.

Signed-off-by: Eddie James 
Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..ef5b131ac0af 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -833,6 +833,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled";
};
 
@@ -846,6 +848,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2_default>;
status = "disabled";
};
 
@@ -859,6 +863,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c3_default>;
};
 
i2c3: i2c@200 {
@@ -871,6 +877,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4_default>;
};
 
i2c4: i2c@280 {
@@ -883,6 +891,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c5_default>;
};
 
i2c5: i2c@300 {
@@ -895,6 +905,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c6_default>;
};
 
i2c6: i2c@380 {
@@ -907,6 +919,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c7_default>;
};
 
i2c7: i2c@400 {
@@ -919,6 +933,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c8_default>;
};
 
i2c8: i2c@480 {
@@ -931,6 +947,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c9_default>;
};
 
i2c9: i2c@500 {
@@ -943,6 +961,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled";
};
 
@@ -956,6 +976,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled";
};
 
@@ -969,6 +991,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c12_default>;
status = "disabled";
};
 
@@ -982,6 +1006,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c13_default>;
status = "disabled";
};
 
@@ -995,6 +1021,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c14_default>;
status = "disabled";
};
 
@@ -1008,6 +1036,8 @@

[PATCH 02/10] ARM: dts: ast2600: Add I2C reset properties

[Joel Stanley]

The same as the upstream Linux device tree, each i2c bus has a property
specifying the reset line.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index ef5b131ac0af..4b23d25ede0a 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -832,6 +832,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
@@ -847,6 +848,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
@@ -862,6 +864,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
@@ -876,6 +879,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
@@ -890,6 +894,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
@@ -904,6 +909,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
@@ -918,6 +924,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
@@ -932,6 +939,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
@@ -946,6 +954,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
@@ -960,6 +969,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
@@ -975,6 +985,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
@@ -990,6 +1001,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = &

[PATCH 03/10] ARM: dts: ast2600: Dsiable I2C nodes by default

[Joel Stanley]

Allow boards to enable the buses they use.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 4b23d25ede0a..a37d062bcad7 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -868,6 +868,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
+   status = "disabled";
};
 
i2c3: i2c@200 {
@@ -883,6 +884,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
+   status = "disabled";
};
 
i2c4: i2c@280 {
@@ -898,6 +900,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
+   status = "disabled";
};
 
i2c5: i2c@300 {
@@ -913,6 +916,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
+   status = "disabled";
};
 
i2c6: i2c@380 {
@@ -928,6 +932,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
+   status = "disabled";
};
 
i2c7: i2c@400 {
@@ -943,6 +948,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
+   status = "disabled";
};
 
i2c8: i2c@480 {
@@ -958,6 +964,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
+   status = "disabled";
};
 
i2c9: i2c@500 {
-- 
2.35.1

[PATCH 04/10] ARM: dts: ast2500-evb: Add I2C devices

[Joel Stanley]

The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2500-evb.dts | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f57..874e042bc4cb 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -73,3 +73,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
 };
+
+&i2c3 {
+status = "okay";
+
+eeprom@50 {
+compatible = "atmel,24c08";
+reg = <0x50>;
+pagesize = <16>;
+};
+};
+
+&i2c7 {
+   status = "okay";
+
+lm75@4d {
+compatible = "national,lm75";
+reg = <0x4d>;
+};
+};
-- 
2.35.1

[PATCH 05/10] ARM: dts: ast2600-evb: Add I2C devices

[Joel Stanley]

The EVB has an EEPROM on bus 7 and a LM75 temp sensor on bus 8. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..cee787ecc0eb 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -174,6 +174,11 @@
 
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
+
+   temp@2e {
+   compatible = "adi,adt7490";
+   reg = <0x2e>;
+   };
 };
 
 &i2c8 {
@@ -181,6 +186,12 @@
 
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
+
+   eeprom@50 {
+   compatible = "atmel,24c08";
+   reg = <0x50>;
+   pagesize = <16>;
+   };
 };
 
 &mdio0 {
-- 
2.35.1

[PATCH 06/10] reset/aspeed: Implement status callback

[Joel Stanley]

The I2C driver shares a reset line between buses, so allow it to test
the state of the reset line before resetting it.

Signed-off-by: Joel Stanley 
---
 drivers/reset/reset-ast2500.c | 19 +++
 drivers/reset/reset-ast2600.c | 17 +
 2 files changed, 36 insertions(+)

diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
index 0a1dd236aff3..d9cecf3a72e8 100644
--- a/drivers/reset/reset-ast2500.c
+++ b/drivers/reset/reset-ast2500.c
@@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl 
*reset_ctl)
return 0;
 }
 
+static int ast2500_reset_status(struct reset_ctl *reset_ctl)
+{
+   struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   struct ast2500_scu *scu = priv->scu;
+   int status;
+
+   debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+   if (reset_ctl->id < 32)
+   status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1);
+   else
+   status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2);
+
+   return !!status;
+}
+
+
+
 static int ast2500_reset_probe(struct udevice *dev)
 {
int rc;
@@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = {
 struct reset_ops ast2500_reset_ops = {
.rst_assert = ast2500_reset_assert,
.rst_deassert = ast2500_reset_deassert,
+   .rst_status = ast2500_reset_status,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
index 985235a3ac46..1732a450efc0 100644
--- a/drivers/reset/reset-ast2600.c
+++ b/drivers/reset/reset-ast2600.c
@@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl 
*reset_ctl)
return 0;
 }
 
+static int ast2600_reset_status(struct reset_ctl *reset_ctl)
+{
+   struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   struct ast2600_scu *scu = priv->scu;
+   int status;
+
+   debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+   if (reset_ctl->id < 32)
+   status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1);
+   else
+   status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2);
+
+   return !!status;
+}
+
 static int ast2600_reset_probe(struct udevice *dev)
 {
int rc;
@@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = {
 struct reset_ops ast2600_reset_ops = {
.rst_assert = ast2600_reset_assert,
.rst_deassert = ast2600_reset_deassert,
+   .rst_status = ast2600_reset_status,
 };
 
 U_BOOT_DRIVER(ast2600_reset) = {
-- 
2.35.1

[PATCH 07/10] i2c/aspeed: Fix reset control

[Joel Stanley]

The reset control was written for the ast2500 and directly programs the
clocking register.

So we can share the code with other SoC generations use the reset device
to deassert the I2C reset line.

Signed-off-by: Joel Stanley 
---
 drivers/i2c/ast_i2c.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 2d3fecaa14ea..0a93d7c82911 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ast_i2c.h"
 
@@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
 
 static int ast_i2c_probe(struct udevice *dev)
 {
-   struct ast2500_scu *scu;
+   struct reset_ctl reset_ctl;
+   int rc;
 
debug("Enabling I2C%u\n", dev_seq(dev));
 
/*
 * Get all I2C devices out of Reset.
-* Only needs to be done once, but doing it for every
-* device does not hurt.
+*
+* Only needs to be done once so test before performing reset.
 */
-   scu = ast_get_scu();
-   ast_scu_unlock(scu);
-   clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
-   ast_scu_lock(scu);
+   rc = reset_get_by_index(dev, 0, &reset_ctl);
+   if (rc) {
+   printf("%s: Failed to get reset signal\n", __func__);
+   return rc;
+   }
+
+   if (reset_status(&reset_ctl) > 0) {
+   reset_assert(&reset_ctl);
+   reset_deassert(&reset_ctl);
+   }
 
ast_i2c_init_bus(dev);
 
-- 
2.35.1

[PATCH 08/10] i2c/aspeed: Add AST2600 compatible

[Joel Stanley]

Signed-off-by: Joel Stanley 
---
 drivers/i2c/ast_i2c.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 0a93d7c82911..c9ffe2d62820 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -351,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = {
 static const struct udevice_id ast_i2c_ids[] = {
{ .compatible = "aspeed,ast2400-i2c-bus" },
{ .compatible = "aspeed,ast2500-i2c-bus" },
+   { .compatible = "aspeed,ast2600-i2c-bus" },
{ },
 };
 
-- 
2.35.1

[PATCH 09/10] config/ast2600: Enable I2C driver

[Joel Stanley]

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..8f34546235a4 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -61,6 +61,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MISC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
-- 
2.35.1

[PATCH 10/10] config/aspeed: Enable EEPROM options

[Joel Stanley]

To allow testing of the I2C driver, enable the eprom command and the
misc driver.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2500_defconfig | 3 +++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 2371cc2742cf..3ae07bd4e9e1 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -18,6 +18,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_AUTO_COMPLETE is not set
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -33,6 +34,8 @@ CONFIG_CLK=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 8f34546235a4..f2ef84c90c5c 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -63,6 +64,7 @@ CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
-- 
2.35.1

Re: [PATCH 05/10] ARM: dts: ast2600-evb: Add I2C devices

[Joel Stanley]

On Tue, 21 Jun 2022 at 05:38, Ryan Chen  wrote:
>
> > -Original Message-
> > From: joel.s...@gmail.com  On Behalf Of Joel Stanley
> > Sent: Monday, June 20, 2022 3:25 PM
> > To: Ryan Chen ; BMC-SW
> > ; Heiko Schocher 
> > Cc: u-boot@lists.denx.de; Cédric Le Goater 
> > Subject: [PATCH 05/10] ARM: dts: ast2600-evb: Add I2C devices
> >
> > The EVB has an EEPROM on bus 7 and a LM75 temp sensor on bus 8. Enable
> > those busses we can test the I2C driver.
> >
> Hello,
> 
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v5.15/arch/arm/boot/dts/aspeed-ast2600-evb.dts#L662-L687
> The eeprom is under the same bus with bus#7. Please add in bus#7.
> Bus#8 have LM75. Not have eeprom.

You're right, I've put them both one bus down.

In testing it didn't matter as the "eeprom" command doesn't use the
device tree description of the devices.

Thanks for the review, I'll send a v2.

>
> > Signed-off-by: Joel Stanley 
> > ---
> >  arch/arm/dts/ast2600-evb.dts | 11 +++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
> > index 0d650543134a..cee787ecc0eb 100644
> > --- a/arch/arm/dts/ast2600-evb.dts
> > +++ b/arch/arm/dts/ast2600-evb.dts
> > @@ -174,6 +174,11 @@
> >
> >   pinctrl-names = "default";
> >   pinctrl-0 = <&pinctrl_i2c8_default>;
> > +
> > + temp@2e {
> > + compatible = "adi,adt7490";
> > + reg = <0x2e>;
> > + };
> >  };
> >
> >  &i2c8 {
> > @@ -181,6 +186,12 @@
> >
> >   pinctrl-names = "default";
> >   pinctrl-0 = <&pinctrl_i2c9_default>;
> > +
> > + eeprom@50 {
> > + compatible = "atmel,24c08";
> > + reg = <0x50>;
> > + pagesize = <16>;
> > + };
> >  };
> >
> >  &mdio0 {
> > --
> > 2.35.1
>

[PATCH v2 00/11] i2c: Improvements for aspeed boards

[Joel Stanley]

This set of patches clean up the aspeed i2c support for the ast2500 and
enable the ast2600.

v2:
 - fixes the device tree
 - adds a new patch that cleans up unnecessary pinctrl nodes
 - Adds Ryan's r-b from v1 to the relevant patches

It has been tested in qemu and on the ast2600-evb.

Eddie James (1):
  ARM: dts: ast2600: Add I2C pinctrl

Joel Stanley (10):
  ARM: dts: ast2600: Add I2C reset properties
  ARM: dts: ast2600: Disable I2C nodes by default
  ARM: dts: ast2600-evb: Remove redundant pinctrl
  ARM: dts: ast2500-evb: Add I2C devices
  ARM: dts: ast2600-evb: Add I2C devices
  reset/aspeed: Implement status callback
  i2c/aspeed: Fix reset control
  i2c/aspeed: Add AST2600 compatible
  config/ast2600: Enable I2C driver
  config/aspeed: Enable EEPROM options

 drivers/i2c/ast_i2c.c | 23 +-
 drivers/reset/reset-ast2500.c | 19 
 drivers/reset/reset-ast2600.c | 17 +++
 arch/arm/dts/ast2500-evb.dts  | 19 
 arch/arm/dts/ast2600-evb.dts  | 27 +
 arch/arm/dts/ast2600.dtsi | 56 +++
 configs/evb-ast2500_defconfig |  3 ++
 configs/evb-ast2600_defconfig |  3 ++
 8 files changed, 147 insertions(+), 20 deletions(-)

-- 
2.35.1

[PATCH v2 01/11] ARM: dts: ast2600: Add I2C pinctrl

[Joel Stanley]

From: Eddie James 

Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.

Signed-off-by: Eddie James 
Reviewed-by: Ryan Chen 
Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..ef5b131ac0af 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -833,6 +833,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled";
};
 
@@ -846,6 +848,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2_default>;
status = "disabled";
};
 
@@ -859,6 +863,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c3_default>;
};
 
i2c3: i2c@200 {
@@ -871,6 +877,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4_default>;
};
 
i2c4: i2c@280 {
@@ -883,6 +891,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c5_default>;
};
 
i2c5: i2c@300 {
@@ -895,6 +905,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c6_default>;
};
 
i2c6: i2c@380 {
@@ -907,6 +919,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c7_default>;
};
 
i2c7: i2c@400 {
@@ -919,6 +933,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c8_default>;
};
 
i2c8: i2c@480 {
@@ -931,6 +947,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c9_default>;
};
 
i2c9: i2c@500 {
@@ -943,6 +961,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled";
};
 
@@ -956,6 +976,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled";
};
 
@@ -969,6 +991,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c12_default>;
status = "disabled";
};
 
@@ -982,6 +1006,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c13_default>;
status = "disabled";
};
 
@@ -995,6 +1021,8 @@
bus-frequency = <10>;
interrupts = ;
clocks = <&scu ASPEED_CLK_APB2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c14_default>;
status = "disabled";
 

[PATCH v2 03/11] ARM: dts: ast2600: Disable I2C nodes by default

[Joel Stanley]

Allow boards to enable the buses they use.

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
v2: Fix spelling
---
 arch/arm/dts/ast2600.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 4b23d25ede0a..a37d062bcad7 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -868,6 +868,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
+   status = "disabled";
};
 
i2c3: i2c@200 {
@@ -883,6 +884,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
+   status = "disabled";
};
 
i2c4: i2c@280 {
@@ -898,6 +900,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
+   status = "disabled";
};
 
i2c5: i2c@300 {
@@ -913,6 +916,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
+   status = "disabled";
};
 
i2c6: i2c@380 {
@@ -928,6 +932,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
+   status = "disabled";
};
 
i2c7: i2c@400 {
@@ -943,6 +948,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
+   status = "disabled";
};
 
i2c8: i2c@480 {
@@ -958,6 +964,7 @@
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
+   status = "disabled";
};
 
i2c9: i2c@500 {
-- 
2.35.1

[PATCH v2 02/11] ARM: dts: ast2600: Add I2C reset properties

[Joel Stanley]

The same as the upstream Linux device tree, each i2c bus has a property
specifying the reset line.

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
 arch/arm/dts/ast2600.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index ef5b131ac0af..4b23d25ede0a 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -832,6 +832,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
@@ -847,6 +848,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
@@ -862,6 +864,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
@@ -876,6 +879,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
@@ -890,6 +894,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
@@ -904,6 +909,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
@@ -918,6 +924,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
@@ -932,6 +939,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
@@ -946,6 +954,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
@@ -960,6 +969,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
@@ -975,6 +985,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
@@ -990,6 +1001,7 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <10>;
interrupts = ;
+   resets = &

[PATCH v2 05/11] ARM: dts: ast2500-evb: Add I2C devices

[Joel Stanley]

The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
 arch/arm/dts/ast2500-evb.dts | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f57..874e042bc4cb 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -73,3 +73,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
 };
+
+&i2c3 {
+status = "okay";
+
+eeprom@50 {
+compatible = "atmel,24c08";
+reg = <0x50>;
+pagesize = <16>;
+};
+};
+
+&i2c7 {
+   status = "okay";
+
+lm75@4d {
+compatible = "national,lm75";
+reg = <0x4d>;
+};
+};
-- 
2.35.1

[PATCH v2 04/11] ARM: dts: ast2600-evb: Remove redundant pinctrl

[Joel Stanley]

Now that these are in the dtsi we don't need them in the EVB device
tree.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..806b76029ac7 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -150,37 +150,22 @@
 
 &i2c4 {
status = "okay";
-
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_i2c5_default>;
 };
 
 &i2c5 {
status = "okay";
-
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_i2c6_default>;
 };
 
 &i2c6 {
status = "okay";
-
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_i2c7_default>;
 };
 
 &i2c7 {
status = "okay";
-
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_i2c8_default>;
 };
 
 &i2c8 {
status = "okay";
-
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_i2c9_default>;
 };
 
 &mdio0 {
-- 
2.35.1

[PATCH v2 06/11] ARM: dts: ast2600-evb: Add I2C devices

[Joel Stanley]

The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7,
and a LM75 temp sensor on bus 8.

Signed-off-by: Joel Stanley 
---
v2: Place devices under correct bus
---
 arch/arm/dts/ast2600-evb.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 806b76029ac7..bb438d57cb6d 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -162,10 +162,26 @@
 
 &i2c7 {
status = "okay";
+
+   temp@2e {
+   compatible = "adi,adt7490";
+   reg = <0x2e>;
+   };
+
+   eeprom@50 {
+   compatible = "atmel,24c08";
+   reg = <0x50>;
+   pagesize = <16>;
+   };
 };
 
 &i2c8 {
status = "okay";
+
+   lm75@4d {
+   compatible = "national,lm75";
+   reg = <0x4d>;
+   };
 };
 
 &mdio0 {
-- 
2.35.1

[PATCH v2 07/11] reset/aspeed: Implement status callback

[Joel Stanley]

The I2C driver shares a reset line between buses, so allow it to test
the state of the reset line before resetting it.

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
 drivers/reset/reset-ast2500.c | 19 +++
 drivers/reset/reset-ast2600.c | 17 +
 2 files changed, 36 insertions(+)

diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
index 0a1dd236aff3..d9cecf3a72e8 100644
--- a/drivers/reset/reset-ast2500.c
+++ b/drivers/reset/reset-ast2500.c
@@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl 
*reset_ctl)
return 0;
 }
 
+static int ast2500_reset_status(struct reset_ctl *reset_ctl)
+{
+   struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   struct ast2500_scu *scu = priv->scu;
+   int status;
+
+   debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+   if (reset_ctl->id < 32)
+   status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1);
+   else
+   status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2);
+
+   return !!status;
+}
+
+
+
 static int ast2500_reset_probe(struct udevice *dev)
 {
int rc;
@@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = {
 struct reset_ops ast2500_reset_ops = {
.rst_assert = ast2500_reset_assert,
.rst_deassert = ast2500_reset_deassert,
+   .rst_status = ast2500_reset_status,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
index 985235a3ac46..1732a450efc0 100644
--- a/drivers/reset/reset-ast2600.c
+++ b/drivers/reset/reset-ast2600.c
@@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl 
*reset_ctl)
return 0;
 }
 
+static int ast2600_reset_status(struct reset_ctl *reset_ctl)
+{
+   struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   struct ast2600_scu *scu = priv->scu;
+   int status;
+
+   debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+   if (reset_ctl->id < 32)
+   status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1);
+   else
+   status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2);
+
+   return !!status;
+}
+
 static int ast2600_reset_probe(struct udevice *dev)
 {
int rc;
@@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = {
 struct reset_ops ast2600_reset_ops = {
.rst_assert = ast2600_reset_assert,
.rst_deassert = ast2600_reset_deassert,
+   .rst_status = ast2600_reset_status,
 };
 
 U_BOOT_DRIVER(ast2600_reset) = {
-- 
2.35.1

[PATCH v2 08/11] i2c/aspeed: Fix reset control

[Joel Stanley]

The reset control was written for the ast2500 and directly programs the
clocking register.

So we can share the code with other SoC generations use the reset device
to deassert the I2C reset line.

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
 drivers/i2c/ast_i2c.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 2d3fecaa14ea..0a93d7c82911 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ast_i2c.h"
 
@@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
 
 static int ast_i2c_probe(struct udevice *dev)
 {
-   struct ast2500_scu *scu;
+   struct reset_ctl reset_ctl;
+   int rc;
 
debug("Enabling I2C%u\n", dev_seq(dev));
 
/*
 * Get all I2C devices out of Reset.
-* Only needs to be done once, but doing it for every
-* device does not hurt.
+*
+* Only needs to be done once so test before performing reset.
 */
-   scu = ast_get_scu();
-   ast_scu_unlock(scu);
-   clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
-   ast_scu_lock(scu);
+   rc = reset_get_by_index(dev, 0, &reset_ctl);
+   if (rc) {
+   printf("%s: Failed to get reset signal\n", __func__);
+   return rc;
+   }
+
+   if (reset_status(&reset_ctl) > 0) {
+   reset_assert(&reset_ctl);
+   reset_deassert(&reset_ctl);
+   }
 
ast_i2c_init_bus(dev);
 
-- 
2.35.1

[PATCH v2 09/11] i2c/aspeed: Add AST2600 compatible

[Joel Stanley]

Signed-off-by: Joel Stanley 
Reviewed-by: Ryan Chen 
---
 drivers/i2c/ast_i2c.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 0a93d7c82911..c9ffe2d62820 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -351,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = {
 static const struct udevice_id ast_i2c_ids[] = {
{ .compatible = "aspeed,ast2400-i2c-bus" },
{ .compatible = "aspeed,ast2500-i2c-bus" },
+   { .compatible = "aspeed,ast2600-i2c-bus" },
{ },
 };
 
-- 
2.35.1

[PATCH v2 10/11] config/ast2600: Enable I2C driver

[Joel Stanley]

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..5c298939da6d 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -62,6 +62,7 @@ CONFIG_HASH_ASPEED=y
 CONFIG_ASPEED_ACRY=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MISC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
-- 
2.35.1

[PATCH v2 11/11] config/aspeed: Enable EEPROM options

[Joel Stanley]

To allow testing of the I2C driver, enable the eprom command and the
misc driver.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2500_defconfig | 3 +++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 2371cc2742cf..3ae07bd4e9e1 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -18,6 +18,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_AUTO_COMPLETE is not set
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -33,6 +34,8 @@ CONFIG_CLK=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 5c298939da6d..caf0db58e640 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -64,6 +65,7 @@ CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
-- 
2.35.1

[PATCH 0/9] mmc: Aspeed fixes

[Joel Stanley]

These changes get the SDHCI hardware on the AST2600 and AST2500 working
using the same device tree layout as upstream Linux.

The series has been tested on the Qemu models of the ast2500-evb and
ast2600-evb, and tested on the ast2600a3-evb hardware.

Joel Stanley (9):
  ARM: dts: ast2600: Update SDHCI nodes
  ARM: dts: ast2500: Update SDHCI nodes
  clk/aspeed: Add debug message when clock fails
  clk/ast2600: Adjust eMMC clock names
  clk/ast2500: Add SD clock
  mmc/aspeed: Add debuging for clock probe failures
  mmc/aspeed: Probe from controller
  mmc/aspeed: Enable controller clocks
  config/ast2600: Enable eMMC related boot options

 drivers/clk/aspeed/clk_ast2500.c | 26 +++
 drivers/clk/aspeed/clk_ast2600.c |  8 ++---
 drivers/mmc/aspeed_sdhci.c   | 45 +++--
 arch/arm/dts/ast2500-evb.dts |  4 +++
 arch/arm/dts/ast2500-u-boot.dtsi | 25 --
 arch/arm/dts/ast2500.dtsi| 28 
 arch/arm/dts/ast2600-evb.dts | 24 ++
 arch/arm/dts/ast2600.dtsi| 57 ++--
 configs/evb-ast2600_defconfig| 13 
 drivers/mmc/Kconfig  |  1 +
 10 files changed, 154 insertions(+), 77 deletions(-)

-- 
2.35.1

[PATCH 1/9] ARM: dts: ast2600: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 24 +++
 arch/arm/dts/ast2600.dtsi| 57 +++-
 2 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..47a0daa6dfbf 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -15,9 +15,9 @@
};
 
aliases {
-   mmc0 = &emmc_slot0;
-   mmc1 = &sdhci_slot0;
-   mmc2 = &sdhci_slot1;
+   mmc0 = &emmc;
+   mmc1 = &sdhci0;
+   mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@@ -134,18 +134,16 @@
};
 };
 
-&emmc {
-   u-boot,dm-pre-reloc;
-   timing-phase = <0x700ff>;
+
+&emmc_controller {
+status = "okay";
 };
 
-&emmc_slot0 {
-   u-boot,dm-pre-reloc;
-   status = "okay";
-   bus-width = <4>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_emmc_default>;
-   sdhci-drive-type = <1>;
+&emmc {
+non-removable;
+bus-width = <4>;
+max-frequency = <1>;
+clk-phase-mmc-hs200 = <9>, <225>;
 };
 
 &i2c4 {
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..3161e76941fd 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -416,60 +416,51 @@
status = "disabled";
};
 
-   sdhci: sdhci@1e74 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-sdhci-irq", 
"simple-mfd";
-   reg = <0x1e74 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
-<&scu ASPEED_CLK_GATE_SDEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   sdc: sdc@1e74 {
+   compatible = "aspeed,ast2600-sd-controller";
+   reg = <0x1e74 0x100>;
#address-cells = <1>;
#size-cells = <1>;
-   ranges = <0x0 0x1e74 0x1000>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
 
-   sdhci_slot0: sdhci_slot0@100 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci0: sdhci@1e740100 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x100 0x100>;
-   interrupts = <0>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
 
-   sdhci_slot1: sdhci_slot1@200 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci1: sdhci@1e740200 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x200 0x100>;
-   interrupts = <1>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
 
-   emmc: emmc@1e75 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-emmc-irq", 
"simple-mfd";
-   reg = <0x1e75 0x1

[PATCH RESEND 0/9] mmc: Fixes for Aspeed boards

[Joel Stanley]

These changes get the SDHCI hardware on the AST2600 and AST2500 working
using the same device tree layout as upstream Linux.

The series has been tested on the Qemu models of the ast2500-evb and
ast2600-evb, and tested on the ast2600a3-evb hardware.

(this is a resend as I had a stray comma in the To list that broke
sending the first attempt)

Joel Stanley (9):
  ARM: dts: ast2600: Update SDHCI nodes
  ARM: dts: ast2500: Update SDHCI nodes
  clk/aspeed: Add debug message when clock fails
  clk/ast2600: Adjust eMMC clock names
  clk/ast2500: Add SD clock
  mmc/aspeed: Add debuging for clock probe failures
  mmc/aspeed: Probe from controller
  mmc/aspeed: Enable controller clocks
  config/ast2600: Enable eMMC related boot options

 drivers/clk/aspeed/clk_ast2500.c | 26 +++
 drivers/clk/aspeed/clk_ast2600.c |  8 ++---
 drivers/mmc/aspeed_sdhci.c   | 45 +++--
 arch/arm/dts/ast2500-evb.dts |  4 +++
 arch/arm/dts/ast2500-u-boot.dtsi | 25 --
 arch/arm/dts/ast2500.dtsi| 28 
 arch/arm/dts/ast2600-evb.dts | 24 ++
 arch/arm/dts/ast2600.dtsi| 57 ++--
 configs/evb-ast2600_defconfig| 13 
 drivers/mmc/Kconfig  |  1 +
 10 files changed, 154 insertions(+), 77 deletions(-)

-- 
2.35.1

[PATCH RESEND 1/9] ARM: dts: ast2600: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 24 +++
 arch/arm/dts/ast2600.dtsi| 57 +++-
 2 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..47a0daa6dfbf 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -15,9 +15,9 @@
};
 
aliases {
-   mmc0 = &emmc_slot0;
-   mmc1 = &sdhci_slot0;
-   mmc2 = &sdhci_slot1;
+   mmc0 = &emmc;
+   mmc1 = &sdhci0;
+   mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@@ -134,18 +134,16 @@
};
 };
 
-&emmc {
-   u-boot,dm-pre-reloc;
-   timing-phase = <0x700ff>;
+
+&emmc_controller {
+status = "okay";
 };
 
-&emmc_slot0 {
-   u-boot,dm-pre-reloc;
-   status = "okay";
-   bus-width = <4>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_emmc_default>;
-   sdhci-drive-type = <1>;
+&emmc {
+non-removable;
+bus-width = <4>;
+max-frequency = <1>;
+clk-phase-mmc-hs200 = <9>, <225>;
 };
 
 &i2c4 {
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..3161e76941fd 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -416,60 +416,51 @@
status = "disabled";
};
 
-   sdhci: sdhci@1e74 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-sdhci-irq", 
"simple-mfd";
-   reg = <0x1e74 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
-<&scu ASPEED_CLK_GATE_SDEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   sdc: sdc@1e74 {
+   compatible = "aspeed,ast2600-sd-controller";
+   reg = <0x1e74 0x100>;
#address-cells = <1>;
#size-cells = <1>;
-   ranges = <0x0 0x1e74 0x1000>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
 
-   sdhci_slot0: sdhci_slot0@100 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci0: sdhci@1e740100 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x100 0x100>;
-   interrupts = <0>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
 
-   sdhci_slot1: sdhci_slot1@200 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci1: sdhci@1e740200 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x200 0x100>;
-   interrupts = <1>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
 
-   emmc: emmc@1e75 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-emmc-irq", 
"simple-mfd";
-   reg = <0x1e75 0x1

[PATCH RESEND 2/9] ARM: dts: ast2500: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2500-evb.dts |  4 
 arch/arm/dts/ast2500-u-boot.dtsi | 25 -
 arch/arm/dts/ast2500.dtsi| 28 
 3 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f57..2f1f246dc460 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -60,6 +60,10 @@
pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
 };
 
+&sdmmc {
+   status = "okay";
+};
+
 &sdhci0 {
status = "okay";
 
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index ea60e4c8db92..057390fe707e 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -28,31 +28,6 @@
clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst ASPEED_RESET_SDRAM>;
};
-
-   ahb {
-   u-boot,dm-pre-reloc;
-
-   apb {
-   u-boot,dm-pre-reloc;
-
-   sdhci0: sdhci@1e740100 {
-   compatible = "aspeed,ast2500-sdhci";
-   reg = <0x1e740100>;
-   #reset-cells = <1>;
-   clocks = <&scu ASPEED_CLK_SDIO>;
-   resets = <&rst ASPEED_RESET_SDIO>;
-   };
-
-   sdhci1: sdhci@1e740200 {
-   compatible = "aspeed,ast2500-sdhci";
-   reg = <0x1e740200>;
-   #reset-cells = <1>;
-   clocks = <&scu ASPEED_CLK_SDIO>;
-   resets = <&rst ASPEED_RESET_SDIO>;
-   };
-   };
-
-   };
 };
 
 &uart1 {
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index ee66ef67042b..cea08e6f08df 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -207,6 +207,34 @@
reg = <0x1e72 0x9000>;  // 36K
};
 
+   sdmmc: sd-controller@1e74 {
+   compatible = "aspeed,ast2500-sd-controller";
+   reg = <0x1e74 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
+
+   sdhci0: sdhci@100 {
+   compatible = "aspeed,ast2500-sdhci";
+   reg = <0x100 0x100>;
+   interrupts = <26>;
+   sdhci,auto-cmd12;
+   clocks = <&scu ASPEED_CLK_SDIO>;
+   status = "disabled";
+   };
+
+   sdhci1: sdhci@200 {
+   compatible = "aspeed,ast2500-sdhci";
+   reg = <0x200 0x100>;
+   interrupts = <26>;
+   sdhci,auto-cmd12;
+   clocks = <&scu ASPEED_CLK_SDIO>;
+   status = "disabled";
+   };
+   };
+
gpio: gpio@1e78 {
#gpio-cells = <2>;
gpio-controller;
-- 
2.35.1

[PATCH RESEND 3/9] clk/aspeed: Add debug message when clock fails

[Joel Stanley]

A common message across platforms that prints the clock number.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2500.c | 3 +++
 drivers/clk/aspeed/clk_ast2600.c | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2c6..dcf299548de1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -173,6 +173,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -438,6 +439,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong 
rate)
new_rate = ast2500_configure_d2pll(priv->scu, rate);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -480,6 +482,7 @@ static int ast2500_clk_enable(struct clk *clk)
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index f191b0f31707..7d85c7f09823 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk)
rate = ast2600_get_uart_huxclk_rate(priv->scu);
break;
default:
-   debug("can't get clk rate\n");
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk)
ast2600_enable_rsaclk(priv->scu);
break;
default:
-   pr_err("can't enable clk\n");
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
-- 
2.35.1

[PATCH RESEND 4/9] clk/ast2600: Adjust eMMC clock names

[Joel Stanley]

Adjust clock to stay compatible with those used by the Linux kernel
device tree.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2600.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 7d85c7f09823..0df1dc3718d3 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_SDCLK:
ast2600_enable_sdclk(priv->scu);
break;
-   case ASPEED_CLK_GATE_SDEXTCLK:
+   case ASPEED_CLK_SDIO:
ast2600_enable_extsdclk(priv->scu);
break;
case ASPEED_CLK_GATE_EMMCCLK:
ast2600_enable_emmcclk(priv->scu);
break;
-   case ASPEED_CLK_GATE_EMMCEXTCLK:
+   case ASPEED_CLK_EMMC:
ast2600_enable_extemmcclk(priv->scu);
break;
case ASPEED_CLK_GATE_FSICLK:
-- 
2.35.1

[PATCH RESEND 5/9] clk/ast2500: Add SD clock

[Joel Stanley]

In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2500.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index dcf299548de1..623c6915b81f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -426,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu 
*scu, ulong rate)
return new_rate;
 }
 
+#define SCU_CLKSTOP_SDIO 27
+static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
+{
+   u32 reset_bit;
+   u32 clkstop_bit;
+
+   reset_bit = BIT(ASPEED_RESET_SDIO);
+   clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
+
+   setbits_le32(&scu->sysreset_ctrl1, reset_bit);
+   udelay(100);
+   //enable clk
+   clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
+   mdelay(10);
+   clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
+
+   return 0;
+}
+
 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 {
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@@ -481,6 +501,9 @@ static int ast2500_clk_enable(struct clk *clk)
case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
+   case ASPEED_CLK_GATE_SDCLK:
+   ast2500_enable_sdclk(priv->scu);
+   break;
default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
-- 
2.35.1

[PATCH RESEND 6/9] mmc/aspeed: Add debuging for clock probe failures

[Joel Stanley]

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 453731571987..c71daae97584 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -26,12 +26,16 @@ static int aspeed_sdhci_probe(struct udevice *dev)
int ret;
 
ret = clk_get_by_index(dev, 0, &clk);
-   if (ret)
+   if (ret) {
+   debug("%s: clock get failed %d\n", __func__, ret);
return ret;
+   }
 
ret = clk_enable(&clk);
-   if (ret)
+   if (ret) {
+   debug("%s: clock enable failed %d\n", __func__, ret);
goto free;
+   }
 
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
@@ -39,6 +43,7 @@ static int aspeed_sdhci_probe(struct udevice *dev)
max_clk = clk_get_rate(&clk);
if (IS_ERR_VALUE(max_clk)) {
ret = max_clk;
+   debug("%s: clock rate get failed %d\n", __func__, ret);
goto err;
}
 
-- 
2.35.1

[PATCH RESEND 7/9] mmc/aspeed: Probe from controller

[Joel Stanley]

The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.

Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:

ofnode node;

dev_for_each_subnode(node, parent) {
struct udevice *dev;
int ret;

ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
 ofnode_get_name(node),
 node, &dev);
if (ret)
return ret;
}

However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.

Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.

Select MISC as the controller driver is implemented as a misc device.

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 21 +
 drivers/mmc/Kconfig|  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index c71daae97584..5591fa2b0891 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct aspeed_sdhci_plat {
struct mmc_config cfg;
@@ -94,3 +95,23 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
.priv_auto  = sizeof(struct sdhci_host),
.plat_auto  = sizeof(struct aspeed_sdhci_plat),
 };
+
+
+static int aspeed_sdc_probe(struct udevice *parent)
+{
+   return 0;
+}
+
+static const struct udevice_id aspeed_sdc_ids[] = {
+   { .compatible = "aspeed,ast2400-sd-controller" },
+   { .compatible = "aspeed,ast2500-sd-controller" },
+   { .compatible = "aspeed,ast2600-sd-controller" },
+   { }
+};
+
+U_BOOT_DRIVER(aspeed_sdc_drv) = {
+   .name   = "aspeed_sdc",
+   .id = UCLASS_MISC,
+   .of_match   = aspeed_sdc_ids,
+   .probe  = aspeed_sdc_probe,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5e2921ce41a7..07ff69afea69 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -489,6 +489,7 @@ config MMC_SDHCI_ASPEED
depends on ARCH_ASPEED
depends on DM_MMC
depends on MMC_SDHCI
+   select MISC
help
  Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
  SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
-- 
2.35.1

[PATCH RESEND 8/9] mmc/aspeed: Enable controller clocks

[Joel Stanley]

Request and enable the controller level clocks.

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 5591fa2b0891..9d79bf58cc70 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -99,6 +99,21 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
 
 static int aspeed_sdc_probe(struct udevice *parent)
 {
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(parent, 0, &clk);
+   if (ret) {
+   debug("%s: clock get failed %d\n", __func__, ret);
+   return ret;
+   }
+
+   ret = clk_enable(&clk);
+   if (ret) {
+   debug("%s: clock enable failed %d\n", __func__, ret);
+   return ret;
+   }
+
return 0;
 }
 
-- 
2.35.1

[PATCH RESEND 9/9] config/ast2600: Enable eMMC related boot options

[Joel Stanley]

Allow booting zImage from ext4 devices with DOS or UEFI partition
layouts.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 13 +
 1 file changed, 13 insertions(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..69f6f30c6543 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -42,6 +42,14 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -49,6 +57,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-- 
2.35.1

[u-boot-test-hooks PATCH 0/2] Aspeed updates

[Joel Stanley]

Hi Tom,

This updates the configuration for the aspeed machines, adding support
for the ast2600.

Joel Stanley (2):
  ast2500: Simplify Qemu command line
  travis-ci: Add Aspeed AST2600 Qemu configuration

 bin/travis-ci/conf.evb-ast2500_qemu  |  2 +-
 bin/travis-ci/conf.evb-ast2600_qemu  | 13 +
 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py |  4 
 3 files changed, 18 insertions(+), 1 deletion(-)
 create mode 100644 bin/travis-ci/conf.evb-ast2600_qemu
 create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py

-- 
2.35.1

[u-boot-test-hooks PATCH 1/2] ast2500: Simplify Qemu command line

[Joel Stanley]

The Aspeed machine in Qemu has appropriate defaults so we don't need to
specify these options.

Signed-off-by: Joel Stanley 
---
 bin/travis-ci/conf.evb-ast2500_qemu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/travis-ci/conf.evb-ast2500_qemu 
b/bin/travis-ci/conf.evb-ast2500_qemu
index 7f0f3c56e006..2e9adc6af9b0 100644
--- a/bin/travis-ci/conf.evb-ast2500_qemu
+++ b/bin/travis-ci/conf.evb-ast2500_qemu
@@ -5,7 +5,7 @@
 console_impl=qemu
 qemu_machine="ast2500-evb"
 qemu_binary="qemu-system-arm"
-qemu_extra_args="-nographic -m 512M -serial mon:stdio -net nic,model=ftgmac100 
-net user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
 qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
 reset_impl=none
 flash_impl=qemu_gen_padded_image
-- 
2.35.1

[u-boot-test-hooks PATCH 2/2] travis-ci: Add Aspeed AST2600 Qemu configuration

[Joel Stanley]

Similar to the AST2500 this machine is emulated by Qemu. It boots from
a 64MB SPI NOR flash device by default.

Signed-off-by: Joel Stanley 
---
 bin/travis-ci/conf.evb-ast2600_qemu  | 13 +
 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py |  4 
 2 files changed, 17 insertions(+)
 create mode 100644 bin/travis-ci/conf.evb-ast2600_qemu
 create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py

diff --git a/bin/travis-ci/conf.evb-ast2600_qemu 
b/bin/travis-ci/conf.evb-ast2600_qemu
new file mode 100644
index ..386ff7d25774
--- /dev/null
+++ b/bin/travis-ci/conf.evb-ast2600_qemu
@@ -0,0 +1,13 @@
+# Copyright 2022 IBM Corp.
+# Joel Stanley 
+# SPDX-License-Identifier: GPL-2.0+
+
+console_impl=qemu
+qemu_machine="ast2600-evb"
+qemu_binary="qemu-system-arm"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
+flash_u_boot_bin="u-boot-with-spl.bin"
+reset_impl=none
+flash_impl=qemu_gen_padded_image
+flash_size=64
diff --git a/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py 
b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
new file mode 100644
index ..396261efa3a3
--- /dev/null
+++ b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
@@ -0,0 +1,4 @@
+import travis_tftp
+
+env__net_dhcp_server = True
+env__net_tftp_readable_file = travis_tftp.file2env('u-boot')
-- 
2.35.1

[PATCH 0/5] aspeed: Add to CI

[Joel Stanley]

The Aspeed AST2600 is modelled in Qemu. This makes some configuration
changes so it can be added to CI.

It has a depednency on the u-boot-test-hooks patches I sent here:

 https://lore.kernel.org/u-boot/20220624023420.3925916-1-j...@jms.id.au

I've given it a run on Azure and the tests passed.

Joel Stanley (5):
  config/ast2600: Enable CRC32
  config/ast2600: Make position independent
  config/ast2600: Disable hash hardware accel
  ast2600: Configure u-boot-with-spl.bin target
  CI: Add Aspeed AST2600

 include/configs/evb_ast2600.h | 3 +++
 .azure-pipelines.yml  | 3 +++
 .gitlab-ci.yml| 6 ++
 configs/evb-ast2600_defconfig | 7 ---
 4 files changed, 16 insertions(+), 3 deletions(-)

-- 
2.35.1

[PATCH 1/5] config/ast2600: Enable CRC32

[Joel Stanley]

Useful for testing images with the default hash type.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..53ba36a28374 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
-- 
2.35.1

[PATCH 2/5] config/ast2600: Make position independent

[Joel Stanley]

Allows loading one u-boot from another. Useful for testing on hardware.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 53ba36a28374..f3a6cb222020 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 CONFIG_ARCH_ASPEED=y
 CONFIG_SYS_TEXT_BASE=0x8000
-- 
2.35.1

[PATCH 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

The Qemu model or the u-boot driver is unable to correctly compute the
SHA256 hash used in a FIT. Disable it by default while that issue is
worked out to enable boot testing in Qemu.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
-- 
2.35.1

[PATCH 4/5] ast2600: Configure u-boot-with-spl.bin target

[Joel Stanley]

For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

With this the following simple steps can be used to build and boot a
system:

  make u-boot-with-spl.bin
  truncate -s 64M u-boot-with-spl.bin
  qemu-system-arm -nographic -M ast2600-evb \
-drive file=u-boot-with-spl.bin,if=mtd,format=raw

Signed-off-by: Joel Stanley 
---
 include/configs/evb_ast2600.h | 3 +++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index 3c2155da46df..f5ac88447b52 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h
@@ -10,6 +10,9 @@
 
 #define CONFIG_SYS_UBOOT_BASE  CONFIG_SYS_TEXT_BASE
 
+/* The maximum size the AST2600 bootrom can load is 64KB */
+#define CONFIG_SPL_MAX_SIZE65536
+
 /* Misc */
 #define STR_HELPER(s)  #s
 #define STR(s) STR_HELPER(s)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..5230515f7ab6 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_SIZE_LIMIT=0x1
 CONFIG_SPL=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_SPL_FIT_SIGNATURE=y
-- 
2.35.1

[PATCH 5/5] CI: Add Aspeed AST2600

[Joel Stanley]

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Signed-off-by: Joel Stanley 
---
 .azure-pipelines.yml | 3 +++
 .gitlab-ci.yml   | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index ad540ea63536..bdc515ebcdc1 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -261,6 +261,9 @@ stages:
 evb_ast2500:
   TEST_PY_BD: "evb-ast2500"
   TEST_PY_ID: "--id qemu"
+evb_ast2600:
+  TEST_PY_BD: "evb-ast2600"
+  TEST_PY_ID: "--id qemu"
 vexpress_ca9x4:
   TEST_PY_BD: "vexpress_ca9x4"
   TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c6a608f7e2a7..f9cd41750791 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -272,6 +272,12 @@ evb-ast2500 test.py:
 TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
+evb-ast2600 test.py:
+  variables:
+TEST_PY_BD: "evb-ast2600"
+TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
 sandbox_flattree test.py:
   variables:
 TEST_PY_BD: "sandbox_flattree"
-- 
2.35.1

Re: [PATCH 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

On Mon, 27 Jun 2022 at 07:12, Cédric Le Goater  wrote:
>
> Hello Chiawei,
>
> On 6/27/22 02:39, ChiaWei Wang wrote:
> > Reply again to leave record on mailing list.

Sorry, I re-sent it to get it on the list and managed to miss that for
the second time.

> >
> >> From: joel.s...@gmail.com  On Behalf Of Joel Stanley
> >> Sent: Friday, June 24, 2022 10:50 AM
> >>
> >> The Qemu model or the u-boot driver is unable to correctly compute the
> >> SHA256 hash used in a FIT. Disable it by default while that issue is 
> >> worked out
> >> to enable boot testing in Qemu.
> >>
> >> Signed-off-by: Joel Stanley 
> >> ---
> >>   configs/evb-ast2600_defconfig | 3 ---
> >>   1 file changed, 3 deletions(-)
> >>
> >> diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
> >> index f3a6cb222020..160bccff48e2 100644
> >> --- a/configs/evb-ast2600_defconfig
> >> +++ b/configs/evb-ast2600_defconfig
> >> @@ -59,9 +59,6 @@ CONFIG_REGMAP=y
> >>   CONFIG_SPL_OF_TRANSLATE=y
> >>   CONFIG_CLK=y
> >>   CONFIG_SPL_CLK=y
> >> -CONFIG_DM_HASH=y
> >> -CONFIG_HASH_ASPEED=y
> >> -CONFIG_ASPEED_ACRY=y
> >
> > Per our previous discussion, SPL code size still exists if all of AST2600 
> > features are upstream-ed.
> > Therefore, HW-assisted crypto drivers are needed.
> >
> > In addition, the current drivers works fine on real EVB to verify Hash + 
> > RSA signature (including the SHA256 in question).
> > This issue described in commit message should be attributed to incomplete 
> > QEMU emulation.
>
> When activating some debug in the hace driver :
>
>U-Boot SPL 2022.07-rc5-dirty (Jun 27 2022 - 09:01:28 +0200)
>already initialized, aspeed_2600_sdmc_write: SDMC is locked! (write to 
> MCR04 blocked)
>Trying to boot from RAM
>## Checking hash(es) for config conf-1 ... OK
>## Checking hash(es) for Image firmware-1 ... crc32Unsupported hash 
> algorithm 'crc32'
> error!
>Unsupported hash algorithm for 'hash-1' hash node in 'firmware-1' image 
> node
>
> It seems the problem comes from the unsupported 'crc32' algo.
> See aspeed_hace_init().

Well spotted. It needs a fallback implementation of the algorithms the
hash API supports but the hardware driver does not implement.

So we have three downsides of using the HACE driver:

 - Cannot DMA from SPI NOR, requiring a copy to RAM
 - Missing MD5 and CRC32 implementations, breaking the hash API
 - Broken Qemu emulation, meaning we cannot use it in OpenBMC as all
commits will fail CI

Obviously we can fix or find workarounds for these issues. However I
suggest while they are worked on we leave the HACE disabled in the
defconfig, so we can have build coverage in u-boot CI.

Once Aspeed completes the upstreaming of its u-boot port and therefore
hits the 64KB space limit, then we can look at re-enabling HACE in the
defconfig. Hopefully by then you will have resolved the issues with
the Qemu model.

Cheers,

Joel



>
> Thanks,
>
> C.
>
>
> >
> > Therefore, fixing QEMU should be the right way to go instead of disabling 
> > these options for real HW.
> >
> > Chiawei
> >
> >>   CONFIG_ASPEED_GPIO=y
> >>   CONFIG_DM_I2C=y
> >>   CONFIG_MISC=y
> >> --
> >> 2.35.1
> >
>

[PATCH RESEND 0/5] aspeed: Add AST2600 machine to CI

[Joel Stanley]

The Aspeed AST2600 is modelled in Qemu. This makes some configuration
changes so it can be added to CI.

It has a depednency on the u-boot-test-hooks patches I sent here:

 https://lore.kernel.org/u-boot/20220624023420.3925916-1-j...@jms.id.au

I've given it a run on Azure and the tests passed.

Joel Stanley (5):
  config/ast2600: Enable CRC32
  config/ast2600: Make position independent
  config/ast2600: Disable hash hardware accel
  ast2600: Configure u-boot-with-spl.bin target
  CI: Add Aspeed AST2600

 include/configs/evb_ast2600.h | 3 +++
 .azure-pipelines.yml  | 3 +++
 .gitlab-ci.yml| 6 ++
 configs/evb-ast2600_defconfig | 7 ---
 4 files changed, 16 insertions(+), 3 deletions(-)

-- 
2.35.1

[PATCH RESEND 2/5] config/ast2600: Make position independent

[Joel Stanley]

Allows loading one u-boot from another. Useful for testing on hardware.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 53ba36a28374..f3a6cb222020 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 CONFIG_ARCH_ASPEED=y
 CONFIG_SYS_TEXT_BASE=0x8000
-- 
2.35.1

[PATCH RESEND 4/5] ast2600: Configure u-boot-with-spl.bin target

[Joel Stanley]

For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

With this the following simple steps can be used to build and boot a
system:

  make u-boot-with-spl.bin
  truncate -s 64M u-boot-with-spl.bin
  qemu-system-arm -nographic -M ast2600-evb \
-drive file=u-boot-with-spl.bin,if=mtd,format=raw

Signed-off-by: Joel Stanley 
---
 include/configs/evb_ast2600.h | 3 +++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index 3c2155da46df..f5ac88447b52 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h
@@ -10,6 +10,9 @@
 
 #define CONFIG_SYS_UBOOT_BASE  CONFIG_SYS_TEXT_BASE
 
+/* The maximum size the AST2600 bootrom can load is 64KB */
+#define CONFIG_SPL_MAX_SIZE65536
+
 /* Misc */
 #define STR_HELPER(s)  #s
 #define STR(s) STR_HELPER(s)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..5230515f7ab6 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_SIZE_LIMIT=0x1
 CONFIG_SPL=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_SPL_FIT_SIGNATURE=y
-- 
2.35.1

[PATCH RESEND 5/5] CI: Add Aspeed AST2600

[Joel Stanley]

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Signed-off-by: Joel Stanley 
---
 .azure-pipelines.yml | 3 +++
 .gitlab-ci.yml   | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index ad540ea63536..bdc515ebcdc1 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -261,6 +261,9 @@ stages:
 evb_ast2500:
   TEST_PY_BD: "evb-ast2500"
   TEST_PY_ID: "--id qemu"
+evb_ast2600:
+  TEST_PY_BD: "evb-ast2600"
+  TEST_PY_ID: "--id qemu"
 vexpress_ca9x4:
   TEST_PY_BD: "vexpress_ca9x4"
   TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c6a608f7e2a7..f9cd41750791 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -272,6 +272,12 @@ evb-ast2500 test.py:
 TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
+evb-ast2600 test.py:
+  variables:
+TEST_PY_BD: "evb-ast2600"
+TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
 sandbox_flattree test.py:
   variables:
 TEST_PY_BD: "sandbox_flattree"
-- 
2.35.1

[PATCH RESEND 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to enable
boot testing in Qemu.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
-- 
2.35.1

[PATCH RESEND 1/5] config/ast2600: Enable CRC32

[Joel Stanley]

Useful for testing images with the default hash type.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..53ba36a28374 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
-- 
2.35.1

Re: [PATCH RESEND 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

On Mon, 27 Jun 2022 at 08:55, Neal Liu  wrote:
>
> > Reviewed-by: Chia-Wei Wang 
> >
> > The QEMU emulation issue is under investigation by Steven.
> > The CRC32 and MD5 SW support will be added before we re-enabling HW
> > crypto drivers.
> >
> > Chiawei
> >
> > > From: joel.s...@gmail.com  On Behalf Of Joel
> > > Stanley
> > > Sent: Monday, June 27, 2022 3:58 PM
> > >
> > > The HACE driver lacks support for all the hash types, causing boot to
> > > fail with the default FIT configuration which uses CRC32.
> > >
> > > Additionally the Qemu model or the u-boot driver is unable to
> > > correctly compute the SHA256 hash used in a FIT.
> > >
> > > Disable HACE by default while the above issues are worked out to
> > > enable boot testing in Qemu.
>
> I don't think this is the right way to do it.
>
> First, it's fine that drivers can only support some algos. There is no rules 
> that it must support CRC32.
> Second, if Qemu test is failure, it should fix the Qemu HACE driver or 
> disable it in Qemu, not in common defconfig in u-boot.
> This will affect lots of people who use mainline for developments and 
> productions.

While I agree with you in general, this board didn't boot until
recently, and it certainly doesn't have any users. Mainline u-boot
lacks drivers for the ast2600 hardware it claims to support. There's
no working storage driver in the tree (SPI NOR or eMMC).

While qemu support is not required for u-boot's CI, it is a hard
dependency of it being used in the OpenBMC project, which is where the
majority of users come from. In that project we use a fork of the
Aspeed SDK, which itself is a few thousand patches on top of u-boot
v2019.04.

I propose this change as a way to get CI working for the board, so we
can have a baseline set of working functionality, and make
improvements from there. I've started submitting those improvements;
we have changes on the list for eMMC support, I2C, and the Aspeed
developers have a spi-nor driver under review.

Cheers,

Joel

> Thanks,
>
> -Neal
>
> > >
> > > Signed-off-by: Joel Stanley 
> > > ---
> > >  configs/evb-ast2600_defconfig | 3 ---
> > >  1 file changed, 3 deletions(-)
> > >
> > > diff --git a/configs/evb-ast2600_defconfig
> > > b/configs/evb-ast2600_defconfig index f3a6cb222020..160bccff48e2
> > > 100644
> > > --- a/configs/evb-ast2600_defconfig
> > > +++ b/configs/evb-ast2600_defconfig
> > > @@ -59,9 +59,6 @@ CONFIG_REGMAP=y
> > >  CONFIG_SPL_OF_TRANSLATE=y
> > >  CONFIG_CLK=y
> > >  CONFIG_SPL_CLK=y
> > > -CONFIG_DM_HASH=y
> > > -CONFIG_HASH_ASPEED=y
> > > -CONFIG_ASPEED_ACRY=y
> > >  CONFIG_ASPEED_GPIO=y
> > >  CONFIG_DM_I2C=y
> > >  CONFIG_MISC=y
> > > --
> > > 2.35.1
>

Re: [PATCH 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

On Mon, 27 Jun 2022 at 08:48, Steven Lee  wrote:
>
> Hi Joel,
>
> I was wondering if you could share the commit hash of u-boot you tested.
> I would like to test it on qemu.

I recommend using master with the patch that fixes FIT hash checking:

https://lore.kernel.org/r/20220620070117.3443066-1-j...@jms.id.au

I use a script to build the image (also attached to this email):

https://ozlabs.org/~joel/build-ast2600-spl.sh

Run that script from the u-boot source tree. It provides an example
qemu commandline when it finishes:

/usr/bin/qemu-system-arm -M ast2600-evb -nographic -drive
file=ast2600-obj/test.img,if=mtd,format=raw -nic user,tftp=/srv/tftp/
U-Boot SPL 2022.07-rc5-00010-g75967970850a (Jun 27 2022 - 19:00:15 +0930)
Trying to boot from RAM
## Checking hash(es) for config conf-1 ... OK
## Checking hash(es) for Image firmware-1 ... sha256 error!
Bad hash value for 'hash-1' hash node in 'firmware-1' image node

One thing to note is the conf-1 check succeeds, but the firmware-1
check fails. I suspect this is because the conf-1 check is less than
64 bytes, so it only requires one pass of the HACE. That's also why
the qemu unit test you wrote works; it only tests one pass, so doesn't
trigger the accumulation part of the model.

I was running with this patch to see the output of the hash operation:

Author: Joel Stanley 
Date:   Sat Jun 18 18:20:08 2022 +0930

fit: Print hash results on failure

Signed-off-by: Joel Stanley 

diff --git a/boot/image-fit.c b/boot/image-fit.c
index df3e5df8836a..63aa46e51270 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -1302,7 +1302,18 @@ static int fit_image_check_hash(const void
*fit, int noffset, const void *data,
*err_msgp = "Bad hash value len";
return -1;
} else if (memcmp(value, fit_value, value_len) != 0) {
+   int i;
*err_msgp = "Bad hash value";
+   printf("\ncalculated: ");
+   for (i=0; ihttps://github.com/shenki/u-boot/

Cheers,

Joel


build-ast2600-spl.sh
Description: Bourne shell script

Re: [PATCH] configs: ast2600: Move SPL bss section to DRAM space

[Joel Stanley]

Hi Chai Wei,

On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang  wrote:
>
> The commit b583348ca8c8 ("image: fit: Align hash output buffers") places
> the hash output buffer at the .bss section. However, AST2600 by default
> executes SPL in the NOR flash XIP way. This results in the hash output
> cannot be written to the buffer as it is located at the R/X only region.
>
> We need to move the .bss section out of the SPL body to the DRAM space,
> where hash output can be written to. This patch includes:
>  - Define the .bss section base and size
>  - A new SPL linker script is added with a separate .bss region specified
>  - Enable CONFIG_SPL_SEPARATE_BSS kconfig option
>
> Signed-off-by: Chia-Wei Wang 

This patch breaks booting for me.

My concern with the approach is it creates extra maintenance work.
When changes are made to the main linker script they need to be
mirrored here, or else the aspeed port will miss out. (Having the
machine tested in CI will help this somewhat, but only for the code
paths we can test under emulation).

I know the patch has been merged, but I have a few questions:

I imagine the ast2600 is not the only board that runs XIP. How do
other boards solve the problem?

What happens when a symbol that is used before DRAM training has
completed is placed in bss?

How do you plan to support systems that don't have NOR?

Cheers,

Joel


> ---
>  arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 94 +
>  configs/evb-ast2600_defconfig   |  3 +
>  include/configs/evb_ast2600.h   |  3 +
>  3 files changed, 100 insertions(+)
>  create mode 100644 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
>
> diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds 
> b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
> new file mode 100644
> index 00..22b4e16d35
> --- /dev/null
> +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
> @@ -0,0 +1,94 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2004-2008 Texas Instruments
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, 
> + *
> + * (C) Copyright 2022
> + * Chia-Wei Wang 
> + */
> +
> +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,
> +   LENGTH = CONFIG_SPL_SIZE_LIMIT }
> +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
> +   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
> +
> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> +OUTPUT_ARCH(arm)
> +ENTRY(_start)
> +SECTIONS
> +{
> +   . = 0x;
> +
> +   . = ALIGN(4);
> +   .text :
> +   {
> +   __image_copy_start = .;
> +   *(.vectors)
> +   CPUDIR/start.o (.text*)
> +   *(.text*)
> +   *(.glue*)
> +   } > .nor
> +
> +   . = ALIGN(4);
> +   .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } > .nor
> +
> +   . = ALIGN(4);
> +   .data : {
> +   *(.data*)
> +   } > .nor
> +
> +   . = ALIGN(4);
> +   .u_boot_list : {
> +   KEEP(*(SORT(.u_boot_list*)));
> +   } > .nor
> +
> +   . = ALIGN(4);
> +   .binman_sym_table : {
> +   __binman_sym_start = .;
> +   KEEP(*(SORT(.binman_sym*)));
> +   __binman_sym_end = .;
> +   } > .nor
> +
> +   . = ALIGN(4);
> +
> +   __image_copy_end = .;
> +
> +   .rel.dyn : {
> +   __rel_dyn_start = .;
> +   *(.rel*)
> +   __rel_dyn_end = .;
> +   } > .nor
> +
> +   .end :
> +   {
> +   *(.__end)
> +   } > .nor
> +
> +   _image_binary_end = .;
> +
> +   .bss : {
> +   __bss_start = .;
> +   *(.bss*)
> +. = ALIGN(4);
> +   __bss_end = .;
> +   } > .bss
> +
> +   __bss_size = __bss_end - __bss_start;
> +}
> +
> +#if defined(IMAGE_MAX_SIZE)
> +ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \
> +   "SPL image too big");
> +#endif
> +
> +#if defined(CONFIG_SPL_BSS_MAX_SIZE)
> +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
> +   "SPL image BSS too big");
> +#endif
> +
> +#if defined(CONFIG_SPL_MAX_FOOTPRINT)
> +ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
> +   "SPL image plus BSS too big");
> +#endif
> diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
> index f84b723bbb..d19e1d79ec 100644
> --- a/configs/evb-ast2600_defconfig
> +++ b/configs/evb-ast2600_defconfig
> @@ -1,6 +1,7 @@
>  CONFIG_ARM=y
>  CONFIG_SYS_DCACHE_OFF=y
>  CONFIG_SPL_SYS_THUMB_BUILD=y
> +CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds"
>  CONFIG_ARCH_ASPEED=y
>  CONFIG_SYS_TEXT_BASE=0x8000
>  CONFIG_SYS_MALLOC_LEN=0x200
> @@ -35,6 +36,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
>  CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>  CONFIG_SPL_STACK_R=y
>  CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
> +CONFIG_SPL_SEPARATE_BSS=y
> +# CONFIG_TPL_SEPARATE_BSS is not se

[PATCH] aspeed/ast2600: Fix SPL linker script

[Joel Stanley]

The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove .
prefix") changed the name of the linker list sections. As the Aspeed SPL
linker wasn't in the tree yet, it missed the change.

This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which
Aspeed was copied from.

Fixes: 442a69c14375 ("configs: ast2600: Move SPL bss section to DRAM space")
Signed-off-by: Joel Stanley 
---

Note that the Aspeed script is still missing the following sections,
which would be a problem if --orphan-handling=warn or similar was added
to LDFLAGS in the future (or if some used data ended up in one of these
sections):

   .dynsym _image_binary_end : { *(.dynsym) }
   .dynbss : { *(.dynbss) }
   .dynstr : { *(.dynstr*) }
   .dynamic : { *(.dynamic*) }
   .hash : { *(.hash*) }
   .plt : { *(.plt*) }
   .interp : { *(.interp*) }
   .gnu : { *(.gnu*) }
   .ARM.exidx : { *(.ARM.exidx*) }

I assume we're safe because they're relating to dynamic objects, so we
don't generate any.

The following sections are not accounted for in both the aspeed linker script 
and
the generic arm one:

 orphan section `.vfp11_veneer' from `linker stubs' being placed in section 
`.vfp11_veneer'
 orphan section `.v4_bx' from `linker stubs' being placed in section `.v4_bx'
 orphan section `.iplt' from `arch/arm/cpu/armv7/start.o' being placed in 
section `.iplt'
 orphan section `.igot.plt' from `arch/arm/cpu/armv7/start.o' being placed in 
section `.igot.plt'

I assume they're not required as u-boot works without them.

 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds 
b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index 22b4e16d35c5..95a509ba3f31 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -40,8 +40,8 @@ SECTIONS
} > .nor
 
. = ALIGN(4);
-   .u_boot_list : {
-   KEEP(*(SORT(.u_boot_list*)));
+   __u_boot_list : {
+   KEEP(*(SORT(__u_boot_list*)));
} > .nor
 
. = ALIGN(4);
@@ -68,7 +68,7 @@ SECTIONS
 
_image_binary_end = .;
 
-   .bss : {
+   .bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
 . = ALIGN(4);
-- 
2.35.1

[PATCH v2 0/7] aspeed: Add AST2600 machine to CI

[Joel Stanley]

The Aspeed AST2600 is modelled in Qemu. This makes some configuration
changes so it can be added to CI.

v2 changes:

The u-boot-test-hooks patches are now merged.

I reworked "ast2600: Configure u-boot-with-spl.bin target" to use the
kconfig SPL_MAX_SIZE. The size is set in the previous patch as a
Kconfig default.

Included in the series is also a fix to the linker script, that resolves
an issue I introduced with the previous fix.

I've added the reviews from Cédric and Chia-Wei to the patches they
approved in v1.

The tests have passed a CI run on Azure:

 https://dev.azure.com/u-boot/u-boot/_build/results?buildId=4607

Joel Stanley (7):
  config/ast2600: Enable CRC32
  config/ast2600: Make position independent
  config/ast2600: Disable hash hardware accel
  spl: Set SPL_MAX_SIZE default for AST2600
  ast2600: Configure u-boot-with-spl.bin target
  aspeed/spl: Remove OVERLAY from linker script
  CI: Add Aspeed AST2600

 .azure-pipelines.yml| 3 +++
 .gitlab-ci.yml  | 6 ++
 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 2 +-
 common/spl/Kconfig  | 1 +
 configs/evb-ast2600_defconfig   | 7 ---
 5 files changed, 15 insertions(+), 4 deletions(-)

-- 
2.35.1

[PATCH v2 1/7] config/ast2600: Enable CRC32

[Joel Stanley]

Useful for testing images with the default hash type.

Reviewed-by: Chia-Wei Wang 
Reviewed-by: Cédric Le Goater 
Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index a91a53da4fc2..867401f101dc 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
 CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
-- 
2.35.1

[PATCH v2 2/7] config/ast2600: Make position independent

[Joel Stanley]

Allows loading one u-boot from another. Useful for testing on hardware.

Reviewed-by: Chia-Wei Wang 
Reviewed-by: Cédric Le Goater 
Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 867401f101dc..07784fe8ac62 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds"
 CONFIG_ARCH_ASPEED=y
-- 
2.35.1

[PATCH v2 3/7] config/ast2600: Disable hash hardware accel

[Joel Stanley]

The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to enable
boot testing in Qemu.

Reviewed-by: Chia-Wei Wang 
Reviewed-by: Cédric Le Goater 
Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 07784fe8ac62..03f90c7818b7 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -66,9 +66,6 @@ CONFIG_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
-- 
2.35.1

[PATCH v2 4/7] spl: Set SPL_MAX_SIZE default for AST2600

[Joel Stanley]

The AST2600 bootrom has a max size of 64KB. This can be overridden if the
system is running the SPL from SPI NOR and not using secure boot.

Signed-off-by: Joel Stanley 
---
New in v2

 common/spl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2ad2351c6eb3..e37aece46eb7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -82,6 +82,7 @@ config SPL_MAX_SIZE
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x2 && !MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+   default 0x1 if ASPEED_AST2600
default 0x0
help
  Maximum size of the SPL image (text, data, rodata, and linker lists
-- 
2.35.1

[PATCH v2 5/7] ast2600: Configure u-boot-with-spl.bin target

[Joel Stanley]

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

The u-boot-with-spl.bin target will add padding according to
CONFIG_SPL_MAX_SIZE which defaults to 64KB on the AST2600.

With this the following simple steps can be used to build and boot a
system:

  make u-boot-with-spl.bin
  truncate -s 64M u-boot-with-spl.bin
  qemu-system-arm -nographic -M ast2600-evb \
-drive file=u-boot-with-spl.bin,if=mtd,format=raw

Reviewed-by: Cédric Le Goater 
Reviewed-by: Chia-Wei Wang 
Signed-off-by: Joel Stanley 
---
v2:
 Removed the change to include/configs/evb_ast2600.h

 configs/evb-ast2600_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 03f90c7818b7..51261e730f3b 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -21,6 +21,8 @@ CONFIG_SPL_SIZE_LIMIT=0x1
 CONFIG_SPL=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_SPL_FIT_SIGNATURE=y
-- 
2.35.1

[PATCH v2 6/7] aspeed/spl: Remove OVERLAY from linker script

[Joel Stanley]

The generic arm linker script contains this section:

   .bss __rel_dyn_start (OVERLAY) : {
   ...
   }

The (OVERLAY) syntax in the description causes the .bss section to be
included in the NOR area of the image:

 $ objdump -t -j .bss spl/u-boot-spl
  SYMBOL TABLE:
  c61c ld  .bss  .bss
  c640 l O .bss 0040 __value.0
  c68c g O .bss  __bss_end
  c61c g O .bss  __bss_start
  c680 g O .bss 000c stdio_devices

This is what the custom linker script tries to avoid, as the NOR area is
read-only.

Remove the OVERLAY syntax to fix the BSS location:

 $ objdump -t -j .bss spl/u-boot-spl
  SYMBOL TABLE:
  8300 ld  .bss  .bss
  8300 l O .bss 0040 __value.0
  c61c g O .bss  __image_copy_end
  834c g O .bss  __bss_end
  8300 g O .bss  __bss_start
  8340 g O .bss 000c stdio_devices

This restores the state of the linker script before the patch that fixed
the linker lists issue.

Fixes: f6810b749f2e ("aspeed/ast2600: Fix SPL linker script")
Signed-off-by: Joel Stanley 
---
I missed this in testing as I also had "image: fit: Use stack allocation
macro" in my tree. The image now boots without that fix (and with it).

I don't understand why __rel_dyn_start is included in the section name.
I'm removing it to restore what was there before, however the image
boots regardless of it's inclusion.

 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds 
b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index 95a509ba3f31..37f0ccd92201 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -68,7 +68,7 @@ SECTIONS
 
_image_binary_end = .;
 
-   .bss __rel_dyn_start (OVERLAY) : {
+   .bss : {
__bss_start = .;
*(.bss*)
 . = ALIGN(4);
-- 
2.35.1

[PATCH v2 7/7] CI: Add Aspeed AST2600

[Joel Stanley]

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Reviewed-by: Chia-Wei Wang 
Reviewed-by: Cédric Le Goater 
Signed-off-by: Joel Stanley 
---
 .azure-pipelines.yml | 3 +++
 .gitlab-ci.yml   | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 915d5115b12d..bc2b437bd999 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -261,6 +261,9 @@ stages:
 evb_ast2500:
   TEST_PY_BD: "evb-ast2500"
   TEST_PY_ID: "--id qemu"
+evb_ast2600:
+  TEST_PY_BD: "evb-ast2600"
+  TEST_PY_ID: "--id qemu"
 vexpress_ca9x4:
   TEST_PY_BD: "vexpress_ca9x4"
   TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c6a608f7e2a7..f9cd41750791 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -272,6 +272,12 @@ evb-ast2500 test.py:
 TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
+evb-ast2600 test.py:
+  variables:
+TEST_PY_BD: "evb-ast2600"
+TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
 sandbox_flattree test.py:
   variables:
 TEST_PY_BD: "sandbox_flattree"
-- 
2.35.1

Re: [PATCH RESEND 4/5] ast2600: Configure u-boot-with-spl.bin target

[Joel Stanley]

On Tue, 28 Jun 2022 at 14:19, Tom Rini  wrote:
>
> On Mon, Jun 27, 2022 at 05:28:10PM +0930, Joel Stanley wrote:
>
> > For the u-boot-with-spl.bin target to be useful for the AST2600, set the
> > maximum SPL size which also sets the padding length.
> >
> > The normal way of loading u-boot is as a FIT, so configure u-boot.img as
> > the SPL playload.
> >
> > With this the following simple steps can be used to build and boot a
> > system:
> >
> >   make u-boot-with-spl.bin
> >   truncate -s 64M u-boot-with-spl.bin
> >   qemu-system-arm -nographic -M ast2600-evb \
> >     -drive file=u-boot-with-spl.bin,if=mtd,format=raw
> >
> > Signed-off-by: Joel Stanley 
> > Reviewed-by: Chia-Wei Wang 
> > Reviewed-by: Cédric Le Goater 
>
> This doesn't quite apply correct now as CONFIG_SPL_MAX_SIZE is in
> Kconfig.  I migrated that manually but now CI doesn't run:
> https://source.denx.de/u-boot/u-boot/-/jobs/457298
> so I wonder if I migrated it wrong, or something else.

Thanks for trying! I've recently worked out that development is
happening on the next branch, whereas my patches last week were sent
against master. I've rebased this series on next and have sent them
out.

> To be clear, I have applied
> https://patchwork.ozlabs.org/project/uboot/patch/20220628042725.217333-1-j...@jms.id.au/
> first.

The linker script fix is required, but I accidentally introduced a new
bug in that one. It was masked because in my testing I also had the
image/fit stack allocation fix in my tree, which avoids the issue with
writing to the bss.

 
http://patchwork.ozlabs.org/project/uboot/patch/20220620070117.3443066-1-j...@jms.id.au/

I included a linker script fix for the new bug in v2 of the series:

 https://lore.kernel.org/u-boot/20220629070525.575426-1-j...@jms.id.au/

Cheers,

Joel

[PATCH v3 0/3] Enable NC-SI support

[Joel Stanley]

Back in 2019 Sam submitted NC-SI support. The NC-SI PHY driver was
merged (patches 1 and 2), but we never got around to merging patches 3
and 4:

 https://lore.kernel.org/u-boot/20190618013720.2823-1-...@mendozajonas.com/

Sam as long since moved on from working on the Aspeed BMCs, but the code
has been in use in the vendor fork for some time.

This refreshes his patches and enables support in the Aspeed defconfigs,
giving compile coverage to the NC-SI phy.

I've called the series v3 to indicate it fixes issues in v2 of Sam's
series. Changelogs in each patch.

Joel Stanley (1):
  config/aspeed: Enable NC-SI support

Samuel Mendoza-Jonas (2):
  net: NC-SI setup and handling
  net/ftgmac100: Add NC-SI mode support

 include/net.h |  2 +-
 include/phy.h |  2 ++
 cmd/net.c | 22 ++
 drivers/net/ftgmac100.c   | 14 ++
 drivers/net/phy/ncsi.c|  1 +
 drivers/net/phy/phy.c |  9 -
 net/net.c | 27 ++-
 cmd/Kconfig   |  8 
 configs/evb-ast2500_defconfig |  2 ++
 configs/evb-ast2600_defconfig |  2 ++
 10 files changed, 82 insertions(+), 7 deletions(-)

-- 
2.35.1

[PATCH v3 1/3] net: NC-SI setup and handling

[Joel Stanley]

From: Samuel Mendoza-Jonas 

Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.
This also adds an "ncsi" command to manually start NC-SI configuration.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 
---
v3:
 - Fix compilation. There were no configs that enabled the NCSI phy code
   so it had bitrotted
 - Use NCSI_PHY instead of CMD_NCSI so NCSI can work without the command
 - Add phy_interface_is_ncsi() helper, thanks Cédric for this suggestion
 - Only create NCSI phy device when driver is configured for it

 include/net.h  |  2 +-
 include/phy.h  |  2 ++
 cmd/net.c  | 22 ++
 drivers/net/phy/ncsi.c |  1 +
 drivers/net/phy/phy.c  |  9 -
 net/net.c  | 27 ++-
 cmd/Kconfig|  8 
 7 files changed, 68 insertions(+), 3 deletions(-)

diff --git a/include/net.h b/include/net.h
index e3889a0bc85e..0681b8246323 100644
--- a/include/net.h
+++ b/include/net.h
@@ -558,7 +558,7 @@ extern int  net_restart_wrap;   /* Tried all 
network devices */
 
 enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP
+   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI
 };
 
 extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/include/phy.h b/include/phy.h
index b32959571069..1e0f8856f629 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -583,6 +583,8 @@ static inline bool phy_interface_is_sgmii(struct phy_device 
*phydev)
phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 }
 
+bool phy_interface_is_ncsi(void);
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340 0x13e51002
 #define PHY_UID_CS4223 0x03e57003
diff --git a/cmd/net.c b/cmd/net.c
index 3619c843d838..2863fe768118 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const 
[]);
 
@@ -524,3 +525,24 @@ U_BOOT_CMD(
"list - list available devices\n"
 );
 #endif // CONFIG_DM_ETH
+
+#if defined(CONFIG_CMD_NCSI)
+static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const 
argv[])
+{
+   if (!phy_interface_is_ncsi() || !ncsi_active()) {
+   printf("Device not configured for NC-SI\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (net_loop(NCSI) < 0)
+   return CMD_RET_FAILURE;
+
+   return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+   ncsi,   1,  1,  do_ncsi,
+   "Configure attached NIC via NC-SI",
+   ""
+);
+#endif  /* CONFIG_CMD_NCSI */
diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index bf1e832be9f1..bb7ecebed382 100644
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1121b99abff5..d04538838852 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1026,7 +1026,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int 
addr,
 #endif
 
 #ifdef CONFIG_PHY_NCSI
-   if (!phydev)
+   if (!phydev && interface == PHY_INTERFACE_MODE_NCSI)
phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
 #endif
 
@@ -1101,3 +1101,10 @@ int phy_modify(struct phy_device *phydev, int devad, int 
regnum, u16 mask,
 
return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
 }
+
+bool phy_interface_is_ncsi(void)
+{
+   struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
+
+   return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+}
diff --git a/net/net.c b/net/net.c
index 81905f631592..a4e645ac4425 100644
--- a/net/net.c
+++ b/net/net.c
@@ -93,6 +93,7 @@
 #include 
 #include 
 #include 
+#include 
 #if defined(CONFIG_CMD_PCAP)
 #include 
 #endif
@@ -410,6 +411,16 @@ int net_loop(enum proto_t protocol)
net_try_count = 1;
debug_cond(DEBUG_INT_STATE, "--- net_loop Entry\n");
 
+#ifdef CONFIG_PHY_NCSI
+   if (phy_interface_is_ncsi() && protocol != NCSI && !ncsi_active()) {
+   printf("%s: configuring NCSI first\n", __func__);
+   if (net_loop(NCSI) < 0)
+   return ret;
+   eth_init_state_only();
+   goto restart;
+   }
+#endif
+
bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
net_init();
if (eth_is_on_demand_init()) {
@@ -423,6 +434,7 @@ int net_loop(enum proto_t protocol)
} else {
eth_init_state_only();
}
+
 restart:
 #ifdef CONFIG_USB_KE

[PATCH v3 2/3] net/ftgmac100: Add NC-SI mode support

[Joel Stanley]

From: Samuel Mendoza-Jonas 

Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.

NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio setup is
skipped in favour of the NC-SI phy.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 
---
v3:
 - Simplify ncsi enable by re-using pdata->phy_interface parsing.
   use-ncsi still overrides this value.
 - Fix up freeing in remove callback per Joe's review

 drivers/net/ftgmac100.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 78779d7d60b9..69370ea5cca2 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -188,7 +188,7 @@ static int ftgmac100_phy_adjust_link(struct ftgmac100_data 
*priv)
struct phy_device *phydev = priv->phydev;
u32 maccr;
 
-   if (!phydev->link) {
+   if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
dev_err(phydev->dev, "No link\n");
return -EREMOTEIO;
}
@@ -228,7 +228,8 @@ static int ftgmac100_phy_init(struct udevice *dev)
if (!phydev)
return -ENODEV;
 
-   phydev->supported &= PHY_GBIT_FEATURES;
+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+   phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
if (ret)
@@ -308,7 +309,8 @@ static void ftgmac100_stop(struct udevice *dev)
 
writel(0, &ftgmac100->maccr);
 
-   phy_shutdown(priv->phydev);
+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+   phy_shutdown(priv->phydev);
 }
 
 static int ftgmac100_start(struct udevice *dev)
@@ -580,6 +582,9 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
 
+   if (dev_read_bool(dev, "use-ncsi"))
+   priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
+
 #ifdef CONFIG_PHY_ADDR
priv->phy_addr = CONFIG_PHY_ADDR;
 #endif
@@ -592,7 +597,8 @@ static int ftgmac100_probe(struct udevice *dev)
 * If DM MDIO is enabled, the MDIO bus will be initialized later in
 * dm_eth_phy_connect
 */
-   if (!IS_ENABLED(CONFIG_DM_MDIO)) {
+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
+   !IS_ENABLED(CONFIG_DM_MDIO)) {
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
-- 
2.35.1

[PATCH v3 3/3] config/aspeed: Enable NC-SI support

[Joel Stanley]

Aspeed BMCs are commonly used with NC-SI. A system indicates the driver
should configure the link over NC-SI using the device tree.

Add it to the defconfig so we get compile coverage of the driver, even
if the EVBs do not normally use it.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2500_defconfig | 2 ++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 9d2c4f81c5ad..866732117aa7 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -38,6 +39,7 @@ CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
 CONFIG_DM_ETH=y
 CONFIG_FTGMAC100=y
 CONFIG_PHY=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 5c4d8426607c..8be22014bb4e 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -54,6 +54,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -73,6 +74,7 @@ CONFIG_MISC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ASPEED=y
 CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_FTGMAC100=y
-- 
2.35.1

Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

[Joel Stanley]

Hi Chin-Ting,

On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo
 wrote:
>
> Add ASPEED BMC FMC/SPI memory controller driver with
> spi-mem interface for AST2500 and AST2600 platform.

Have you considered including 2400 support in your patch set?

I have prepared a series that adds upstream support for the 2400. We
already have support in other drivers (gpio, i2c, sdhci, timer, wdt)
so there's no blocker in including support in your patch.

Cheers,

Joel

>
> There are three SPI memory controllers embedded in an ASPEED SoC.
> - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
>fetches initial device boot image from FMC chip select(CS) 0.
>
> - SPI1: Play the role of a SPI Master controller. Or, there is a
> dedicated path for HOST(X86) to access its BIOS flash mounted
> under BMC. spi-aspeed.c implements the control sequence when
> SPI1 is a SPI master.
>
> - SPI2: It is a pure SPI flash controller. For most scenarios, flashes
> mounted under it are for pure storage purpose.
>
> ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
> Three types of command mode are supported, normal mode, command
> read/write mode and user mode.
> - Normal mode: Default mode. After power on, normal read command 03h or
>13h is used to fetch boot image from SPI flash.
>- AST2500: Only 03h command can be used after power on
>   or reset.
>- AST2600: If FMC04[6:4] is set, 13h command is used,
>   otherwise, 03h command.
>The address length is decided by FMC04[2:0].
>
> - Command mode: SPI controller can send command and address
> automatically when CPU read/write the related remapped
> or decoded address area. The command used by this mode
> can be configured by FMC10/14/18[23:16]. Also, the
> address length is decided by FMC04[2:0]. This mode will
> be implemented in the following patch series.
>
> - User mode: It is a traditional and pure SPI operation, where
>  SPI transmission is controlled by CPU. It is the main
>  mode in this patch.
>
> Each SPI controller in ASPEED SoC has its own decoded address mapping.
> Within each SPI controller decoded address, driver can assign a specific
> address region for each CS of a SPI controller. The decoded address
> cannot overlap to each other. With normal mode and command mode, the
> decoded address accessed by the CPU determines which CS is active.
> When user mode is adopted, the CS decoded address is a FIFO, CPU can
> send/receive any SPI transmission by accessing the related decoded
> address for the target CS.
>
> Signed-off-by: Chin-Ting Kuo 
> ---
> v2: Remove defconfig files from this patch.
>
>  drivers/spi/Kconfig  |   8 +
>  drivers/spi/Makefile |   1 +
>  drivers/spi/spi-aspeed.c | 822 +++
>  3 files changed, 831 insertions(+)
>  create mode 100644 drivers/spi/spi-aspeed.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index a1e515cb2b..a616294910 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -387,6 +387,14 @@ config SANDBOX_SPI
> };
>   };
>
> +config SPI_ASPEED
> +   bool "ASPEED SPI controller driver"
> +   depends on DM_SPI && SPI_MEM
> +   default n
> +   help
> + Enable ASPEED SPI controller driver for AST2500
> + and AST2600 SoCs.
> +
>  config SPI_SIFIVE
> bool "SiFive SPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 06e81b465b..36a4bd5dce 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -9,6 +9,7 @@ obj-y += spi-uclass.o
>  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>  obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
>  obj-$(CONFIG_SOFT_SPI) += soft_spi.o
> +obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o
>  obj-$(CONFIG_SPI_MEM) += spi-mem.o
>  obj-$(CONFIG_TI_QSPI) += ti_qspi.o
>  obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
> diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
> new file mode 100644
> index 00..9574aff793
> --- /dev/null
> +++ b/drivers/spi/spi-aspeed.c
> @@ -0,0 +1,822 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * ASPEED FMC/SPI Controller driver
> + *
> + * Copyright (c) 2022 ASPEED Corporation.
> + * Copyright (c) 2022 IBM Corporation.
> + *
> + * Author:
> + * Chin-Ting Kuo 
> + * Cedric Le Goater 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* ASPEED FMC/SPI memory control register related */
> +#define REG_CE_TYPE_SETTING  0x00
> +#define REG_CE_ADDR_MODE_CTRL0x04
> +#define REG_INTR_CTRL_STATUS 0x08
> +#define REG_CE0_CTRL_REG  

Re: [PATCH v4 0/4] net: Enable NC-SI support

[Joel Stanley]

On Thu, 15 Sept 2022 at 01:11, Joel Stanley  wrote:
>
> On Tue, 23 Aug 2022 at 04:54, Joel Stanley  wrote:
> >
> > On Mon, 8 Aug 2022 at 12:16, Joel Stanley  wrote:
> > >
> > > Back in 2019 Sam submitted NC-SI support. The NC-SI PHY driver was
> > > merged (patches 1 and 2), but we never got around to merging patches 3
> > > and 4:
> > >
> > >  
> > > https://lore.kernel.org/u-boot/20190618013720.2823-1-...@mendozajonas.com/
> > >
> > > Sam as long since moved on from working on the Aspeed BMCs, but the code
> > > has been in use in the vendor fork for some time.
> > >
> > > This refreshes his patches and enables support in the Aspeed defconfigs,
> > > giving compile coverage to the NC-SI phy.
> > >
> > > v4 splits the ncsi integration and cmd code into separate patches, and
> > > adds r-b from Ramon and Cédric to patches 3 and 4.
> >
> > We have review on these patches now. Can we get them merged?
>
> ping

Hello! Is there anything I can do to help get these merged?

>
> >
> > >
> > > Joel Stanley (1):
> > >   config/aspeed: Enable NC-SI support
> > >
> > > Samuel Mendoza-Jonas (3):
> > >   net: NC-SI setup and handling
> > >   cmd: Add ncsi command
> > >   net/ftgmac100: Add NC-SI mode support
> > >
> > >  include/net.h |  2 +-
> > >  include/phy.h |  2 ++
> > >  cmd/net.c | 22 ++
> > >  drivers/net/ftgmac100.c   | 14 ++
> > >  drivers/net/phy/ncsi.c|  1 +
> > >  drivers/net/phy/phy.c |  9 -
> > >  net/net.c | 27 ++-
> > >  cmd/Kconfig   |  8 
> > >  configs/evb-ast2500_defconfig |  2 ++
> > >  configs/evb-ast2600_defconfig |  2 ++
> > >  10 files changed, 82 insertions(+), 7 deletions(-)
> > >
> > > --
> > > 2.35.1
> > >

Re: [PATCH 1/4] configs: evb-ast2500: Remove MMC support from default settings

[Joel Stanley]

On Wed, 26 Oct 2022 at 13:11, Cédric Le Goater  wrote:
>
> This saves ~50K in the resulting u-boot.bin file which is important to
> fit in the U-Boot partition defined in the flash layout of upstream Linux.

The downside is we stop testing it builds for ast2500. I guess as long
as it's being built for the 2600 that's okay?

>
> Signed-off-by: Cédric Le Goater 
> ---
>  configs/evb-ast2500_defconfig | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index 500c85b8d500..ad0feeb71df5 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -23,7 +23,7 @@ CONFIG_SYS_PBSIZE=276
>  CONFIG_CMD_EEPROM=y
>  CONFIG_CMD_GPIO=y
>  CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> +# CONFIG_CMD_MMC is not set
>  CONFIG_CMD_DHCP=y
>  CONFIG_BOOTP_BOOTFILESIZE=y
>  CONFIG_CMD_MII=y
> @@ -38,8 +38,7 @@ CONFIG_ASPEED_GPIO=y
>  CONFIG_DM_I2C=y
>  CONFIG_SYS_I2C_ASPEED=y
>  CONFIG_I2C_EEPROM=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_ASPEED=y
> +# CONFIG_MMC is not set
>  CONFIG_DM_SPI_FLASH=y
>  CONFIG_SPI_FLASH_SFDP_SUPPORT=y
>  CONFIG_SPI_FLASH_GIGADEVICE=y
> --
> 2.37.3
>

Re: [PATCH 2/4] configs: evb-ast2500: Adjust boot command

[Joel Stanley]

On Wed, 26 Oct 2022 at 13:11, Cédric Le Goater  wrote:
>
> Loading a kernel image is enough.
>
> Signed-off-by: Cédric Le Goater 

Reviewed-by: Joel Stanley 

> ---
>  configs/evb-ast2500_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index ad0feeb71df5..8646e6944803 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -13,7 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x8300
>  CONFIG_USE_BOOTARGS=y
>  CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
>  CONFIG_USE_BOOTCOMMAND=y
> -CONFIG_BOOTCOMMAND="bootm 2008 2030"
> +CONFIG_BOOTCOMMAND="bootm 2008"
>  CONFIG_PRE_CONSOLE_BUFFER=y
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_HUSH_PARSER=y
> --
> 2.37.3
>

Re: [PATCH 3/4] configs: evb-ast2500: Add support for FIT format

[Joel Stanley]

On Wed, 26 Oct 2022 at 13:11, Cédric Le Goater  wrote:
>
> Signed-off-by: Cédric Le Goater 

Reviewed-by: Joel Stanley 

> ---
>  configs/evb-ast2500_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index 8646e6944803..5364b6ac3703 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y
>  CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
>  CONFIG_PRE_CON_BUF_ADDR=0x1e72
>  CONFIG_SYS_LOAD_ADDR=0x8300
> +CONFIG_FIT=y
>  CONFIG_USE_BOOTARGS=y
>  CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
>  CONFIG_USE_BOOTCOMMAND=y
> --
> 2.37.3
>

Re: [PATCH 4/4] configs: evb-ast2500: Set environment in SPI flash

[Joel Stanley]

On Wed, 26 Oct 2022 at 13:11, Cédric Le Goater  wrote:
>
> We now have a SPI flash driver. Let's use it.
>
> Signed-off-by: Cédric Le Goater 

Reviewed-by: Joel Stanley 

> ---
>  configs/evb-ast2500_defconfig | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index 5364b6ac3703..65a7056ebdbf 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -5,7 +5,9 @@ CONFIG_SYS_TEXT_BASE=0x0
>  CONFIG_SYS_MALLOC_LEN=0x200
>  CONFIG_TARGET_EVB_AST2500=y
>  CONFIG_NR_DRAM_BANKS=1
> -CONFIG_ENV_SIZE=0x2
> +CONFIG_ENV_SIZE=0x1
> +CONFIG_ENV_OFFSET=0x6
> +CONFIG_ENV_SECT_SIZE=0x1000
>  CONFIG_DM_GPIO=y
>  CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
>  CONFIG_PRE_CON_BUF_ADDR=0x1e72
> @@ -31,6 +33,7 @@ CONFIG_CMD_MII=y
>  CONFIG_CMD_PING=y
>  CONFIG_CMD_NCSI=y
>  CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>  CONFIG_NET_RANDOM_ETHADDR=y
>  CONFIG_REGMAP=y
> --
> 2.37.3
>

Re: [PATCH 2/2] tpm: add support for TPMv2.x I2C chips

[Joel Stanley]

  .read32 = tpm_tis_i2c_read32,
> +   .write32 = tpm_tis_i2c_write32,
> +};
> +
> +static int tpm_tis_i2c_probe(struct udevice *udev)
> +{
> +   struct tpm_tis_chip_data *drv_data = (void 
> *)dev_get_driver_data(udev);
> +   struct tpm_chip_priv *priv = dev_get_uclass_priv(udev);
> +   int rc;
> +   u8 loc = 0;
> +
> +   tpm_tis_ops_register(udev, &phy_ops);
> +
> +   /*
> +* Force locality 0. The core driver doesn't actually write the
> +* locality register and instead just reads/writes various access
> +* bits of the selected locality.
> +*/
> +   rc = dm_i2c_write(udev, 0, &loc, 1);
> +   if (rc)
> +   return rc;
> +
> +   rc = tpm_tis_init(udev);
> +   if (rc)
> +   return rc;
> +
> +   priv->pcr_count = drv_data->pcr_count;
> +   priv->pcr_select_min = drv_data->pcr_select_min;
> +   priv->version = TPM_V2;
> +
> +   return 0;
> +}
> +
> +static int tpm_tis_i2c_remove(struct udevice *udev)
 > +{
> +   return tpm_tis_cleanup(udev);
> +}
> +
> +static const struct tpm_ops tpm_tis_i2c_ops = {
> +   .open = tpm_tis_open,
> +   .close = tpm_tis_close,
> +   .get_desc = tpm_tis_get_desc,
> +   .send = tpm_tis_send,
> +   .recv = tpm_tis_recv,
> +   .cleanup = tpm_tis_cleanup,
> +};
> +
> +static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
> +   .pcr_count = 24,
> +   .pcr_select_min = 3,
> +};
> +
> +static const struct udevice_id tpm_tis_i2c_ids[] = {
> +   {
> +   .compatible = "nuvoton,npct75x",
> +   .data = (ulong)&tpm_tis_std_chip_data,
> +   },
> +   {
> +   .compatible = "tcg,tpm-tis-i2c",
> +   .data = (ulong)&tpm_tis_std_chip_data,

The .data pointers are the same, so could we do away with it all
together and just have

#define TPM_TIS_I2C_PCR_COUNT 24
#define TPM_TIS_I2C_PCR_SELECT_MIN 3

Aside from that small cleanup:

Reviewed-by: Joel Stanley 


> +   },
> +   { }
> +};
> +
> +U_BOOT_DRIVER(tpm_tis_i2c) = {
> +   .name = "tpm_tis_i2c",
> +   .id = UCLASS_TPM,
> +   .of_match = tpm_tis_i2c_ids,
> +   .ops = &tpm_tis_i2c_ops,
> +   .probe = tpm_tis_i2c_probe,
> +   .remove = tpm_tis_i2c_remove,
> +   .priv_auto_alloc_size = sizeof(struct tpm_chip),
> +};
> --
> 2.27.0
>