[PATCH 0/2] Add HS configs for J7200 and J721S2 TI SOCs

[Jayesh Choudhary]

This series adds the r5 and a72 defconfigs for 2 platforms:
- J7200 HS
- J721S2 HS

Andrew Davis (1):
  configs: Add configs for J7200 High Security EVM

Jayesh Choudhary (1):
  configs: Add configs for j721s2 High Security EVM

 MAINTAINERS |   4 +
 configs/j7200_hs_evm_a72_defconfig  | 208 ++
 configs/j7200_hs_evm_r5_defconfig   | 172 ++
 configs/j721s2_hs_evm_a72_defconfig | 217 
 configs/j721s2_hs_evm_r5_defconfig  | 178 +++
 5 files changed, 779 insertions(+)
 create mode 100644 configs/j7200_hs_evm_a72_defconfig
 create mode 100644 configs/j7200_hs_evm_r5_defconfig
 create mode 100644 configs/j721s2_hs_evm_a72_defconfig
 create mode 100644 configs/j721s2_hs_evm_r5_defconfig

-- 
2.25.1

[PATCH 1/2] configs: Add configs for J7200 High Security EVM

[Jayesh Choudhary]

From: Andrew Davis 

Add J7200 High Security EVM defconfig.

These defconfigs are the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_BOOTCOMMAND uses FIT images for booting

Signed-off-by: Andrew Davis 
[j-choudh...@ti.com: add few configs from GP variant which were missing]
Signed-off-by: Jayesh Choudhary 
---
 MAINTAINERS|   2 +
 configs/j7200_hs_evm_a72_defconfig | 208 +
 configs/j7200_hs_evm_r5_defconfig  | 172 
 3 files changed, 382 insertions(+)
 create mode 100644 configs/j7200_hs_evm_a72_defconfig
 create mode 100644 configs/j7200_hs_evm_r5_defconfig

diff --git a/MAINTAINERS b/MAINTAINERS
index 36a2b69fcb..e7c9a7359d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1377,6 +1377,8 @@ F:configs/am65x_hs_evm_r5_defconfig
 F: configs/am65x_hs_evm_a53_defconfig
 F: configs/j721e_hs_evm_r5_defconfig
 F: configs/j721e_hs_evm_a72_defconfig
+F: configs/j7200_hs_evm_r5_defconfig
+F: configs/j7200_hs_evm_a72_defconfig
 
 TPM DRIVERS
 M: Ilias Apalodimas 
diff --git a/configs/j7200_hs_evm_a72_defconfig 
b/configs/j7200_hs_evm_a72_defconfig
new file mode 100644
index 00..0583a2ab62
--- /dev/null
+++ b/configs/j7200_hs_evm_a72_defconfig
@@ -0,0 +1,208 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x200
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J7200_A72_EVM=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0x68
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_ENV_OFFSET_REDUND=0x6A
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run 
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_MAX_SIZE=0xc
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a0
+CONFIG_SPL_BSS_MAX_SIZE=0x8
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_DMA_CHANNELS=

[PATCH 2/2] configs: Add configs for j721s2 High Security EVM

[Jayesh Choudhary]

Add j721s2 High Security EVM defconfig.

These configs are same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_BOOTCOMMAND uses FIT images for booting

Signed-off-by: Jayesh Choudhary 
---
 MAINTAINERS |   2 +
 configs/j721s2_hs_evm_a72_defconfig | 217 
 configs/j721s2_hs_evm_r5_defconfig  | 178 +++
 3 files changed, 397 insertions(+)
 create mode 100644 configs/j721s2_hs_evm_a72_defconfig
 create mode 100644 configs/j721s2_hs_evm_r5_defconfig

diff --git a/MAINTAINERS b/MAINTAINERS
index e7c9a7359d..763b6cd529 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1379,6 +1379,8 @@ F:configs/j721e_hs_evm_r5_defconfig
 F: configs/j721e_hs_evm_a72_defconfig
 F: configs/j7200_hs_evm_r5_defconfig
 F: configs/j7200_hs_evm_a72_defconfig
+F: configs/j721s2_hs_evm_r5_defconfig
+F: configs/j721s2_hs_evm_a72_defconfig
 
 TPM DRIVERS
 M: Ilias Apalodimas 
diff --git a/configs/j721s2_hs_evm_a72_defconfig 
b/configs/j721s2_hs_evm_a72_defconfig
new file mode 100644
index 00..851c98577d
--- /dev/null
+++ b/configs/j721s2_hs_evm_a72_defconfig
@@ -0,0 +1,217 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x200
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0x68
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_ENV_OFFSET_REDUND=0x6A
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run 
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_MAX_SIZE=0xc
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a0
+CONFIG_SPL_BSS_MAX_SIZE=0x8
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_

[PATCH] arch: mach-k3: j721s2_init: Disable the firewalls

[Jayesh Choudhary]

Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721s2_init.c | 53 ++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 09e55ed456..7d347b5156 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -22,6 +22,51 @@
 #include 
 #include 
 
+struct fwl_data cbass_hc_cfg0_fwls[] = {
+   { "PCIE0_CFG", 2577, 7 },
+   { "EMMC8SS0_CFG", 2579, 4 },
+   { "USB3SS0_CORE", 2580, 4 },
+   { "USB3SS1_CORE", 2581, 1 },
+}, cbass_hc2_fwls[] = {
+   { "PCIE0", 2547, 24 },
+   { "HC2_WIZ16B8M4CT2", 2552, 1 },
+}, cbass_rc_cfg0_fwls[] = {
+   { "EMMCSD4SS0_CFG", 2400, 4 },
+}, infra_cbass0_fwls[] = {
+   { "PSC0", 5, 1 },
+   { "PLL_CTRL0", 6, 1 },
+   { "PLL_MMR0", 8, 26 },
+   { "CTRL_MMR0", 9, 16 },
+   { "GPIO0", 16, 1 },
+}, mcu_cbass0_fwls[] = {
+   { "MCU_R5FSS0_CORE0", 1024, 4 },
+   { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
+   { "MCU_R5FSS0_CORE1", 1028, 4 },
+   { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
+   { "MCU_FSS0_CFG", 1032, 12 },
+   { "MCU_FSS0_S1", 1033, 8 },
+   { "MCU_FSS0_S0", 1036, 8 },
+   { "MCU_PSROM49152X32", 1048, 1 },
+   { "MCU_MSRAM128KX64", 1050, 8 },
+   { "MCU_MSRAM128KX64_CFG", 1051, 1 },
+   { "MCU_TIMER0", 1056, 1 },
+   { "MCU_TIMER9", 1065, 1 },
+   { "MCU_USART0", 1120, 1 },
+   { "MCU_I2C0", 1152, 1 },
+   { "MCU_CTRL_MMR0", 1200, 8 },
+   { "MCU_PLL_MMR0", 1201, 3 },
+   { "MCU_CPSW0", 1220, 2 },
+}, wkup_cbass0_fwls[] = {
+   { "WKUP_PSC0", 129, 1 },
+   { "WKUP_PLL_CTRL0", 130, 1 },
+   { "WKUP_CTRL_MMR0", 131, 16 },
+   { "WKUP_GPIO0", 132, 1 },
+   { "WKUP_I2C0", 144, 1 },
+   { "WKUP_USART0", 160, 1 },
+}, navss_cbass0_fwls[] = {
+   { "NACSS_VIRT0", 6253, 1 },
+};
+
 static void ctrl_mmr_unlock(void)
 {
/* Unlock all WKUP_CTRL_MMR0 module registers */
@@ -150,6 +195,14 @@ void k3_spl_init(void)
if (ret)
panic("Failed to initialize clk-k3!\n");
}
+
+   remove_fwl_configs(cbass_hc_cfg0_fwls, 
ARRAY_SIZE(cbass_hc_cfg0_fwls));
+   remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
+   remove_fwl_configs(cbass_rc_cfg0_fwls, 
ARRAY_SIZE(cbass_rc_cfg0_fwls));
+   remove_fwl_configs(infra_cbass0_fwls, 
ARRAY_SIZE(infra_cbass0_fwls));
+   remove_fwl_configs(mcu_cbass0_fwls, 
ARRAY_SIZE(mcu_cbass0_fwls));
+   remove_fwl_configs(wkup_cbass0_fwls, 
ARRAY_SIZE(wkup_cbass0_fwls));
+   remove_fwl_configs(navss_cbass0_fwls, 
ARRAY_SIZE(navss_cbass0_fwls));
}
 
/* Output System Firmware version info */
-- 
2.25.1

[PATCH 09/14] arch: mach-k3: Introduce basic files to support J722S SoC family

[Jayesh Choudhary]

Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/Kconfig  |   7 +-
 arch/arm/mach-k3/Makefile |   1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   4 +
 .../arm/mach-k3/include/mach/j722s_hardware.h |  83 ++
 arch/arm/mach-k3/include/mach/j722s_spl.h |  49 
 arch/arm/mach-k3/include/mach/spl.h   |   4 +
 arch/arm/mach-k3/j722s/Kconfig|  32 ++
 arch/arm/mach-k3/j722s/Makefile   |   6 +
 arch/arm/mach-k3/j722s/j722s_init.c   | 277 ++
 9 files changed, 462 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
 create mode 100644 arch/arm/mach-k3/j722s/Kconfig
 create mode 100644 arch/arm/mach-k3/j722s/Makefile
 create mode 100644 arch/arm/mach-k3/j722s/j722s_init.c

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2bb970c2d4..f3f42b3921 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -25,6 +25,9 @@ config SOC_K3_J721E
 config SOC_K3_J721S2
bool "TI's K3 based J721S2 SoC Family Support"
 
+config SOC_K3_J722S
+   bool "TI's K3 based J722S SoC Family Support"
+
 config SOC_K3_J784S4
bool "TI's K3 based J784S4 SoC Family Support"
 
@@ -84,6 +87,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
default 0x43c4f290 if SOC_K3_AM62P5
+   default 0x43c7f290 if SOC_K3_J722S
help
  Address at which ROM stores the value which determines if SPL
  is booted up by primary boot media or secondary boot media.
@@ -122,7 +126,7 @@ config K3_EARLY_CONS_IDX
 
 config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
-   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
+   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 
|| SOC_K3_J722S)
default 0x7000
help
  The load address for the ATF image. This value is used to build the
@@ -163,6 +167,7 @@ source "arch/arm/mach-k3/am62ax/Kconfig"
 source "arch/arm/mach-k3/am62px/Kconfig"
 source "arch/arm/mach-k3/j721e/Kconfig"
 source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j722s/Kconfig"
 source "arch/arm/mach-k3/j784s4/Kconfig"
 
 endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 2b3ebd5c53..8c4f6786a5 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_SOC_K3_AM642) += am64x/
 obj-$(CONFIG_SOC_K3_AM654) += am65x/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index 26c5bfcf76..86e3e6b355 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -36,6 +36,10 @@
 #include "j721s2_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J722S
+#include "j722s_hardware.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h 
b/arch/arm/mach-k3/include/mach/j722s_hardware.h
new file mode 100644
index 00..8d0bec2206
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J722S SoC definitions, structures etc.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __ASM_ARCH_J722S_HARDWARE_H
+#define __ASM_ARCH_J722S_HARDWARE_H
+
+#include 
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#define PADCFG_MMR0_BASE   0x0408
+#define PADCFG_MMR1_BASE   0x000f
+#define CTRL_MMR0_BASE 0x0010
+#define MCU_CTRL_MMR0_BASE 0x0450
+#define WKUP_CTRL_MMR0_BASE0x4300
+
+#define CTRLMMR_MAIN_DEVSTAT   (WKUP_CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT3
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT7
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK  GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK  BIT(13)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SH

[PATCH 11/14] firmware: ti_sci_static_data: Add static DMA channel

[Jayesh Choudhary]

Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 drivers/firmware/ti_sci_static_data.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/ti_sci_static_data.h 
b/drivers/firmware/ti_sci_static_data.h
index 9662bd95f2..3370f80231 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -85,7 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 #endif /* CONFIG_SOC_K3_J721S2 */
 
 #if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
-   IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S)
 static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
-- 
2.25.1

[PATCH 10/14] board: ti: Introduce basic board files for the J722S family

[Jayesh Choudhary]

Introduce the basic files needed to support the TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 board/ti/j722s/Kconfig  |   26 +
 board/ti/j722s/MAINTAINERS  |9 +
 board/ti/j722s/Makefile |7 +
 board/ti/j722s/board-cfg.yaml   |   36 +
 board/ti/j722s/evm.c|   29 +
 board/ti/j722s/j722s.env|   15 +
 board/ti/j722s/pm-cfg.yaml  |   12 +
 board/ti/j722s/rm-cfg.yaml  | 1119 +++
 board/ti/j722s/sec-cfg.yaml |  379 +++
 board/ti/j722s/tifs-rm-cfg.yaml |  981 +++
 10 files changed, 2613 insertions(+)
 create mode 100644 board/ti/j722s/Kconfig
 create mode 100644 board/ti/j722s/MAINTAINERS
 create mode 100644 board/ti/j722s/Makefile
 create mode 100644 board/ti/j722s/board-cfg.yaml
 create mode 100644 board/ti/j722s/evm.c
 create mode 100644 board/ti/j722s/j722s.env
 create mode 100644 board/ti/j722s/pm-cfg.yaml
 create mode 100644 board/ti/j722s/rm-cfg.yaml
 create mode 100644 board/ti/j722s/sec-cfg.yaml
 create mode 100644 board/ti/j722s/tifs-rm-cfg.yaml

diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig
new file mode 100644
index 00..68c214e473
--- /dev/null
+++ b/board/ti/j722s/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM
+
+config SYS_BOARD
+   default "j722s"
+
+config SYS_VENDOR
+   default "ti"
+
+config SYS_CONFIG_NAME
+   default "j722s_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_EVM
+
+config SPL_LDSCRIPT
+   default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS
new file mode 100644
index 00..7908c30def
--- /dev/null
+++ b/board/ti/j722s/MAINTAINERS
@@ -0,0 +1,9 @@
+J722S BOARD
+M: Vaishnav Achath 
+M: Jayesh Choudhary 
+M: Tom Rini 
+S: Maintained
+F: board/ti/j722s/
+F: include/configs/j722s_evm.h
+F: configs/j722s_evm_r5_defconfig
+F: configs/j722s_evm_a53_defconfig
diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile
new file mode 100644
index 00..20d2ec934b
--- /dev/null
+++ b/board/ti/j722s/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evm.o
diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml
new file mode 100644
index 00..f9a4c438ca
--- /dev/null
+++ b/board/ti/j722s/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable: 0x5A
+main_isolation_hostid: 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor: 0x1
+scaling_profile: 0x1
+disable_main_nav_secure_proxy: 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size: 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables: 0x00
+trace_src_enables: 0x00
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
new file mode 100644
index 00..515aaa8187
--- /dev/null
+++ b/board/ti/j722s/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J722S platforms
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int board_init(void)
+{
+   return 0;
+}
+
+int dram_init(void)
+{
+   return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+   return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
new file mode 100644
index 00..f8b6aff2c2
--- /dev/null
+++ b/board/ti/j722s/j722s.env
@@ -0,0 +1,15 @@
+#include 
+#include 
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+   ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml
new file mode 100644
index 00..46b3ad2010
--- /dev/null
+++ b/board/ti/j722s/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https:

[PATCH 13/14] configs: introduce configs needed for the J722S

[Jayesh Choudhary]

Introduce the initial configs needed to support the J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 configs/j722s_evm_a53_defconfig | 177 
 configs/j722s_evm_r5_defconfig  | 137 
 include/configs/j722s_evm.h |  14 +++
 3 files changed, 328 insertions(+)
 create mode 100644 configs/j722s_evm_a53_defconfig
 create mode 100644 configs/j722s_evm_r5_defconfig
 create mode 100644 include/configs/j722s_evm.h

diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
new file mode 100644
index 00..8d29c9601b
--- /dev/null
+++ b/configs/j722s_evm_a53_defconfig
@@ -0,0 +1,177 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+CONFIG_SF_DEFAULT_SPEED=2500
+CONFIG_ENV_SIZE=0x4
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a0
+CONFIG_SPL_BSS_MAX_SIZE=0x8
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET

[PATCH 14/14] doc: board: ti: Add J722S-EVM documentation

[Jayesh Choudhary]

Introduce basic documentation for the J722S-EVM.

Signed-off-by: Jayesh Choudhary 
---
 doc/board/ti/j722s_evm.rst | 260 +
 doc/board/ti/k3.rst|   1 +
 2 files changed, 261 insertions(+)
 create mode 100644 doc/board/ti/j722s_evm.rst

diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
new file mode 100644
index 00..10b243908a
--- /dev/null
+++ b/doc/board/ti/j722s_evm.rst
@@ -0,0 +1,260 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jayesh Choudhary 
+
+J722S-EVM Platform
+==
+
+The J722S is a family of  application processors built for Automotive and
+Linux Application development. J722S family of SoCs is a superset of the
+AM62P SoC family and shares similar memory map, thus the nodes are being
+reused from AM62P includes instead of duplicating the definitions.
+
+Some highlights of J722S SoC (in addition to AM62P SoC features) are:
+
+* Two Cortex-R5F for Functional Safety or general-purpose usage and
+  two C7x floating point vector DSP with Matrix Multiply Accelerator
+  for deep learning.
+
+* Vision Processing Accelerator (VPAC) with image signal processor
+  and Depth and Motion Processing Accelerator (DMPAC).
+
+* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
+  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
+  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
+  ePWM, among other peripherals.
+
+For those interested, more details about this SoC can be found in the
+Technical Reference Manual here: https://www.ti.com/lit/zip/sprujb3
+
+Boot Flow:
+--
+
+The bootflow is exactly the same as all SoCs in the am62xxx extended SoC
+family. Below is the pictorial representation:
+
+.. image:: img/boot_diagram_k3_current.svg
+  :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+  requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+
+
+0. Setup the environment variables:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. j722s_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_tfa
+:end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_optee
+:end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_spl_r5
+:end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_uboot
+:end-before: .. k3_rst_include_end_build_steps_uboot
+.. j722s_evm_rst_include_end_build_steps
+
+Target Images
+--
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img.  Each SoC
+variant (HS-FS, HS-SE) requires a different source for these files.
+
+ - HS-FS
+
+* tiboot3-j722s-hs-fs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+* tiboot3-j722s-hs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+  :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+  :alt: tispl.bin image format
+
+A53 SPL DDR Memory Layout
+-
+
+.. j722s_evm_rst_include_start_ddr_mem_layout
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+ - Start Address
+ - End Address
+
+   * - EMPTY
+ - 0x8000
+ - 0x8008
+
+   * - TEXT BASE
+ - 0x8008
+ - 0x800d8000
+
+   * - EMPTY
+ - 0x800d8000
+ - 0x80477660
+
+   * - STACK
+ - 0x80477660
+ - 0x80477e60
+
+   * - GD
+ - 0x80477e60
+ - 0x80478000
+
+   * - MALLOC
+ - 0x80478000
+ - 

[PATCH 12/14] arm: dts: Introduce J722S U-Boot dts files

[Jayesh Choudhary]

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/dts/Makefile  |2 +
 arch/arm/dts/k3-j722s-binman.dtsi  |  172 ++
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   18 +
 arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
 5 files changed, 3069 insertions(+)
 create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f7032f1e17..65d56354ab 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1207,6 +1207,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += 
k3-am68-sk-r5-base-board.dtb\
 dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
   k3-j784s4-r5-evm.dtb
 
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
  k3-am642-r5-sk.dtb \
  k3-am642-r5-phycore-som-2gb.dtb
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi 
b/arch/arm/dts/k3-j722s-binman.dtsi
new file mode 100644
index 00..28087a3b6f
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
+
+&binman {
+   tiboot3-j722s-hs-fs-evm.bin {
+   filename = "tiboot3-j722s-hs-fs-evm.bin";
+   symlink = "tiboot3.bin";
+
+   ti-secure-rom {
+   content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, 
<&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <&u_boot_spl_fs>;
+   content-sysfw = <&ti_fs_enc_fs>;
+   content-sysfw-data = <&combined_tifs_cfg_fs>;
+   content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+   content-dm-data = <&combined_dm_cfg_fs>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c7a800>;
+   };
+
+   u_boot_spl_fs: u-boot-spl {
+   no-expanded;
+   };
+
+   ti_fs_enc_fs: ti-fs-enc.bin {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   type = "blob-ext";
+   };
+
+   sysfw_inner_cert_fs: sysfw-inner-cert {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_dm_cfg_fs: combined-dm-cfg.bin {
+   filename = "combined-dm-cfg.bin";
+   type = "blob-ext";
+   };
+   };
+};
+#endif /*CONFIG_TARGET_J722S_R5_EVM*/
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_EVM)
+
+#define SPL_J722S_EVM_DTB "spl/dts/ti/k3-j722s-evm.dtb"
+#define J722S_EVM_DTB "u-boot.dtb"
+
+&binman {
+   ti-dm {
+   filename = "ti-dm.bin";
+
+   blob-ext {
+   filename = 
"ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+   optional;
+   };
+   };
+
+   ti-spl {
+   insert-template = <&ti_spl_template>;
+
+   fit {
+   images {
+   dm {
+   ti-secure {
+   content = <&dm>;
+   keyfile = "custMpk.pem";
+   };
+
+   dm: ti-dm {
+  

Re: [PATCH 03/14] soc: add info to identify the J722S SoC family

[Jayesh Choudhary]

Hello Andrew,

On 29/05/24 20:36, Andrew Davis wrote:

On 5/29/24 8:24 AM, Jayesh Choudhary wrote:

Include the part number for TI's j722s family of SoC
to identify it during boot.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/include/mach/hardware.h | 2 ++
  drivers/soc/soc_ti_k3.c  | 3 +++
  2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h

index c3aaded8dc..26c5bfcf76 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -55,6 +55,7 @@
  #define JTAG_ID_PARTNO_J7200    0xbb6d
  #define JTAG_ID_PARTNO_J721E    0xbb64
  #define JTAG_ID_PARTNO_J721S2    0xbb75
+#define JTAG_ID_PARTNO_J722S    0xbba0


All the others use tab, you used spaces here. Personally I like spaces
for alignment, but unless you fix all the others, stick with tab for now.


Okay! Will fix it in v2.

-Jayesh




  #define JTAG_ID_PARTNO_J784S4    0xbb80
  #define K3_SOC_ID(id, ID) \
@@ -72,6 +73,7 @@ K3_SOC_ID(am65x, AM65X)
  K3_SOC_ID(j7200, J7200)
  K3_SOC_ID(j721e, J721E)
  K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(j722s, J722S)
  #define K3_SEC_MGR_SYS_STATUS    0x44234100
  #define SYS_STATUS_DEV_TYPE_SHIFT    0
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 0838808515..f948914d21 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -47,6 +47,9 @@ static const char *get_family_string(u32 idreg)
  case JTAG_ID_PARTNO_J721S2:
  family = "J721S2";
  break;
+    case JTAG_ID_PARTNO_J722S:
+    family = "J722S";
+    break;
  case JTAG_ID_PARTNO_J784S4:
  family = "J784S4";
  break;

Re: [PATCH 01/14] arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries

[Jayesh Choudhary]

Hello Andrew,

On 29/05/24 20:35, Andrew Davis wrote:

On 5/29/24 8:24 AM, Jayesh Choudhary wrote:

Sort CONFIG_SOC* and K3_SOC_ID alphabetically.


Why? I kinda like the chronological order we have today, helps me remember
what are the newer/older parts. Which then helps in seeing where the line
is between when features are added, all parts after have it, etc..

No issue with alphabetical either, just looking for a "why" in the
commit message, otherwise,


TI SoC J784S4-EVM UBOOT series had few such cleanups.
So while posting this series, for files which I was touching,
if such generic cleanups seemed appropriate, I did it.



Reviewed-by: Andrew Davis 



Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/include/mach/hardware.h | 37 
  1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h

index c724450638..c3aaded8dc 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -8,37 +8,38 @@
  #include 
-#ifdef CONFIG_SOC_K3_AM654
-#include "am6_hardware.h"
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
  #endif
-#ifdef CONFIG_SOC_K3_J721E
-#include "j721e_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62A7
+#include "am62a_hardware.h"
  #endif
-#ifdef CONFIG_SOC_K3_J721S2
-#include "j721s2_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62P5
+#include "am62p_hardware.h"
  #endif
  #ifdef CONFIG_SOC_K3_AM642
  #include "am64_hardware.h"
  #endif
-#ifdef CONFIG_SOC_K3_AM625
-#include "am62_hardware.h"
+#ifdef CONFIG_SOC_K3_AM654
+#include "am6_hardware.h"
  #endif
-#ifdef CONFIG_SOC_K3_AM62A7
-#include "am62a_hardware.h"
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
  #endif
  #ifdef CONFIG_SOC_K3_J784S4
  #include "j784s4_hardware.h"
  #endif
-#ifdef CONFIG_SOC_K3_AM62P5
-#include "am62p_hardware.h"
-#endif
  /* Assuming these addresses and definitions stay common across K3 
devices */

  #define CTRLMMR_WKUP_JTAG_ID    (WKUP_CTRL_MMR0_BASE + 0x14)
@@ -63,14 +64,14 @@ static inline bool soc_is_##id(void) \
  JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
  return soc == JTAG_ID_PARTNO_##ID; \
  }
-K3_SOC_ID(am65x, AM65X)
-K3_SOC_ID(j721e, J721E)
-K3_SOC_ID(j7200, J7200)
-K3_SOC_ID(am64x, AM64X)
-K3_SOC_ID(j721s2, J721S2)
  K3_SOC_ID(am62x, AM62X)
  K3_SOC_ID(am62ax, AM62AX)
  K3_SOC_ID(am62px, AM62PX)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j721s2, J721S2)
  #define K3_SEC_MGR_SYS_STATUS    0x44234100
  #define SYS_STATUS_DEV_TYPE_SHIFT    0

Re: [PATCH 09/14] arch: mach-k3: Introduce basic files to support J722S SoC family

[Jayesh Choudhary]

Hello Andrew,

Thanks for the review.

On 29/05/24 20:47, Andrew Davis wrote:

On 5/29/24 8:24 AM, Jayesh Choudhary wrote:

Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/Kconfig  |   7 +-
  arch/arm/mach-k3/Makefile |   1 +
  arch/arm/mach-k3/include/mach/hardware.h  |   4 +
  .../arm/mach-k3/include/mach/j722s_hardware.h |  83 ++
  arch/arm/mach-k3/include/mach/j722s_spl.h |  49 
  arch/arm/mach-k3/include/mach/spl.h   |   4 +
  arch/arm/mach-k3/j722s/Kconfig    |  32 ++
  arch/arm/mach-k3/j722s/Makefile   |   6 +
  arch/arm/mach-k3/j722s/j722s_init.c   | 277 ++
  9 files changed, 462 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
  create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
  create mode 100644 arch/arm/mach-k3/j722s/Kconfig
  create mode 100644 arch/arm/mach-k3/j722s/Makefile
  create mode 100644 arch/arm/mach-k3/j722s/j722s_init.c

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2bb970c2d4..f3f42b3921 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -25,6 +25,9 @@ config SOC_K3_J721E
  config SOC_K3_J721S2
  bool "TI's K3 based J721S2 SoC Family Support"
+config SOC_K3_J722S
+    bool "TI's K3 based J722S SoC Family Support"
+
  config SOC_K3_J784S4
  bool "TI's K3 based J784S4 SoC Family Support"
@@ -84,6 +87,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
  default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
  default 0x7000f290 if SOC_K3_AM62A7 && ARM64
  default 0x43c4f290 if SOC_K3_AM62P5
+    default 0x43c7f290 if SOC_K3_J722S
  help
    Address at which ROM stores the value which determines if SPL
    is booted up by primary boot media or secondary boot media.
@@ -122,7 +126,7 @@ config K3_EARLY_CONS_IDX
  config K3_ATF_LOAD_ADDR
  hex "Load address of ATF image"
-    default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || 
SOC_K3_AM62P5)
+    default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || 
SOC_K3_AM62P5 || SOC_K3_J722S)


You may need to fixup the DT if it uses the old address. You'll
need to do the same as done for AM62p here:

https://patchwork.ozlabs.org/project/uboot/patch/20240520-am62p-fdt-fix-v1-1-49845dcb3...@ti.com/

Andrew


Will add this fixup in v2 series!

Warm Regards,
-Jayesh


[...]

Re: [PATCH 09/14] arch: mach-k3: Introduce basic files to support J722S SoC family

[Jayesh Choudhary]

Hello Neha,

Thanks for the review.

On 30/05/24 08:15, Neha Malcom Francis wrote:

Hi Jayesh

On 29/05/24 18:54, Jayesh Choudhary wrote:

Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/Kconfig  |   7 +-
  arch/arm/mach-k3/Makefile |   1 +
  arch/arm/mach-k3/include/mach/hardware.h  |   4 +
  .../arm/mach-k3/include/mach/j722s_hardware.h |  83 ++
  arch/arm/mach-k3/include/mach/j722s_spl.h |  49 
  arch/arm/mach-k3/include/mach/spl.h   |   4 +
  arch/arm/mach-k3/j722s/Kconfig    |  32 ++
  arch/arm/mach-k3/j722s/Makefile   |   6 +
  arch/arm/mach-k3/j722s/j722s_init.c   | 277 ++
  9 files changed, 462 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
  create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
  create mode 100644 arch/arm/mach-k3/j722s/Kconfig
  create mode 100644 arch/arm/mach-k3/j722s/Makefile
  create mode 100644 arch/arm/mach-k3/j722s/j722s_init.c



[...]


+
+void board_init_f(ulong dummy)
+{


J784S4 went through quite a bit of revisions and I personally would like 
to use it as an example (for now) for our code layout for all future 
devices until we cleanup further. See [1] where it was addressed to have 
board_init_f split up into calling smaller logical functions instead.


[1] 
https://lore.kernel.org/u-boot/20240103162504.xgbx73pnmthtzthl@vengeful/




Okay!
I will make the simpler flow for board_init_f similar to maybe j721s2.

Warm Regards,
Jayesh



+    struct udevice *dev;
+    int ret;
+
+    if (IS_ENABLED(CONFIG_CPU_V7R))
+    setup_k3_mpu_regions();
+
+    /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC 
section.

+ */
+    store_boot_info_from_rom();
+
+    ctrl_mmr_unlock();
+
+    /* Init DM early */
+    ret = spl_early_init();
+    if (ret)
+    panic("spl_early_init() failed: %d\n", ret);
+
+    /*
+ * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and 
continue


[...]

Re: [PATCH 1/7] arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file

[Jayesh Choudhary]

Hello Tom, Andrew,

On 23/05/24 04:36, Tom Rini wrote:

On Wed, May 22, 2024 at 10:21:28AM -0500, Andrew Davis wrote:

On 5/22/24 6:37 AM, Jayesh Choudhary wrote:

QoS bit mapping are common across all K3 SoCs so move those defines
to common header file (k3_qos.h).
This ensures that we do not define these for each SoC.

Signed-off-by: Jayesh Choudhary 
---
   arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++
   arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 --
   2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h 
b/arch/arm/mach-k3/include/mach/k3-qos.h
index e00e1de5b9..6ed5704803 100644
--- a/arch/arm/mach-k3/include/mach/k3-qos.h
+++ b/arch/arm/mach-k3/include/mach/k3-qos.h
@@ -9,6 +9,80 @@
   #include 
+#define QOS_0  (0 << 0)
+#define QOS_1  (1 << 0)
+#define QOS_2  (2 << 0)
+#define QOS_3  (3 << 0)
+#define QOS_4  (4 << 0)
+#define QOS_5  (5 << 0)
+#define QOS_6  (6 << 0)
+#define QOS_7  (7 << 0)
+
+#define ORDERID_0  (0 << 4)
+#define ORDERID_1  (1 << 4)
+#define ORDERID_2  (2 << 4)
+#define ORDERID_3  (3 << 4)
+#define ORDERID_4  (4 << 4)
+#define ORDERID_5  (5 << 4)
+#define ORDERID_6  (6 << 4)
+#define ORDERID_7  (7 << 4)
+#define ORDERID_8  (8 << 4)
+#define ORDERID_9  (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10(10 << 8)
+#define ASEL_11(11 << 8)
+#define ASEL_12(12 << 8)
+#define ASEL_13(13 << 8)
+#define ASEL_14(14 << 8)
+#define ASEL_15(15 << 8)
+
+#define EPRIORITY_0(0 << 12)
+#define EPRIORITY_1(1 << 12)
+#define EPRIORITY_2(2 << 12)
+#define EPRIORITY_3(3 << 12)
+#define EPRIORITY_4(4 << 12)
+#define EPRIORITY_5(5 << 12)
+#define EPRIORITY_6(6 << 12)
+#define EPRIORITY_7(7 << 12)
+
+#define VIRTID_0   (0 << 16)
+#define VIRTID_1   (1 << 16)
+#define VIRTID_2   (2 << 16)
+#define VIRTID_3   (3 << 16)
+#define VIRTID_4   (4 << 16)
+#define VIRTID_5   (5 << 16)
+#define VIRTID_6   (6 << 16)
+#define VIRTID_7   (7 << 16)
+#define VIRTID_8   (8 << 16)
+#define VIRTID_9   (9 << 16)
+#define VIRTID_10  (10 << 16)
+#define VIRTID_11  (11 << 16)
+#define VIRTID_12  (12 << 16)
+#define VIRTID_13  (13 << 16)
+#define VIRTID_14  (14 << 16)
+#define VIRTID_15  (15 << 16)



This all seem like it could be made into some macro, something like

#define K3_QOS(qos, orderid, asel, epriority, virtid, atype) \
(qos << 0 | \
 orderid << 4 | \
 asel<< 8 | \
etc..

Then use that instead of raw values. That might also make it more clear
we are setting the other values to 0 when we are setting these registers:

.val = K3_QOS(0, 15, 0, 0, 0, 3),


This sounds good to me too and to be clear, move in one patch, clean up
macro follow-up patch in this series.



Okay so 1st patch will be similar to this.
And in the next patch, macros will be defined and cleanup for
arch/arm/mach-k3/r5/am62a/am62ax_qos_uboot.c will be done in an atomic
step.
Rest of the platforms will be added after that.

Also, just for clarity, this implies changes in k3-resource-partitioning
tool which would be generating these files.
So is it okay to post v2 with manual changes here and then picking up
the changes in the tool later according to the final file template that
we settle on?

Warm Regards,
Jayesh

Re: [PATCH 2/7] arm: mach-k3: j721e: Enable QoS for DSS

[Jayesh Choudhary]

Hello Andrew,

On 22/05/24 21:14, Andrew Davis wrote:

On 5/22/24 6:37 AM, Jayesh Choudhary wrote:

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
ATYPE 3 is selected so that the traffic takes non-coherent path and does


So this is the part I'm not sure about, this change is not just a 
performance
adjustment, it can and does break things. The ORDERID setting is fine 
with me,
but changing ATYPE should be done in a separate patch so it can be 
debated on

its own.


not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM 
sources

using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/j721e/j721e_init.c |  28 +
  arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
  arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
  arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 
  4 files changed, 250 insertions(+)
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c

index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c



[...]

diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c 
b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

new file mode 100644
index 00..c829057200
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j721e Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ */
+
+#include 
+#include "j721e_qos.h"
+
+struct k3_qos_data qos_data[] = {
+    /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0,


0x100 being the instance, and 0x4 * x being the specific device register 
right?

That could be encoded in a macro (the "Resource Partitioning tool" would
be updated to generate that too).

Andrew



Okay both val and reg could be updated.


+    .val = ATYPE_3 | ORDERID_15,
+    },
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1,
+    .val = ATYPE_3 | ORDERID_15,
+    },


[...]


+
+    /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+    /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0,
+    .val = 0x76543210,
+    },
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4,
+    .val = 0xfedcba98,
+    },


From the looks of it, these register and val can also be encoded as
K3_QOS_GROUP_REG and K3_QOS_GROUP_VAL_HIGH (0xfedcba98) and
K3_QOS_GROUP_VAL_LOW (0x76543210)

[...]


+
+u32 qos_count = ARRAY_SIZE(qos_data);

[PATCH v2 01/14] arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries

[Jayesh Choudhary]

Sort CONFIG_SOC* and K3_SOC_ID alphabetically.

Signed-off-by: Jayesh Choudhary 
Reviewed-by: Andrew Davis 
Reviewed-by: Neha Malcom Francis 
---
 arch/arm/mach-k3/include/mach/hardware.h | 37 
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index c724450638..c3aaded8dc 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -8,37 +8,38 @@
 
 #include 
 
-#ifdef CONFIG_SOC_K3_AM654
-#include "am6_hardware.h"
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721E
-#include "j721e_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62A7
+#include "am62a_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721S2
-#include "j721s2_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62P5
+#include "am62p_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_AM642
 #include "am64_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM625
-#include "am62_hardware.h"
+#ifdef CONFIG_SOC_K3_AM654
+#include "am6_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62A7
-#include "am62a_hardware.h"
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62P5
-#include "am62p_hardware.h"
-#endif
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_ID   (WKUP_CTRL_MMR0_BASE + 0x14)
@@ -63,14 +64,14 @@ static inline bool soc_is_##id(void) \
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
return soc == JTAG_ID_PARTNO_##ID; \
 }
-K3_SOC_ID(am65x, AM65X)
-K3_SOC_ID(j721e, J721E)
-K3_SOC_ID(j7200, J7200)
-K3_SOC_ID(am64x, AM64X)
-K3_SOC_ID(j721s2, J721S2)
 K3_SOC_ID(am62x, AM62X)
 K3_SOC_ID(am62ax, AM62AX)
 K3_SOC_ID(am62px, AM62PX)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j721s2, J721S2)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
-- 
2.25.1

[PATCH v2 03/14] soc: add info to identify the J722S SoC family

[Jayesh Choudhary]

Include the part number for TI's j722s family of SoC
to identify it during boot.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/hardware.h | 2 ++
 drivers/soc/soc_ti_k3.c  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index c3aaded8dc..1024ee6872 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -55,6 +55,7 @@
 #define JTAG_ID_PARTNO_J7200   0xbb6d
 #define JTAG_ID_PARTNO_J721E   0xbb64
 #define JTAG_ID_PARTNO_J721S2  0xbb75
+#define JTAG_ID_PARTNO_J722S   0xbba0
 #define JTAG_ID_PARTNO_J784S4  0xbb80
 
 #define K3_SOC_ID(id, ID) \
@@ -72,6 +73,7 @@ K3_SOC_ID(am65x, AM65X)
 K3_SOC_ID(j7200, J7200)
 K3_SOC_ID(j721e, J721E)
 K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(j722s, J722S)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 0838808515..f948914d21 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -47,6 +47,9 @@ static const char *get_family_string(u32 idreg)
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
+   case JTAG_ID_PARTNO_J722S:
+   family = "J722S";
+   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-- 
2.25.1

[PATCH v2 04/14] clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order

[Jayesh Choudhary]

Use IS_ENABLED macro for the platform clock-data list and add them
in alphabetical order.

Reviewed-by: Bryan Brattlof 
Signed-off-by: Jayesh Choudhary 
---
 drivers/clk/ti/clk-k3.c | 41 +
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 41e5022ea0..9e17755c24 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -59,6 +59,24 @@ static void clk_add_map(struct ti_clk_data *data, struct clk 
*clk,
 }
 
 static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_clk_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -68,35 +86,18 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = &j7200_clk_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = &j721s2_clk_platdata,
},
 #endif
-#ifdef CONFIG_SOC_K3_AM625
-   {
-   .family = "AM62X",
-   .data = &am62x_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_AM62A7
-   {
-   .family = "AM62AX",
-   .data = &am62ax_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_J784S4
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_clk_platdata,
},
-#endif
-#ifdef CONFIG_SOC_K3_AM62P5
-   {
-   .family = "AM62PX",
-   .data = &am62px_clk_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[PATCH v2 00/14] Add basic U-Boot Support for J722S-EVM

[Jayesh Choudhary]

Hello there,

This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.

Some highlights of J722S SoC (in addition to AM62P SoC features) are:

- Two Cortex-R5F for Functional Safety or general-purpose usage and
  two C7x floating point vector DSP with Matrix Multiply Accelerator
  for deep learning.
  
- Vision Processing Accelerator (VPAC) with image signal processor
  and Depth and Motion Processing Accelerator (DMPAC).

- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
  ePWM, among other peripherals.
  
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>

Boot test log:
<https://gist.github.com/Jayesh2000/0313e58fde377f877a9a8f1acc2579ef>

v1 patch:
<https://patchwork.ozlabs.org/project/uboot/list/?series=408713>

Changelog v1->v2:
- Fix space tab inconsistency in [3/14]
- Break board_init_f into smaller logical functions as suggested by
  Neha[7]
- Add DT fixup as suggested by Andrew[8]
- Sync configs with savedefconfig to take care of redundant and invalid
  configs.
- Pick up R-by for rest of the patches.

RFC series that was posted before this:
<https://lore.kernel.org/all/20240404090039.87458-1-j-choudh...@ti.com/>

Changes from RFC series to this series:
- Remove main_pktdma node and k3_sysreset node from
  k3-j722s-evm-u-boot.dtsi as suggested by Andrew[0]
  k3_sysreset will be taken care of in [1] which is not
  a real dependency for this series
- Fix documentation according to comments here[2]
- Pick up R-by for 2 patches from RFC series[3][4]
- Pick the binman change for optional DM[5]
- Move init code according to [6]


[0]: https://lore.kernel.org/all/d738eaaf-6f13-4502-98a1-ef1bfe82d...@ti.com/
[1]: https://lore.kernel.org/all/20240402160908.508974-3-...@ti.com/
[2]: https://lore.kernel.org/all/ac5780c5-f1ca-4138-a027-d3ed65911...@ti.com/
[3]: 
https://lore.kernel.org/all/20240404163641.6qmcierya6svc...@bryanbrattlof.com/
[4]: 
https://lore.kernel.org/all/20240404163714.p2wonpenkiz44...@bryanbrattlof.com/
[5]: https://lore.kernel.org/all/20240529074849.363281-1-n-fran...@ti.com/
[6]: https://lore.kernel.org/all/20240510202124.794448-1-...@ti.com/
[7]: 
https://patchwork.ozlabs.org/project/uboot/patch/20240529132448.459330-10-j-choudh...@ti.com/#3319318
[8]: 
https://patchwork.ozlabs.org/project/uboot/patch/20240529132448.459330-10-j-choudh...@ti.com/#3318999

Jayesh Choudhary (14):
  arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries
  soc: ti: k3-socinfo: Fix SOC JTAG entry order
  soc: add info to identify the J722S SoC family
  clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order
  power: domain: ti: Fix the order for platform data entries
  arm: mach-k3: r5: Makefile: Fix the order for entries
  arm: mach-k3: j722s: introduce clock and device files for wkup spl
  ram: k3-ddrss: Enable the am62ax's DDR controller for J722S
  arch: mach-k3: Introduce basic files to support J722S SoC family
  board: ti: Introduce basic board files for the J722S family
  firmware: ti_sci_static_data: Add static DMA channel
  arm: dts: Introduce J722S U-Boot dts files
  configs: introduce configs needed for the J722S
  doc: board: ti: Add J722S-EVM documentation

 arch/arm/dts/Makefile |2 +
 arch/arm/dts/k3-j722s-binman.dtsi |  172 +
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi| 2795 +
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi |   18 +
 arch/arm/dts/k3-j722s-r5-evm.dts  |   82 +
 arch/arm/mach-k3/Kconfig  |7 +-
 arch/arm/mach-k3/Makefile |1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   43 +-
 .../arm/mach-k3/include/mach/j722s_hardware.h |   83 +
 arch/arm/mach-k3/include/mach/j722s_spl.h |   49 +
 arch/arm/mach-k3/include/mach/spl.h   |4 +
 arch/arm/mach-k3/j722s/Kconfig|   33 +
 arch/arm/mach-k3/j722s/Makefile   |7 +
 arch/arm/mach-k3/j722s/j722s_fdt.c|   16 +
 arch/arm/mach-k3/j722s/j722s_init.c   |  287 ++
 arch/arm/mach-k3/r5/Makefile  |7 +-
 arch/arm/mach-k3/r5/j722s/Makefile|6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c  |  312 ++
 arch/arm/mach-k3/r5/j722s/dev-data.c  |   69 +
 board/ti/j722s/Kconfig|   26 +
 board/ti/j722s/MAINTAINERS|9 +
 board/ti/j722s/Makefile   |7 +
 board/ti/j722s/board-cfg.yaml |   36 +
 board/ti/j722s/evm.c  |   29 +
 board/ti/j722s/j722s.env  |   15 +
 board/ti/j722s/pm-cfg.yaml  

[PATCH v2 05/14] power: domain: ti: Fix the order for platform data entries

[Jayesh Choudhary]

Add the power domain platform data entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
Reviewed-by: Neha Malcom Francis 
---
 drivers/power/domain/ti-power-domain.c | 36 +-
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
index b059dd3737..362fae86a2 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -71,6 +71,24 @@ static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 
reg)
 }
 
 static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_pd_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -87,29 +105,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.data = &j721s2_pd_platdata,
},
 #endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM625)
-   {
-   .family = "AM62X",
-   .data = &am62x_pd_platdata,
-   },
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
-   {
-   .family = "AM62AX",
-   .data = &am62ax_pd_platdata,
-   },
-#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_pd_platdata,
},
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
-   {
-   .family = "AM62PX",
-   .data = &am62px_pd_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[PATCH v2 02/14] soc: ti: k3-socinfo: Fix SOC JTAG entry order

[Jayesh Choudhary]

Add JTAG_ID_PARTNO_* in alphabetical order.

Signed-off-by: Jayesh Choudhary 
Reviewed-by: Neha Malcom Francis 
---
 drivers/soc/soc_ti_k3.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b585e47d46..0838808515 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -23,33 +23,33 @@ static const char *get_family_string(u32 idreg)
soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
switch (soc) {
+   case JTAG_ID_PARTNO_AM62X:
+   family = "AM62X";
+   break;
+   case JTAG_ID_PARTNO_AM62AX:
+   family = "AM62AX";
+   break;
+   case JTAG_ID_PARTNO_AM62PX:
+   family = "AM62PX";
+   break;
+   case JTAG_ID_PARTNO_AM64X:
+   family = "AM64X";
+   break;
case JTAG_ID_PARTNO_AM65X:
family = "AM65X";
break;
-   case JTAG_ID_PARTNO_J721E:
-   family = "J721E";
-   break;
case JTAG_ID_PARTNO_J7200:
family = "J7200";
break;
-   case JTAG_ID_PARTNO_AM64X:
-   family = "AM64X";
+   case JTAG_ID_PARTNO_J721E:
+   family = "J721E";
break;
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
-   case JTAG_ID_PARTNO_AM62X:
-   family = "AM62X";
-   break;
-   case JTAG_ID_PARTNO_AM62AX:
-   family = "AM62AX";
-   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-   case JTAG_ID_PARTNO_AM62PX:
-   family = "AM62PX";
-   break;
default:
family = "Unknown Silicon";
};
-- 
2.25.1

[PATCH v2 06/14] arm: mach-k3: r5: Makefile: Fix the order for entries

[Jayesh Choudhary]

Add the entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
Reviewed-by: Neha Malcom Francis 
---
 arch/arm/mach-k3/r5/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index 1cfc8e3ade..f1e61c8548 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -3,13 +3,13 @@
 # Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 #  Andrew Davis 
 
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
-obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 
 obj-y += common.o
 obj-y += lowlevel_init.o
-- 
2.25.1

[PATCH v2 07/14] arm: mach-k3: j722s: introduce clock and device files for wkup spl

[Jayesh Choudhary]

Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.

Reviewed-by: Bryan Brattlof 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/r5/Makefile   |   1 +
 arch/arm/mach-k3/r5/j722s/Makefile |   6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c   | 312 +
 arch/arm/mach-k3/r5/j722s/dev-data.c   |  69 ++
 drivers/clk/ti/clk-k3.c|   6 +
 drivers/power/domain/ti-power-domain.c |   6 +
 include/k3-clk.h   |   1 +
 include/k3-dev.h   |   1 +
 8 files changed, 402 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j722s/Makefile
 create mode 100644 arch/arm/mach-k3/r5/j722s/clk-data.c
 create mode 100644 arch/arm/mach-k3/r5/j722s/dev-data.c

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index f1e61c8548..d3886caa06 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
 
 obj-y += common.o
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile 
b/arch/arm/mach-k3/r5/j722s/Makefile
new file mode 100644
index 00..2a0dbf5f5a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c 
b/arch/arm/mach-k3/r5/j722s/clk-data.c
new file mode 100644
index 00..b4f27af333
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J722S specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   NULL,
+   NULL,
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_hfosc0_clkout",
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+   "board_0_mmc1_clklb_out",
+   "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+   "board_0_ospi0_dqs_out",
+   "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = 
{
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_2_hsdivout5_clk",
+   "postdiv4_16ff_main_0_hsdivout6_clk",
+   "board_0_cp_gemac_cpts0_rft_clk_out",
+   NULL,
+   "board_0_mcu_ext_refclk0_out",
+   "board_0_ext_refclk1_out",
+   "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+   "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_main_0_hsdivout1_clk",
+   "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "clk_32k_rc_sel_out0",
+   "postdiv4_16ff_main_0_hsdivout7_clk",
+   "g

[PATCH v2 08/14] ram: k3-ddrss: Enable the am62ax's DDR controller for J722S

[Jayesh Choudhary]

The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
Reviewed-by: Neha Malcom Francis 
---
 drivers/ram/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 9838a2798f..a64d2dff68 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,7 +65,7 @@ choice
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
-   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5
+   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
 
 config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
-- 
2.25.1

[PATCH v2 09/14] arch: mach-k3: Introduce basic files to support J722S SoC family

[Jayesh Choudhary]

Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/Kconfig  |   7 +-
 arch/arm/mach-k3/Makefile |   1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   4 +
 .../arm/mach-k3/include/mach/j722s_hardware.h |  83 +
 arch/arm/mach-k3/include/mach/j722s_spl.h |  49 +++
 arch/arm/mach-k3/include/mach/spl.h   |   4 +
 arch/arm/mach-k3/j722s/Kconfig|  33 ++
 arch/arm/mach-k3/j722s/Makefile   |   7 +
 arch/arm/mach-k3/j722s/j722s_fdt.c|  16 +
 arch/arm/mach-k3/j722s/j722s_init.c   | 287 ++
 10 files changed, 490 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
 create mode 100644 arch/arm/mach-k3/j722s/Kconfig
 create mode 100644 arch/arm/mach-k3/j722s/Makefile
 create mode 100644 arch/arm/mach-k3/j722s/j722s_fdt.c
 create mode 100644 arch/arm/mach-k3/j722s/j722s_init.c

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2bb970c2d4..f3f42b3921 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -25,6 +25,9 @@ config SOC_K3_J721E
 config SOC_K3_J721S2
bool "TI's K3 based J721S2 SoC Family Support"
 
+config SOC_K3_J722S
+   bool "TI's K3 based J722S SoC Family Support"
+
 config SOC_K3_J784S4
bool "TI's K3 based J784S4 SoC Family Support"
 
@@ -84,6 +87,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
default 0x43c4f290 if SOC_K3_AM62P5
+   default 0x43c7f290 if SOC_K3_J722S
help
  Address at which ROM stores the value which determines if SPL
  is booted up by primary boot media or secondary boot media.
@@ -122,7 +126,7 @@ config K3_EARLY_CONS_IDX
 
 config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
-   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
+   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 
|| SOC_K3_J722S)
default 0x7000
help
  The load address for the ATF image. This value is used to build the
@@ -163,6 +167,7 @@ source "arch/arm/mach-k3/am62ax/Kconfig"
 source "arch/arm/mach-k3/am62px/Kconfig"
 source "arch/arm/mach-k3/j721e/Kconfig"
 source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j722s/Kconfig"
 source "arch/arm/mach-k3/j784s4/Kconfig"
 
 endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 2b3ebd5c53..8c4f6786a5 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_SOC_K3_AM642) += am64x/
 obj-$(CONFIG_SOC_K3_AM654) += am65x/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index 1024ee6872..b191d53a0f 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -36,6 +36,10 @@
 #include "j721s2_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J722S
+#include "j722s_hardware.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h 
b/arch/arm/mach-k3/include/mach/j722s_hardware.h
new file mode 100644
index 00..8d0bec2206
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J722S SoC definitions, structures etc.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __ASM_ARCH_J722S_HARDWARE_H
+#define __ASM_ARCH_J722S_HARDWARE_H
+
+#include 
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#define PADCFG_MMR0_BASE   0x0408
+#define PADCFG_MMR1_BASE   0x000f
+#define CTRL_MMR0_BASE 0x0010
+#define MCU_CTRL_MMR0_BASE 0x0450
+#define WKUP_CTRL_MMR0_BASE0x4300
+
+#define CTRLMMR_MAIN_DEVSTAT   (WKUP_CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT3
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT7
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK  GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 1

[PATCH v2 11/14] firmware: ti_sci_static_data: Add static DMA channel

[Jayesh Choudhary]

Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 drivers/firmware/ti_sci_static_data.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/ti_sci_static_data.h 
b/drivers/firmware/ti_sci_static_data.h
index 9662bd95f2..3370f80231 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -85,7 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 #endif /* CONFIG_SOC_K3_J721S2 */
 
 #if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
-   IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S)
 static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
-- 
2.25.1

[PATCH v2 10/14] board: ti: Introduce basic board files for the J722S family

[Jayesh Choudhary]

Introduce the basic files needed to support the TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 board/ti/j722s/Kconfig  |   26 +
 board/ti/j722s/MAINTAINERS  |9 +
 board/ti/j722s/Makefile |7 +
 board/ti/j722s/board-cfg.yaml   |   36 +
 board/ti/j722s/evm.c|   29 +
 board/ti/j722s/j722s.env|   15 +
 board/ti/j722s/pm-cfg.yaml  |   12 +
 board/ti/j722s/rm-cfg.yaml  | 1119 +++
 board/ti/j722s/sec-cfg.yaml |  379 +++
 board/ti/j722s/tifs-rm-cfg.yaml |  981 +++
 10 files changed, 2613 insertions(+)
 create mode 100644 board/ti/j722s/Kconfig
 create mode 100644 board/ti/j722s/MAINTAINERS
 create mode 100644 board/ti/j722s/Makefile
 create mode 100644 board/ti/j722s/board-cfg.yaml
 create mode 100644 board/ti/j722s/evm.c
 create mode 100644 board/ti/j722s/j722s.env
 create mode 100644 board/ti/j722s/pm-cfg.yaml
 create mode 100644 board/ti/j722s/rm-cfg.yaml
 create mode 100644 board/ti/j722s/sec-cfg.yaml
 create mode 100644 board/ti/j722s/tifs-rm-cfg.yaml

diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig
new file mode 100644
index 00..68c214e473
--- /dev/null
+++ b/board/ti/j722s/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM
+
+config SYS_BOARD
+   default "j722s"
+
+config SYS_VENDOR
+   default "ti"
+
+config SYS_CONFIG_NAME
+   default "j722s_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_EVM
+
+config SPL_LDSCRIPT
+   default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS
new file mode 100644
index 00..7908c30def
--- /dev/null
+++ b/board/ti/j722s/MAINTAINERS
@@ -0,0 +1,9 @@
+J722S BOARD
+M: Vaishnav Achath 
+M: Jayesh Choudhary 
+M: Tom Rini 
+S: Maintained
+F: board/ti/j722s/
+F: include/configs/j722s_evm.h
+F: configs/j722s_evm_r5_defconfig
+F: configs/j722s_evm_a53_defconfig
diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile
new file mode 100644
index 00..20d2ec934b
--- /dev/null
+++ b/board/ti/j722s/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evm.o
diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml
new file mode 100644
index 00..f9a4c438ca
--- /dev/null
+++ b/board/ti/j722s/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable: 0x5A
+main_isolation_hostid: 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor: 0x1
+scaling_profile: 0x1
+disable_main_nav_secure_proxy: 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size: 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables: 0x00
+trace_src_enables: 0x00
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
new file mode 100644
index 00..515aaa8187
--- /dev/null
+++ b/board/ti/j722s/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J722S platforms
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int board_init(void)
+{
+   return 0;
+}
+
+int dram_init(void)
+{
+   return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+   return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
new file mode 100644
index 00..f8b6aff2c2
--- /dev/null
+++ b/board/ti/j722s/j722s.env
@@ -0,0 +1,15 @@
+#include 
+#include 
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+   ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml
new file mode 100644
index 00..46b3ad2010
--- /dev/null
+++ b/board/ti/j722s/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https:

[PATCH v2 13/14] configs: introduce configs needed for the J722S

[Jayesh Choudhary]

Introduce the initial configs needed to support the J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 configs/j722s_evm_a53_defconfig | 172 
 configs/j722s_evm_r5_defconfig  | 131 
 include/configs/j722s_evm.h |  14 +++
 3 files changed, 317 insertions(+)
 create mode 100644 configs/j722s_evm_a53_defconfig
 create mode 100644 configs/j722s_evm_r5_defconfig
 create mode 100644 include/configs/j722s_evm.h

diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
new file mode 100644
index 00..da0e9f4d52
--- /dev/null
+++ b/configs/j722s_evm_a53_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+CONFIG_SF_DEFAULT_SPEED=2500
+CONFIG_ENV_SIZE=0x4
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a0
+CONFIG_SPL_BSS_MAX_SIZE=0x8
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y

[PATCH v2 14/14] doc: board: ti: Add J722S-EVM documentation

[Jayesh Choudhary]

Introduce basic documentation for the J722S-EVM.

Signed-off-by: Jayesh Choudhary 
Reviewed-by: Neha Malcom Francis 
---
 doc/board/ti/j722s_evm.rst | 260 +
 doc/board/ti/k3.rst|   1 +
 2 files changed, 261 insertions(+)
 create mode 100644 doc/board/ti/j722s_evm.rst

diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
new file mode 100644
index 00..10b243908a
--- /dev/null
+++ b/doc/board/ti/j722s_evm.rst
@@ -0,0 +1,260 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jayesh Choudhary 
+
+J722S-EVM Platform
+==
+
+The J722S is a family of  application processors built for Automotive and
+Linux Application development. J722S family of SoCs is a superset of the
+AM62P SoC family and shares similar memory map, thus the nodes are being
+reused from AM62P includes instead of duplicating the definitions.
+
+Some highlights of J722S SoC (in addition to AM62P SoC features) are:
+
+* Two Cortex-R5F for Functional Safety or general-purpose usage and
+  two C7x floating point vector DSP with Matrix Multiply Accelerator
+  for deep learning.
+
+* Vision Processing Accelerator (VPAC) with image signal processor
+  and Depth and Motion Processing Accelerator (DMPAC).
+
+* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
+  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
+  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
+  ePWM, among other peripherals.
+
+For those interested, more details about this SoC can be found in the
+Technical Reference Manual here: https://www.ti.com/lit/zip/sprujb3
+
+Boot Flow:
+--
+
+The bootflow is exactly the same as all SoCs in the am62xxx extended SoC
+family. Below is the pictorial representation:
+
+.. image:: img/boot_diagram_k3_current.svg
+  :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+  requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+
+
+0. Setup the environment variables:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. j722s_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_tfa
+:end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_optee
+:end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_spl_r5
+:end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_uboot
+:end-before: .. k3_rst_include_end_build_steps_uboot
+.. j722s_evm_rst_include_end_build_steps
+
+Target Images
+--
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img.  Each SoC
+variant (HS-FS, HS-SE) requires a different source for these files.
+
+ - HS-FS
+
+* tiboot3-j722s-hs-fs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+* tiboot3-j722s-hs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+  :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+  :alt: tispl.bin image format
+
+A53 SPL DDR Memory Layout
+-
+
+.. j722s_evm_rst_include_start_ddr_mem_layout
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+ - Start Address
+ - End Address
+
+   * - EMPTY
+ - 0x8000
+ - 0x8008
+
+   * - TEXT BASE
+ - 0x8008
+ - 0x800d8000
+
+   * - EMPTY
+ - 0x800d8000
+ - 0x80477660
+
+   * - STACK
+ - 0x80477660
+ - 0x80477e60
+
+   * - GD
+ - 0x80477e60
+ - 0x80478000
+
+   

[PATCH v2 12/14] arm: dts: Introduce J722S U-Boot dts files

[Jayesh Choudhary]

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/dts/Makefile  |2 +
 arch/arm/dts/k3-j722s-binman.dtsi  |  172 ++
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   18 +
 arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
 5 files changed, 3069 insertions(+)
 create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cef42ab53a..86d9f133ba 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1191,6 +1191,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += 
k3-am68-sk-r5-base-board.dtb\
 dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
   k3-j784s4-r5-evm.dtb
 
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
  k3-am642-r5-sk.dtb \
  k3-am642-r5-phycore-som-2gb.dtb
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi 
b/arch/arm/dts/k3-j722s-binman.dtsi
new file mode 100644
index 00..28087a3b6f
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
+
+&binman {
+   tiboot3-j722s-hs-fs-evm.bin {
+   filename = "tiboot3-j722s-hs-fs-evm.bin";
+   symlink = "tiboot3.bin";
+
+   ti-secure-rom {
+   content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, 
<&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <&u_boot_spl_fs>;
+   content-sysfw = <&ti_fs_enc_fs>;
+   content-sysfw-data = <&combined_tifs_cfg_fs>;
+   content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+   content-dm-data = <&combined_dm_cfg_fs>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c7a800>;
+   };
+
+   u_boot_spl_fs: u-boot-spl {
+   no-expanded;
+   };
+
+   ti_fs_enc_fs: ti-fs-enc.bin {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   type = "blob-ext";
+   };
+
+   sysfw_inner_cert_fs: sysfw-inner-cert {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_dm_cfg_fs: combined-dm-cfg.bin {
+   filename = "combined-dm-cfg.bin";
+   type = "blob-ext";
+   };
+   };
+};
+#endif /*CONFIG_TARGET_J722S_R5_EVM*/
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_EVM)
+
+#define SPL_J722S_EVM_DTB "spl/dts/ti/k3-j722s-evm.dtb"
+#define J722S_EVM_DTB "u-boot.dtb"
+
+&binman {
+   ti-dm {
+   filename = "ti-dm.bin";
+
+   blob-ext {
+   filename = 
"ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+   optional;
+   };
+   };
+
+   ti-spl {
+   insert-template = <&ti_spl_template>;
+
+   fit {
+   images {
+   dm {
+   ti-secure {
+   content = <&dm>;
+   keyfile = "custMpk.pem";
+   };
+
+   dm: ti-dm {
+  

[PATCH v2 0/8] Enable QoS for DSS on J7 family of TI SoCs

[Jayesh Choudhary]

Hello All,
This series adds the QoS for DSS on J721E, J721S2 and J784S4 family of
SoCs.

Before adding the support, cleanup is done for AM62A QoS support[0]
and common bit mask defines are moved to the common file so that they
are not defined every time we add QoS support for a new K3 platform.

Further, to simplify the logic, macros are used to populate the value
of registers and values as suggested by Andrew[1]

Before adding QoS support, we need to map the ORDERID to the traffic
type (RT/NRT) in J7 platforms.
On J721E, ORDERID 0-7 and 8-15 are two groups which needs to be mapped.
We are mapping 0-7 to NRT and 8-15 ORDERID as RT for both NAVSS0_NBSS_NB0
and NAVSS0_NBSS_NB1
On J721S2 and J784S4, we have 3 groups, 0-3, 4-9, 10-15. Here we are
mapping first two groups as NRT and 10-15 as RT for both NAVSS0_NBSS_NB0
and NAVSS0_NBSS_NB1.

Changelog v1->v2:
- Simplify the logic to populate values[1]
- Remove ASEL type which is to be taken up separately as suggested in [2]

v1 patch link:
<https://patchwork.ozlabs.org/project/uboot/list/?series=407729&state=%2A&archive=both>

[0]: https://lore.kernel.org/all/20230414072725.8802-1-a-bhat...@ti.com/
[1]: 
https://patchwork.ozlabs.org/project/uboot/patch/20240522113726.302908-2-j-choudh...@ti.com/#3315446
[2]: 
https://patchwork.ozlabs.org/project/uboot/patch/20240522113726.302908-3-j-choudh...@ti.com/#3315467


Jayesh Choudhary (8):
  arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file
  arm: mach-k3: am62a: Simplify the logic for QOS reg and val
propagation
  arm: mach-k3: j721e: Enable QoS for DSS
  arm: mach-k3: j721s2: Enable QoS for DSS
  arm: mach-k3: j784s4: Enable QoS for DSS
  configs: j721e_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: j721s2_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: j784s4_evm_r5_defconfig: Enable CONFIG_K3_QOS

 arch/arm/mach-k3/include/mach/k3-qos.h|  20 +++
 arch/arm/mach-k3/j721e/j721e_init.c   |  28 
 arch/arm/mach-k3/j721s2/j721s2_init.c |  30 +
 arch/arm/mach-k3/j784s4/j784s4_init.c |  30 +
 arch/arm/mach-k3/r5/am62ax/am62a_qos.h|  74 --
 arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c  |  24 ++--
 arch/arm/mach-k3/r5/j721e/Makefile|   1 +
 arch/arm/mach-k3/r5/j721e/j721e_qos.h |  96 +
 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c   | 126 ++
 arch/arm/mach-k3/r5/j721s2/Makefile   |   1 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h   |  79 +++
 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 110 +++
 arch/arm/mach-k3/r5/j784s4/Makefile   |   1 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h   |  83 
 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 110 +++
 configs/j721e_evm_r5_defconfig|   1 +
 configs/j721s2_evm_r5_defconfig   |   1 +
 configs/j784s4_evm_r5_defconfig   |   1 +
 18 files changed, 730 insertions(+), 86 deletions(-)
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c

-- 
2.25.1

[PATCH v2 1/8] arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file

[Jayesh Choudhary]

QoS bit mapping are common across all K3 SoCs so move those defines
to common header file (k3_qos.h).
This ensures that we do not define these for each SoC.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++
 arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 --
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h 
b/arch/arm/mach-k3/include/mach/k3-qos.h
index e00e1de5b9..6ed5704803 100644
--- a/arch/arm/mach-k3/include/mach/k3-qos.h
+++ b/arch/arm/mach-k3/include/mach/k3-qos.h
@@ -9,6 +9,80 @@
 
 #include 
 
+#define QOS_0  (0 << 0)
+#define QOS_1  (1 << 0)
+#define QOS_2  (2 << 0)
+#define QOS_3  (3 << 0)
+#define QOS_4  (4 << 0)
+#define QOS_5  (5 << 0)
+#define QOS_6  (6 << 0)
+#define QOS_7  (7 << 0)
+
+#define ORDERID_0  (0 << 4)
+#define ORDERID_1  (1 << 4)
+#define ORDERID_2  (2 << 4)
+#define ORDERID_3  (3 << 4)
+#define ORDERID_4  (4 << 4)
+#define ORDERID_5  (5 << 4)
+#define ORDERID_6  (6 << 4)
+#define ORDERID_7  (7 << 4)
+#define ORDERID_8  (8 << 4)
+#define ORDERID_9  (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10(10 << 8)
+#define ASEL_11(11 << 8)
+#define ASEL_12(12 << 8)
+#define ASEL_13(13 << 8)
+#define ASEL_14(14 << 8)
+#define ASEL_15(15 << 8)
+
+#define EPRIORITY_0(0 << 12)
+#define EPRIORITY_1(1 << 12)
+#define EPRIORITY_2(2 << 12)
+#define EPRIORITY_3(3 << 12)
+#define EPRIORITY_4(4 << 12)
+#define EPRIORITY_5(5 << 12)
+#define EPRIORITY_6(6 << 12)
+#define EPRIORITY_7(7 << 12)
+
+#define VIRTID_0   (0 << 16)
+#define VIRTID_1   (1 << 16)
+#define VIRTID_2   (2 << 16)
+#define VIRTID_3   (3 << 16)
+#define VIRTID_4   (4 << 16)
+#define VIRTID_5   (5 << 16)
+#define VIRTID_6   (6 << 16)
+#define VIRTID_7   (7 << 16)
+#define VIRTID_8   (8 << 16)
+#define VIRTID_9   (9 << 16)
+#define VIRTID_10  (10 << 16)
+#define VIRTID_11  (11 << 16)
+#define VIRTID_12  (12 << 16)
+#define VIRTID_13  (13 << 16)
+#define VIRTID_14  (14 << 16)
+#define VIRTID_15  (15 << 16)
+
+#define ATYPE_0(0 << 28)
+#define ATYPE_1(1 << 28)
+#define ATYPE_2(2 << 28)
+#define ATYPE_3(3 << 28)
+
 struct k3_qos_data {
u32 reg;
u32 val;
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h 
b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
index c74d69a28f..84a6dc7240 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
@@ -6,80 +6,6 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#define QOS_0  (0 << 0)
-#define QOS_1  (1 << 0)
-#define QOS_2  (2 << 0)
-#define QOS_3  (3 << 0)
-#define QOS_4  (4 << 0)
-#define QOS_5  (5 << 0)
-#define QOS_6  (6 << 0)
-#define QOS_7  (7 << 0)
-
-#define ORDERID_0  (0 << 4)
-#define ORDERID_1  (1 << 4)
-#define ORDERID_2  (2 << 4)
-#define ORDERID_3  (3 << 4)
-#define ORDERID_4  (4 << 4)
-#define ORDERID_5  (5 << 4)
-#define ORDERID_6  (6 << 4)
-#define ORDERID_7  (7 << 4)
-#define ORDERID_8  (8 << 4)
-#define ORDERID_9  (9 << 4)
-#define ORDERID_10 (10 << 4)
-#define ORDERID_11 (11 << 4)
-#define ORDERID_12 (12 << 4)
-#define ORDERID_13 (13 << 4)
-#define ORDERID_14 (14 << 4)
-#define ORDERID_15 (15 << 4)
-
-#define ASEL_0 (0 << 8)
-#define ASEL_1 (1 << 8)
-#define ASEL_2 (2 << 8)
-#define ASEL_3 (3 << 8)
-#define ASEL_4 (4 << 8)
-#define ASEL_5 (5 << 8)
-#define ASEL_6 (6 << 8)
-#define ASEL_7 (7 << 8)
-#define ASEL_8 (8 << 8)
-#define ASEL_9 (9 << 8)
-#define ASEL_10(10 << 8)
-#define ASEL_11(11 << 8)
-#define ASEL_12(12 << 8)
-#define ASEL_13(13 << 8)
-#define ASEL_14(14 << 8)
-#define ASEL_15

[PATCH v2 2/8] arm: mach-k3: am62a: Simplify the logic for QOS reg and val propagation

[Jayesh Choudhary]

For the QOS registers, instead of using the raw values for calculation
for each reg field, use a defined macro which takes in argument for all
the reg fields to get the desired value.
Do the similar simplification for QOS register and group registers and
make the corresponding changes for am62a_qos_uboot file.

Suggested-by: Andrew Davis 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/k3-qos.h   | 86 
 arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c | 24 +++---
 2 files changed, 28 insertions(+), 82 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h 
b/arch/arm/mach-k3/include/mach/k3-qos.h
index 6ed5704803..eb0f2a0448 100644
--- a/arch/arm/mach-k3/include/mach/k3-qos.h
+++ b/arch/arm/mach-k3/include/mach/k3-qos.h
@@ -9,80 +9,26 @@
 
 #include 
 
-#define QOS_0  (0 << 0)
-#define QOS_1  (1 << 0)
-#define QOS_2  (2 << 0)
-#define QOS_3  (3 << 0)
-#define QOS_4  (4 << 0)
-#define QOS_5  (5 << 0)
-#define QOS_6  (6 << 0)
-#define QOS_7  (7 << 0)
+/* K3_QOS_REG: Registers to configure the channel for a given endpoint */
 
-#define ORDERID_0  (0 << 4)
-#define ORDERID_1  (1 << 4)
-#define ORDERID_2  (2 << 4)
-#define ORDERID_3  (3 << 4)
-#define ORDERID_4  (4 << 4)
-#define ORDERID_5  (5 << 4)
-#define ORDERID_6  (6 << 4)
-#define ORDERID_7  (7 << 4)
-#define ORDERID_8  (8 << 4)
-#define ORDERID_9  (9 << 4)
-#define ORDERID_10 (10 << 4)
-#define ORDERID_11 (11 << 4)
-#define ORDERID_12 (12 << 4)
-#define ORDERID_13 (13 << 4)
-#define ORDERID_14 (14 << 4)
-#define ORDERID_15 (15 << 4)
+#define K3_QOS_REG(base_reg, i)(base_reg + 0x100 + (i) * 4)
 
-#define ASEL_0 (0 << 8)
-#define ASEL_1 (1 << 8)
-#define ASEL_2 (2 << 8)
-#define ASEL_3 (3 << 8)
-#define ASEL_4 (4 << 8)
-#define ASEL_5 (5 << 8)
-#define ASEL_6 (6 << 8)
-#define ASEL_7 (7 << 8)
-#define ASEL_8 (8 << 8)
-#define ASEL_9 (9 << 8)
-#define ASEL_10(10 << 8)
-#define ASEL_11(11 << 8)
-#define ASEL_12(12 << 8)
-#define ASEL_13(13 << 8)
-#define ASEL_14(14 << 8)
-#define ASEL_15(15 << 8)
+#define K3_QOS_VAL(qos, orderid, asel, epriority, virtid, atype) \
+   (qos<< 0  | \
+orderid<< 4  | \
+asel   << 8  | \
+epriority  << 12 | \
+virtid << 16 | \
+atype  << 28)
 
-#define EPRIORITY_0(0 << 12)
-#define EPRIORITY_1(1 << 12)
-#define EPRIORITY_2(2 << 12)
-#define EPRIORITY_3(3 << 12)
-#define EPRIORITY_4(4 << 12)
-#define EPRIORITY_5(5 << 12)
-#define EPRIORITY_6(6 << 12)
-#define EPRIORITY_7(7 << 12)
-
-#define VIRTID_0   (0 << 16)
-#define VIRTID_1   (1 << 16)
-#define VIRTID_2   (2 << 16)
-#define VIRTID_3   (3 << 16)
-#define VIRTID_4   (4 << 16)
-#define VIRTID_5   (5 << 16)
-#define VIRTID_6   (6 << 16)
-#define VIRTID_7   (7 << 16)
-#define VIRTID_8   (8 << 16)
-#define VIRTID_9   (9 << 16)
-#define VIRTID_10  (10 << 16)
-#define VIRTID_11  (11 << 16)
-#define VIRTID_12  (12 << 16)
-#define VIRTID_13  (13 << 16)
-#define VIRTID_14  (14 << 16)
-#define VIRTID_15  (15 << 16)
-
-#define ATYPE_0(0 << 28)
-#define ATYPE_1(1 << 28)
-#define ATYPE_2(2 << 28)
-#define ATYPE_3(3 << 28)
+/*
+ * K3_QOS_GROUP_REG: Registers to set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers.
+ */
+#define K3_QOS_GROUP_REG(base_reg, i)  (base_reg + (i) * 4)
 
+#define K3_QOS_GROUP_DEFAULT_VAL_LOW   0x76543210
+#define K3_QOS_GROUP_DEFAULT_VAL_HIGH  0xfedcba98
 struct k3_qos_data {
u32 reg;
u32 val;
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c 
b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
index 9a82944d5f..1d588acea4 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
@@ -12,20 +12,20 @@
 struct k3_qos_data qos_data[] = {
/* modules_qosConfig0 - 1 endpoints, 4 channels */
{
-   .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
-   .val = ORDERID_8,
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+   .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0),
},
{
-   .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
-   .val = ORDERID_8,
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+   .val = K3_QOS_VAL(0, 8,

[PATCH v2 3/8] arm: mach-k3: j721e: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721e/j721e_init.c |  28 +
 arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
 arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 126 
 4 files changed, 251 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c
index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -23,6 +23,22 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
+/* NAVSS North Bridge (NB) registers */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-7 to VBUSM.C thread number
+ * Bit[1] maps orderID 8-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
 #if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void)
 }
 #endif
 
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
 #endif
spl_enable_cache();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile 
b/arch/arm/mach-k3/r5/j721e/Makefile
index 78325db402..07bfb0dd93 100644
--- a/arch/arm/mach-k3/r5/j721e/Makefile
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j721e_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h 
b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
new file mode 100644
index 00..9ec0b7c630
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0   0x45D1
+#define PULSAR_SL_MCU_0_MEMBDG_WMST0   0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_MEMBDG_RMST1   0x45D11000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST1   0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA2_UL_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define ICSS_G_MAIN_0_PR1_EXT_VBUSM0x45D8
+#define ICSS_G_MAIN_1_PR1_EXT_VBUSM0x45D80400
+#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000
+#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D82C00
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST0  0x45D84000
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST1  0x45D84400
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST0  0x45D84800
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST1  0x45D84C00
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST0  0x45D85000
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST1  0x45D85400
+#define PULSAR_SL_MAIN_1_MEMBDG_WMST0  0x45D85800
+#define 

[PATCH v2 4/8] arm: mach-k3: j721s2: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.

Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])

Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruj28

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721s2/j721s2_init.c |  30 +
 arch/arm/mach-k3/r5/j721s2/Makefile   |   1 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h   |  79 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 110 ++
 4 files changed, 220 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c 
b/arch/arm/mach-k3/j721s2/j721s2_init.c
index fe9766e9b4..05453fcad4 100644
--- a/arch/arm/mach-k3/j721s2/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -22,6 +22,24 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+#define NB_THREADMAP_BIT2  BIT(2)
+
 struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2577, 7 },
{ "EMMC8SS0_CFG", 2579, 4 },
@@ -123,6 +141,13 @@ void k3_mmc_restart_clock(void)
}
 }
 
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -295,6 +320,11 @@ void board_init_f(ulong dummy)
do_dt_magic();
 #endif
k3_mem_init();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 #endif
 
diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile 
b/arch/arm/mach-k3/r5/j721s2/Makefile
index 8588c5e4c3..89c0284b56 100644
--- a/arch/arm/mach-k3/r5/j721s2/Makefile
+++ b/arch/arm/mach-k3/r5/j721s2/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j721s2_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h 
b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
new file mode 100644
index 00..ab3e4773a4
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M0x45D0
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST  0x45D1
+#define PULSAR_SL_MCU_0_CPU0_WMST  0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST  0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST  0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST00x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST00x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST10x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST10x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM  0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM  0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD   0x45D98400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR   0x45D98C00
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD   0x45D99400
+#defin

[PATCH v2 5/8] arm: mach-k3: j784s4: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.

Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])

Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruj52

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j784s4/j784s4_init.c |  30 +
 arch/arm/mach-k3/r5/j784s4/Makefile   |   1 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h   |  83 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 110 ++
 4 files changed, 224 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 1ce13e0f49..07b5d7d750 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -23,6 +23,24 @@
 
 #define J784S4_MAX_DDR_CONTROLLERS 4
 
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+#define NB_THREADMAP_BIT2  BIT(2)
+
 struct fwl_data infra_cbass0_fwls[] = {
{ "PSC0", 5, 1 },
{ "PLL_CTRL0", 6, 1 },
@@ -94,6 +112,13 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(CTRL_MMR0_BASE, 7);
 }
 
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -210,6 +235,11 @@ void board_init_f(ulong dummy)
 {
k3_spl_init();
k3_mem_init();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile 
b/arch/arm/mach-k3/r5/j784s4/Makefile
index 9ce88305f5..0fd6cabd3f 100644
--- a/arch/arm/mach-k3/r5/j784s4/Makefile
+++ b/arch/arm/mach-k3/r5/j784s4/Makefile
@@ -5,3 +5,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j784s4_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h 
b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
new file mode 100644
index 00..5851f889fe
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M0x45D0
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST  0x45D1
+#define PULSAR_SL_MCU_0_CPU0_WMST  0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST  0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST  0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST00x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST00x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST10x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST10x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM  0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM  0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD   0x45D98400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR   0x45D98C00
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD   0x45D99400
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR   0x45D99C00
+#define U

[PATCH v2 6/8] configs: j721e_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j721e_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 37d582b775..ffaf21d499 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J721E=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
-- 
2.25.1

[PATCH v2 7/8] configs: j721s2_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j721s2_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 7413ddd081..df5910a48f 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J721S2=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J721S2_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-- 
2.25.1

[PATCH v2 8/8] configs: j784s4_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j784s4_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index f5fe743220..d1bcf792d7 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J784S4=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J784S4_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-- 
2.25.1

[PATCH 0/7] Enable QoS for DSS on J7 family of TI SoCs

[Jayesh Choudhary]

Hello All,
This series adds the QoS for DSS on J721E, J721S2 and J784S4 family of
SoCs.

Before adding the support, cleanup is done for AM62A QoS support[0]
and common bit mask defines are moved to the common file so that they
are not defined every time we add QoS support for a new K3 platform.

Before adding QoS support, we need to map the ORDERID to the traffic
type (RT/NRT).
On J721E, ORDERID 0-7 and 8-15 are two groups which needs to be mapped.
We are mapping 0-7 to NRT and 8-15 ORDERID as RT for both NAVSS0_NBSS_NB0
and NAVSS0_NBSS_NB1
On J721S2 and J784S4, we have 3 groups, 0-3, 4-9, 10-15. Here we are
mapping first two groups as NRT and 10-15 as RT for both NAVSS0_NBSS_NB0
and NAVSS0_NBSS_NB1.

[0]: https://lore.kernel.org/all/20230414072725.8802-1-a-bhat...@ti.com/

Jayesh Choudhary (7):
  arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file
  arm: mach-k3: j721e: Enable QoS for DSS
  arm: mach-k3: j721s2: Enable QoS for DSS
  arm: mach-k3: j784s4: Enable QoS for DSS
  configs: j721e_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: j721s2_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: j784s4_evm_r5_defconfig: Enable CONFIG_K3_QOS

 arch/arm/mach-k3/include/mach/k3-qos.h|  74 +++
 arch/arm/mach-k3/j721e/j721e_init.c   |  28 
 arch/arm/mach-k3/j721s2/j721s2_init.c |  30 +
 arch/arm/mach-k3/j784s4/j784s4_init.c |  30 +
 arch/arm/mach-k3/r5/am62ax/am62a_qos.h|  74 ---
 arch/arm/mach-k3/r5/j721e/Makefile|   1 +
 arch/arm/mach-k3/r5/j721e/j721e_qos.h |  96 ++
 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c   | 125 ++
 arch/arm/mach-k3/r5/j721s2/Makefile   |   1 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h   |  79 +++
 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 109 +++
 arch/arm/mach-k3/r5/j784s4/Makefile   |   1 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h   |  83 
 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 109 +++
 configs/j721e_evm_r5_defconfig|   1 +
 configs/j721s2_evm_r5_defconfig   |   1 +
 configs/j784s4_evm_r5_defconfig   |   1 +
 17 files changed, 769 insertions(+), 74 deletions(-)
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c

-- 
2.25.1

[PATCH 1/7] arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file

[Jayesh Choudhary]

QoS bit mapping are common across all K3 SoCs so move those defines
to common header file (k3_qos.h).
This ensures that we do not define these for each SoC.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++
 arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 --
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h 
b/arch/arm/mach-k3/include/mach/k3-qos.h
index e00e1de5b9..6ed5704803 100644
--- a/arch/arm/mach-k3/include/mach/k3-qos.h
+++ b/arch/arm/mach-k3/include/mach/k3-qos.h
@@ -9,6 +9,80 @@
 
 #include 
 
+#define QOS_0  (0 << 0)
+#define QOS_1  (1 << 0)
+#define QOS_2  (2 << 0)
+#define QOS_3  (3 << 0)
+#define QOS_4  (4 << 0)
+#define QOS_5  (5 << 0)
+#define QOS_6  (6 << 0)
+#define QOS_7  (7 << 0)
+
+#define ORDERID_0  (0 << 4)
+#define ORDERID_1  (1 << 4)
+#define ORDERID_2  (2 << 4)
+#define ORDERID_3  (3 << 4)
+#define ORDERID_4  (4 << 4)
+#define ORDERID_5  (5 << 4)
+#define ORDERID_6  (6 << 4)
+#define ORDERID_7  (7 << 4)
+#define ORDERID_8  (8 << 4)
+#define ORDERID_9  (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10(10 << 8)
+#define ASEL_11(11 << 8)
+#define ASEL_12(12 << 8)
+#define ASEL_13(13 << 8)
+#define ASEL_14(14 << 8)
+#define ASEL_15(15 << 8)
+
+#define EPRIORITY_0(0 << 12)
+#define EPRIORITY_1(1 << 12)
+#define EPRIORITY_2(2 << 12)
+#define EPRIORITY_3(3 << 12)
+#define EPRIORITY_4(4 << 12)
+#define EPRIORITY_5(5 << 12)
+#define EPRIORITY_6(6 << 12)
+#define EPRIORITY_7(7 << 12)
+
+#define VIRTID_0   (0 << 16)
+#define VIRTID_1   (1 << 16)
+#define VIRTID_2   (2 << 16)
+#define VIRTID_3   (3 << 16)
+#define VIRTID_4   (4 << 16)
+#define VIRTID_5   (5 << 16)
+#define VIRTID_6   (6 << 16)
+#define VIRTID_7   (7 << 16)
+#define VIRTID_8   (8 << 16)
+#define VIRTID_9   (9 << 16)
+#define VIRTID_10  (10 << 16)
+#define VIRTID_11  (11 << 16)
+#define VIRTID_12  (12 << 16)
+#define VIRTID_13  (13 << 16)
+#define VIRTID_14  (14 << 16)
+#define VIRTID_15  (15 << 16)
+
+#define ATYPE_0(0 << 28)
+#define ATYPE_1(1 << 28)
+#define ATYPE_2(2 << 28)
+#define ATYPE_3(3 << 28)
+
 struct k3_qos_data {
u32 reg;
u32 val;
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h 
b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
index c74d69a28f..84a6dc7240 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
@@ -6,80 +6,6 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#define QOS_0  (0 << 0)
-#define QOS_1  (1 << 0)
-#define QOS_2  (2 << 0)
-#define QOS_3  (3 << 0)
-#define QOS_4  (4 << 0)
-#define QOS_5  (5 << 0)
-#define QOS_6  (6 << 0)
-#define QOS_7  (7 << 0)
-
-#define ORDERID_0  (0 << 4)
-#define ORDERID_1  (1 << 4)
-#define ORDERID_2  (2 << 4)
-#define ORDERID_3  (3 << 4)
-#define ORDERID_4  (4 << 4)
-#define ORDERID_5  (5 << 4)
-#define ORDERID_6  (6 << 4)
-#define ORDERID_7  (7 << 4)
-#define ORDERID_8  (8 << 4)
-#define ORDERID_9  (9 << 4)
-#define ORDERID_10 (10 << 4)
-#define ORDERID_11 (11 << 4)
-#define ORDERID_12 (12 << 4)
-#define ORDERID_13 (13 << 4)
-#define ORDERID_14 (14 << 4)
-#define ORDERID_15 (15 << 4)
-
-#define ASEL_0 (0 << 8)
-#define ASEL_1 (1 << 8)
-#define ASEL_2 (2 << 8)
-#define ASEL_3 (3 << 8)
-#define ASEL_4 (4 << 8)
-#define ASEL_5 (5 << 8)
-#define ASEL_6 (6 << 8)
-#define ASEL_7 (7 << 8)
-#define ASEL_8 (8 << 8)
-#define ASEL_9 (9 << 8)
-#define ASEL_10(10 << 8)
-#define ASEL_11(11 << 8)
-#define ASEL_12(12 << 8)
-#define ASEL_13(13 << 8)
-#define ASEL_14(14 << 8)
-#define ASEL_15

[PATCH 2/7] arm: mach-k3: j721e: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
ATYPE 3 is selected so that the traffic takes non-coherent path and does
not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721e/j721e_init.c |  28 +
 arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
 arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 
 4 files changed, 250 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c
index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -23,6 +23,22 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
+/* NAVSS North Bridge (NB) registers */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-7 to VBUSM.C thread number
+ * Bit[1] maps orderID 8-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
 #if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void)
 }
 #endif
 
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
 #endif
spl_enable_cache();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile 
b/arch/arm/mach-k3/r5/j721e/Makefile
index 78325db402..07bfb0dd93 100644
--- a/arch/arm/mach-k3/r5/j721e/Makefile
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j721e_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h 
b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
new file mode 100644
index 00..9ec0b7c630
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0   0x45D1
+#define PULSAR_SL_MCU_0_MEMBDG_WMST0   0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_MEMBDG_RMST1   0x45D11000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST1   0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA2_UL_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define ICSS_G_MAIN_0_PR1_EXT_VBUSM0x45D8
+#define ICSS_G_MAIN_1_PR1_EXT_VBUSM0x45D80400
+#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000
+#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D82C00
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST0  0x45D84000
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST1  0x45D84400
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST0  0x45D84800
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST1  0x45D84C00
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 

[PATCH 3/7] arm: mach-k3: j721s2: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.
ATYPE 3 is selected so that the traffic takes non-coherent path and does
not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])

Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruj28

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721s2/j721s2_init.c |  30 +
 arch/arm/mach-k3/r5/j721s2/Makefile   |   1 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h   |  79 +
 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 109 ++
 4 files changed, 219 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c 
b/arch/arm/mach-k3/j721s2/j721s2_init.c
index fe9766e9b4..05453fcad4 100644
--- a/arch/arm/mach-k3/j721s2/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -22,6 +22,24 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+#define NB_THREADMAP_BIT2  BIT(2)
+
 struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2577, 7 },
{ "EMMC8SS0_CFG", 2579, 4 },
@@ -123,6 +141,13 @@ void k3_mmc_restart_clock(void)
}
 }
 
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -295,6 +320,11 @@ void board_init_f(ulong dummy)
do_dt_magic();
 #endif
k3_mem_init();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 #endif
 
diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile 
b/arch/arm/mach-k3/r5/j721s2/Makefile
index 8588c5e4c3..89c0284b56 100644
--- a/arch/arm/mach-k3/r5/j721s2/Makefile
+++ b/arch/arm/mach-k3/r5/j721s2/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j721s2_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h 
b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
new file mode 100644
index 00..ab3e4773a4
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M0x45D0
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST  0x45D1
+#define PULSAR_SL_MCU_0_CPU0_WMST  0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST  0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST  0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST00x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST00x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST10x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST10x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM  0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM  0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD   0x45D9840

[PATCH 4/7] arm: mach-k3: j784s4: Enable QoS for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.
ATYPE 3 is selected so that the traffic takes non-coherent path and does
not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])

Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruj52

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j784s4/j784s4_init.c |  30 +
 arch/arm/mach-k3/r5/j784s4/Makefile   |   1 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h   |  83 +
 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 109 ++
 4 files changed, 223 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 1ce13e0f49..07b5d7d750 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -23,6 +23,24 @@
 
 #define J784S4_MAX_DDR_CONTROLLERS 4
 
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+#define NB_THREADMAP_BIT2  BIT(2)
+
 struct fwl_data infra_cbass0_fwls[] = {
{ "PSC0", 5, 1 },
{ "PLL_CTRL0", 6, 1 },
@@ -94,6 +112,13 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(CTRL_MMR0_BASE, 7);
 }
 
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -210,6 +235,11 @@ void board_init_f(ulong dummy)
 {
k3_spl_init();
k3_mem_init();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile 
b/arch/arm/mach-k3/r5/j784s4/Makefile
index 9ce88305f5..0fd6cabd3f 100644
--- a/arch/arm/mach-k3/r5/j784s4/Makefile
+++ b/arch/arm/mach-k3/r5/j784s4/Makefile
@@ -5,3 +5,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j784s4_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h 
b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
new file mode 100644
index 00..5851f889fe
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M0x45D0
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST  0x45D1
+#define PULSAR_SL_MCU_0_CPU0_WMST  0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST  0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST  0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST00x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST00x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST10x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST10x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM  0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM  0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD   0x45D98400
+#define PCIE_G3X4_128_MAIN

[PATCH 5/7] configs: j721e_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j721e_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index cea48b2613..5d48f48367 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J721E=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
-- 
2.25.1

[PATCH 6/7] configs: j721s2_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j721s2_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 3c958cafbe..d53c5e33d6 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J721S2=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J721S2_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-- 
2.25.1

[PATCH 7/7] configs: j784s4_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j784s4_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index f5fe743220..d1bcf792d7 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J784S4=y
 CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
 CONFIG_TARGET_J784S4_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-- 
2.25.1

[PATCH 01/14] arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries

[Jayesh Choudhary]

Sort CONFIG_SOC* and K3_SOC_ID alphabetically.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/hardware.h | 37 
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index c724450638..c3aaded8dc 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -8,37 +8,38 @@
 
 #include 
 
-#ifdef CONFIG_SOC_K3_AM654
-#include "am6_hardware.h"
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721E
-#include "j721e_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62A7
+#include "am62a_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721S2
-#include "j721s2_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62P5
+#include "am62p_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_AM642
 #include "am64_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM625
-#include "am62_hardware.h"
+#ifdef CONFIG_SOC_K3_AM654
+#include "am6_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62A7
-#include "am62a_hardware.h"
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62P5
-#include "am62p_hardware.h"
-#endif
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_ID   (WKUP_CTRL_MMR0_BASE + 0x14)
@@ -63,14 +64,14 @@ static inline bool soc_is_##id(void) \
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
return soc == JTAG_ID_PARTNO_##ID; \
 }
-K3_SOC_ID(am65x, AM65X)
-K3_SOC_ID(j721e, J721E)
-K3_SOC_ID(j7200, J7200)
-K3_SOC_ID(am64x, AM64X)
-K3_SOC_ID(j721s2, J721S2)
 K3_SOC_ID(am62x, AM62X)
 K3_SOC_ID(am62ax, AM62AX)
 K3_SOC_ID(am62px, AM62PX)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j721s2, J721S2)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
-- 
2.25.1

[PATCH 00/14] Add basic U-Boot Support for J722S-EVM

[Jayesh Choudhary]

Hello there,

This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.

Some highlights of J722S SoC (in addition to AM62P SoC features) are:

- Two Cortex-R5F for Functional Safety or general-purpose usage and
  two C7x floating point vector DSP with Matrix Multiply Accelerator
  for deep learning.
  
- Vision Processing Accelerator (VPAC) with image signal processor
  and Depth and Motion Processing Accelerator (DMPAC).

- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
  ePWM, among other peripherals.
  
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>

Boot test log:
<https://gist.github.com/Jayesh2000/838fe1b6f69cb3a6e44c56d07c835c65>

RFC series that was posted before this:
<https://lore.kernel.org/all/20240404090039.87458-1-j-choudh...@ti.com/>

Changes from RFC series to this series:
- Remove main_pktdma node and k3_sysreset node from
  k3-j722s-evm-u-boot.dtsi as suggested by Andrew[0]
  k3_sysreset will be taken care of in [1] which is not
  a real dependency for this series
- Fix documentation according to comments here[2]
- Pick up R-by for 2 patches from RFC series[3][4]
- Pick the binman change for optional DM[5]
- Move init code according to [6]


[0]: https://lore.kernel.org/all/d738eaaf-6f13-4502-98a1-ef1bfe82d...@ti.com/
[1]: https://lore.kernel.org/all/20240402160908.508974-3-...@ti.com/
[2]: https://lore.kernel.org/all/ac5780c5-f1ca-4138-a027-d3ed65911...@ti.com/
[3]: 
https://lore.kernel.org/all/20240404163641.6qmcierya6svc...@bryanbrattlof.com/
[4]: 
https://lore.kernel.org/all/20240404163714.p2wonpenkiz44...@bryanbrattlof.com/
[5]: https://lore.kernel.org/all/20240529074849.363281-1-n-fran...@ti.com/
[6]: https://lore.kernel.org/all/20240510202124.794448-1-...@ti.com/

Jayesh Choudhary (14):
  arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries
  soc: ti: k3-socinfo: Fix SOC JTAG entry order
  soc: add info to identify the J722S SoC family
  clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order
  power: domain: ti: Fix the order for platform data entries
  arm: mach-k3: r5: Makefile: Fix the order for entries
  arm: mach-k3: j722s: introduce clock and device files for wkup spl
  ram: k3-ddrss: Enable the am62ax's DDR controller for J722S
  arch: mach-k3: Introduce basic files to support J722S SoC family
  board: ti: Introduce basic board files for the J722S family
  firmware: ti_sci_static_data: Add static DMA channel
  arm: dts: Introduce J722S U-Boot dts files
  configs: introduce configs needed for the J722S
  doc: board: ti: Add J722S-EVM documentation

 arch/arm/dts/Makefile |2 +
 arch/arm/dts/k3-j722s-binman.dtsi |  172 +
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi| 2795 +
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi |   18 +
 arch/arm/dts/k3-j722s-r5-evm.dts  |   82 +
 arch/arm/mach-k3/Kconfig  |7 +-
 arch/arm/mach-k3/Makefile |1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   43 +-
 .../arm/mach-k3/include/mach/j722s_hardware.h |   83 +
 arch/arm/mach-k3/include/mach/j722s_spl.h |   49 +
 arch/arm/mach-k3/include/mach/spl.h   |4 +
 arch/arm/mach-k3/j722s/Kconfig|   32 +
 arch/arm/mach-k3/j722s/Makefile   |6 +
 arch/arm/mach-k3/j722s/j722s_init.c   |  277 ++
 arch/arm/mach-k3/r5/Makefile  |7 +-
 arch/arm/mach-k3/r5/j722s/Makefile|6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c  |  312 ++
 arch/arm/mach-k3/r5/j722s/dev-data.c  |   69 +
 board/ti/j722s/Kconfig|   26 +
 board/ti/j722s/MAINTAINERS|9 +
 board/ti/j722s/Makefile   |7 +
 board/ti/j722s/board-cfg.yaml |   36 +
 board/ti/j722s/evm.c  |   29 +
 board/ti/j722s/j722s.env  |   15 +
 board/ti/j722s/pm-cfg.yaml|   12 +
 board/ti/j722s/rm-cfg.yaml| 1119 +++
 board/ti/j722s/sec-cfg.yaml   |  379 +++
 board/ti/j722s/tifs-rm-cfg.yaml   |  981 ++
 configs/j722s_evm_a53_defconfig   |  177 ++
 configs/j722s_evm_r5_defconfig|  137 +
 doc/board/ti/j722s_evm.rst|  260 ++
 doc/board/ti/k3.rst   |1 +
 drivers/clk/ti/clk-k3.c   |   41 +-
 drivers/firmware/ti_sci_static_data.h |2 +-
 drivers/power/domain/ti-power-domain.c|   36 +-
 drivers/ram/Kconfig   |

[PATCH 02/14] soc: ti: k3-socinfo: Fix SOC JTAG entry order

[Jayesh Choudhary]

Add JTAG_ID_PARTNO_* in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 drivers/soc/soc_ti_k3.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b585e47d46..0838808515 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -23,33 +23,33 @@ static const char *get_family_string(u32 idreg)
soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
switch (soc) {
+   case JTAG_ID_PARTNO_AM62X:
+   family = "AM62X";
+   break;
+   case JTAG_ID_PARTNO_AM62AX:
+   family = "AM62AX";
+   break;
+   case JTAG_ID_PARTNO_AM62PX:
+   family = "AM62PX";
+   break;
+   case JTAG_ID_PARTNO_AM64X:
+   family = "AM64X";
+   break;
case JTAG_ID_PARTNO_AM65X:
family = "AM65X";
break;
-   case JTAG_ID_PARTNO_J721E:
-   family = "J721E";
-   break;
case JTAG_ID_PARTNO_J7200:
family = "J7200";
break;
-   case JTAG_ID_PARTNO_AM64X:
-   family = "AM64X";
+   case JTAG_ID_PARTNO_J721E:
+   family = "J721E";
break;
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
-   case JTAG_ID_PARTNO_AM62X:
-   family = "AM62X";
-   break;
-   case JTAG_ID_PARTNO_AM62AX:
-   family = "AM62AX";
-   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-   case JTAG_ID_PARTNO_AM62PX:
-   family = "AM62PX";
-   break;
default:
family = "Unknown Silicon";
};
-- 
2.25.1

[PATCH 03/14] soc: add info to identify the J722S SoC family

[Jayesh Choudhary]

Include the part number for TI's j722s family of SoC
to identify it during boot.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/hardware.h | 2 ++
 drivers/soc/soc_ti_k3.c  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index c3aaded8dc..26c5bfcf76 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -55,6 +55,7 @@
 #define JTAG_ID_PARTNO_J7200   0xbb6d
 #define JTAG_ID_PARTNO_J721E   0xbb64
 #define JTAG_ID_PARTNO_J721S2  0xbb75
+#define JTAG_ID_PARTNO_J722S0xbba0
 #define JTAG_ID_PARTNO_J784S4  0xbb80
 
 #define K3_SOC_ID(id, ID) \
@@ -72,6 +73,7 @@ K3_SOC_ID(am65x, AM65X)
 K3_SOC_ID(j7200, J7200)
 K3_SOC_ID(j721e, J721E)
 K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(j722s, J722S)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 0838808515..f948914d21 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -47,6 +47,9 @@ static const char *get_family_string(u32 idreg)
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
+   case JTAG_ID_PARTNO_J722S:
+   family = "J722S";
+   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-- 
2.25.1

[PATCH 04/14] clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order

[Jayesh Choudhary]

Use IS_ENABLED macro for the platform clock-data list and add them
in alphabetical order.

Reviewed-by: Bryan Brattlof 
Signed-off-by: Jayesh Choudhary 
---
 drivers/clk/ti/clk-k3.c | 41 +
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 41e5022ea0..9e17755c24 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -59,6 +59,24 @@ static void clk_add_map(struct ti_clk_data *data, struct clk 
*clk,
 }
 
 static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_clk_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -68,35 +86,18 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = &j7200_clk_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = &j721s2_clk_platdata,
},
 #endif
-#ifdef CONFIG_SOC_K3_AM625
-   {
-   .family = "AM62X",
-   .data = &am62x_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_AM62A7
-   {
-   .family = "AM62AX",
-   .data = &am62ax_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_J784S4
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_clk_platdata,
},
-#endif
-#ifdef CONFIG_SOC_K3_AM62P5
-   {
-   .family = "AM62PX",
-   .data = &am62px_clk_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[PATCH 05/14] power: domain: ti: Fix the order for platform data entries

[Jayesh Choudhary]

Add the power domain platform data entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 drivers/power/domain/ti-power-domain.c | 36 +-
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
index b059dd3737..362fae86a2 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -71,6 +71,24 @@ static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 
reg)
 }
 
 static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_pd_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -87,29 +105,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.data = &j721s2_pd_platdata,
},
 #endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM625)
-   {
-   .family = "AM62X",
-   .data = &am62x_pd_platdata,
-   },
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
-   {
-   .family = "AM62AX",
-   .data = &am62ax_pd_platdata,
-   },
-#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_pd_platdata,
},
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
-   {
-   .family = "AM62PX",
-   .data = &am62px_pd_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[PATCH 06/14] arm: mach-k3: r5: Makefile: Fix the order for entries

[Jayesh Choudhary]

Add the entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/r5/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index 1cfc8e3ade..f1e61c8548 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -3,13 +3,13 @@
 # Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 #  Andrew Davis 
 
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
-obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 
 obj-y += common.o
 obj-y += lowlevel_init.o
-- 
2.25.1

[PATCH 08/14] ram: k3-ddrss: Enable the am62ax's DDR controller for J722S

[Jayesh Choudhary]

The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 drivers/ram/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 9838a2798f..a64d2dff68 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,7 +65,7 @@ choice
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
-   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5
+   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
 
 config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
-- 
2.25.1

[PATCH 07/14] arm: mach-k3: j722s: introduce clock and device files for wkup spl

[Jayesh Choudhary]

Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.

Reviewed-by: Bryan Brattlof 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/r5/Makefile   |   1 +
 arch/arm/mach-k3/r5/j722s/Makefile |   6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c   | 312 +
 arch/arm/mach-k3/r5/j722s/dev-data.c   |  69 ++
 drivers/clk/ti/clk-k3.c|   6 +
 drivers/power/domain/ti-power-domain.c |   6 +
 include/k3-clk.h   |   1 +
 include/k3-dev.h   |   1 +
 8 files changed, 402 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j722s/Makefile
 create mode 100644 arch/arm/mach-k3/r5/j722s/clk-data.c
 create mode 100644 arch/arm/mach-k3/r5/j722s/dev-data.c

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index f1e61c8548..d3886caa06 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
 
 obj-y += common.o
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile 
b/arch/arm/mach-k3/r5/j722s/Makefile
new file mode 100644
index 00..2a0dbf5f5a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c 
b/arch/arm/mach-k3/r5/j722s/clk-data.c
new file mode 100644
index 00..b4f27af333
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J722S specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   NULL,
+   NULL,
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_hfosc0_clkout",
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+   "board_0_mmc1_clklb_out",
+   "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+   "board_0_ospi0_dqs_out",
+   "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = 
{
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_2_hsdivout5_clk",
+   "postdiv4_16ff_main_0_hsdivout6_clk",
+   "board_0_cp_gemac_cpts0_rft_clk_out",
+   NULL,
+   "board_0_mcu_ext_refclk0_out",
+   "board_0_ext_refclk1_out",
+   "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+   "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_main_0_hsdivout1_clk",
+   "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "clk_32k_rc_sel_out0",
+   "postdiv4_16ff_main_0_hsdivout7_clk",
+   "g

[RFC PATCH 00/15] Add basic U-Boot Support for J722S-EVM

[Jayesh Choudhary]

Hello there,

This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.

Some highlights of J722S SoC (in addition to AM62P SoC features) are:

- Two Cortex-R5F for Functional Safety or general-purpose usage and
  two C7x floating point vector DSP with Matrix Multiply Accelerator
  for deep learning.
  
- Vision Processing Accelerator (VPAC) with image signal processor
  and Depth and Motion Processing Accelerator (DMPAC).

- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
  ePWM, among other peripherals.
  
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>

Bootlog test:
<https://gist.github.com/Jayesh2000/3a662b380e64aaa227256dbbcef3fe0d>

NOTE: This series depends on the latest dts pull form upstream that will
add the dts changes for J722S-EVM. So the first patch adds the relavent
dts updates which is *NOT SUPPOSED TO BE MERGED*

Jayesh Choudhary (15):
  DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts
  arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries
  soc: ti: k3-socinfo: Fix SOC JTAG entry order
  soc: add info to identify the J722S SoC family
  clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order
  power: domain: ti: Fix the order for platform data entries
  arm: mach-k3: r5: Makefile: Fix the order for entries
  arm: mach-k3: j722s: introduce clock and device files for wkup spl
  ram: k3-ddrss: Enable the am62ax's DDR controller for J722S
  arch: mach-k3: Introduce basic files to support J722S SoC family
  board: ti: Introduce basic board files for the J722S family
  firmware: ti_sci_static_data: Add static DMA channel
  arm: dts: Introduce J722S U-Boot dts files
  configs: introduce configs needed for the J722S
  doc: board: ti: Add J722S-EVM documentation

 arch/arm/dts/Makefile |2 +
 arch/arm/dts/k3-j722s-binman.dtsi |  171 +
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi| 2795 +
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi |   36 +
 arch/arm/dts/k3-j722s-r5-evm.dts  |   82 +
 arch/arm/mach-k3/Kconfig  |7 +-
 arch/arm/mach-k3/Makefile |1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   43 +-
 .../arm/mach-k3/include/mach/j722s_hardware.h |   83 +
 arch/arm/mach-k3/include/mach/j722s_spl.h |   49 +
 arch/arm/mach-k3/include/mach/spl.h   |4 +
 arch/arm/mach-k3/j722s/Kconfig|   32 +
 arch/arm/mach-k3/j722s_init.c |  276 ++
 arch/arm/mach-k3/r5/Makefile  |7 +-
 arch/arm/mach-k3/r5/j722s/Makefile|6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c  |  312 ++
 arch/arm/mach-k3/r5/j722s/dev-data.c  |   69 +
 board/ti/j722s/Kconfig|   26 +
 board/ti/j722s/MAINTAINERS|9 +
 board/ti/j722s/Makefile   |7 +
 board/ti/j722s/board-cfg.yaml |   36 +
 board/ti/j722s/evm.c  |   29 +
 board/ti/j722s/j722s.env  |   15 +
 board/ti/j722s/pm-cfg.yaml|   12 +
 board/ti/j722s/rm-cfg.yaml| 1119 +++
 board/ti/j722s/sec-cfg.yaml   |  379 +++
 board/ti/j722s/tifs-rm-cfg.yaml   |  981 ++
 configs/j722s_evm_a53_defconfig   |  177 ++
 configs/j722s_evm_r5_defconfig|  137 +
 doc/board/ti/j722s_evm.rst|  262 ++
 doc/board/ti/k3.rst   |1 +
 drivers/clk/ti/clk-k3.c   |   41 +-
 drivers/firmware/ti_sci_static_data.h |2 +-
 drivers/power/domain/ti-power-domain.c|   36 +-
 drivers/ram/Kconfig   |2 +-
 drivers/soc/soc_ti_k3.c   |   29 +-
 dts/upstream/Bindings/arm/ti/k3.yaml  |6 +
 dts/upstream/src/arm64/ti/k3-j722s-evm.dts|  383 +++
 dts/upstream/src/arm64/ti/k3-j722s.dtsi   |   89 +
 dts/upstream/src/arm64/ti/k3-pinctrl.h|3 +
 include/configs/j722s_evm.h   |   14 +
 include/k3-clk.h  |1 +
 include/k3-dev.h  |1 +
 43 files changed, 7703 insertions(+), 69 deletions(-)
 create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
 crea

[RFC PATCH 04/15] soc: add info to identify the J722S SoC family

[Jayesh Choudhary]

Include the part number for TI's j722s family of SoC
to identify it during boot.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/hardware.h | 2 ++
 drivers/soc/soc_ti_k3.c  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index bbe1fe5c80..b4bc121cbf 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -55,6 +55,7 @@
 #define JTAG_ID_PARTNO_J7200   0xbb6d
 #define JTAG_ID_PARTNO_J721E   0xbb64
 #define JTAG_ID_PARTNO_J721S2  0xbb75
+#define JTAG_ID_PARTNO_J722S0xbba0
 #define JTAG_ID_PARTNO_J784S4  0xbb80
 
 #define K3_SOC_ID(id, ID) \
@@ -72,6 +73,7 @@ K3_SOC_ID(am65x, AM65X)
 K3_SOC_ID(j7200, J7200)
 K3_SOC_ID(j721e, J721E)
 K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(j722s, J722S)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index bcc11e6bff..92a99ec8db 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -48,6 +48,9 @@ static const char *get_family_string(u32 idreg)
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
+   case JTAG_ID_PARTNO_J722S:
+   family = "J722S";
+   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-- 
2.25.1

[RFC PATCH 06/15] power: domain: ti: Fix the order for platform data entries

[Jayesh Choudhary]

Add the power domain platform data entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 drivers/power/domain/ti-power-domain.c | 36 +-
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
index 8996c40ddc..a280859aa5 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -72,6 +72,24 @@ static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 
reg)
 }
 
 static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_pd_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_pd_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -88,29 +106,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.data = &j721s2_pd_platdata,
},
 #endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM625)
-   {
-   .family = "AM62X",
-   .data = &am62x_pd_platdata,
-   },
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
-   {
-   .family = "AM62AX",
-   .data = &am62ax_pd_platdata,
-   },
-#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_pd_platdata,
},
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
-   {
-   .family = "AM62PX",
-   .data = &am62px_pd_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[RFC PATCH 03/15] soc: ti: k3-socinfo: Fix SOC JTAG entry order

[Jayesh Choudhary]

Add JTAG_ID_PARTNO_* in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 drivers/soc/soc_ti_k3.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 3a4e58bba6..bcc11e6bff 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -24,33 +24,33 @@ static const char *get_family_string(u32 idreg)
soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
switch (soc) {
+   case JTAG_ID_PARTNO_AM62X:
+   family = "AM62X";
+   break;
+   case JTAG_ID_PARTNO_AM62AX:
+   family = "AM62AX";
+   break;
+   case JTAG_ID_PARTNO_AM62PX:
+   family = "AM62PX";
+   break;
+   case JTAG_ID_PARTNO_AM64X:
+   family = "AM64X";
+   break;
case JTAG_ID_PARTNO_AM65X:
family = "AM65X";
break;
-   case JTAG_ID_PARTNO_J721E:
-   family = "J721E";
-   break;
case JTAG_ID_PARTNO_J7200:
family = "J7200";
break;
-   case JTAG_ID_PARTNO_AM64X:
-   family = "AM64X";
+   case JTAG_ID_PARTNO_J721E:
+   family = "J721E";
break;
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
-   case JTAG_ID_PARTNO_AM62X:
-   family = "AM62X";
-   break;
-   case JTAG_ID_PARTNO_AM62AX:
-   family = "AM62AX";
-   break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
-   case JTAG_ID_PARTNO_AM62PX:
-   family = "AM62PX";
-   break;
default:
family = "Unknown Silicon";
};
-- 
2.25.1

[RFC PATCH 05/15] clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order

[Jayesh Choudhary]

Use IS_ENABLED macro for the platform clock-data list and add them
in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 drivers/clk/ti/clk-k3.c | 41 +
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 7aa162c2f7..a3c6e79db7 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -60,6 +60,24 @@ static void clk_add_map(struct ti_clk_data *data, struct clk 
*clk,
 }
 
 static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+   {
+   .family = "AM62X",
+   .data = &am62x_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+   {
+   .family = "AM62AX",
+   .data = &am62ax_clk_platdata,
+   },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   {
+   .family = "AM62PX",
+   .data = &am62px_clk_platdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -69,35 +87,18 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = &j7200_clk_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = &j721s2_clk_platdata,
},
 #endif
-#ifdef CONFIG_SOC_K3_AM625
-   {
-   .family = "AM62X",
-   .data = &am62x_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_AM62A7
-   {
-   .family = "AM62AX",
-   .data = &am62ax_clk_platdata,
-   },
-#endif
-#ifdef CONFIG_SOC_K3_J784S4
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_clk_platdata,
},
-#endif
-#ifdef CONFIG_SOC_K3_AM62P5
-   {
-   .family = "AM62PX",
-   .data = &am62px_clk_platdata,
-   },
 #endif
{ /* sentinel */ }
 };
-- 
2.25.1

[RFC PATCH 07/15] arm: mach-k3: r5: Makefile: Fix the order for entries

[Jayesh Choudhary]

Add the entries in alphabetical order.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/r5/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index 1cfc8e3ade..f1e61c8548 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -3,13 +3,13 @@
 # Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 #  Andrew Davis 
 
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
-obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 
 obj-y += common.o
 obj-y += lowlevel_init.o
-- 
2.25.1

[RFC PATCH 02/15] arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries

[Jayesh Choudhary]

Sort CONFIG_SOC* and K3_SOC_ID alphabetically.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/include/mach/hardware.h | 37 
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index af982e70d1..bbe1fe5c80 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -8,37 +8,38 @@
 
 #include 
 
-#ifdef CONFIG_SOC_K3_AM654
-#include "am6_hardware.h"
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721E
-#include "j721e_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62A7
+#include "am62a_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_J721S2
-#include "j721s2_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62P5
+#include "am62p_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_AM642
 #include "am64_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM625
-#include "am62_hardware.h"
+#ifdef CONFIG_SOC_K3_AM654
+#include "am6_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62A7
-#include "am62a_hardware.h"
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
 
-#ifdef CONFIG_SOC_K3_AM62P5
-#include "am62p_hardware.h"
-#endif
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_ID   (WKUP_CTRL_MMR0_BASE + 0x14)
@@ -63,14 +64,14 @@ static inline bool soc_is_##id(void) \
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
return soc == JTAG_ID_PARTNO_##ID; \
 }
-K3_SOC_ID(am65x, AM65X)
-K3_SOC_ID(j721e, J721E)
-K3_SOC_ID(j7200, J7200)
-K3_SOC_ID(am64x, AM64X)
-K3_SOC_ID(j721s2, J721S2)
 K3_SOC_ID(am62x, AM62X)
 K3_SOC_ID(am62ax, AM62AX)
 K3_SOC_ID(am62px, AM62PX)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j721s2, J721S2)
 
 #define K3_SEC_MGR_SYS_STATUS  0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT  0
-- 
2.25.1

[RFC PATCH 01/15] DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts

[Jayesh Choudhary]

j722s dts support that needs to be pulled from devicetree-rebasing
tree. The whole series depends on this support.

Signed-off-by: Jayesh Choudhary 
---
 dts/upstream/Bindings/arm/ti/k3.yaml   |   6 +
 dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 +
 dts/upstream/src/arm64/ti/k3-j722s.dtsi|  89 +
 dts/upstream/src/arm64/ti/k3-pinctrl.h |   3 +
 4 files changed, 481 insertions(+)
 create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts
 create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi

diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml 
b/dts/upstream/Bindings/arm/ti/k3.yaml
index c6506bccfe..d526723484 100644
--- a/dts/upstream/Bindings/arm/ti/k3.yaml
+++ b/dts/upstream/Bindings/arm/ti/k3.yaml
@@ -123,6 +123,12 @@ properties:
   - ti,j721s2-evm
   - const: ti,j721s2
 
+  - description: K3 J722S SoC and Boards
+items:
+  - enum:
+  - ti,j722s-evm
+  - const: ti,j722s
+
   - description: K3 J784s4 SoC
 items:
   - enum:
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts 
b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
new file mode 100644
index 00..cee3a8661d
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S EVM
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Schematics: https://www.ti.com/lit/zip/sprr495
+ */
+
+/dts-v1/;
+
+#include 
+#include "k3-j722s.dtsi"
+
+/ {
+   compatible = "ti,j722s-evm", "ti,j722s";
+   model = "Texas Instruments J722S EVM";
+
+   aliases {
+   serial0 = &wkup_uart0;
+   serial2 = &main_uart0;
+   mmc0 = &sdhci0;
+   mmc1 = &sdhci1;
+   };
+
+   chosen {
+   stdout-path = &main_uart0;
+   };
+
+   memory@8000 {
+   /* 8G RAM */
+   reg = <0x 0x8000 0x 0x8000>,
+ <0x0008 0x8000 0x0001 0x8000>;
+   device_type = "memory";
+   bootph-pre-ram;
+   };
+
+   reserved_memory: reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   secure_tfa_ddr: tfa@9e78 {
+   reg = <0x00 0x9e78 0x00 0x8>;
+   no-map;
+   };
+
+   secure_ddr: optee@9e80 {
+   reg = <0x00 0x9e80 0x00 0x0180>;
+   no-map;
+   };
+
+   wkup_r5fss0_core0_memory_region: r5f-memory@a010 {
+   compatible = "shared-dma-pool";
+   reg = <0x00 0xa010 0x00 0xf0>;
+   no-map;
+   };
+
+   };
+
+   vmain_pd: regulator-0 {
+   /* TPS65988 PD CONTROLLER OUTPUT */
+   compatible = "regulator-fixed";
+   regulator-name = "vmain_pd";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   bootph-all;
+   };
+
+   vsys_5v0: regulator-vsys5v0 {
+   /* Output of LM5140 */
+   compatible = "regulator-fixed";
+   regulator-name = "vsys_5v0";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&vmain_pd>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vdd_mmc1: regulator-mmc1 {
+   /* TPS22918DBVR */
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_mmc1";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   enable-active-high;
+   gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
+   bootph-all;
+   };
+
+   vdd_sd_dv: regulator-TLV71033 {
+   compatible = "regulator-gpio";
+   regulator-name = "tlv71033";
+   pinctrl-names = "default";
+   pinctrl-0 = <&vdd_sd_dv_pins_default>;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   vin-supply = <&vsys_5v0>;
+   gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+   states = &l

[RFC PATCH 09/15] ram: k3-ddrss: Enable the am62ax's DDR controller for J722S

[Jayesh Choudhary]

The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 drivers/ram/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 9838a2798f..a64d2dff68 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,7 +65,7 @@ choice
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
-   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5
+   default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
 
 config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
-- 
2.25.1

[RFC PATCH 08/15] arm: mach-k3: j722s: introduce clock and device files for wkup spl

[Jayesh Choudhary]

Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/r5/Makefile   |   1 +
 arch/arm/mach-k3/r5/j722s/Makefile |   6 +
 arch/arm/mach-k3/r5/j722s/clk-data.c   | 312 +
 arch/arm/mach-k3/r5/j722s/dev-data.c   |  69 ++
 drivers/clk/ti/clk-k3.c|   6 +
 drivers/power/domain/ti-power-domain.c |   6 +
 include/k3-clk.h   |   1 +
 include/k3-dev.h   |   1 +
 8 files changed, 402 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j722s/Makefile
 create mode 100644 arch/arm/mach-k3/r5/j722s/clk-data.c
 create mode 100644 arch/arm/mach-k3/r5/j722s/dev-data.c

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index f1e61c8548..d3886caa06 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
 obj-$(CONFIG_SOC_K3_J721E) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
 
 obj-y += common.o
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile 
b/arch/arm/mach-k3/r5/j722s/Makefile
new file mode 100644
index 00..2a0dbf5f5a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c 
b/arch/arm/mach-k3/r5/j722s/clk-data.c
new file mode 100644
index 00..b4f27af333
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J722S specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   NULL,
+   NULL,
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_hfosc0_clkout",
+   "gluelogic_rcosc_clk_1p0v_97p65k",
+   "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+   "board_0_mmc1_clklb_out",
+   "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+   "board_0_ospi0_dqs_out",
+   "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = 
{
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+   "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_0_hsdivout5_clk",
+   "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+   "postdiv4_16ff_main_2_hsdivout5_clk",
+   "postdiv4_16ff_main_0_hsdivout6_clk",
+   "board_0_cp_gemac_cpts0_rft_clk_out",
+   NULL,
+   "board_0_mcu_ext_refclk0_out",
+   "board_0_ext_refclk1_out",
+   "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+   "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_main_0_hsdivout1_clk",
+   "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "clk_32k_rc_sel_out0",
+   "postdiv4_16ff_main_0_hsdivout7_clk",
+   "gluelogic_rcosc_clkout",

[RFC PATCH 10/15] arch: mach-k3: Introduce basic files to support J722S SoC family

[Jayesh Choudhary]

Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/Kconfig  |   7 +-
 arch/arm/mach-k3/Makefile |   1 +
 arch/arm/mach-k3/include/mach/hardware.h  |   4 +
 .../arm/mach-k3/include/mach/j722s_hardware.h |  83 ++
 arch/arm/mach-k3/include/mach/j722s_spl.h |  49 
 arch/arm/mach-k3/include/mach/spl.h   |   4 +
 arch/arm/mach-k3/j722s/Kconfig|  32 ++
 arch/arm/mach-k3/j722s_init.c | 276 ++
 8 files changed, 455 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h
 create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h
 create mode 100644 arch/arm/mach-k3/j722s/Kconfig
 create mode 100644 arch/arm/mach-k3/j722s_init.c

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2bb970c2d4..f3f42b3921 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -25,6 +25,9 @@ config SOC_K3_J721E
 config SOC_K3_J721S2
bool "TI's K3 based J721S2 SoC Family Support"
 
+config SOC_K3_J722S
+   bool "TI's K3 based J722S SoC Family Support"
+
 config SOC_K3_J784S4
bool "TI's K3 based J784S4 SoC Family Support"
 
@@ -84,6 +87,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
default 0x43c4f290 if SOC_K3_AM62P5
+   default 0x43c7f290 if SOC_K3_J722S
help
  Address at which ROM stores the value which determines if SPL
  is booted up by primary boot media or secondary boot media.
@@ -122,7 +126,7 @@ config K3_EARLY_CONS_IDX
 
 config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
-   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
+   default 0x8000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 
|| SOC_K3_J722S)
default 0x7000
help
  The load address for the ATF image. This value is used to build the
@@ -163,6 +167,7 @@ source "arch/arm/mach-k3/am62ax/Kconfig"
 source "arch/arm/mach-k3/am62px/Kconfig"
 source "arch/arm/mach-k3/j721e/Kconfig"
 source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j722s/Kconfig"
 source "arch/arm/mach-k3/j784s4/Kconfig"
 
 endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 6ee9864c72..87baa6f313 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
 obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
 obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
+obj-$(CONFIG_SOC_K3_J722S) += j722s_init.o
 endif
 obj-y += common.o security.o
diff --git a/arch/arm/mach-k3/include/mach/hardware.h 
b/arch/arm/mach-k3/include/mach/hardware.h
index b4bc121cbf..e8abe01137 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -36,6 +36,10 @@
 #include "j721s2_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J722S
+#include "j722s_hardware.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J784S4
 #include "j784s4_hardware.h"
 #endif
diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h 
b/arch/arm/mach-k3/include/mach/j722s_hardware.h
new file mode 100644
index 00..8d0bec2206
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J722S SoC definitions, structures etc.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __ASM_ARCH_J722S_HARDWARE_H
+#define __ASM_ARCH_J722S_HARDWARE_H
+
+#include 
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#define PADCFG_MMR0_BASE   0x0408
+#define PADCFG_MMR1_BASE   0x000f
+#define CTRL_MMR0_BASE 0x0010
+#define MCU_CTRL_MMR0_BASE 0x0450
+#define WKUP_CTRL_MMR0_BASE0x4300
+
+#define CTRLMMR_MAIN_DEVSTAT   (WKUP_CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT3
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT7
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK  GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK  BIT(13)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* Primary Bootmode MMC Config macros */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
+#define MAIN

[RFC PATCH 12/15] firmware: ti_sci_static_data: Add static DMA channel

[Jayesh Choudhary]

Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 drivers/firmware/ti_sci_static_data.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/ti_sci_static_data.h 
b/drivers/firmware/ti_sci_static_data.h
index 9662bd95f2..3370f80231 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -85,7 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 #endif /* CONFIG_SOC_K3_J721S2 */
 
 #if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
-   IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+   IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S)
 static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
-- 
2.25.1

[RFC PATCH 11/15] board: ti: Introduce basic board files for the J722S family

[Jayesh Choudhary]

Introduce the basic files needed to support the TI J722S family of SoCs.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 board/ti/j722s/Kconfig  |   26 +
 board/ti/j722s/MAINTAINERS  |9 +
 board/ti/j722s/Makefile |7 +
 board/ti/j722s/board-cfg.yaml   |   36 +
 board/ti/j722s/evm.c|   29 +
 board/ti/j722s/j722s.env|   15 +
 board/ti/j722s/pm-cfg.yaml  |   12 +
 board/ti/j722s/rm-cfg.yaml  | 1119 +++
 board/ti/j722s/sec-cfg.yaml |  379 +++
 board/ti/j722s/tifs-rm-cfg.yaml |  981 +++
 10 files changed, 2613 insertions(+)
 create mode 100644 board/ti/j722s/Kconfig
 create mode 100644 board/ti/j722s/MAINTAINERS
 create mode 100644 board/ti/j722s/Makefile
 create mode 100644 board/ti/j722s/board-cfg.yaml
 create mode 100644 board/ti/j722s/evm.c
 create mode 100644 board/ti/j722s/j722s.env
 create mode 100644 board/ti/j722s/pm-cfg.yaml
 create mode 100644 board/ti/j722s/rm-cfg.yaml
 create mode 100644 board/ti/j722s/sec-cfg.yaml
 create mode 100644 board/ti/j722s/tifs-rm-cfg.yaml

diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig
new file mode 100644
index 00..68c214e473
--- /dev/null
+++ b/board/ti/j722s/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM
+
+config SYS_BOARD
+   default "j722s"
+
+config SYS_VENDOR
+   default "ti"
+
+config SYS_CONFIG_NAME
+   default "j722s_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_EVM
+
+config SPL_LDSCRIPT
+   default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS
new file mode 100644
index 00..7908c30def
--- /dev/null
+++ b/board/ti/j722s/MAINTAINERS
@@ -0,0 +1,9 @@
+J722S BOARD
+M: Vaishnav Achath 
+M: Jayesh Choudhary 
+M: Tom Rini 
+S: Maintained
+F: board/ti/j722s/
+F: include/configs/j722s_evm.h
+F: configs/j722s_evm_r5_defconfig
+F: configs/j722s_evm_a53_defconfig
diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile
new file mode 100644
index 00..20d2ec934b
--- /dev/null
+++ b/board/ti/j722s/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evm.o
diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml
new file mode 100644
index 00..f9a4c438ca
--- /dev/null
+++ b/board/ti/j722s/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable: 0x5A
+main_isolation_hostid: 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor: 0x1
+scaling_profile: 0x1
+disable_main_nav_secure_proxy: 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size: 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables: 0x00
+trace_src_enables: 0x00
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
new file mode 100644
index 00..515aaa8187
--- /dev/null
+++ b/board/ti/j722s/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J722S platforms
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int board_init(void)
+{
+   return 0;
+}
+
+int dram_init(void)
+{
+   return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+   return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
new file mode 100644
index 00..f8b6aff2c2
--- /dev/null
+++ b/board/ti/j722s/j722s.env
@@ -0,0 +1,15 @@
+#include 
+#include 
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+   ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml
new file mode 100644
index 00..46b3ad2010
--- /dev/null
+++ b/board/ti/j722s/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https:

[RFC PATCH 14/15] configs: introduce configs needed for the J722S

[Jayesh Choudhary]

Introduce the initial configs needed to support the J722S SoC family.

Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 configs/j722s_evm_a53_defconfig | 177 
 configs/j722s_evm_r5_defconfig  | 137 
 include/configs/j722s_evm.h |  14 +++
 3 files changed, 328 insertions(+)
 create mode 100644 configs/j722s_evm_a53_defconfig
 create mode 100644 configs/j722s_evm_r5_defconfig
 create mode 100644 include/configs/j722s_evm.h

diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
new file mode 100644
index 00..8d29c9601b
--- /dev/null
+++ b/configs/j722s_evm_a53_defconfig
@@ -0,0 +1,177 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+CONFIG_SF_DEFAULT_SPEED=2500
+CONFIG_ENV_SIZE=0x4
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a0
+CONFIG_SPL_BSS_MAX_SIZE=0x8
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET

[RFC PATCH 15/15] doc: board: ti: Add J722S-EVM documentation

[Jayesh Choudhary]

Introduce basic documentation for the J722S-EVM.

Signed-off-by: Jayesh Choudhary 
---
 doc/board/ti/j722s_evm.rst | 262 +
 doc/board/ti/k3.rst|   1 +
 2 files changed, 263 insertions(+)
 create mode 100644 doc/board/ti/j722s_evm.rst

diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
new file mode 100644
index 00..150330f637
--- /dev/null
+++ b/doc/board/ti/j722s_evm.rst
@@ -0,0 +1,262 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jayesh Choudhary 
+
+J722S-EVM Platform
+==
+
+The J722S is a family of  application processors built for Automotive and
+Linux Application development. J722S family of SoCs is a superset of the
+AM62P SoC family and shares similar memory map, thus the nodes are being
+reused from AM62P includes instead of duplicating the definitions.
+
+Some highlights of J722S SoC (in addition to AM62P SoC features) are:
+
+* Two Cortex-R5F for Functional Safety or general-purpose usage and
+  two C7x floating point vector DSP with Matrix Multiply Accelerator
+  for deep learning.
+
+* Vision Processing Accelerator (VPAC) with image signal processor
+  and Depth and Motion Processing Accelerator (DMPAC).
+
+* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
+  NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
+  4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
+  ePWM, among other peripherals.
+
+For those interested, more details about this SoC can be found in the
+Technical Reference Manual here: https://www.ti.com/lit/zip/sprujb3
+
+Boot Flow:
+--
+
+The bootflow is exactly the same as all SoCs in the am62xxx extended SoC
+family. Below is the pictorial representation:
+
+.. image:: img/boot_diagram_k3_current.svg
+  :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+  requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+
+
+0. Setup the environment variables:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. j722s_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_tfa
+:end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_optee
+:end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_spl_r5
+:end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include::  ../ti/k3.rst
+:start-after: .. k3_rst_include_start_build_steps_uboot
+:end-before: .. k3_rst_include_end_build_steps_uboot
+.. j722s_evm_rst_include_end_build_steps
+
+Target Images
+--
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img.  Each SoC
+variant (HS-FS, HS-SE) requires a different source for these files.
+
+ - HS-FS
+
+* tiboot3-j722s-hs-fs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+* tiboot3-j722s-hs-evm.bin from step 3.1
+* tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+  :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+  :alt: tispl.bin image format
+
+A53 SPL DDR Memory Layout
+-
+
+.. j722s_evm_rst_include_start_ddr_mem_layout
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+ - Start Address
+ - End Address
+
+   * - EMPTY
+ - 0x8000
+ - 0x8008
+
+   * - TEXT BASE
+ - 0x8008
+ - 0x800d8000
+
+   * - EMPTY
+ - 0x800d8000
+ - 0x80477660
+
+   * - STACK
+ - 0x80477660
+ - 0x80477e60
+
+   * - GD
+ - 

[RFC PATCH 13/15] arm: dts: Introduce J722S U-Boot dts files

[Jayesh Choudhary]

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/dts/Makefile  |2 +
 arch/arm/dts/k3-j722s-binman.dtsi  |  171 ++
 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
 arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   36 +
 arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
 5 files changed, 3086 insertions(+)
 create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7b7788f755..83b1f267cb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1407,6 +1407,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
 dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
   k3-j784s4-r5-evm.dtb
 
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
  k3-am642-r5-sk.dtb \
  k3-am642-phyboard-electra-rdk.dtb \
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi 
b/arch/arm/dts/k3-j722s-binman.dtsi
new file mode 100644
index 00..fa9a16bc98
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
+
+&binman {
+   tiboot3-j722s-hs-fs-evm.bin {
+   filename = "tiboot3-j722s-hs-fs-evm.bin";
+   symlink = "tiboot3.bin";
+
+   ti-secure-rom {
+   content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, 
<&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <&u_boot_spl_fs>;
+   content-sysfw = <&ti_fs_enc_fs>;
+   content-sysfw-data = <&combined_tifs_cfg_fs>;
+   content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+   content-dm-data = <&combined_dm_cfg_fs>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c7a800>;
+   };
+
+   u_boot_spl_fs: u-boot-spl {
+   no-expanded;
+   };
+
+   ti_fs_enc_fs: ti-fs-enc.bin {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   type = "blob-ext";
+   };
+
+   sysfw_inner_cert_fs: sysfw-inner-cert {
+   filename = 
"ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_dm_cfg_fs: combined-dm-cfg.bin {
+   filename = "combined-dm-cfg.bin";
+   type = "blob-ext";
+   };
+   };
+};
+#endif /*CONFIG_TARGET_J722S_R5_EVM*/
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_EVM)
+
+#define SPL_J722S_EVM_DTB "spl/dts/ti/k3-j722s-evm.dtb"
+#define J722S_EVM_DTB "u-boot.dtb"
+
+&binman {
+   ti-dm {
+   filename = "ti-dm.bin";
+
+   blob-ext {
+   filename = 
"ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+   };
+   };
+
+   ti-spl {
+   insert-template = <&ti_spl_template>;
+
+   fit {
+   images {
+   dm {
+   ti-secure {
+   content = <&dm>;
+   keyfile = "custMpk.pem";
+   };
+
+   dm: ti-dm {
+  

Re: [RFC PATCH 01/15] DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts

[Jayesh Choudhary]

Hello Sumit,

On 05/04/24 10:27, Sumit Garg wrote:

Hi Jayesh,

On Thu, 4 Apr 2024 at 14:30, Jayesh Choudhary  wrote:


j722s dts support that needs to be pulled from devicetree-rebasing
tree. The whole series depends on this support.



Which devicetree-rebasing tag does this patch depend upon? v6.8-dts
has already made its way to U-Boot mainline [1].

[1] 
https://source.denx.de/u-boot/u-boot/-/commit/bc39e06778168a34bb4e0a34fbee4edbde4414d8



These patches are on top of the next branch (same commit)
The required patches[0][2][3] are in tag v6.9-rc1-dts.

[0]: 
<https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=1339c374a4c10f184d2bb4c6dadd3155f9260599>
[2]: 
<https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=4dd9e11aa40f6d7bb2bd4993a8ddf17c935c9686>
[3]: 
<https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=ec136bb18fcc85d32787530bc065bd97ee3bba60>


-Jayesh



-Sumit


Signed-off-by: Jayesh Choudhary 
---
  dts/upstream/Bindings/arm/ti/k3.yaml   |   6 +
  dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 +
  dts/upstream/src/arm64/ti/k3-j722s.dtsi|  89 +
  dts/upstream/src/arm64/ti/k3-pinctrl.h |   3 +
  4 files changed, 481 insertions(+)
  create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts
  create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi

diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml 
b/dts/upstream/Bindings/arm/ti/k3.yaml
index c6506bccfe..d526723484 100644
--- a/dts/upstream/Bindings/arm/ti/k3.yaml
+++ b/dts/upstream/Bindings/arm/ti/k3.yaml
@@ -123,6 +123,12 @@ properties:
- ti,j721s2-evm
- const: ti,j721s2

+  - description: K3 J722S SoC and Boards
+items:
+  - enum:
+  - ti,j722s-evm
+  - const: ti,j722s
+
- description: K3 J784s4 SoC
  items:
- enum:


[...]

Re: [RFC PATCH 15/15] doc: board: ti: Add J722S-EVM documentation

[Jayesh Choudhary]

Hello Andrew,

On 04/04/24 21:19, Andrew Davis wrote:

On 4/4/24 4:00 AM, Jayesh Choudhary wrote:

Introduce basic documentation for the J722S-EVM.

Signed-off-by: Jayesh Choudhary 
---
  doc/board/ti/j722s_evm.rst | 262 +
  doc/board/ti/k3.rst    |   1 +
  2 files changed, 263 insertions(+)
  create mode 100644 doc/board/ti/j722s_evm.rst

diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
new file mode 100644
index 00..150330f637
--- /dev/null
+++ b/doc/board/ti/j722s_evm.rst
@@ -0,0 +1,262 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jayesh Choudhary 
+
+J722S-EVM Platform
+==
+


[...]



+
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS


Why unset, who is setting in the first place?


Ok this might be unnecessary. Could be removed.




+ $ export OPTEE_PLATFORM=k3-am62x


None of the addresses OPTEE cares about changed from AM62?


Nope. We have been carrying the same OPTEE flavour since AM62
in AM62A, AM62P and now in J722S

Yocto machine configurations:

AM62A: 
<https://git.ti.com/cgit/arago-project/meta-ti/tree/meta-ti-bsp/conf/machine/include/am62axx.inc#n18>
AM62P: 
<https://git.ti.com/cgit/arago-project/meta-ti/tree/meta-ti-bsp/conf/machine/include/am62pxx.inc#n15>
J722S: 
<https://git.ti.com/cgit/arago-project/meta-ti/tree/meta-ti-bsp/conf/machine/include/j722s.inc#n15>





+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"


Do you still need this, the HW RNG should work now.



Yes. We still need SW RNG.

Warm Regards,
-Jayesh

[...]

Re: [RFC PATCH 13/15] arm: dts: Introduce J722S U-Boot dts files

[Jayesh Choudhary]

Hi,

On 04/04/24 20:59, Andrew Davis wrote:

On 4/4/24 4:00 AM, Jayesh Choudhary wrote:

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/dts/Makefile  |    2 +
  arch/arm/dts/k3-j722s-binman.dtsi  |  171 ++
  arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
  arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   36 +
  arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
  5 files changed, 3086 insertions(+)
  create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts



[...]

diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi 
b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi

new file mode 100644
index 00..056ef08455
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common J722S EVM dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - 
https://www.ti.com/

+ */
+
+#include "k3-j722s-binman.dtsi"
+
+/ {
+    chosen {
+    stdout-path = "serial2:115200n8";
+    tick-timer = &main_timer0;
+    };
+};
+
+&main_pktdma {
+    reg = <0x00 0x485c 0x00 0x000100>,
+  <0x00 0x4a80 0x00 0x02>,
+  <0x00 0x4aa0 0x00 0x04>,
+  <0x00 0x4b80 0x00 0x40>,
+  <0x00 0x485e 0x00 0x02>,
+  <0x00 0x484a 0x00 0x004000>,
+  <0x00 0x484c 0x00 0x002000>,
+  <0x00 0x4843 0x00 0x004000>;
+    reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+    "cfg", "tchan", "rchan", "rflow";


Is this needed? Do we still not have the correct regs in
upstream kernel?


I missed this change when I was going through j722s dts changes.

u-boot dts currently does not have this fixed.
Tag v6.9-rc1-dts from devicetree-rebasing would have this fix.

Will keep this in mind.

Also from TRM memory map, the range is off for 'tchanrt'
Will send a fix patch for that after checking for all platforms
to linux upstream if required.




+};
+
+&dmsc {
+    bootph-pre-ram;
+
+    k3_sysreset: sysreset-controller {
+    compatible = "ti,sci-sysreset";
+    bootph-pre-ram;


This node won't be needed soon either[0]. Should mean an
almost empty -u-boot.dtsi file, which should be the goal.



Okay. I will remove the node.

Should I mark [0] as dependency or is it okay without it.
Impact would only be on U-Boot RESET I think. Base support
would still be functional.

Thanks,
Jayesh


Andrew

[0] https://lore.kernel.org/all/20240402160908.508974-1-...@ti.com/


+    };


[...]

[PATCH] configs: j721s2_evm_a72_defconfig: fix the bootcmd

[Jayesh Choudhary]

Remove the main_cpsw0_qsgmii_phyinit variable from the boot
command as there is no ethernet firmware in j721s2.

Fixes: 8886341aa670 ('configs: j721s2_evm_a72_defconfig: Add A72 specific 
defconfig')
Signed-off-by: Jayesh Choudhary 
---
 configs/j721s2_evm_a72_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 14dfb6946f..1577b40393 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -32,7 +32,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run 
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run 
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run 
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run 
get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-- 
2.25.1

[PATCH] arm: dts: k3-j722s-binman: Add support for HS-SE

[Jayesh Choudhary]

From: Udit Kumar 

J722S SOC have two variants as HS-FS and HS-SE.
Add binman support for HS-SE variant.

Signed-off-by: Udit Kumar 
[j-choudh...@ti.com: Fix load-dm-data entry and indentation]
Signed-off-by: Jayesh Choudhary 
---
 arch/arm/dts/k3-j722s-binman.dtsi | 50 +++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/dts/k3-j722s-binman.dtsi 
b/arch/arm/dts/k3-j722s-binman.dtsi
index 28087a3b6f..6b52116657 100644
--- a/arch/arm/dts/k3-j722s-binman.dtsi
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -7,6 +7,56 @@
 
 #if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
 
+&binman {
+   tiboot3-j722s-hs-evm.bin {
+   filename = "tiboot3-j722s-hs-evm.bin";
+   ti-secure-rom {
+   content = <&u_boot_spl>, <&ti_fs_enc>, 
<&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <&u_boot_spl>;
+   content-sysfw = <&ti_fs_enc>;
+   content-sysfw-data = <&combined_tifs_cfg>;
+   content-sysfw-inner-cert = <&sysfw_inner_cert>;
+   content-dm-data = <&combined_dm_cfg>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c7a800>;
+   };
+
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+
+   ti_fs_enc: ti-fs-enc.bin {
+   filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_tifs_cfg: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   type = "blob-ext";
+   };
+
+   sysfw_inner_cert: sysfw-inner-cert {
+   filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+
+   combined_dm_cfg: combined-dm-cfg.bin {
+   filename = "combined-dm-cfg.bin";
+   type = "blob-ext";
+   };
+   };
+};
+
 &binman {
tiboot3-j722s-hs-fs-evm.bin {
filename = "tiboot3-j722s-hs-fs-evm.bin";
-- 
2.34.1

Re: [PATCH] board: ti: j722s: Update Resource Management configs

[Jayesh Choudhary]

Hello Vaishnav,

On 16/09/24 02:17, Vaishnav Achath wrote:

Update J722S Resource Management configs to the latest output
generated by K3 Resource Partitioning tool. Main change includes
allocating more BCDMA channels to A53 for CSI2RX to support
4 x CSIRX capture instance simultaneously.

Signed-off-by: Vaishnav Achath 


Reviewed-by: Jayesh Choudhary 


---

Test logs (CSI capture + RM config dump):
https://gist.github.com/vachath/7b37cd288ef16ad8a2ac6ff5710d1e9a

  board/ti/j722s/rm-cfg.yaml  | 48 ++---
  board/ti/j722s/tifs-rm-cfg.yaml | 28 +--
  2 files changed, 53 insertions(+), 23 deletions(-)

diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml
index 21ca30104c..e32beb8479 100644
--- a/board/ti/j722s/rm-cfg.yaml
+++ b/board/ti/j722s/rm-cfg.yaml
@@ -244,7 +244,7 @@ rm-cfg:
  subhdr:
  magic: 0x7B25
  size: 8
-resasg_entries_size: 1160
+resasg_entries_size: 1184
  reserved: 0
  resasg_entries:
  -
@@ -1017,13 +1017,13 @@ rm-cfg:
  reserved: 0
  -
  start_resource: 8
-num_resource: 12
+num_resource: 32
  type: 12750
  host_id: 12
  reserved: 0
  -
-start_resource: 20
-num_resource: 20
+start_resource: 8
+num_resource: 32
  type: 12750
  host_id: 38
  reserved: 0
@@ -1035,13 +1035,13 @@ rm-cfg:
  reserved: 0
  -
  start_resource: 0
-num_resource: 12
+num_resource: 32
  type: 12769
  host_id: 12
  reserved: 0
  -
-start_resource: 12
-num_resource: 20
+start_resource: 0
+num_resource: 32
  type: 12769
  host_id: 38
  reserved: 0
@@ -1053,10 +1053,22 @@ rm-cfg:
  reserved: 0
  -
  start_resource: 0
-num_resource: 8
+num_resource: 2
  type: 12810
  host_id: 12
  reserved: 0
+-
+start_resource: 2
+num_resource: 2
+type: 12810
+host_id: 20
+reserved: 0
+-
+start_resource: 4
+num_resource: 2
+type: 12810
+host_id: 22
+reserved: 0
  -
  start_resource: 22
  num_resource: 18
@@ -1065,21 +1077,27 @@ rm-cfg:
  reserved: 0
  -
  start_resource: 12288
-num_resource: 64
+num_resource: 56
  type: 12813
  host_id: 12
  reserved: 0
  -
-start_resource: 12352
-num_resource: 64
+start_resource: 12344
+num_resource: 48
  type: 12813
-host_id: 38
+host_id: 20
  reserved: 0
  -
-start_resource: 12416
-num_resource: 88
+start_resource: 12392
+num_resource: 48
  type: 12813
-host_id: 128
+host_id: 22
+reserved: 0
+-
+start_resource: 12440
+num_resource: 64
+type: 12813
+host_id: 38
  reserved: 0
  -
  start_resource: 1536
diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml
index 5e8d7e0444..4a2af0ebca 100644
--- a/board/ti/j722s/tifs-rm-cfg.yaml
+++ b/board/ti/j722s/tifs-rm-cfg.yaml
@@ -244,7 +244,7 @@ tifs-rm-cfg:
  subhdr:
  magic: 0x7B25
  size: 8
-resasg_entries_size: 976
+resasg_entries_size: 992
  reserved: 0
  resasg_entries:
  -
@@ -897,13 +897,13 @@ tifs-rm-cfg:
  reserved: 0
  -
  start_resource: 8
-num_resource: 12
+num_resource: 32
  type: 12750
  host_id: 12
  reserved: 0
  -
-start_resource: 20
-num_resource: 20
+start_resource: 8
+num_resource: 32
  type: 12750
  host_id: 38
  reserved: 0
@@ -915,13 +915,13 @@ tifs-rm-cfg:
  reserved: 0
  -
  start_resource: 0
-num_resource: 12
+num_resource: 32
  type: 12769
  host_id: 12
  reserved: 0
  -
-start_resource: 12
-num_resource: 20
+start_resource: 0
+num_resource: 32
  type: 12769
  host_id: 38
  reserved: 0
@@ -933,10

Re: [PATCH 2/4] arm: mach-k3: am62p: Add QoS support for DSS

[Jayesh Choudhary]

Hello All,

On 06/11/24 12:09, Jayesh Choudhary wrote:

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

The C7x and VPAC can overwhelm the DSS's access to the DDR because of


This part here is wrong as AM62P does not have C7x core.
So I will fix the commit message in the next revision appropriately.
Sorry about that!

(I will re-roll after sometime to see if there are any more comments)


their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.

Signed-off-by: Jayesh Choudhary 
---




[...]

Thanks,
Jayesh

[PATCH 2/4] arm: mach-k3: am62p: Add QoS support for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

The C7x and VPAC can overwhelm the DSS's access to the DDR because of
their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/am62px/am62p5_init.c|  2 +
 arch/arm/mach-k3/r5/am62px/Makefile  |  1 +
 arch/arm/mach-k3/r5/am62px/am62p_qos.h   | 42 ++
 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c | 58 
 4 files changed, 103 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos.h
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c

diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c 
b/arch/arm/mach-k3/am62px/am62p5_init.c
index 34ed01cd78..2d35a7ce77 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -159,6 +159,8 @@ void board_init_f(ulong dummy)
}
 
spl_enable_cache();
+
+   setup_qos();
debug("am62px_init: %s done\n", __func__);
 }
 
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile 
b/arch/arm/mach-k3/r5/am62px/Makefile
index 091d4fa5b4..066c3cef8d 100644
--- a/arch/arm/mach-k3/r5/am62px/Makefile
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += am62p_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos.h 
b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
new file mode 100644
index 00..99e2ee4856
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R   0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W   0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW  0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR  0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM   0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM   0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D23C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC0x45D27400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC0x45D2A000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D3
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0  0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0  0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0  0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0  0x45D35400
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c 
b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
new file mode 100644
index 00..d25512a038
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62p Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "am62p_qos.h"
+
+struct k3_qos_data qos_data[] = {
+   /* modules_qosConfig0 - 1 endpoints, 4 channels */
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   .reg = K3_QOS_REG(K3_D

[PATCH 0/4] Add QOS support for J722S and AM62P

[Jayesh Choudhary]

Add QOS support for DSS in TI K3 SoC to route the DSS traffic through
RT queue by setting orderID as 15:
- J722S
- AM62P

Jayesh Choudhary (4):
  arm: mach-k3: j722s: Add QoS support for DSS
  arm: mach-k3: am62p: Add QoS support for DSS
  configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS

 arch/arm/mach-k3/am62px/am62p5_init.c|  2 +
 arch/arm/mach-k3/j722s/j722s_init.c  |  1 +
 arch/arm/mach-k3/r5/am62px/Makefile  |  1 +
 arch/arm/mach-k3/r5/am62px/am62p_qos.h   | 42 ++
 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c | 58 
 arch/arm/mach-k3/r5/j722s/Makefile   |  1 +
 arch/arm/mach-k3/r5/j722s/j722s_qos.h| 51 +
 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c  | 58 
 configs/am62px_evm_r5_defconfig  |  1 +
 configs/j722s_evm_r5_defconfig   |  1 +
 10 files changed, 216 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos.h
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c

-- 
2.34.1

[PATCH 1/4] arm: mach-k3: j722s: Add QoS support for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

The C7x and VPAC can overwhelm the DSS's access to the DDR because of
their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j722s/j722s_init.c |  1 +
 arch/arm/mach-k3/r5/j722s/Makefile  |  1 +
 arch/arm/mach-k3/r5/j722s/j722s_qos.h   | 51 ++
 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c | 58 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c

diff --git a/arch/arm/mach-k3/j722s/j722s_init.c 
b/arch/arm/mach-k3/j722s/j722s_init.c
index 01b00681f6..0313e1148b 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -165,6 +165,7 @@ void board_init_f(ulong dummy)
 {
k3_spl_init();
k3_mem_init();
+   setup_qos();
 }
 
 static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile 
b/arch/arm/mach-k3/r5/j722s/Makefile
index 2a0dbf5f5a..2f0b35a41e 100644
--- a/arch/arm/mach-k3/r5/j722s/Makefile
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j722s_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos.h 
b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
new file mode 100644
index 00..88fa208322
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R   0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W   0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW  0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR  0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM   0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM   0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D23C00
+#define USB3P0SS64_16FFC_MAIN_0_MSTR0  0x45D24800
+#define USB3P0SS64_16FFC_MAIN_0_MSTW0  0x45D24C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W   0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R   0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC0x45D27400
+#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC0x45D27800
+#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST  0x45D28000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD0x45D29000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR0x45D29400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC0x45D2A000
+#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC0x45D2C000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D3
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0  0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0  0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0  0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0  0x45D35400
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c 
b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
new file mode 100644
index 00..1d59f49252
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j722s Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "j722s_qos.h"
+
+struct k3_qos_data qos_data[] = {
+   /* modules_qosConfig0 - 1 endpoi

[PATCH 4/4] configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/am62px_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index 4f7be44cfb..edff75de74 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -91,6 +91,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
-- 
2.34.1

[PATCH 3/4] configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j722s_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index e574be9e19..d119e46ff1 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -91,6 +91,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
-- 
2.34.1

[PATCH v2 2/4] arm: mach-k3: am62p: Add QoS support for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

DDR intensive software applications can overwhelm the DSS's access to
the DDR because of their higher frequency DDR accesses. This can cause
flickering in display with certain applications running parallely if
the DSS traffic is being serviced through non-RT queue.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/am62px/am62p5_init.c|  2 +
 arch/arm/mach-k3/r5/am62px/Makefile  |  1 +
 arch/arm/mach-k3/r5/am62px/am62p_qos.h   | 42 ++
 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c | 58 
 4 files changed, 103 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos.h
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c

diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c 
b/arch/arm/mach-k3/am62px/am62p5_init.c
index 34ed01cd78..2d35a7ce77 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -159,6 +159,8 @@ void board_init_f(ulong dummy)
}
 
spl_enable_cache();
+
+   setup_qos();
debug("am62px_init: %s done\n", __func__);
 }
 
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile 
b/arch/arm/mach-k3/r5/am62px/Makefile
index 091d4fa5b4..066c3cef8d 100644
--- a/arch/arm/mach-k3/r5/am62px/Makefile
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += am62p_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos.h 
b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
new file mode 100644
index 00..99e2ee4856
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R   0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W   0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW  0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR  0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM   0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM   0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D23C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC0x45D27400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC0x45D2A000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D3
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0  0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0  0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0  0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0  0x45D35400
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c 
b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
new file mode 100644
index 00..d25512a038
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62p Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "am62p_qos.h"
+
+struct k3_qos_data qos_data[] = {
+   /* modules_qosConfig0 - 1 endpoints, 4 channels */
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+   .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+   },
+   {
+   

[PATCH v2 3/4] configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/j722s_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index a3c13fedef..0f7cd4bf37 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
-- 
2.34.1

[PATCH v2 0/4] Add QOS support for J722S and AM62P

[Jayesh Choudhary]

Add QOS support for DSS in TI K3 SoC to route the DSS traffic through
RT queue by setting orderID as 15:
- J722S
- AM62P

Changelog v1->v2:
- Rebased on the tip of next branch
- Corrected the commit message in patch 2/4

v1:
<https://lore.kernel.org/all/20241106063930.59870-1-j-choudh...@ti.com/>

Jayesh Choudhary (4):
  arm: mach-k3: j722s: Add QoS support for DSS
  arm: mach-k3: am62p: Add QoS support for DSS
  configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS
  configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS

 arch/arm/mach-k3/am62px/am62p5_init.c|  2 +
 arch/arm/mach-k3/j722s/j722s_init.c  |  1 +
 arch/arm/mach-k3/r5/am62px/Makefile  |  1 +
 arch/arm/mach-k3/r5/am62px/am62p_qos.h   | 42 ++
 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c | 58 
 arch/arm/mach-k3/r5/j722s/Makefile   |  1 +
 arch/arm/mach-k3/r5/j722s/j722s_qos.h| 51 +
 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c  | 58 
 configs/am62px_evm_r5_defconfig  |  1 +
 configs/j722s_evm_r5_defconfig   |  1 +
 10 files changed, 216 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos.h
 create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c

-- 
2.34.1

[PATCH v2 4/4] configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS

[Jayesh Choudhary]

Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.

Signed-off-by: Jayesh Choudhary 
---
 configs/am62px_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index a93c33c1d9..a0eaa128f4 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
-- 
2.34.1

[PATCH v2 1/4] arm: mach-k3: j722s: Add QoS support for DSS

[Jayesh Choudhary]

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.

The C7x and VPAC can overwhelm the DSS's access to the DDR because of
their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j722s/j722s_init.c |  1 +
 arch/arm/mach-k3/r5/j722s/Makefile  |  1 +
 arch/arm/mach-k3/r5/j722s/j722s_qos.h   | 51 ++
 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c | 58 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c

diff --git a/arch/arm/mach-k3/j722s/j722s_init.c 
b/arch/arm/mach-k3/j722s/j722s_init.c
index 01b00681f6..0313e1148b 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -165,6 +165,7 @@ void board_init_f(ulong dummy)
 {
k3_spl_init();
k3_mem_init();
+   setup_qos();
 }
 
 static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile 
b/arch/arm/mach-k3/r5/j722s/Makefile
index 2a0dbf5f5a..2f0b35a41e 100644
--- a/arch/arm/mach-k3/r5/j722s/Makefile
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j722s_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos.h 
b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
new file mode 100644
index 00..88fa208322
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R   0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W   0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW  0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR  0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM   0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM   0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D23C00
+#define USB3P0SS64_16FFC_MAIN_0_MSTR0  0x45D24800
+#define USB3P0SS64_16FFC_MAIN_0_MSTW0  0x45D24C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W   0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R   0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC0x45D27400
+#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC0x45D27800
+#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST  0x45D28000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD0x45D29000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR0x45D29400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC0x45D2A000
+#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC0x45D2C000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D3
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0  0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0  0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0  0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0  0x45D35400
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c 
b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
new file mode 100644
index 00..1d59f49252
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j722s Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include 
+#include "j722s_qos.h"
+
+struct k3_qos_data qos_data[] = {
+   /* modules_qosConfig0 - 1 endpoi

Re: [PATCH] arch: arm: mach-k3: j784s4_init: Set CTRL_MMR for AUDIO_REFCLK1 clk_sel

[Jayesh Choudhary]

Hello Andrew,

On 06/01/25 20:42, Andrew Davis wrote:

On 1/6/25 4:04 AM, Jayesh Choudhary wrote:

The default value for the mux to select the parent clock,
AUDIO_REFCLK1_CTRL_CLK_SEL is '1' (31) but the mux input for 31
is marked as 'Reserved' so the ti-sci-clk call for get-parent fails.
Mark it to a valid value, '11100' (28) for MAIN_PLL4_HSDIV2_CLKOUT
to get rid of the linux failures during boot-time like:


So the default value of the mux isn't known by firmware? Sounds like
a firmware issue..

No issue with using the bootloader to making the hardware's default state
more sane. Maybe just add a comment above the writel() line as right now
this is just writing a magic value to a magic address.


Will add the comments in v2.

Thanks,
Jayesh



Andrew


"[    1.573193] ti-sci-clk 44083000.system-controller:clock-controller:
  get-parent failed for dev=157, clk=34, ret=-19"

Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/j784s4/j784s4_init.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c

index 8a41cd3bb5..787cf6261e 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -23,6 +23,9 @@
  #define J784S4_MAX_DDR_CONTROLLERS    4
+#define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL    0x001082e4
+#define AUDIO_REFCLK1_DEFAULT    0x1c
+
  /* NAVSS North Bridge (NB) */
  #define NAVSS0_NBSS_NB0_CFG_MMRS    0x03702000
  #define NAVSS0_NBSS_NB1_CFG_MMRS    0x03703000
@@ -201,6 +204,8 @@ void k3_spl_init(void)
  remove_fwl_configs(navss_cbass0_fwls, 
ARRAY_SIZE(navss_cbass0_fwls));

  }
+    writel(AUDIO_REFCLK1_DEFAULT, 
(uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);

+
  /* Output System Firmware version info */
  k3_sysfw_print_ver();
  }

[PATCH] arch: arm: mach-k3: j784s4_init: Set CTRL_MMR for AUDIO_REFCLK1 clk_sel

[Jayesh Choudhary]

The default value for the mux to select the parent clock,
AUDIO_REFCLK1_CTRL_CLK_SEL is '1' (31) but the mux input for 31
is marked as 'Reserved' so the ti-sci-clk call for get-parent fails.
Mark it to a valid value, '11100' (28) for MAIN_PLL4_HSDIV2_CLKOUT
to get rid of the linux failures during boot-time like:
"[1.573193] ti-sci-clk 44083000.system-controller:clock-controller:
 get-parent failed for dev=157, clk=34, ret=-19"

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 8a41cd3bb5..787cf6261e 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -23,6 +23,9 @@
 
 #define J784S4_MAX_DDR_CONTROLLERS 4
 
+#define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL   0x001082e4
+#define AUDIO_REFCLK1_DEFAULT  0x1c
+
 /* NAVSS North Bridge (NB) */
 #define NAVSS0_NBSS_NB0_CFG_MMRS   0x03702000
 #define NAVSS0_NBSS_NB1_CFG_MMRS   0x03703000
@@ -201,6 +204,8 @@ void k3_spl_init(void)
remove_fwl_configs(navss_cbass0_fwls, 
ARRAY_SIZE(navss_cbass0_fwls));
}
 
+   writel(AUDIO_REFCLK1_DEFAULT, 
(uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);
+
/* Output System Firmware version info */
k3_sysfw_print_ver();
 }
-- 
2.34.1