[U-Boot] [PATCH 0/3] samsung: Add mmc controller to use dw mmc
This patch set for use dw mmc controller. First, add dw mmc controller initialization. And then, change exynos4 mmc gpio configuration. Additionally, I have removed exynos4x12_set_mmc_clk function. Because samsung_get_base_clock() (exynos4x12/ exynos4) return same value. This patch set is tested on Trats2 board. Beomho Seo (3): board: samsung: trats2: Add DW MMC controller initialization arm: exynos: pinmux: Add sdmmc4 gpio confifuration arm: exynos: clock: Remove exynos4x12_set_mmc_clk function arch/arm/cpu/armv7/exynos/clock.c | 29 + arch/arm/cpu/armv7/exynos/pinmux.c | 20 +++- board/samsung/trats2/trats2.c | 31 +-- 3 files changed, 37 insertions(+), 43 deletions(-) -- Best Regards, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] board: samsung: trats2: Add DW MMC controller initialization
Add DW MMC controller initialization.
Selectively use DW MMC controller instead of SDHCI controller.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Minkyu Kang
---
board/samsung/trats2/trats2.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index c17c24d..11bebb9 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -280,18 +281,19 @@ int board_mmc_init(bd_t *bis)
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
+ /* eMMC_EN: SD_0_CDn or SD_4_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio2->k0, 2, 1);
s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
/*
* eMMC GPIO:
* SDR 8-bit@48MHz at MMC0
-* GPK0[0] SD_0_CLK(2)
-* GPK0[1] SD_0_CMD(2)
-* GPK0[2] SD_0_CDn-> Not used
-* GPK0[3:6]SD_0_DATA[0:3](2)
-* GPK1[3:6]SD_0_DATA[0:3](3)
+* SDHCI DW-MMC
+* GPK0[0] SD_0_CLK(2) SD_4_CLK(3)
+* GPK0[1] SD_0_CMD(2) SD_4_CMD(3)
+* GPK0[2] SD_0_CDnSD_4_CDn-> Not used
+* GPK0[3:6]SD_0_DATA[0:3](2) SD_4_DATA[0:3](3)
+* GPK1[3:6]SD_0_DATA[4:7](3) SD_4_DATA[4:7](4)
*
* DDR 4-bit@26MHz at MMC4
* GPK0[0] SD_4_CLK(3)
@@ -301,17 +303,26 @@ int board_mmc_init(bd_t *bis)
* GPK1[3:6]SD_4_DATA[4:7](4)
*/
- err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-
/*
* MMC device init
-* mmc0 : eMMC (8-bit buswidth)
-* mmc2 : SD card (4-bit buswidth)
+* mmc0 : eMMC, sdhci controller (8-bit buswidth)
+* mmc2 : SD card, sdhci controller (4-bit buswidth)
+* mmc4 : eMMC, dw-mmc controller (8-bit buswidth)
*/
+
+#ifndef CONFIG_DWMMC
+ err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err0)
debug("SDMMC0 not configured\n");
else
err0 = s5p_mmc_init(0, 8);
+#else
+ err0 = exynos_pinmux_config(PERIPH_ID_SDMMC4, PINMUX_FLAG_8BIT_MODE);
+ if (err0)
+ debug("SDMMC4 not configured\n");
+ else
+ err0 = exynos_dwmci_add_port(4, 0x1255, 8, 0x0001);
+#endif
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
--
1.7.9.5
--
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[U-Boot] [PATCH 2/3] arm: exynos: pinmux: Add sdmmc4 gpio configuration
For use dwmmc controller, add SDMMC4 gpio configuration.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/pinmux.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 645c497..a67664f 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -623,16 +623,25 @@ static int exynos4_mmc_config(int peripheral, int flags)
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
struct s5p_gpio_bank *bank, *bank_ext;
+ unsigned int func, func_ext = 0;
int i;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio2->k0;
bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x2);
+ func_ext = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
bank = &gpio2->k2;
- bank_ext = &gpio2->k3;
+ func = GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SDMMC4:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x3);
+ func_ext = GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -640,13 +649,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(bank, i, func);
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
- if (flags & PINMUX_FLAG_8BIT_MODE) {
+ if ((flags & PINMUX_FLAG_8BIT_MODE) &&
+ ~(peripheral & PERIPH_ID_SDMMC2)) {
for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(bank_ext, i, func_ext);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
@@ -710,10 +720,10 @@ static int exynos4_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
--
1.7.9.5
--
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[U-Boot] [PATCH 3/3] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
Remove exynos4x12_set_mmc_clk.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 29 +
1 file changed, 1 insertion(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6..2c2029a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
(div & 0xff) << ((dev_index << 4) + 8));
}
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
-* CLK_DIV_FSYS1
-* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-* CLK_DIV_FSYS2
-* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-*/
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
--
1.7.9.5
--
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Re: [U-Boot] [PATCH 1/3] board: samsung: trats2: Add DW MMC controller initialization
Thank you for your reply.
On 03/06/2014 03:58 PM, Minkyu Kang wrote:
> On 05/03/14 10:57, Beomho Seo wrote:
>> Add DW MMC controller initialization.
>> Selectively use DW MMC controller instead of SDHCI controller.
>>
>> Signed-off-by: Beomho Seo
>> Signed-off-by: Jaehoon Chung
>> Cc: Minkyu Kang
>> ---
>> board/samsung/trats2/trats2.c | 31 +--
>> 1 file changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
>> index c17c24d..11bebb9 100644
>> --- a/board/samsung/trats2/trats2.c
>> +++ b/board/samsung/trats2/trats2.c
>> @@ -11,6 +11,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -280,18 +281,19 @@ int board_mmc_init(bd_t *bis)
>>
>> gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
>>
>> -/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
>> +/* eMMC_EN: SD_0_CDn or SD_4_CDn: GPK0[2] Output High */
>> s5p_gpio_direction_output(&gpio2->k0, 2, 1);
>> s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
>>
>> /*
>> * eMMC GPIO:
>> * SDR 8-bit@48MHz at MMC0
>> - * GPK0[0] SD_0_CLK(2)
>> - * GPK0[1] SD_0_CMD(2)
>> - * GPK0[2] SD_0_CDn-> Not used
>> - * GPK0[3:6]SD_0_DATA[0:3](2)
>> - * GPK1[3:6]SD_0_DATA[0:3](3)
>> + * SDHCI DW-MMC
>> + * GPK0[0] SD_0_CLK(2) SD_4_CLK(3)
>> + * GPK0[1] SD_0_CMD(2) SD_4_CMD(3)
>> + * GPK0[2] SD_0_CDnSD_4_CDn-> Not used
>> + * GPK0[3:6]SD_0_DATA[0:3](2) SD_4_DATA[0:3](3)
>> + * GPK1[3:6]SD_0_DATA[4:7](3) SD_4_DATA[4:7](4)
>> *
>> * DDR 4-bit@26MHz at MMC4
>> * GPK0[0] SD_4_CLK(3)
>> @@ -301,17 +303,26 @@ int board_mmc_init(bd_t *bis)
>> * GPK1[3:6]SD_4_DATA[4:7](4)
>> */
>>
>> -err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
>> -
>> /*
>> * MMC device init
>> - * mmc0 : eMMC (8-bit buswidth)
>> - * mmc2 : SD card (4-bit buswidth)
>> + * mmc0 : eMMC, sdhci controller (8-bit buswidth)
>> + * mmc2 : SD card, sdhci controller (4-bit buswidth)
>> + * mmc4 : eMMC, dw-mmc controller (8-bit buswidth)
>> */
>> +
>> +#ifndef CONFIG_DWMMC
>> +err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
>> if (err0)
>> debug("SDMMC0 not configured\n");
>> else
>> err0 = s5p_mmc_init(0, 8);
>> +#else
>> +err0 = exynos_pinmux_config(PERIPH_ID_SDMMC4, PINMUX_FLAG_8BIT_MODE);
>> +if (err0)
>> + debug("SDMMC4 not configured\n");
>> +else
>> +err0 = exynos_dwmci_add_port(4, 0x1255, 8, 0x0001);
>
> what means 0x1255, 0x0001?
>
Firstly, 0x1255 is base address for mobile storage host(SDMMC4).
0x0001 is value for set on CLKSEL register.
I will revise more readable.
>> +#endif
>>
>> /* T-flash detect */
>> s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
>>
>
> Thanks,
> Minkyu Kang.
>
--
Best Regards,
Beomho Seo
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Re: [U-Boot] [PATCH 3/3] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
On 03/06/2014 04:00 PM, Minkyu Kang wrote:
> On 05/03/14 10:57, Beomho Seo wrote:
>> Remove exynos4x12_set_mmc_clk.
>
> Please describe here why you remove it.
>
exynos4x12_set_mmc_clk function have been removed.
Because exynos4x12_clock/ exnos4_clock have same div_fsys* value.
I will describe here again when I send next version.
>>
>> Signed-off-by: Beomho Seo
>> Signed-off-by: Jaehoon Chung
>> Cc: Minkyu Kang
>> ---
>> arch/arm/cpu/armv7/exynos/clock.c | 29 +
>> 1 file changed, 1 insertion(+), 28 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 1fea4d6..2c2029a 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
>> int div)
>> (div & 0xff) << ((dev_index << 4) + 8));
>> }
>>
>> -/* exynos4x12: set the mmc clock */
>> -static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
>> -{
>> -struct exynos4x12_clock *clk =
>> -(struct exynos4x12_clock *)samsung_get_base_clock();
>> -unsigned int addr;
>> -
>> -/*
>> - * CLK_DIV_FSYS1
>> - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
>> - * CLK_DIV_FSYS2
>> - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
>> - */
>> -if (dev_index < 2) {
>> -addr = (unsigned int)&clk->div_fsys1;
>> -} else {
>> -addr = (unsigned int)&clk->div_fsys2;
>> -dev_index -= 2;
>> -}
>> -
>> -clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
>> -(div & 0xff) << ((dev_index << 4) + 8));
>> -}
>> -
>> /* exynos5: set the mmc clock */
>> static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
>> {
>> @@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
>> else
>> exynos5_set_mmc_clk(dev_index, div);
>> } else {
>> -if (proid_is_exynos4412())
>> -exynos4x12_set_mmc_clk(dev_index, div);
>> -else
>> -exynos4_set_mmc_clk(dev_index, div);
>> +exynos4_set_mmc_clk(dev_index, div);
>> }
>> }
>>
>
> Thanks,
> Minkyu Kang.
>
--
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[U-Boot] [PATCH v2 2/4] arm: exynos: pinmux: Add sdmmc4 gpio configuration
For use dwmmc controller at exynos4, add SDMMC gpio configuration.
In case SDMMC2, do not use 8bit mode at exynos4.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v2:
- Fixed value initialise.
- Comment add in function.
arch/arm/cpu/armv7/exynos/pinmux.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 9edb475..3dce5d2 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -632,16 +632,26 @@ static int exynos4_mmc_config(int peripheral, int flags)
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
struct s5p_gpio_bank *bank, *bank_ext;
+ unsigned int func, func_ext;
int i;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio2->k0;
bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x2);
+ func_ext = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
bank = &gpio2->k2;
- bank_ext = &gpio2->k3;
+ func = GPIO_FUNC(0x2);
+ func_ext = 0;
+ break;
+ case PERIPH_ID_SDMMC4:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x3);
+ func_ext = GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -649,13 +659,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(bank, i, func);
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
+ /* SDMMC do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(bank_ext, i, func_ext);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
@@ -722,10 +733,10 @@ static int exynos4_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
--
1.7.9.5
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[U-Boot] [PATCH v2 0/4] samsung: Add mmc controller to use dwmmc
This patch set for use dw mmc controller. Patch enable supporting device tree for dw mmc controller. For use dwmmc controller on trats2 board, enable configuration dw_mmc, exynos_dwmmc, bounce_buffer and then disable sdhci configuration. This patch set tested on TRATS2 board. Changes for v2: - Use device tree for dw mmc controller. - dw mmc node is added device node on exynos4 device tree. - dw mmc controller driver is fixed for use exynos4 and 5. - add fdt compat id of exynos4 dwmmc. - Add comment. Beomho Seo (4): drivers: mmc: dwmmc: enable support for DT arm: exynos: pinmux: Add sdmmc4 gpio configuration arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 arch/arm/cpu/armv7/exynos/clock.c | 29 + arch/arm/cpu/armv7/exynos/pinmux.c | 19 +++ arch/arm/dts/exynos4.dtsi |8 arch/arm/dts/exynos4412-trats2.dts |8 drivers/mmc/exynos_dw_mmc.c| 20 include/fdtdec.h |1 + lib/fdtdec.c |1 + 7 files changed, 50 insertions(+), 36 deletions(-) -- 1.7.9.5 -- Best Regards, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] drivers: mmc: dwmmc: enable support for DT
This patch enable support for device tree for dw-mmc driver.
Driver have been fixed because it is used exynos5 and exynos4.
And then, add fdt compat id of exynos4 dwmmc.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
drivers/mmc/exynos_dw_mmc.c | 20
include/fdtdec.h|1 +
lib/fdtdec.c|1 +
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index de8cdcc..47119e2 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#defineDWMMC_MAX_CH_NUM4
#defineDWMMC_MAX_FREQ 5200
@@ -118,15 +119,21 @@ int exynos_dwmmc_init(const void *blob)
{
int index, bus_width;
int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
+ int err = 0, dev_id, flag, count, i, compat_id;
u32 clksel_val, base, timing[3];
+#ifdef CONFIG_EXYNOS4
+ compat_id = COMPAT_SAMSUNG_EXYNOS4_DWMMC;
+#else
+ compat_id = COMPAT_SAMSUNG_EXYNOS5_DWMMC;
+#endif
+
count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
- DWMMC_MAX_CH_NUM);
+ compat_id, node_list, DWMMC_MAX_CH_NUM);
for (i = 0; i < count; i++) {
int node = node_list[i];
+ struct fdt_gpio_state pwr_gpio;
if (node <= 0)
continue;
@@ -145,6 +152,9 @@ int exynos_dwmmc_init(const void *blob)
else
flag = PINMUX_FLAG_NONE;
+ fdtdec_decode_gpio(blob, node, "pwr-gpios", &pwr_gpio);
+ if (fdt_gpio_isvalid(&pwr_gpio))
+ gpio_direction_output(pwr_gpio.gpio, 1);
/* config pinmux for each mmc channel */
err = exynos_pinmux_config(dev_id, flag);
if (err) {
@@ -152,7 +162,9 @@ int exynos_dwmmc_init(const void *blob)
return err;
}
- index = dev_id - PERIPH_ID_SDMMC0;
+ index = fdtdec_get_int(blob, node, "index", dev_id);
+ if (index == dev_id)
+ index = dev_id - PERIPH_ID_SDMMC0;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 63027bd..15f50fe 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -83,6 +83,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
+ COMPAT_SAMSUNG_EXYNOS4_DWMMC, /* Exynos4 DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index be04598..79179cf 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -56,6 +56,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
+ COMPAT(SAMSUNG_EXYNOS4_DWMMC, "samsung,exynos4412-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
--
1.7.9.5
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[U-Boot] [PATCH v2 3/4] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
exynos4x12_set_mmc_clk function have been removed.
Because exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v2:
- None.
arch/arm/cpu/armv7/exynos/clock.c | 29 +
1 file changed, 1 insertion(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6..2c2029a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
(div & 0xff) << ((dev_index << 4) + 8));
}
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
-* CLK_DIV_FSYS1
-* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-* CLK_DIV_FSYS2
-* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-*/
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
--
1.7.9.5
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[U-Boot] [PATCH v2 4/4] board: trats2: Enable device tree on Trats2
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v2:
- None.
arch/arm/dts/exynos4.dtsi |8
arch/arm/dts/exynos4412-trats2.dts |8
2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 71dc7eb..ab99906 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
+ dwmmc@1255 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos4412-dwmmc";
+ reg = <0x1255 0x1000>;
+ interrupts = <0 131 0>;
+ };
+
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 7d32067..438e70e 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -31,6 +31,7 @@
console = "/serial@1382";
mmc0 = "sdhci@1251";
mmc2 = "sdhci@1253";
+ mmc4 = "dwmmc@1255";
};
i2c@138d {
@@ -431,4 +432,11 @@
sdhci@1254 {
status = "disabled";
};
+
+ dwmmc@1255 {
+ samsung,bus-width = <8>;
+ samsung,timing = <0 1 0>;
+ pwr-gpios = <&gpio 0x2004002 0>;
+ index = <4>;
+ };
};
--
1.7.9.5
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[U-Boot] [PATCH v3 0/4] samsung: Add mmc controller to use dwmmc
This patch set for use dw mmc controller. Patch enable supporting device tree for dw mmc controller. For use dwmmc controller on trats2 board, enable configuration dw_mmc, exynos_dwmmc, bounce_buffer and then disable sdhci configuration. This patch set tested on TRATS2 board. Changes for v3: - Set bank_ext of SDMMC2 for prevent compile warning. - Subtract one from div to set accurate frequency. Changes for v2: - Use device tree for dw mmc controller. - dw mmc node is added device node on exynos4 device tree. - dw mmc controller driver is fixed for use exynos4 and 5. - Add fdt compat id of exynos4 dwmmc. - Add comment. Beomho Seo (4): drivers: mmc: dwmmc: enable support for DT arm: exynos: pinmux: Add sdmmc4 gpio configuration arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 arch/arm/cpu/armv7/exynos/clock.c | 29 + arch/arm/cpu/armv7/exynos/pinmux.c | 18 +++--- arch/arm/dts/exynos4.dtsi |8 arch/arm/dts/exynos4412-trats2.dts |8 drivers/mmc/exynos_dw_mmc.c| 21 + include/fdtdec.h |1 + lib/fdtdec.c |1 + 7 files changed, 51 insertions(+), 35 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/4]drivers: mmc: dwmmc: enable support for DT
This patch enables for device tree for dw-mmc driver.
Driver have been fixed because it is used exynos5 and exynos4.
Add, fdt compat id of exynos4 dwmmc.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v3:
- None.
drivers/mmc/exynos_dw_mmc.c | 21 +
include/fdtdec.h|1 +
lib/fdtdec.c|1 +
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index de8cdcc..b9d41d4 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#defineDWMMC_MAX_CH_NUM4
#defineDWMMC_MAX_FREQ 5200
@@ -82,6 +83,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int
bus_width, u32 clksel)
freq = 5200;
sclk = get_mmc_clk(index);
div = DIV_ROUND_UP(sclk, freq);
+ div -= 1;
/* set the clock divisor for mmc */
set_mmc_clk(index, div);
@@ -118,15 +120,21 @@ int exynos_dwmmc_init(const void *blob)
{
int index, bus_width;
int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
+ int err = 0, dev_id, flag, count, i, compat_id;
u32 clksel_val, base, timing[3];
+#ifdef CONFIG_EXYNOS4
+ compat_id = COMPAT_SAMSUNG_EXYNOS4_DWMMC;
+#else
+ compat_id = COMPAT_SAMSUNG_EXYNOS5_DWMMC;
+#endif
+
count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
- DWMMC_MAX_CH_NUM);
+ compat_id, node_list, DWMMC_MAX_CH_NUM);
for (i = 0; i < count; i++) {
int node = node_list[i];
+ struct fdt_gpio_state pwr_gpio;
if (node <= 0)
continue;
@@ -145,6 +153,9 @@ int exynos_dwmmc_init(const void *blob)
else
flag = PINMUX_FLAG_NONE;
+ fdtdec_decode_gpio(blob, node, "pwr-gpios", &pwr_gpio);
+ if (fdt_gpio_isvalid(&pwr_gpio))
+ gpio_direction_output(pwr_gpio.gpio, 1);
/* config pinmux for each mmc channel */
err = exynos_pinmux_config(dev_id, flag);
if (err) {
@@ -152,7 +163,9 @@ int exynos_dwmmc_init(const void *blob)
return err;
}
- index = dev_id - PERIPH_ID_SDMMC0;
+ index = fdtdec_get_int(blob, node, "index", dev_id);
+ if (index == dev_id)
+ index = dev_id - PERIPH_ID_SDMMC0;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 63027bd..15f50fe 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -83,6 +83,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
+ COMPAT_SAMSUNG_EXYNOS4_DWMMC, /* Exynos4 DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index be04598..79179cf 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -56,6 +56,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
+ COMPAT(SAMSUNG_EXYNOS4_DWMMC, "samsung,exynos4412-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
--
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[U-Boot] {PATCH v3 3/4] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return smae div_fsys* value.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v3:
- None.
Changes for v2:
- None.
arch/arm/cpu/armv7/exynos/clock.c | 29 +
1 file changed, 1 insertion(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6..2c2029a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
(div & 0xff) << ((dev_index << 4) + 8));
}
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
-* CLK_DIV_FSYS1
-* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-* CLK_DIV_FSYS2
-* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-*/
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
--
1.7.9.5
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[U-Boot] {PATCH v3 4/4] board: trats2: Enable device tree on Trats2
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v3:
- Subtract one from div to set accurate frequency.
Changes for v2:
- None.
arch/arm/dts/exynos4.dtsi |8
arch/arm/dts/exynos4412-trats2.dts |8
2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 71dc7eb..ab99906 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
+ dwmmc@1255 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos4412-dwmmc";
+ reg = <0x1255 0x1000>;
+ interrupts = <0 131 0>;
+ };
+
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 7d32067..438e70e 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -31,6 +31,7 @@
console = "/serial@1382";
mmc0 = "sdhci@1251";
mmc2 = "sdhci@1253";
+ mmc4 = "dwmmc@1255";
};
i2c@138d {
@@ -431,4 +432,11 @@
sdhci@1254 {
status = "disabled";
};
+
+ dwmmc@1255 {
+ samsung,bus-width = <8>;
+ samsung,timing = <0 1 0>;
+ pwr-gpios = <&gpio 0x2004002 0>;
+ index = <4>;
+ };
};
--
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[U-Boot] [PATCH v3 2/4] arm: exynos: pinmux: add sdmmc4 gpio configratuion
For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
In case SDMMC2, do not use 8 bit mode at exynos4.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
Changes for v3:
- Set bank_ext of SDMMC2 for prevent compile warning.
Changes for v2:
- Fixed value initialinse.
- Comment add in function.
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 9edb475..55c1c95 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -632,16 +632,27 @@ static int exynos4_mmc_config(int peripheral, int flags)
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
struct s5p_gpio_bank *bank, *bank_ext;
+ unsigned int func, func_ext;
int i;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio2->k0;
bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x2);
+ func_ext = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
bank = &gpio2->k2;
bank_ext = &gpio2->k3;
+ func = GPIO_FUNC(0x2);
+ func_ext = GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ func = GPIO_FUNC(0x3);
+ func_ext = GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -649,13 +660,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(bank, i, func);
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
+ /* SDMMC2 do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(bank_ext, i, func_ext);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
@@ -722,10 +734,10 @@ static int exynos4_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
--
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Re: [U-Boot] {PATCH v3 4/4] board: trats2: Enable device tree on Trats2
On 03/20/2014 01:14 PM, Beomho Seo wrote:
> This patch add dwmmc emmc controller node on exynos4 and exynos4412 device
> tree.
>
> Signed-off-by: Beomho Seo
> Signed-off-by: Jaehoon Chung
> Tested-by: Piotr Wilczek
> Cc: Lukasz Majewski
> Cc: Piotr Wilczek
> Cc: Minkyu Kang
> ---
> Changes for v3:
> - Subtract one from div to set accurate frequency.
>
Sorry for the mistake.
This change log for the patch 1.(drivers: mmc: dwmmc: enable support for DT)
> Changes for v2:
> - None.
>
> arch/arm/dts/exynos4.dtsi |8
> arch/arm/dts/exynos4412-trats2.dts |8
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
> index 71dc7eb..ab99906 100644
> --- a/arch/arm/dts/exynos4.dtsi
> +++ b/arch/arm/dts/exynos4.dtsi
> @@ -128,6 +128,14 @@
> interrupts = <0 78 0>;
> };
>
> + dwmmc@1255 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos4412-dwmmc";
> + reg = <0x1255 0x1000>;
> + interrupts = <0 131 0>;
> + };
> +
> gpio: gpio {
> gpio-controller;
> #gpio-cells = <2>;
> diff --git a/arch/arm/dts/exynos4412-trats2.dts
> b/arch/arm/dts/exynos4412-trats2.dts
> index 7d32067..438e70e 100644
> --- a/arch/arm/dts/exynos4412-trats2.dts
> +++ b/arch/arm/dts/exynos4412-trats2.dts
> @@ -31,6 +31,7 @@
> console = "/serial@1382";
> mmc0 = "sdhci@1251";
> mmc2 = "sdhci@1253";
> + mmc4 = "dwmmc@1255";
> };
>
> i2c@138d {
> @@ -431,4 +432,11 @@
> sdhci@1254 {
> status = "disabled";
> };
> +
> + dwmmc@1255 {
> + samsung,bus-width = <8>;
> + samsung,timing = <0 1 0>;
> + pwr-gpios = <&gpio 0x2004002 0>;
> + index = <4>;
> + };
> };
>
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Re: [U-Boot] {PATCH v3 3/4] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
On 04/08/2014 11:53 AM, Minkyu Kang wrote:
> Dear Beomho Seo,
>
> On 20/03/14 13:14, Beomho Seo wrote:
>> exynos4x12_set_mmc_clk function have been removed.
>> Because, exynos4x12_clock and exynos4_clock return smae div_fsys* value.
>
> typo, smae -> same?
>
Thank you. I will fix this mistake.
>>
>> Signed-off-by: Beomho Seo
>> Signed-off-by: Jaehoon Chung
>> Tested-by: Piotr Wilczek
>> Cc: Lukasz Majewski
>> Cc: Piotr Wilczek
>> Cc: Minkyu Kang
>> ---
>> Changes for v3:
>> - None.
>>
>> Changes for v2:
>> - None.
>>
>> arch/arm/cpu/armv7/exynos/clock.c | 29 +
>> 1 file changed, 1 insertion(+), 28 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 1fea4d6..2c2029a 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
>> int div)
>> (div & 0xff) << ((dev_index << 4) + 8));
>> }
>>
>> -/* exynos4x12: set the mmc clock */
>> -static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
>> -{
>> -struct exynos4x12_clock *clk =
>> -(struct exynos4x12_clock *)samsung_get_base_clock();
>> -unsigned int addr;
>> -
>> -/*
>> - * CLK_DIV_FSYS1
>> - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
>> - * CLK_DIV_FSYS2
>> - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
>> - */
>> -if (dev_index < 2) {
>> -addr = (unsigned int)&clk->div_fsys1;
>> -} else {
>> -addr = (unsigned int)&clk->div_fsys2;
>> -dev_index -= 2;
>> -}
>> -
>> -clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
>> -(div & 0xff) << ((dev_index << 4) + 8));
>> -}
>> -
>> /* exynos5: set the mmc clock */
>> static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
>> {
>> @@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
>> else
>> exynos5_set_mmc_clk(dev_index, div);
>> } else {
>> -if (proid_is_exynos4412())
>> -exynos4x12_set_mmc_clk(dev_index, div);
>> -else
>> -exynos4_set_mmc_clk(dev_index, div);
>> +exynos4_set_mmc_clk(dev_index, div);
>> }
>> }
>>
>
> Thanks,
> Minkyu Kang.
>
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Re: [U-Boot] [PATCH v3 1/4]drivers: mmc: dwmmc: enable support for DT
Thank you for your advice.
On 04/08/2014 11:53 AM, Minkyu Kang wrote:
> Dear Beonho Seo,
>
> On 20/03/14 13:14, Beomho Seo wrote:
>> This patch enables for device tree for dw-mmc driver.
>> Driver have been fixed because it is used exynos5 and exynos4.
>> Add, fdt compat id of exynos4 dwmmc.
>>
>> Signed-off-by: Beomho Seo
>> Signed-off-by: Jaehoon Chung
>> Tested-by: Piotr Wilczek
>> Cc: Lukasz Majewski
>> Cc: Piotr Wilczek
>> Cc: Minkyu Kang
>> ---
>> Changes for v3:
>> - None.
>>
>> drivers/mmc/exynos_dw_mmc.c | 21 +
>> include/fdtdec.h|1 +
>> lib/fdtdec.c|1 +
>> 3 files changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>> index de8cdcc..b9d41d4 100644
>> --- a/drivers/mmc/exynos_dw_mmc.c
>> +++ b/drivers/mmc/exynos_dw_mmc.c
>> @@ -13,6 +13,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #define DWMMC_MAX_CH_NUM4
>> #define DWMMC_MAX_FREQ 5200
>> @@ -82,6 +83,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int
>> bus_width, u32 clksel)
>> freq = 5200;
>> sclk = get_mmc_clk(index);
>> div = DIV_ROUND_UP(sclk, freq);
>> +div -= 1;
>
> why?
>
It need for set accurately required frequency.
Above code prevent to set below the required frequency.
For example above case,
If sclk is 100 MHz and required frequency 50 MHz, Where div = 2.
and then mmc clock set 33 MHz calculating.
So It need div minus one.
>> /* set the clock divisor for mmc */
>> set_mmc_clk(index, div);
>>
>> @@ -118,15 +120,21 @@ int exynos_dwmmc_init(const void *blob)
>> {
>> int index, bus_width;
>> int node_list[DWMMC_MAX_CH_NUM];
>> -int err = 0, dev_id, flag, count, i;
>> +int err = 0, dev_id, flag, count, i, compat_id;
>> u32 clksel_val, base, timing[3];
>>
>> +#ifdef CONFIG_EXYNOS4
>> +compat_id = COMPAT_SAMSUNG_EXYNOS4_DWMMC;
>> +#else
>> +compat_id = COMPAT_SAMSUNG_EXYNOS5_DWMMC;
>> +#endif
>
> NAK.
> please don't use ifdef.
>
OK. I will change it.
>> +
>> count = fdtdec_find_aliases_for_id(blob, "mmc",
>> -COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
>> -DWMMC_MAX_CH_NUM);
>> +compat_id, node_list, DWMMC_MAX_CH_NUM);
>>
>> for (i = 0; i < count; i++) {
>> int node = node_list[i];
>> +struct fdt_gpio_state pwr_gpio;
>>
>> if (node <= 0)
>> continue;
>> @@ -145,6 +153,9 @@ int exynos_dwmmc_init(const void *blob)
>> else
>> flag = PINMUX_FLAG_NONE;
>>
>> +fdtdec_decode_gpio(blob, node, "pwr-gpios", &pwr_gpio);
>> +if (fdt_gpio_isvalid(&pwr_gpio))
>> +gpio_direction_output(pwr_gpio.gpio, 1);
>
> please add blank line.
>
OK. I will add blank line.
>> /* config pinmux for each mmc channel */
>> err = exynos_pinmux_config(dev_id, flag);
>> if (err) {
>> @@ -152,7 +163,9 @@ int exynos_dwmmc_init(const void *blob)
>> return err;
>> }
>>
>> -index = dev_id - PERIPH_ID_SDMMC0;
>> +index = fdtdec_get_int(blob, node, "index", dev_id);
>> +if (index == dev_id)
>> +index = dev_id - PERIPH_ID_SDMMC0;
>
> I can't understand why this routine is needed.
> Could you please explain?
>
SDMMC index(0, 1 ... 4) is need to get/set mmc clk.
It is decided the difference between dev_id and PERIPH_ID_SDMMC0(=75).
But If dev_id is PERIPH_ID_SDMMC4(=131), index is set inaccurately.
So I add index property at device tree. and then parse it.
If index property not exist, index is decided the difference between dev_id and
PERIPH_ID_SDMMC0.
>>
>> /* Get the base address from the device node */
>> base = fdtdec_get_addr(blob, node, "reg");
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 63027bd..15f50fe 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -83,6 +83,7 @@ enum fdt_compat_id {
>> COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
>> COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Ex
