Re: [PATCH v2 1/1] RFC: Move Odroid-C2 to use binman to produce the image
Hi Simon !
On 01/04/2023 20:54, Simon Glass wrote:
This shows how binman can be used to replace the long and complicated
instructions with an automated build. It is still complicated to read
but users don't have to worry about the details.
It needs some tidying up and only supports Odroid-C2 at present.
Like the v1, the work is really nice, but the dependency on vendor binary-only
tools doesn't make feel confident about merging this.
We have open source implementation for all boards, but still dependeing on
tools we must manually build isn't optimal.
What would be optimal would be to re-implement those tools into python
libraries and merge them into the u-boot tree then use them from binman.
But this could be merged as first step, them the python libaray could be
modified to support the binary tools & a probable python re-implementation.
Neil
Signed-off-by: Simon Glass
---
Changes in v2:
- Rebase to -next
arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi | 107
arch/arm/mach-meson/Kconfig | 1 +
doc/board/amlogic/odroid-c4.rst | 127 +--
tools/binman/etype/aml_encrypt.py| 124 ++
tools/binman/ftest.py| 3 +
tools/binman/missing-blob-help | 6 +
tools/binman/test/213_aml_encrypt.dts| 38 ++
tools/binman/test/214_list_no_dtb.dts| 23
8 files changed, 337 insertions(+), 92 deletions(-)
create mode 100644 tools/binman/etype/aml_encrypt.py
create mode 100644 tools/binman/test/213_aml_encrypt.dts
create mode 100644 tools/binman/test/214_list_no_dtb.dts
diff --git a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
index 963bf96b2567..b221ce6920b0 100644
--- a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
+++ b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
@@ -6,6 +6,113 @@
#include "meson-sm1-u-boot.dtsi"
+/{
+ binman {
+ /* run --bootmk on all the included inputs */
+ aml-encrypt {
+ missing-msg = "aml-encrypt";
+ aml-algo = "g12a";
+ aml-op = "bootmk";
+ aml-level = "v3";
+
+ /* produce a bl2, containing signed bl2 binaries */
+ bl2 {
+ type = "aml-encrypt";
+ aml-algo = "g12a";
+ aml-op = "bl2sig";
+
+ /* sign the binary contaiing bl2 and acs */
+ aml-input {
+ type = "section";
+ bl2 {
+ type = "blob-ext";
+ size = <0xe000>;
+ filename = "bl2.bin";
+ };
+ acs {
+ type = "blob-ext";
+ size = <0x1000>;
+ filename = "acs.bin";
+ };
+ };
+ };
+
+ /* produce a bl30, containing signed bl30 binaries */
+ bl30 {
+ type = "aml-encrypt";
+ aml-algo = "g12a";
+ aml-op = "bl3sig";
+ aml-level = "v3";
+ aml-type = "bl30";
+
+ /* sign the binary contaiing bl30 and bl301 */
+ aml-input {
+ type = "aml-encrypt";
+ aml-algo = "g12a";
+ aml-op = "bl30sig";
+ aml-level = "v3";
+
+ /*
+* put bl30 and bl301 together, with
+* the necessary paddiung
+*/
+ aml-input {
+ type = "section";
+ bl30 {
+ type = "blob-ext";
+ size = <0xa000>;
+ filename = "bl30.bin";
+ };
+ bl301 {
+ type = "blob-ext";
+ size = <0x3400>;
+
Re: [PATCH] ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family
Hi,
On 4/3/23 08:04, Patrice Chotard wrote:
Add QSPI support on STM32MP13x SoC family
Signed-off-by: Patrice Chotard
---
arch/arm/dts/stm32mp131.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 3cf51f09bcb..5a064d5566e 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -191,6 +191,21 @@
dma-requests = <48>;
};
+ qspi: spi@58003000 {
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x7000 0x1000>;
+ reg-names = "qspi", "qspi_mm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ dmas = <&mdma 26 0x2 0x1012 0x0 0x0>,
+ <&mdma 26 0x2 0x1018 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x",
"arm,primecell";
arm,primecell-periphid = <0x20253180>;
Reviewed-by: Patrick Delaunay
Thanks
Patrick
Re: [PATCH v2 0/1] meson: Demonstration of using binman to produce the image
> On 2 Apr 2023, at 6:41 am, Simon Glass wrote: > > Hi Mark, > > On Sun, 2 Apr 2023 at 09:28, Mark Kettenis wrote: > > > > > From: Simon Glass > > > Date: Sun, 2 Apr 2023 06:54:57 +1200 > > > > > > The Odroid-C2 is quite a complicated image with many steps. It is an ideal > > > example for how Binman can be used. > > > > You say Odroid-C2, but the patches seem to address the Odroid-C4... > > Ah, yes. The difference seems to be an Amlogic S905 on the C2 and an S902X3 > on the C4. I wonder if that affects the image makeup? There are currently four different signing recipes that depend on the board family that you are building for: - GXBB - GXL/GXM - G12A/SM1 - G12B The G12A/SM1 and G12B recipes are identical except for a different signing binary used. The latest Amlogic boards (S905X4, T7, etc.) also have incremental changes, but none are currently supported in Linux or u-boot. One of the challenges for binman will be the signing tools. Currently this patchset depends upon Amlogic binaries. Apart from them being closed-source and thus undesirable, they are also x86_64 only and there are quite a few users (and at least one major distro) needing to build on arm64 hardware. There is an open-source tool called gxlimg which supports GXL and newer boards. IMHO it would make a lot of sense for u-boot to absorb the functionality of gxlimg (and extend support backwards to GXBB) as this would remove the dependency on Amlogic binaries and allow u-boot build and binman signing to be done anywhere. https://github.com/repk/gxlimg > The patch is for testing by Christian, who I hope can help get this landed > for all the Amlogic boards. I will try to find the time to test this, but it’s not something I could do more with (as only supporting 1/4 of the board families that I need to build for, bu I do appreciate it’s a POC). In case you’re not aware, Makefile based signing is implemented in the amlogic-boot-fip repo that I’m currently tooled around: https://github.com/LibreELEC/amlogic-boot-fip This is the “competition” so to speak. It’s quite simple and widely used by most of the Amlogic supporting distros right now. Christian > > > > > Add a binman description and update the instructions accordingly. > > > > > > Changes in v2: > > > - Rebase to -next > > > > > > Simon Glass (1): > > > RFC: Move Odroid-C2 to use binman to produce the image > > > > > > arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi | 107 > > > arch/arm/mach-meson/Kconfig | 1 + > > > doc/board/amlogic/odroid-c4.rst | 127 +-- > > > tools/binman/etype/aml_encrypt.py| 124 ++ > > > tools/binman/ftest.py| 3 + > > > tools/binman/missing-blob-help | 6 + > > > tools/binman/test/213_aml_encrypt.dts| 38 ++ > > > tools/binman/test/214_list_no_dtb.dts| 23 > > > 8 files changed, 337 insertions(+), 92 deletions(-) > > > create mode 100644 tools/binman/etype/aml_encrypt.py > > > create mode 100644 tools/binman/test/213_aml_encrypt.dts > > > create mode 100644 tools/binman/test/214_list_no_dtb.dts > > > > > Regards, > SImon
[PATCH V5 00/13] Add splash screen support at u-boot SPL
To enable splash screen at SPL stage move video driver and splash screen framework at SPL, which will bring up image on display very quickly and thus have early display support in SPL. Changes in V5 - Drop patch cmd: Makefile: Rule to compile bmp_cmd. - Squash common: splash: Replace CONFIG_CMD_BMP patch into patches common: Enable splash functions at SPL include: Enable video related global data variable and splash at SPL - Fix merge issue for next branch - Replace cmd/bmp_cmd with cmd/bmp - Use CONFIG_$(SPL_TPL_) to compile files in drivers: video: Makefile: Rule to compile necessary video driver files. - Add Reviewed-by tag in apprpriate patch Changes in V4 - Add Reviewed-by tag in apprpriate patch Changes in V3 - Add separate video configs for SPL splash screen - Add rule to compile video driver in drivers/Makefile at SPL - Add rule to compile splash.c and splash_source.c - Squash drivers: video: video-uclass: Disable u-boot logo at SPL into drivers: video: Use CONFIG_IS_ENABLED and CONFIG_VAL - Split cmd/bmp.c to separate bmp functions and commands. - Add CONFIG_BMP and CONFIG_SPL_BMP. - Add rule to compile necessary files required for video driver. - Add rule to compile common/bmp.c Changes in V2 - Removed artifacts from bad patch apply. Nikhil M Jain (13): drivers: video: Kconfig: Add configs for enabling video at SPL drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL drivers: Makefile: Add rule to compile video driver drivers: video: Makefile: Rule to compile necessary video driver files drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL common: Makefile: Add rule to compile splash and splash_source at SPL common: Kconfig: Add BMP configs cmd: bmp: Split bmp commands and functions common: Makefile: Rule to compile bmp.c drivers: video: Enable necessary video functions at SPL common: Enable splash functions at SPL include: Enable video related global data variable and splash at SPL board: ti: am62x: evm: OSPI support for splash screen board/ti/am62x/evm.c | 11 +- cmd/bmp.c | 161 +- common/Kconfig| 12 ++ common/Makefile | 3 + common/bmp.c | 153 + common/splash.c | 10 +- drivers/Makefile | 1 + drivers/video/Kconfig | 221 ++ drivers/video/Makefile| 14 +- drivers/video/console_core.c | 6 +- drivers/video/tidss/Kconfig | 6 + drivers/video/tidss/Makefile | 2 +- drivers/video/vidconsole-uclass.c | 2 +- drivers/video/video-uclass.c | 14 +- drivers/video/video_bmp.c | 8 +- include/asm-generic/global_data.h | 4 +- include/splash.h | 6 +- include/video.h | 7 + 18 files changed, 447 insertions(+), 194 deletions(-) create mode 100644 common/bmp.c -- 2.34.1
[PATCH V5 02/13] drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL
To enable tidss video driver only at SPL stage, add necessary config, CONFIG_SPL_VIDEO_TIDSS. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass --- V5: - No change V4: - Add Reviewed-By tag V3: - No change V2: - No change drivers/video/tidss/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 2a5e56ea4e..748c332281 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -16,3 +16,9 @@ menuconfig VIDEO_TIDSS DPI . This option enables these supports which can be used on devices which have OLDI or HDMI display connected. +config SPL_VIDEO_TIDSS + bool "Enable TIDSS video support in SPL Stage" + depends on SPL_VIDEO + help + This options enables tidss driver in SPL stage. If + you need to use tidssat SPL stage use this config. -- 2.34.1
[PATCH V5 03/13] drivers: Makefile: Add rule to compile video driver
CONFIG_$(SPL_)VIDEO checks for CONFIG_SPL_VIDEO at SPL and CONFIG_VIDEO at u-boot proper and compiles video driver at respective stage. Signed-off-by: Nikhil M Jain --- V5: - Add rule to build video at SPL using CONFIG_SPL_VIDEO and retain obj-y +=video for u-boot proper. V4: - No change V3 (patch introduced): - Add rule to compile video driver at SPL. drivers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/Makefile b/drivers/Makefile index 58be410135..928a8b0e9d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_VIDEO) +=video/ endif endif -- 2.34.1
[PATCH V5 07/13] common: Kconfig: Add BMP configs
Add CONFIG_BMP and CONFIG_SPL_BMP which enable displaying bmp images at u-boot proper and SPL. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass --- V5: - Added Reviewed-by tag. V4: - No change. V3 (patch introduced): - Add CONFIG BMP and SPL_BMP. common/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/common/Kconfig b/common/Kconfig index 7ff62552cb..7329dc8253 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1154,3 +1154,15 @@ config FDT_SIMPLEFB config IO_TRACE bool + +config BMP + bool "Enable bmp image display" + default y if CMD_BMP + help + Enable bmp functions to display bmp image and get bmp info. + +config SPL_BMP + bool "Enable bmp image display at SPL" + depends on SPL_VIDEO + help + Enable bmp functions to display bmp image and get bmp info at SPL. -- 2.34.1
[PATCH V5 04/13] drivers: video: Makefile: Rule to compile necessary video driver files
To enable video driver at SPL, need to compile video-uclass, vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add rules to compile them at SPL only. To support splash_display at SPL, need to compile video-bmp, add rule to compile at SPL stage. Signed-off-by: Nikhil M Jain --- V5: - Use $(SPL_TPL_) to check for stage specific configs and compile at specific stages. - Removed ifdef CONFIG_SPL_BUILD V4: - No change V3: - Rule to compile backlight, console and panel files - Not added Reiewed-by tag due to changes V2: - No change drivers/video/Makefile | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index cb3f373645..bb139f550c 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -4,12 +4,12 @@ # Wolfgang Denk, DENX Software Engineering, w...@denx.de. ifdef CONFIG_DM -obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o +obj-$(CONFIG_$(SPL_TPL_)BACKLIGHT) += backlight-uclass.o obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o -obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o +obj-$(CONFIG_$(SPL_TPL)CONSOLE_NORMAL) += console_normal.o obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o -ifdef CONFIG_CONSOLE_NORMAL +ifdef CONFIG_$(SPL_TPL_)CONSOLE_NORMAL obj-y += console_core.o else ifdef CONFIG_CONSOLE_ROTATION obj-y += console_core.o @@ -18,9 +18,9 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o -obj-$(CONFIG_VIDEO) += video-uclass.o vidconsole-uclass.o -obj-$(CONFIG_VIDEO) += video_bmp.o -obj-$(CONFIG_PANEL) += panel-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video-uclass.o vidconsole-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video_bmp.o +obj-$(CONFIG_$(SPL_TPL_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o -- 2.34.1
[PATCH V5 06/13] common: Makefile: Add rule to compile splash and splash_source at SPL
To enable splash screen and loading bmp from boot media, add rules to compile splash.c and splash_source.c at SPL stage only when CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_SPLASH_SOURCE are defined. Signed-off-by: Nikhil M Jain --- V5: - No change V4: - No change V3 (patch introduced): - Rule to compile splash.c and splash_source.c. common/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/Makefile b/common/Makefile index a50302d8b5..3a6ca337e0 100644 --- a/common/Makefile +++ b/common/Makefile @@ -56,6 +56,8 @@ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o obj-$(CONFIG_SPL_MUSB_NEW) += usb.o +obj-$(CONFIG_SPL_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SPL_SPLASH_SOURCE) += splash_source.o endif # CONFIG_SPL_BUILD #others -- 2.34.1
[PATCH V5 05/13] drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS
video driver.
CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if
CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if
CONFIG_VIDEO_TIDSS is defined.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
---
V5:
- Use CONFIG_$(SPL_)VIDEO_TIDSS to build TIDSS driver at SPL and u-boot
proper.
V4:
- Added Reviewed-by tag.
V3:
- No change.
V2:
- No change.
drivers/video/Makefile | 2 +-
drivers/video/tidss/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index bb139f550c..096a087c81 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -32,7 +32,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-${CONFIG_VIDEO_TIDSS} += tidss/
+obj-${CONFIG_$(SPL_)VIDEO_TIDSS} += tidss/
obj-y += ti/
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile
index f4f8c6c470..a29cee2a41 100644
--- a/drivers/video/tidss/Makefile
+++ b/drivers/video/tidss/Makefile
@@ -9,4 +9,4 @@
# Author: Tomi Valkeinen
-obj-${CONFIG_VIDEO_TIDSS} = tidss_drv.o
+obj-${CONFIG_$(SPL_)VIDEO_TIDSS} = tidss_drv.o
--
2.34.1
[PATCH V5 09/13] common: Makefile: Rule to compile bmp.c
Add rule to compile bmp.c at SPL and u-boot proper when CONFIG_SPL_BMP and CONFIG_BMP are defined. Signed-off-by: Nikhil M Jain --- V5: - Remove obj-y+= read.o. V4: - No change. V3 (patch introduced): - Rule to compile common/bmp. common/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/common/Makefile b/common/Makefile index 3a6ca337e0..c87bb2e78b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -45,6 +45,7 @@ endif # !CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o +obj-$(CONFIG_$(SPL_)BMP) += bmp.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_DFU -- 2.34.1
[PATCH V5 01/13] drivers: video: Kconfig: Add configs for enabling video at SPL
Add Kconfigs which enable the video driver and splash screen at SPL stage only and not at u-boot proper. The existing Kconfigs from u-boot proper were not used to make SPL splash screen independent to them. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar --- V5: - Added Reviewed-by tag. V4: - No change. V3: - Add separate SPL video and splash configs. - Reviewed-by tag not added due to additional changes in V3. V2: - No change. drivers/video/Kconfig | 221 ++ 1 file changed, 221 insertions(+) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 60f4a4bf9c..3d44853e86 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -930,4 +930,225 @@ config BMP_32BPP endif # VIDEO +config SPL_VIDEO + bool "Enable driver model support for LCD/video" + depends on SPL_DM + help + The video subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use video drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up video within SPL, and allows the same drivers to be + used as U-Boot proper. + +if SPL_VIDEO +source "drivers/video/tidss/Kconfig" + +config SPL_VIDEO_LOGO + bool "Show the U-Boot logo on the display atSPL" + default y if !SPL_SPLASH_SCREEN + select VIDEO_BMP_RLE8 + help + This enables showing the U-Boot logo on the display when a video + device is probed. It appears at the top right. The logo itself is at + tools/logos/u-boot_logo.bmp and looks best when the display has a + black background. + +config SPL_SPLASH_SCREEN + bool "Show a splash-screen image at SPL" + help + If this option is set, the environment is checked for a variable + "splashimage" at spl stage. + +config SPL_SYS_WHITE_ON_BLACK + bool "Display console as white on a black background at SPL" + help +Normally the display is black on a white background, Enable this +option to invert this, i.e. white on a black background at spl stage. +This can be better in low-light situations or to reduce eye strain in +some cases. + +config SPL_VIDEO_PCI_DEFAULT_FB_SIZE + hex "Default framebuffer size to use if no drivers request it at SPL" + default 0x100 if X86 && PCI + default 0 if !(X86 && PCI) + help + Generally, video drivers request the amount of memory they need for + the frame buffer when they are bound, by setting the size field in + struct video_uc_plat. That memory is then reserved for use after + relocation. But PCI drivers cannot be bound before relocation unless + they are mentioned in the devicetree. + + With this value set appropriately, it is possible for PCI video + devices to have a framebuffer allocated by U-Boot. + + Note: the framebuffer needs to be large enough to store all pixels at + maximum resolution. For example, at 1920 x 1200 with 32 bits per + pixel, 2560 * 1600 * 32 / 8 = 0xfa bytes are needed. + +config SPL_CONSOLE_SCROLL_LINES + int "Number of lines to scroll the console by at SPL" + default 1 + help + When the console need to be scrolled, this is the number of + lines to scroll by. It defaults to 1. Increasing this makes the + console jump but can help speed up operation when scrolling + is slow. + +config SPL_CONSOLE_NORMAL + bool "Support a simple text console at SPL" + default y + help + Support drawing text on the frame buffer console so that it can be + used as a console. Rotation is not supported by this driver (see + CONFIG_CONSOLE_ROTATION for that). A built-in 8x16 font is used + for the display. + +config SPL_BACKLIGHT + bool "Enable panel backlight uclass support at SPL" + default y + help + This provides backlight uclass driver that enables basic panel + backlight support. + +config SPL_PANEL + bool "Enable panel uclass support at SPL" + default y + help + This provides panel uclass driver that enables basic panel support. + +config SPL_SIMPLE_PANEL + bool "Enable simple panel support at SPL" + depends on SPL_PANEL && SPL_BACKLIGHT && SPL_DM_GPIO + default y + help + This turns on a simple panel driver that enables a compatible + video panel. + +config SPL_SYS_WHITE_ON_BLACK + bool "Display console as white on a black background at SPL" + help +Normally the display is black on a white background, Enable this +option to invert this, i.e. white on a black background at spl stage. +This can be better in low-light situations or to reduce eye strain in +some cases. + +if SPL_SPLASH_SCREEN + +config SPL_SPLASH_SCREEN_ALIGN +
[PATCH V5 11/13] common: Enable splash functions at SPL
To support splash screen at SPL use CONFIG_IS_ENABLED and CONFIG_VAL. To
check for stage specific configs at u-boot proper and SPL.
Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
at u-boot proper and SPL.
Signed-off-by: Nikhil M Jain
---
V5:
- Replace CONFIG_CMD_BMP with CONFIG_BMP.
V4:
- No change
V3 (patch introduced):
- Enable splash functions at SPL
common/bmp.c| 10 +-
common/splash.c | 10 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/common/bmp.c b/common/bmp.c
index 540d06e63f..51766b3c21 100644
--- a/common/bmp.c
+++ b/common/bmp.c
@@ -33,7 +33,7 @@
* Returns NULL if decompression failed, or if the decompressed data
* didn't contain a valid BMP signature.
*/
-#ifdef CONFIG_VIDEO_BMP_GZIP
+#if CONFIG_IS_ENABLED(VIDEO_BMP_GZIP)
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
{
@@ -44,9 +44,9 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
/*
* Decompress bmp image
*/
- len = CONFIG_VIDEO_LOGO_MAX_SIZE;
+ len = CONFIG_VAL(VIDEO_LOGO_MAX_SIZE);
/* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
- dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
+ dst = malloc(CONFIG_VAL(VIDEO_LOGO_MAX_SIZE) + 3);
if (!dst) {
puts("Error: malloc in gunzip failed!\n");
return NULL;
@@ -55,12 +55,12 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
/* align to 32-bit-aligned-address + 2 */
bmp = dst + 2;
- if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
+ if (gunzip(bmp, CONFIG_VAL(VIDEO_LOGO_MAX_SIZE), map_sysmem(addr, 0),
&len)) {
free(dst);
return NULL;
}
- if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
+ if (len == CONFIG_VAL(VIDEO_LOGO_MAX_SIZE))
puts("Image could be truncated (increase
CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
/*
diff --git a/common/splash.c b/common/splash.c
index 4bc54b1bf9..a4e68b7042 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -89,14 +89,14 @@ static inline int splash_video_logo_load(void) { return
-ENOSYS; }
__weak int splash_screen_prepare(void)
{
- if (IS_ENABLED(CONFIG_SPLASH_SOURCE))
+ if (CONFIG_IS_ENABLED(SPLASH_SOURCE))
return splash_source_load(default_splash_locations,
ARRAY_SIZE(default_splash_locations));
return splash_video_logo_load();
}
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y)
{
char *s = env_get("splashpos");
@@ -119,7 +119,7 @@ void splash_get_pos(int *x, int *y)
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
+#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
#ifdef CONFIG_VIDEO_LOGO
#include
@@ -159,7 +159,7 @@ void splash_display_banner(void)
* Common function to show a splash image if env("splashimage") is set.
* For additional details please refer to doc/README.splashprepare.
*/
-#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
int splash_display(void)
{
ulong addr;
@@ -183,7 +183,7 @@ int splash_display(void)
if (x || y)
goto end;
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
+#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
splash_display_banner();
#endif
end:
--
2.34.1
[PATCH V5 08/13] cmd: bmp: Split bmp commands and functions
To enable splash screen at spl, need to compile cmd/bmp.c which also
includes bmp commands, since SPL can't have commands split bmp.c into
common/bmp.c which includes all bmp functions and cmd/bmp.c contains
bmp commands.
Add delclaration for bmp_info in video.h.
Signed-off-by: Nikhil M Jain
---
V5:
- Rename cmd/bmp_cmd to cmd/bmp.
V4:
- No change.
V3 (patch introduced):
- Split bmp functions and commands.
cmd/bmp.c | 161 +---
common/bmp.c| 153 +
include/video.h | 7 +++
3 files changed, 162 insertions(+), 159 deletions(-)
create mode 100644 common/bmp.c
diff --git a/cmd/bmp.c b/cmd/bmp.c
index 46d0d916e8..735790fda7 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -11,82 +11,11 @@
#include
#include
#include
-#include
-#include
#include
-#include
-#include
#include
#include
#include
-#include
-
-static int bmp_info (ulong addr);
-
-/*
- * Allocate and decompress a BMP image using gunzip().
- *
- * Returns a pointer to the decompressed image data. This pointer is
- * aligned to 32-bit-aligned-address + 2.
- * See doc/README.displaying-bmps for explanation.
- *
- * The allocation address is passed to 'alloc_addr' and must be freed
- * by the caller after use.
- *
- * Returns NULL if decompression failed, or if the decompressed data
- * didn't contain a valid BMP signature.
- */
-#ifdef CONFIG_VIDEO_BMP_GZIP
-struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
-void **alloc_addr)
-{
- void *dst;
- unsigned long len;
- struct bmp_image *bmp;
-
- /*
-* Decompress bmp image
-*/
- len = CONFIG_VIDEO_LOGO_MAX_SIZE;
- /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
- dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
- if (!dst) {
- puts("Error: malloc in gunzip failed!\n");
- return NULL;
- }
-
- /* align to 32-bit-aligned-address + 2 */
- bmp = dst + 2;
-
- if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
- &len)) {
- free(dst);
- return NULL;
- }
- if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
- puts("Image could be truncated (increase
CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
-
- /*
-* Check for bmp mark 'BM'
-*/
- if (!((bmp->header.signature[0] == 'B') &&
- (bmp->header.signature[1] == 'M'))) {
- free(dst);
- return NULL;
- }
-
- debug("Gzipped BMP image detected!\n");
-
- *alloc_addr = dst;
- return bmp;
-}
-#else
-struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
-void **alloc_addr)
-{
- return NULL;
-}
-#endif
+#include
static int do_bmp_info(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -137,7 +66,7 @@ static int do_bmp_display(struct cmd_tbl *cmdtp, int flag,
int argc,
return CMD_RET_USAGE;
}
-return (bmp_display(addr, x, y));
+ return (bmp_display(addr, x, y));
}
static struct cmd_tbl cmd_bmp_sub[] = {
@@ -145,22 +74,6 @@ static struct cmd_tbl cmd_bmp_sub[] = {
U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void bmp_reloc(void) {
- fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
-}
-#endif
-
-/*
- * Subroutine: do_bmp
- *
- * Description: Handler for 'bmp' command..
- *
- * Inputs: argv[1] contains the subcommand
- *
- * Return: None
- *
- */
static int do_bmp(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
struct cmd_tbl *c;
@@ -183,73 +96,3 @@ U_BOOT_CMD(
"info - display image info\n"
"bmp display [x y] - display image at x,y"
);
-
-/*
- * Subroutine: bmp_info
- *
- * Description: Show information about bmp file in memory
- *
- * Inputs: addraddress of the bmp file
- *
- * Return: None
- *
- */
-static int bmp_info(ulong addr)
-{
- struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0);
- void *bmp_alloc_addr = NULL;
- unsigned long len;
-
- if (!((bmp->header.signature[0]=='B') &&
- (bmp->header.signature[1]=='M')))
- bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr);
-
- if (bmp == NULL) {
- printf("There is no valid bmp file at the given address\n");
- return 1;
- }
-
- printf("Image size: %d x %d\n", le32_to_cpu(bmp->header.width),
- le32_to_cpu(bmp->header.height));
- printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
- printf("Compression : %d\n", le32_to_cpu(bmp->header.compression));
-
- if (bmp_alloc_addr)
- free(bmp_alloc_addr);
-
- return(0);
-}
-
-int bmp_displ
[PATCH V5 12/13] include: Enable video related global data variable and splash at SPL
To include video related global data variables and splash functions at
SPL, use CONFIG_IS_ENABLED.
Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
at u-boot proper and SPL.
Signed-off-by: Nikhil M Jain
---
V5:
- Replace CONFIG_CMD_BMP with CONFIG_BMP.
V4:
- No change.
V3 (patch introduced):
- Include video related global data variables.
- Include splash display functions.
include/asm-generic/global_data.h | 4 ++--
include/splash.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 987fb66c17..65bf8df1e5 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -68,7 +68,7 @@ struct global_data {
* @mem_clk: memory clock rate in Hz
*/
unsigned long mem_clk;
-#if defined(CONFIG_VIDEO)
+#if CONFIG_IS_ENABLED(VIDEO)
/**
* @fb_base: base address of frame buffer memory
*/
@@ -359,7 +359,7 @@ struct global_data {
*/
struct membuff console_in;
#endif
-#ifdef CONFIG_VIDEO
+#if CONFIG_IS_ENABLED(VIDEO)
/**
* @video_top: top of video frame buffer area
*/
diff --git a/include/splash.h b/include/splash.h
index 33e45e6941..b6a100ffc3 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -49,7 +49,7 @@ struct splash_location {
char *ubivol; /* UBI volume-name for ubifsmount */
};
-#ifdef CONFIG_SPLASH_SOURCE
+#if CONFIG_IS_ENABLED(SPLASH_SOURCE)
int splash_source_load(struct splash_location *locations, uint size);
#else
static inline int splash_source_load(struct splash_location *locations,
@@ -61,13 +61,13 @@ static inline int splash_source_load(struct splash_location
*locations,
int splash_screen_prepare(void);
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y);
#else
static inline void splash_get_pos(int *x, int *y) { }
#endif
-#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
int splash_display(void);
#else
static inline int splash_display(void)
--
2.34.1
[PATCH V5 13/13] board: ti: am62x: evm: OSPI support for splash screen
Add ospi boot media support to load splash image from OSPI memory,
add offset to read image from ospi and necessary flags defininig type
of storage and storage device.
Use CONFIG_IS_ENBALED to use the splash locations at SPL and u-boot
proper.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
Reviewed-by: Devarsh Thakkar
---
V5:
- Replace #ifdef with #if
- Add Reviewed-by tag
V4:
- Added Reviewed-by tag
V3:
- Enable splash location at SPL
V2:
- no change
board/ti/am62x/evm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 584b4ec552..f2deb90712 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -20,8 +20,15 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPLASH_SCREEN
-static struct splash_location default_splash_locations[] = {
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN)
+static struct splash_location default_splash_locations[] =
+{
+ {
+ .name = "sf",
+ .storage = SPLASH_STORAGE_SF,
+ .flags = SPLASH_STORAGE_RAW,
+ .offset = 0x70,
+ },
{
.name = "mmc",
.storage= SPLASH_STORAGE_MMC,
--
2.34.1
[PATCH V5 10/13] drivers: video: Enable necessary video functions at SPL
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL,
which checks for stage specific configs and thus enables video support
at respective stage.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
---
V5:
- Add Reviewed-By tag.
- Use COFIG_IS_ENABLED in console_core in place of console_normal.
V4:
- No change.
V3 (patch introduced):
- Enable necessary video functions at SPL.
drivers/video/console_core.c | 6 +++---
drivers/video/vidconsole-uclass.c | 2 +-
drivers/video/video-uclass.c | 14 +++---
drivers/video/video_bmp.c | 8
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index d4f79c656a..1f93b1b85f 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -46,11 +46,11 @@ static int console_set_font(struct udevice *dev, struct
video_fontdata *fontdata
int check_bpix_support(int bpix)
{
- if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8))
+ if (bpix == VIDEO_BPP8 && CONFIG_IS_ENABLED(VIDEO_BPP8))
return 0;
- else if (bpix == VIDEO_BPP16 && IS_ENABLED(CONFIG_VIDEO_BPP16))
+ else if (bpix == VIDEO_BPP16 && CONFIG_IS_ENABLED(VIDEO_BPP16))
return 0;
- else if (bpix == VIDEO_BPP32 && IS_ENABLED(CONFIG_VIDEO_BPP32))
+ else if (bpix == VIDEO_BPP32 && CONFIG_IS_ENABLED(VIDEO_BPP32))
return 0;
else
return -ENOSYS;
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index 1225de2333..a21fde0e1d 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -86,7 +86,7 @@ static void vidconsole_newline(struct udevice *dev)
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
struct udevice *vid_dev = dev->parent;
struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev);
- const int rows = CONFIG_CONSOLE_SCROLL_LINES;
+ const int rows = CONFIG_VAL(CONSOLE_SCROLL_LINES);
int i, ret;
priv->xcur_frac = priv->xstart_frac;
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index da89f43144..8396bdfb11 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -132,7 +132,7 @@ int video_reserve(ulong *addrp)
/* Allocate space for PCI video devices in case there were not bound */
if (*addrp == gd->video_top)
- *addrp -= CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE;
+ *addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE);
gd->video_bottom = *addrp;
gd->fb_base = *addrp;
@@ -149,7 +149,7 @@ int video_fill(struct udevice *dev, u32 colour)
switch (priv->bpix) {
case VIDEO_BPP16:
- if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP16)) {
u16 *ppix = priv->fb;
u16 *end = priv->fb + priv->fb_size;
@@ -158,7 +158,7 @@ int video_fill(struct udevice *dev, u32 colour)
break;
}
case VIDEO_BPP32:
- if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
u32 *ppix = priv->fb;
u32 *end = priv->fb + priv->fb_size;
@@ -212,14 +212,14 @@ u32 video_index_to_colour(struct video_priv *priv,
unsigned int idx)
{
switch (priv->bpix) {
case VIDEO_BPP16:
- if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP16)) {
return ((colours[idx].r >> 3) << 11) |
((colours[idx].g >> 2) << 5) |
((colours[idx].b >> 3) << 0);
}
break;
case VIDEO_BPP32:
- if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
if (priv->format == VIDEO_X2R10G10B10)
return (colours[idx].r << 22) |
(colours[idx].g << 12) |
@@ -513,8 +513,8 @@ static int video_post_probe(struct udevice *dev)
return ret;
}
- if (IS_ENABLED(CONFIG_VIDEO_LOGO) &&
- !IS_ENABLED(CONFIG_SPLASH_SCREEN) && !plat->hide_logo) {
+ if (CONFIG_IS_ENABLED(VIDEO_LOGO) &&
+ !CONFIG_IS_ENABLED(SPLASH_SCREEN) && !plat->hide_logo) {
ret = show_splash(dev);
if (ret) {
log_debug("Cannot show splash screen\n");
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 6188a13e44..47e52c4f69 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -320,7 +320,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image,
int x, int y,
switch (bmp_bpix) {
case 1:
case 8:
-
Re: WIP: Signing TI x509 certificates using binman
Hi Simon On 03/04/23 00:16, Simon Glass wrote: Hi Neha, On Mon, 3 Apr 2023 at 02:19, Neha Malcom Francis wrote: Hi Simon On 02/04/23 18:00, Neha Malcom Francis wrote: Hi Simon On 01/04/23 12:02, Simon Glass wrote: Hi Neha, On Sat, 1 Apr 2023 at 00:14, Neha Malcom Francis wrote: Hi Simon On 31/03/23 02:01, Simon Glass wrote: Hi Neha, On Fri, 24 Mar 2023 at 22:28, Neha Malcom Francis wrote: Hi Simon, Before I roll out the entire series that works for packaging K3 bootloader images, wanted to get some reviews and comments regarding the implementation of the signing etype [1] . I believe I've taken into consideration what we've discussed earlier [2]. Let me know your thoughts. The tree is also WIP, and was mainly designed for testing the signing etype on two of the devices. I will add the remaining and refine the series based on the next comments. Yes this looks reasonable to me. For the openssl method, can you create a new 'real' method and put the cert stuff in there instead of using a 'custom' one? It seems to have a lot in common with what is there. We should really have an internal cert-generator method in that class, with other functions in that class doing appropriate things. I am looking for code reuse here, as well as clear indication of what the cert is for or does. So you're suggesting to include the config creation within the openssl btool, am I right? For example methods to generate a config, add section to a config, add extension to a section of a config... etc? I can take a look at implementing this if this is what you have suggested. I am more thinking that your use case could be a new method in that file, with arguments that suit your case, but with common code to create a cert of the correct type. That means pulling out the existing cert creation into a new (internal) function in that btool that does both types of cert. For the CN args I think a dict would be suitable to pass in the settings. I'm trying to avoid people passing in a cert every time, since that is going to create a lot of code duplication and it will be hard to take advantage of common algos. Okay I think I get it, let me respin with this in mind. I am still a little doubtful about putting in *this* cert generation in the openssl btool. These sections and extensions are TI specific and I don't think there would be code duplication in future. The least code duplication along with functionality would be acheived by allowing creating configs, sections, extensions etc. in openssl btool or x509 etype. and then creating the final cert binary in openssl. What do you think? It is tricky because we only have one example in the etype at present so it is always hard to know which way to go. I think it will be clearer down the track when we have a bit more code here. But if we go with having the bintool just be a shell, then we definitely won't get any reuse for the next customer. The bit I would like to see in the bintool is the creation of the text file containing the cert. The etype should ideally provide properties (which can be set up the ti_secure etype in the __init__() method) that cover the required openssl params. The simplest thing would be just 'this is TI signing' but I would like to pick this apart a bit so that the properties are more generic, if possible. So the btool takes arguments that tell it about the text file to create. It creates the text file and runs openssl. The x509 etype calls the openssl bintool's z509 method to actually create the cert, presumably passing quite a few args and maybe a dict. So: - expand openssl.x509_cert() with more args - expand x509 etype with more properties (using the defaults) - update your ti-secure etype to set those properties in certain ways Since the bintool code that is there is just an example cert, you can switch it to do whatever you want for this case, i.e. change the defaults. That might simplify things for you. Anyway, for an initial series I think that will provide a good basis for this work. If we need to refactor later, we have our test coverage to help us. Regards, Simon Thanks for explaining! I will work on it this way. If most of the cert is the same, you could pass a dict for the CN stuff, perhaps? What is the taml for? It is hard to tell, from the example provided. Did you mean YAML? If so in the patch I linked, I don't think I had a example for that. Could you point out what exactly you're asking about? Well I am wondering why it is in the code...is there a yaml file that you need to ingest and process? What is it for? ...actually I see the yaml files in your tree mentioned below. Does this come out of some other tool? Right, so currently we have certain board specific configurations in YAML. This is input to our board configuration binary entry type [6], which converts YAML into binary blobs prepended with certain headers needed. Do you have a .dts which shows the full image for a board? I think the
Re: rk3399 issue: no DMA in Linux with mainline TF-A and U-Boot SPL
Hi Christoph, The ARM PL330 DMA driver in kernel only relate to: - DTS kernel used, can be check in /proc/device-tree/ - kernel driver which should mach the compatible name. This driver should has nothing to do with U-Boot SPL or TF-A, because we don't have any special setting for PL330 in loader stage. Thanks, - Kever On 2023/4/3 03:01, Christoph Fritz wrote: Hello Kever, on a rk3399, booting current U-Boot SPL with mainline TF-A leads to missing DMA (and no sound) on Linux. However, when using rockchip its so called mini-loader (rk3399_miniloader_v1.26.bin) and their BL31 (rk3399_bl31_v1.35.elf) to boot, DMA works perfectly fine. Tested on a custom rk3399 board and on ROCK Pi4. Attached to this mail are two boot logs with some debug prints: - good_amba_log.txt (DMA works) - no_amba_log.txt (no DMA device) The main difference I can spot between the two logs is that on Linux (drivers/amba/bus.c) AMBA_CID (0xb105f00d) cannot be found. Instead, only some CORESIGHT_CIDs (presumably for debugging) and four 0x CIDs are detected. As a result, the "PL330 DMAC-241330" driver does not load. My theory is that DMA needs to be allowed somewhere in the undocumented syscon- registers, similar to what U-Boot is already doing for eMMC in arch_cpu_init() (arch/arm/mach-rockchip/rk3399/rk3399.c). Any ideas? Or maybe I'm just missing some configuration? Since multiple software projects are involved (TF-A, OP-TEE, U-Boot, Linux), I Cc'ed a bit. Thanks -- Christoph
Re: [PATCH] watchdog: arm_smc_wdt: add watchdog support
Hi,
On 3/31/23 09:59, Stefan Roese wrote:
Hi Lionel,
On 3/31/23 09:14, Lionel Debieve wrote:
Implement a ARM SMCCC based driver that allow to use
a secure watchdog on the platform.
Signed-off-by: Lionel Debieve
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/arm_smc_wdt.c | 116 +
3 files changed, 125 insertions(+)
create mode 100644 drivers/watchdog/arm_smc_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b5ac8f7f50d..3a0341f609d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -352,6 +352,14 @@ config WDT_TANGIER
Intel Tangier SoC. If you're using a board with Intel Tangier
SoC, say Y here.
+config WDT_ARM_SMC
+ bool "ARM SMC watchdog timer support"
+ depends on WDT && ARM_SMCCC
+ imply WATCHDOG
+ help
+ Select this to enable Arm SMC watchdog timer. This watchdog
will manage
+ a watchdog based on ARM SMCCC communication.
+
config SPL_WDT
bool "Enable driver model for watchdog timer drivers in SPL"
depends on SPL_DM
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 446d961d7d2..a4633c0d2fa 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ALARM_SANDBOX) += sandbox_alarm-wdt.o
obj-$(CONFIG_WDT_APPLE) += apple_wdt.o
+obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
diff --git a/drivers/watchdog/arm_smc_wdt.c
b/drivers/watchdog/arm_smc_wdt.c
new file mode 100644
index 000..e2e3c455082
--- /dev/null
+++ b/drivers/watchdog/arm_smc_wdt.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
Please replace with correct SPDX identifier for new file => GPL-2.0-or-later
GPL-2.0+ identifier is deprecated as indicated in https://spdx.org/licenses/
+/*
+ * ARM Secure Monitor Call watchdog driver
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * This file is based on Linux driver drivers/watchdog/arm_smc_wdt.c
?
+ */
+
please add the LOG define for this new driver:
#define LOG_CATEGORY UCLASS_WDT
+#include
+#include
dm/device_compat.h is needed ?
no call for dev debug function (printk / dev_err() /...)
+#include
of_access.h is really needed ?
no of_XXX() function call...
+#include
+#include
+#include
+
+#define DRV_NAME "arm_smc_wdt"
+#define DRV_VERSION "1.0"
NITS: DRV_VERSION is not used,
its is only for alignment with kernel driver ?
+
+#define WDT_TIMEOUT_SECS(TIMEOUT) ((TIMEOUT) / 1000)
+
+enum smcwd_call {
+ SMCWD_INIT = 0,
+ SMCWD_SET_TIMEOUT = 1,
+ SMCWD_ENABLE = 2,
+ SMCWD_PET = 3,
+ SMCWD_GET_TIMELEFT = 4,
+};
+
+struct smcwd_priv_data {
+ u32 smc_id;
+ unsigned int min_timeout;
+ unsigned int max_timeout;
+};
+
+static int smcwd_call(struct udevice *dev, enum smcwd_call call,
+ unsigned long arg, struct arm_smccc_res *res)
+{
+ struct arm_smccc_res local_res;
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
+
+ if (!res)
+ res = &local_res;
+
+ arm_smccc_smc(priv->smc_id, call, arg, 0, 0, 0, 0, 0, res);
+
+ if (res->a0 == PSCI_RET_NOT_SUPPORTED)
+ return -ENODEV;
+ if (res->a0 == PSCI_RET_INVALID_PARAMS)
+ return -EINVAL;
+ if (res->a0 != PSCI_RET_SUCCESS)
+ return -EIO;
+
+ return 0;
+}
+
+static int smcwd_reset(struct udevice *dev)
+{
+ return smcwd_call(dev, SMCWD_PET, 0, NULL);
+}
+
+static int smcwd_stop(struct udevice *dev)
+{
+ return smcwd_call(dev, SMCWD_ENABLE, 0, NULL);
+}
+
+static int smcwd_start(struct udevice *dev, u64 timeout_ms, ulong
flags)
+{
+ int err;
+ u64 timeout_sec = WDT_TIMEOUT_SECS(timeout_ms);
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
Nitpicking: It's generally more common to use the reverse xmas tree
style for variable declaration ordering. On other places in this code
as well.
+
+ if (timeout_sec < priv->min_timeout || timeout_sec >
priv->max_timeout)
+ return -EINVAL;
An error message would be good here. Or at least some debug level
message.
+
+ err = smcwd_call(dev, SMCWD_SET_TIMEOUT, timeout_sec, NULL);
+ if (err)
+ return err;
Again, please enhance the driver with some error or at least debug
level logging.
Thanks,
Stefan
+
+ return smcwd_call(dev, SMCWD_ENABLE, 1, NULL);
+}
+
+static int smcwd_probe(struct udevice *dev)
+{
+ int err;
+ struct arm_smccc_res res;
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
+
+ priv->smc_id = dev_read_u32_default(dev, "arm,smc-id", 0x82003D06);
+
+ err = smcwd_call(dev, SMCWD_INIT, 0, &res);
+ if (err < 0)
+ return err
Re: [PATCH] common: cli_hush: Restore clear local variable support
Hi Simon,
Am 01.04.2023 um 08:31 schrieb Simon Glass:
Hi Stefan,
On Sat, 1 Apr 2023 at 03:43, Stefan Herbrechtsmeier
wrote:
From: Stefan Herbrechtsmeier
The u-boot hush shell doesn’t support the unset command to clear a
variable and therefore an empty value ("c=") should be a valid value
for the set_local_var function to clear the variable. This partial
reverts commit aa722529635c ("common: cli_hush: avoid dead code") and
only checks for a `=` in the string. Additionally explicit call the
unset_local_var function to remove the variable if the value is empty.
Signed-off-by: Stefan Herbrechtsmeier
---
common/cli_hush.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 1ad7a509df..c3f7dd12a0 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -2171,12 +2171,18 @@ int set_local_var(const char *s, int flg_export)
* NAME=VALUE format. So the first order of business is to
* split 's' on the '=' into 'name' and 'value' */
value = strchr(name, '=');
- if (value == NULL || *(value + 1) == 0) {
+ if (value == NULL) {
if (!value)
I reuse the existing style of the file. Should I always use the kernel /
u-boot style for changes?
free(name);
return -1;
}
*value++ = 0;
+ if (*value == 0) {
if (!*value)
+ unset_local_var(name);
+ free(name);
+ return 0;
+ }
+
for(cur = top_vars; cur; cur = cur->next) {
if(strcmp(cur->name, name)==0)
break;
--
2.30.2
I think this should have a test, e.g. in
test/py/tests/test_hush_if_test.py or perhaps a C test?
I will extend the python test.
Regards
Stefan
Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
Geschäftsführer: Dr. Timo Berger, Volker Bibelhausen, Dr. Sebastian Durst,
André Sombecki;
USt-ID-Nr. DE124599660
Re: [PATCH v5 3/8] bootstd: Support booting EFI where multiple options exist
On Sat, Apr 01, 2023 at 07:31:49PM +1300, Simon Glass wrote: > Hi Tom, > > On Sat, 1 Apr 2023 at 07:02, Tom Rini wrote: > > > > On Fri, Mar 31, 2023 at 10:25:56AM +1300, Simon Glass wrote: > > > > > The current EFI implementation has a strange quirk where it watches > > > loaded files and uses the last-loaded file to determine the device that > > > is being booted from. > > > > > > This is confusing with bootstd, where multiple options may exist. Even > > > loading a device tree will cause it to go wrong. There is no API for > > > passing this information, since the only entry into booting an EFI image > > > is the 'bootefi' command. > > > > > > To work around this, call efi_set_bootdev() for EFI images, if possible, > > > just before booting. > > > > > > Signed-off-by: Simon Glass > > > > Shouldn't this all be a simple wrapper around the EFI Standard > > BootDeviceOrder or whatever that's called? > > I think you are referring to boot manager, which isn't used here. This > is replicating the existing distroboot functionality in standard boot. The distroboot functionality *was* trying to behave like the EFI spec expects the bootmanager to behave. Unfortunately I haven't had time to review the distroboot patches closely, but back when this started, my point was that EFI doesn't need anything. Whenever the EFI flow is added bootstd should 'just' call the bootmanager. Regards/Ilias > I've been trying to tease out the rules around finding the image and > the devicetree files, and this is what I've got it. > > Regards, > Simon
Re: [PATCH v10 10/10] arm_ffa: efi: corstone1000: enable MM communication
On Sun, Apr 02, 2023 at 02:41:17PM +1200, Simon Glass wrote: > Hi Abdellatif, > > On Wed, 29 Mar 2023 at 05:12, Abdellatif El Khlifi < > abdellatif.elkhl...@arm.com> wrote: > > > > turn on EFI MM communication > > > > On corstone1000 platform MM communication between u-boot > > and the secure world (Optee) is done using the FF-A bus. > > > > Signed-off-by: Abdellatif El Khlifi > > Cc: Tom Rini > > Cc: Simon Glass > > Cc: Ilias Apalodimas > > Cc: Jens Wiklander > > > > --- > > Changelog: > > === > > > > v9: update copyright string > > > > v8: > > > > * drop OP-TEE configs from Corstone-1000 defconfig > > > > v7: > > > > * improve the definition of FFA_SHARED_MM_BUFFER_ADDR and > > FFA_SHARED_MM_BUFFER_OFFSET > > * update FFA_SHARED_MM_BUFFER_ADDR value > > > > v6: > > > > * corstone-1000: enable optee driver > > * corstone-1000: remove CONFIG_ARM_FFA_EFI_RUNTIME_MODE from the defconfig > > > > v4: > > > > * corstone-1000: turn on EFI MM communication > > > > configs/corstone1000_defconfig | 2 ++ > > include/configs/corstone1000.h | 15 +-- > > 2 files changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/configs/corstone1000_defconfig > b/configs/corstone1000_defconfig > > index 74250c7524..a7bfcbb2b9 100644 > > --- a/configs/corstone1000_defconfig > > +++ b/configs/corstone1000_defconfig > > @@ -52,3 +52,5 @@ CONFIG_DM_SERIAL=y > > CONFIG_USB=y > > CONFIG_USB_ISP1760=y > > CONFIG_ERRNO_STR=y > > +CONFIG_EFI_MM_COMM_TEE=y > > +CONFIG_ARM_FFA_TRANSPORT=y > > diff --git a/include/configs/corstone1000.h > b/include/configs/corstone1000.h > > index 3347c11792..4ef1f05e40 100644 > > --- a/include/configs/corstone1000.h > > +++ b/include/configs/corstone1000.h > > @@ -1,9 +1,11 @@ > > /* SPDX-License-Identifier: GPL-2.0+ */ > > /* > > - * (C) Copyright 2022 ARM Limited > > * (C) Copyright 2022 Linaro > > * Rui Miguel Silva > > - * Abdellatif El Khlifi > > + * Copyright 2022-2023 Arm Limited and/or its affiliates < > open-source-off...@arm.com> > > + * > > + * Authors: > > + * Abdellatif El Khlifi > > * > > * Configuration for Corstone1000. Parts were derived from other ARM > > * configurations. > > @@ -14,6 +16,15 @@ > > > > #include > > > > +#define FFA_SHARED_MM_BUFFER_SIZE SZ_4K /* 4 KB */ > > + > > +/* > > + * shared buffer physical address used for communication between > > + * u-boot and the MM SP > > + */ > > +#define FFA_SHARED_MM_BUFFER_ADDR 0x0200UL > > +#define FFA_SHARED_MM_BUFFER_OFFSET0 > > + > > #define V2M_BASE 0x8000 > > > > #define CFG_PL011_CLOCK5000 > > -- > > 2.25.1 > > > > As a higher-level question, could this whole FFA implementation code be put > into Linux or fwupd? Hi Simon, FF-A is basically a communication mechanism between the secure and non-secure world for Arm. Linux has support for it. fwupd should be completely agnostic to the protocol Regards /Ilias > > Regards, > Simon
Re: [PATCH v4 1/2] regulator: implement basic reference counter
On 4/2/23 13:45, Jonas Karlman wrote:
Hi Eugen,
On 2023-03-31 11:15, Eugen Hristev wrote:
Some devices share a regulator supply, when the first one will request
regulator disable, the second device will have it's supply cut off before
graciously shutting down. Hence there will be timeouts and other failed
operations.
Implement a reference counter mechanism similar with what is done in
Linux, to keep track of enable and disable requests, and only disable the
regulator when the last of the consumers has requested shutdown.
Signed-off-by: Eugen Hristev
Reviewed-by: Simon Glass
---
Changes in v4:
- add documentation for error codes
Changes in v3:
- add error return codes
Changes in v2:
- add info in header regarding the function
drivers/power/regulator/regulator_common.c | 22 ++
drivers/power/regulator/regulator_common.h | 21 +
2 files changed, 43 insertions(+)
diff --git a/drivers/power/regulator/regulator_common.c
b/drivers/power/regulator/regulator_common.c
index 93d8196b381e..484a4fc31ef7 100644
--- a/drivers/power/regulator/regulator_common.c
+++ b/drivers/power/regulator/regulator_common.c
@@ -73,6 +73,23 @@ int regulator_common_set_enable(const struct udevice *dev,
return 0;
}
+ /* If previously enabled, increase count */
+ if (enable && dev_pdata->enable_count > 0) {
+ dev_pdata->enable_count++;
+ return -EALREADY;
+ }
+
+ if (!enable) {
+ if (dev_pdata->enable_count > 1) {
+ /* If enabled multiple times, decrease count */
+ dev_pdata->enable_count--;
+ return -EBUSY;
+ } else if (!dev_pdata->enable_count) {
+ /* If already disabled, do nothing */
+ return -EALREADY;
+ }
+ }
+
ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
if (ret) {
pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
@@ -87,5 +104,10 @@ int regulator_common_set_enable(const struct udevice *dev,
if (!enable && dev_pdata->off_on_delay_us)
udelay(dev_pdata->off_on_delay_us);
+ if (enable)
+ dev_pdata->enable_count++;
+ else
+ dev_pdata->enable_count--;
+
return 0;
}
diff --git a/drivers/power/regulator/regulator_common.h
b/drivers/power/regulator/regulator_common.h
index c10492f01675..0faab447d099 100644
--- a/drivers/power/regulator/regulator_common.h
+++ b/drivers/power/regulator/regulator_common.h
@@ -13,6 +13,7 @@ struct regulator_common_plat {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
unsigned int off_on_delay_us;
+ unsigned int enable_count;
};
int regulator_common_of_to_plat(struct udevice *dev,
@@ -20,6 +21,26 @@ int regulator_common_of_to_plat(struct udevice *dev,
char *enable_gpio_name);
int regulator_common_get_enable(const struct udevice *dev,
struct regulator_common_plat *dev_pdata);
+/*
+ * Enable or Disable a regulator
+ *
+ * This is a reentrant function and subsequent calls that enable will
+ * increase an internal counter, and disable calls will decrease the counter.
+ * The actual resource will be enabled when the counter gets to 1 coming from
0,
+ * and disabled when it reaches 0 coming from 1.
+ *
+ * @dev: regulator device
+ * @dev_pdata: Platform data
+ * @enable: bool indicating whether to enable or disable the regulator
+ * @return:
+ * 0 on Success
+ * -EBUSY if the regulator cannot be disabled because it's requested by
+ *another device
+ * -EALREADY if the regulator has already been enabled or has already been
+ *disabled
With this new return value added this has potential to break IO voltage
switching for mmc UHS support. Main pattern for IO voltage switch seem
to be: disable regulator, set voltage, enable regulator.
How can the breakage happen in this case ?
regulator_set_enable_if_allowed should probably be updated to return
success on -EALREADY, but that also has the potential to hide regulators
enabled at boot not being disabled unless initial enable_count reflects
the initial regulator state.
If the regulators enabled at boot are fixed/gpio regulators (which have
the enable count), then at boot , the autoset should call the
enable_common, thus taking into account the enable_count.
So I think that if I updated regulator_set_enable_if_allowed to return
success on -EALREADY it should be fine. Do you have any other scenario
in mind ?
Guessing initial enable_count will match for regulator-boot-on regulators
in Rockchip and few other platforms/boards because they the call
regulators_enable_boot_on, does not look like all platform will have
initial enable_count match regulator initial state.
If the other platforms do not call regulator enable,
[PATCH 1/1] test: improve configuration for Kconfig test options
* Fix dependencies
* Provide labels that are easier to grasp.
* Fix typo %s/whgch/which/
* Fix type %s/Is/is/
Fixes: 29784d62eded ("test: Add some tests for kconfig.h")
Signed-off-by: Heinrich Schuchardt
---
test/lib/Kconfig | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/test/lib/Kconfig b/test/lib/Kconfig
index dbb03e4a36..ae0aa2ff7a 100644
--- a/test/lib/Kconfig
+++ b/test/lib/Kconfig
@@ -1,23 +1,24 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright 2022 Google LLC
-if SANDBOX
-
config TEST_KCONFIG
bool "Enable detection of Kconfig macro errors"
+ depends on SANDBOX
help
This is used to test that the IF_ENABLED_INT() macro causes a build
error
- if the value is used when the CONFIG Is not enabled.
+ if the value is used when the CONFIG is not enabled.
+
+if TEST_KCONFIG
config TEST_KCONFIG_ENABLE
- bool "Option to enable"
+ bool "Provide a value for the Kconfig test"
help
This is the option that controls whether the value is present.
config TEST_KCONFIG_VALUE
- int "Value associated with the option"
+ int "Value used in Kconfig test"
depends on TEST_KCONFIG_ENABLE
help
- This is the value whgch is present if TEST_KCONFIG_ENABLE is enabled.
+ This is the value which is present if TEST_KCONFIG_ENABLE is enabled.
-endif # SANDBOX
+endif # TEST_KCONFIG
--
2.39.2
Re: rk3399 issue: no DMA in Linux with mainline TF-A and U-Boot SPL
> > The ARM PL330 DMA driver in kernel only relate to: > > - DTS kernel used, can be check in /proc/device-tree/ > > - kernel driver which should mach the compatible name. drivers/dma/pl330.c needs also a successfully matched amba, but this fails when using mainline TF-A and U-Boot SPL. I'm using the same kernel and devicetree on both tests, the only thing changed is TF-A and U-Boot SPL vs mini-loader and rk3399_bl31. > This driver should has nothing to do with U-Boot SPL or TF-A, because we > don't have any special setting for PL330 in loader stage. It is drivers/amba/bus.c, which is unable to find an AMBA_CID on the ARM bus. The DMA driver not loading is just a symptom of this issue. Any ideas? Thanks -- Christoph
Re: [PATCH v10 10/10] arm_ffa: efi: corstone1000: enable MM communication
On Mon, Apr 03, 2023 at 12:59:06PM +0300, Ilias Apalodimas wrote: > On Sun, Apr 02, 2023 at 02:41:17PM +1200, Simon Glass wrote: > > Hi Abdellatif, > > > > On Wed, 29 Mar 2023 at 05:12, Abdellatif El Khlifi < > > abdellatif.elkhl...@arm.com> wrote: > > > > > > turn on EFI MM communication > > > > > > On corstone1000 platform MM communication between u-boot > > > and the secure world (Optee) is done using the FF-A bus. > > > > > > Signed-off-by: Abdellatif El Khlifi > > > Cc: Tom Rini > > > Cc: Simon Glass > > > Cc: Ilias Apalodimas > > > Cc: Jens Wiklander > > > > > > --- > > > Changelog: > > > === > > > > > > v9: update copyright string > > > > > > v8: > > > > > > * drop OP-TEE configs from Corstone-1000 defconfig > > > > > > v7: > > > > > > * improve the definition of FFA_SHARED_MM_BUFFER_ADDR and > > > FFA_SHARED_MM_BUFFER_OFFSET > > > * update FFA_SHARED_MM_BUFFER_ADDR value > > > > > > v6: > > > > > > * corstone-1000: enable optee driver > > > * corstone-1000: remove CONFIG_ARM_FFA_EFI_RUNTIME_MODE from the defconfig > > > > > > v4: > > > > > > * corstone-1000: turn on EFI MM communication > > > > > > configs/corstone1000_defconfig | 2 ++ > > > include/configs/corstone1000.h | 15 +-- > > > 2 files changed, 15 insertions(+), 2 deletions(-) > > > > > > diff --git a/configs/corstone1000_defconfig > > b/configs/corstone1000_defconfig > > > index 74250c7524..a7bfcbb2b9 100644 > > > --- a/configs/corstone1000_defconfig > > > +++ b/configs/corstone1000_defconfig > > > @@ -52,3 +52,5 @@ CONFIG_DM_SERIAL=y > > > CONFIG_USB=y > > > CONFIG_USB_ISP1760=y > > > CONFIG_ERRNO_STR=y > > > +CONFIG_EFI_MM_COMM_TEE=y > > > +CONFIG_ARM_FFA_TRANSPORT=y > > > diff --git a/include/configs/corstone1000.h > > b/include/configs/corstone1000.h > > > index 3347c11792..4ef1f05e40 100644 > > > --- a/include/configs/corstone1000.h > > > +++ b/include/configs/corstone1000.h > > > @@ -1,9 +1,11 @@ > > > /* SPDX-License-Identifier: GPL-2.0+ */ > > > /* > > > - * (C) Copyright 2022 ARM Limited > > > * (C) Copyright 2022 Linaro > > > * Rui Miguel Silva > > > - * Abdellatif El Khlifi > > > + * Copyright 2022-2023 Arm Limited and/or its affiliates < > > open-source-off...@arm.com> > > > + * > > > + * Authors: > > > + * Abdellatif El Khlifi > > > * > > > * Configuration for Corstone1000. Parts were derived from other ARM > > > * configurations. > > > @@ -14,6 +16,15 @@ > > > > > > #include > > > > > > +#define FFA_SHARED_MM_BUFFER_SIZE SZ_4K /* 4 KB */ > > > + > > > +/* > > > + * shared buffer physical address used for communication between > > > + * u-boot and the MM SP > > > + */ > > > +#define FFA_SHARED_MM_BUFFER_ADDR 0x0200UL > > > +#define FFA_SHARED_MM_BUFFER_OFFSET0 > > > + > > > #define V2M_BASE 0x8000 > > > > > > #define CFG_PL011_CLOCK5000 > > > -- > > > 2.25.1 > > > > > > > As a higher-level question, could this whole FFA implementation code be put > > into Linux or fwupd? > > Hi Simon, FF-A is basically a communication mechanism between the secure > and non-secure world for Arm. Linux has support for it. fwupd should be > completely agnostic to the protocol Hi Simon, I'd like to add to Ilias's explanation the following helpful resources: - The patchset cover letter for a high level overview of what FF-A is about [1]. - A closer look at the FF-A implementation in U-Boot the readme [2]. Cheers [1]: https://lore.kernel.org/all/20230328161157.219375-1-abdellatif.elkhl...@arm.com/ [2]: doc/arch/arm64.ffa.rst > > Regards > /Ilias > > > > Regards, > > Simon
Re: [PATCH 1/2] Boot var automatic management for removable medias
Hi Raymond,
[...]
> + }
> + }
> + }
> +
> +out:
> + if (opt) {
> + for (i = 0; i < count; i++) {
> + if (opt[i].lo)
> + free(opt[i].lo);
> + }
> + free(opt);
> + }
> + efi_free_pool(volume_handles);
> +
> + return ret;
> +}
> diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> index d2256713a8..1309e28134 100644
> --- a/lib/efi_loader/efi_disk.c
> +++ b/lib/efi_loader/efi_disk.c
> @@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
> return -1;
> }
>
> + /* only do the boot option management when UEFI sub-system is
> initialized */
> + if (efi_obj_list_initialized == EFI_SUCCESS) {
> + ret = efi_bootmgr_update_media_device_boot_option();
I am not sure if this is the problem, but with these patches applied and no
media attached QEMU fails to initialize the EFI sub-system. IOW running
qemu-system-aarch64 -bios u-boot.bin -machine virt,secure=off -cpu cortex-a53
-m 2G -nographic -no-acpi
=> efidebug boot dump
No EFI system partition
Error: Cannot initialize UEFI sub-system, r = 14
We should always start EFI, even if scanning for boot options fails.
> + if (ret)
> + return -1;
> + }
> +
> return 0;
> }
>
> diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
> index 1f4ab2b419..cdfd16ea77 100644
> --- a/lib/efi_loader/efi_helper.c
> +++ b/lib/efi_loader/efi_helper.c
> @@ -257,3 +257,28 @@ efi_status_t efi_next_variable_name(efi_uintn_t *size,
> u16 **buf, efi_guid_t *gu
>
> return ret;
> }
> +
> +/**
> + * efi_search_bootorder() - search the boot option index in BootOrder
> + *
> + * @bootorder: pointer to the BootOrder variable
> + * @num: number of BootOrder entry
> + * @target: target boot option index to search
> + * @index: pointer to store the index of BootOrder variable
> + * Return: true if exists, false otherwise
> + */
> +bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32
> *index)
> +{
> + u32 i;
> +
> + for (i = 0; i < num; i++) {
> + if (target == bootorder[i]) {
> + if (index)
> + *index = i;
> +
> + return true;
> + }
> + }
> +
> + return false;
> +}
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index be95ed44e6..2f251553e1 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -476,6 +476,10 @@ efi_status_t efi_init_variables(void)
> log_err("Invalid EFI variable seed\n");
> }
>
> + ret = efi_init_secure_state();
> + if (ret != EFI_SUCCESS)
> + return ret;
>
> - return efi_init_secure_state();
> + /* update boot option management after variable service initialized */
> + return efi_bootmgr_update_media_device_boot_option();
> }
> diff --git a/lib/efi_loader/efi_variable_tee.c
> b/lib/efi_loader/efi_variable_tee.c
> index dfef18435d..a48d313ef0 100644
> --- a/lib/efi_loader/efi_variable_tee.c
> +++ b/lib/efi_loader/efi_variable_tee.c
> @@ -748,5 +748,6 @@ efi_status_t efi_init_variables(void)
> if (ret != EFI_SUCCESS)
> return ret;
>
> - return EFI_SUCCESS;
> + /* update boot option management after variable service initialized */
> + return efi_bootmgr_update_media_device_boot_option();
> }
> --
> 2.25.1
>
Regards
/Ilias
[PATCH v2] mmc: dw_mmc: reset controller after data error
From: Ziyuan Xu
Per dw_mmc databook, it's recommended to reset the host controller if
some data-related error occurred.
Implement a reset mechanism.
Signed-off-by: Ziyuan Xu
Co-developed-by: Jason Zhu
Signed-off-by: Jason Zhu
[eugen.hris...@collabora.com: modified a bit the variables initialization]
Signed-off-by: Eugen Hristev
---
Changes in v2:
- actually decrement the reset timeout timer
drivers/mmc/dw_mmc.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 5085a3b491da..d6cad998b0cd 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -138,7 +138,7 @@ static int dwmci_data_transfer(struct dwmci_host *host,
struct mmc_data *data)
{
struct mmc *mmc = host->mmc;
int ret = 0;
- u32 timeout, mask, size, i, len = 0;
+ u32 timeout, reset_timeout = 100, status, ctrl, mask, size, i, len = 0;
u32 *buf = NULL;
ulong start = get_timer(0);
u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
@@ -159,6 +159,24 @@ static int dwmci_data_transfer(struct dwmci_host *host,
struct mmc_data *data)
/* Error during data transfer. */
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
debug("%s: DATA ERROR!\n", __func__);
+
+ dwmci_wait_reset(host, DWMCI_RESET_ALL);
+ dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
+DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+
+ do {
+ status = dwmci_readl(host, DWMCI_CMD);
+ if (!reset_timeout--)
+ break;
+ udelay(100);
+ } while (status & DWMCI_CMD_START);
+
+ if (!host->fifo_mode) {
+ ctrl = dwmci_readl(host, DWMCI_BMOD);
+ ctrl |= DWMCI_BMOD_IDMAC_RESET;
+ dwmci_writel(host, DWMCI_BMOD, ctrl);
+ }
+
ret = -EINVAL;
break;
}
--
2.34.1
Re: [PATCH V5 02/13] drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL
Hi Nikhil, On 03/04/23 13:44, Nikhil M Jain wrote: > To enable tidss video driver only at SPL stage, add necessary config, > CONFIG_SPL_VIDEO_TIDSS. > > Signed-off-by: Nikhil M Jain > Reviewed-by: Simon Glass > --- > V5: > - No change > > V4: > - Add Reviewed-By tag > > V3: > - No change > > V2: > - No change > > drivers/video/tidss/Kconfig | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig > index 2a5e56ea4e..748c332281 100644 > --- a/drivers/video/tidss/Kconfig > +++ b/drivers/video/tidss/Kconfig > @@ -16,3 +16,9 @@ menuconfig VIDEO_TIDSS > DPI . This option enables these supports which can be used on > devices which have OLDI or HDMI display connected. > > +config SPL_VIDEO_TIDSS > + bool "Enable TIDSS video support in SPL Stage" > + depends on SPL_VIDEO > + help > + This options enables tidss driver in SPL stage. If > + you need to use tidssat SPL stage use this config. Minor typo "you need to use tidss display driver at SPL stage" After that is fixed, feel free to add Reviewed-by: Devarsh Thakkar Regards Devarsh
Re: [PATCH V5 03/13] drivers: Makefile: Add rule to compile video driver
Hi Nikhil, On 03/04/23 13:44, Nikhil M Jain wrote: > CONFIG_$(SPL_)VIDEO checks for CONFIG_SPL_VIDEO at SPL and CONFIG_VIDEO > at u-boot proper and compiles video driver at respective stage. > Please update above commit message per the new patch change as CONFIG_$(SPL_)VIDEO is not used now. After above change, kindly add, > Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Regards Devarsh > --- > V5: > - Add rule to build video at SPL using CONFIG_SPL_VIDEO and retain > obj-y +=video for u-boot proper. > > V4: > - No change > > V3 (patch introduced): > - Add rule to compile video driver at SPL. > > drivers/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/Makefile b/drivers/Makefile > index 58be410135..928a8b0e9d 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -61,6 +61,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ > obj-$(CONFIG_SPL_SATA) += ata/ scsi/ > obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ > obj-$(CONFIG_SPL_THERMAL) += thermal/ > +obj-$(CONFIG_SPL_VIDEO) +=video/ > > endif > endif
Re: [PATCH V5 04/13] drivers: video: Makefile: Rule to compile necessary video driver files
Hi Nikhil, On 03/04/23 13:44, Nikhil M Jain wrote: > To enable video driver at SPL, need to compile video-uclass, > vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add > rules to compile them at SPL only. To support splash_display at SPL, > need to compile video-bmp, add rule to compile at SPL stage. > > Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Regards Devarsh > --- > V5: > - Use $(SPL_TPL_) to check for stage specific configs and compile at > specific stages. > - Removed ifdef CONFIG_SPL_BUILD > > V4: > - No change > > V3: > - Rule to compile backlight, console and panel files > - Not added Reiewed-by tag due to changes > > V2: > - No change > > drivers/video/Makefile | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/video/Makefile b/drivers/video/Makefile > index cb3f373645..bb139f550c 100644 > --- a/drivers/video/Makefile > +++ b/drivers/video/Makefile > @@ -4,12 +4,12 @@ > # Wolfgang Denk, DENX Software Engineering, w...@denx.de. > > ifdef CONFIG_DM > -obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o > +obj-$(CONFIG_$(SPL_TPL_)BACKLIGHT) += backlight-uclass.o > obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o > obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o > -obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o > +obj-$(CONFIG_$(SPL_TPL)CONSOLE_NORMAL) += console_normal.o > obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o > -ifdef CONFIG_CONSOLE_NORMAL > +ifdef CONFIG_$(SPL_TPL_)CONSOLE_NORMAL > obj-y += console_core.o > else ifdef CONFIG_CONSOLE_ROTATION > obj-y += console_core.o > @@ -18,9 +18,9 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o > obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ > obj-$(CONFIG_DISPLAY) += display-uclass.o > obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o > -obj-$(CONFIG_VIDEO) += video-uclass.o vidconsole-uclass.o > -obj-$(CONFIG_VIDEO) += video_bmp.o > -obj-$(CONFIG_PANEL) += panel-uclass.o > +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video-uclass.o vidconsole-uclass.o > +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video_bmp.o > +obj-$(CONFIG_$(SPL_TPL_)PANEL) += panel-uclass.o > obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o > obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o >
Re: [PATCH V5 06/13] common: Makefile: Add rule to compile splash and splash_source at SPL
Hi Nikhil, On 03/04/23 13:44, Nikhil M Jain wrote: > To enable splash screen and loading bmp from boot media, add rules to > compile splash.c and splash_source.c at SPL stage only when > CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_SPLASH_SOURCE are defined. > > Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar > --- > V5: > - No change > > V4: > - No change > > V3 (patch introduced): > - Rule to compile splash.c and splash_source.c. > > common/Makefile | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/common/Makefile b/common/Makefile > index a50302d8b5..3a6ca337e0 100644 > --- a/common/Makefile > +++ b/common/Makefile > @@ -56,6 +56,8 @@ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o > obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o > obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o > obj-$(CONFIG_SPL_MUSB_NEW) += usb.o > +obj-$(CONFIG_SPL_SPLASH_SCREEN) += splash.o > +obj-$(CONFIG_SPL_SPLASH_SOURCE) += splash_source.o > endif # CONFIG_SPL_BUILD > > #others
Re: [PATCH V5 07/13] common: Kconfig: Add BMP configs
Hi Nikhil, On 03/04/23 13:44, Nikhil M Jain wrote: > Add CONFIG_BMP and CONFIG_SPL_BMP which enable displaying bmp images at > u-boot proper and SPL. > > Signed-off-by: Nikhil M Jain > Reviewed-by: Simon Glass Reviewed-by: Devarsh Thakkar Regards Devarsh > --- > V5: > - Added Reviewed-by tag. > > V4: > - No change. > > V3 (patch introduced): > - Add CONFIG BMP and SPL_BMP. > > common/Kconfig | 12 > 1 file changed, 12 insertions(+) > > diff --git a/common/Kconfig b/common/Kconfig > index 7ff62552cb..7329dc8253 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -1154,3 +1154,15 @@ config FDT_SIMPLEFB > > config IO_TRACE > bool > + > +config BMP > + bool "Enable bmp image display" > + default y if CMD_BMP > + help > + Enable bmp functions to display bmp image and get bmp info. > + > +config SPL_BMP > + bool "Enable bmp image display at SPL" > + depends on SPL_VIDEO > + help > + Enable bmp functions to display bmp image and get bmp info at SPL.
[PATCH v1 0/2] colibri-imx8x: snvs and firmware info
This series updates recent Colibri iMX8X support refresh with following: * initialize secure non-volatile storage, aka snvs * print firmware versions during boot Andrejs Cainikovs (2): colibri-imx8x: print firmware versions board: colibri-imx8x: initialize snvs board/toradex/colibri-imx8x/colibri-imx8x.c | 10 ++ 1 file changed, 10 insertions(+) -- 2.34.1
[PATCH v1 1/2] colibri-imx8x: print firmware versions
Print firmware versions during U-Boot start:
BuildInfo:
- SCFW f5623878, SECO-FW c9de51c0, IMX-MKIMAGE 0, ATF c6a19b1
- U-Boot 2022.04-00335-g65192567f81-dirty
Signed-off-by: Andrejs Cainikovs
---
board/toradex/colibri-imx8x/colibri-imx8x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c
b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 6ed9cc4fa80..4f4d45fe0f3 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -170,6 +170,8 @@ int board_late_init(void)
env_set("board_rev", "v1.0");
#endif
+ build_info();
+
select_dt_from_module_version();
return 0;
--
2.34.1
[PATCH v1 2/2] board: colibri-imx8x: initialize snvs
Initialize Secure Non-Volatile Storage, aka SNVS.
Signed-off-by: Andrejs Cainikovs
---
board/toradex/colibri-imx8x/colibri-imx8x.c | 8
1 file changed, 8 insertions(+)
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c
b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 4f4d45fe0f3..03fc88a54bd 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -139,6 +140,13 @@ int board_init(void)
{
board_gpio_init();
+ if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) {
+ int ret = snvs_security_sc_init();
+
+ if (ret)
+ return ret;
+ }
+
return 0;
}
--
2.34.1
Re: [PATCH v3 1/3] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
On 4/2/23 14:00, Jonas Karlman wrote:
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add USB 2.0 host nodes and PHYs.
Co-developed-by: William Wu
Signed-off-by: William Wu
Signed-off-by: Eugen Hristev
---
Changes in v2,v3:
- none
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169
1 file changed, 169 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 2386edf90deb..e1d240baf35d 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -4,6 +4,9 @@
*/
#include "rk3588-u-boot.dtsi"
+#include
+#include
+#include
/ {
aliases {
@@ -13,6 +16,105 @@
chosen {
u-boot,spl-boot-order = &sdmmc;
};
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ u-boot,dm-pre-reloc;
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ usb_host0_ehci: usb@fc80 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xfc80 0x0 0x4>;
+ interrupts = ;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
+ clock-names = "usbhost", "arbiter";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@fc84 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfc84 0x0 0x4>;
+ interrupts = ;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
+ clock-names = "usbhost", "arbiter";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@fc88 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xfc88 0x0 0x4>;
+ interrupts = ;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
+ clock-names = "usbhost", "arbiter";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@fc8c {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfc8c 0x0 0x4>;
+ interrupts = ;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
+ clock-names = "usbhost", "arbiter";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb2phy2_grf: syscon@fd5d8000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+"simple-mfd";
+ reg = <0x0 0xfd5d8000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy2: usb2-phy@8000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x8000 0x10>;
+ interrupts = ;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy2_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb2phy3_grf: syscon@fd5dc000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+"simple-mfd";
+ reg = <0x0 0xfd5dc000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy3: usb2-phy@c000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0xc000 0x10>;
+ interrupts = ;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy3_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
Most of these nodes could be added to the soc u-boot dtsi and not the
board specific file. Also wondering if some of the reset and clock
related properties below are board specific or soc specific and can go
into the above soc nodes directly.
That is right, but , it would spread all the -u-boot.dtsi nodes into a
lot of files. So I ke
Re: [PATCH V5 08/13] cmd: bmp: Split bmp commands and functions
On 03/04/23 13:44, Nikhil M Jain wrote:
> To enable splash screen at spl, need to compile cmd/bmp.c which also
s/spl/SPL
> includes bmp commands, since SPL can't have commands split bmp.c into
since SPL doesn't use bmp commands, split cmd/bmp.c into ...
> common/bmp.c which includes all bmp functions and cmd/bmp.c contains
cmd/bmp.c which only contains
> bmp commands.
>
> Add delclaration for bmp_info in video.h.
s/delclaration/function declaration
>
> Signed-off-by: Nikhil M Jain
> ---
> V5:
> - Rename cmd/bmp_cmd to cmd/bmp.
>
> V4:
> - No change.
>
> V3 (patch introduced):
> - Split bmp functions and commands.
>
> cmd/bmp.c | 161 +---
> common/bmp.c| 153 +
> include/video.h | 7 +++
> 3 files changed, 162 insertions(+), 159 deletions(-)
> create mode 100644 common/bmp.c
>
> diff --git a/cmd/bmp.c b/cmd/bmp.c
> index 46d0d916e8..735790fda7 100644
> --- a/cmd/bmp.c
> +++ b/cmd/bmp.c
> @@ -11,82 +11,11 @@
> #include
> #include
> #include
> -#include
> -#include
> #include
> -#include
> -#include
> #include
> #include
> #include
> -#include
> -
Just to confirm, please test once with u-boot proper and bmp display command
too if not done already.
> -static int bmp_info (ulong addr);
> -
> -/*
> - * Allocate and decompress a BMP image using gunzip().
> - *
> - * Returns a pointer to the decompressed image data. This pointer is
> - * aligned to 32-bit-aligned-address + 2.
> - * See doc/README.displaying-bmps for explanation.
> - *
> - * The allocation address is passed to 'alloc_addr' and must be freed
> - * by the caller after use.
> - *
> - * Returns NULL if decompression failed, or if the decompressed data
> - * didn't contain a valid BMP signature.
> - */
> -#ifdef CONFIG_VIDEO_BMP_GZIP
> -struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
> - void **alloc_addr)
> -{
> - void *dst;
> - unsigned long len;
> - struct bmp_image *bmp;
> -
> - /*
> - * Decompress bmp image
> - */
> - len = CONFIG_VIDEO_LOGO_MAX_SIZE;
> - /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
> - dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
> - if (!dst) {
> - puts("Error: malloc in gunzip failed!\n");
> - return NULL;
> - }
> -
> - /* align to 32-bit-aligned-address + 2 */
> - bmp = dst + 2;
> -
> - if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
> -&len)) {
> - free(dst);
> - return NULL;
> - }
> - if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
> - puts("Image could be truncated (increase
> CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
> -
> - /*
> - * Check for bmp mark 'BM'
> - */
> - if (!((bmp->header.signature[0] == 'B') &&
> - (bmp->header.signature[1] == 'M'))) {
> - free(dst);
> - return NULL;
> - }
> -
> - debug("Gzipped BMP image detected!\n");
> -
> - *alloc_addr = dst;
> - return bmp;
> -}
> -#else
> -struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
> - void **alloc_addr)
> -{
> - return NULL;
> -}
> -#endif
> +#include
>
> static int do_bmp_info(struct cmd_tbl *cmdtp, int flag, int argc,
> char *const argv[])
> @@ -137,7 +66,7 @@ static int do_bmp_display(struct cmd_tbl *cmdtp, int flag,
> int argc,
> return CMD_RET_USAGE;
> }
>
> - return (bmp_display(addr, x, y));
> + return (bmp_display(addr, x, y));
> }
>
> static struct cmd_tbl cmd_bmp_sub[] = {
> @@ -145,22 +74,6 @@ static struct cmd_tbl cmd_bmp_sub[] = {
> U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
> };
>
> -#ifdef CONFIG_NEEDS_MANUAL_RELOC
> -void bmp_reloc(void) {
> - fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
> -}
> -#endif
> -
> -/*
> - * Subroutine: do_bmp
> - *
> - * Description: Handler for 'bmp' command..
> - *
> - * Inputs: argv[1] contains the subcommand
> - *
> - * Return: None
> - *
> - */
> static int do_bmp(struct cmd_tbl *cmdtp, int flag, int argc, char *const
> argv[])
> {
> struct cmd_tbl *c;
> @@ -183,73 +96,3 @@ U_BOOT_CMD(
> "info - display image info\n"
> "bmp display [x y] - display image at x,y"
> );
> -
> -/*
> - * Subroutine: bmp_info
> - *
> - * Description: Show information about bmp file in memory
> - *
> - * Inputs: addraddress of the bmp file
> - *
> - * Return: None
> - *
> - */
> -static int bmp_info(ulong addr)
> -{
> - struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0);
> - void *bmp_alloc_addr = NULL;
> - unsigned long len;
> -
> - if (!((bmp->header.signature[0]=='B') &&
> - (bmp->header.signature[1]=='M')))
> - bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr);
> -
> -
Re: [PATCH v3 2/3] phy: rockchip-inno-usb2: add initial support for rk3588 PHY
On 4/2/23 14:04, Jonas Karlman wrote: Hi Eugen, On 2023-03-31 11:40, Eugen Hristev wrote: Add initial support for the rk3588 PHY variant. The driver now looks for phy-supply and enables/disables the vbus accordingly. Maybe this should be added to core phy uclass to closer match linux? Look like e.g. meson phy drivers also handle a phy-supply and could also benefit from having this in phy uclass instead of in each phy driver. This can be done yes. I can try it. Regards, Jonas
Re: [PATCH V5 09/13] common: Makefile: Rule to compile bmp.c
On 03/04/23 13:44, Nikhil M Jain wrote: > Add rule to compile bmp.c at SPL and u-boot proper when CONFIG_SPL_BMP > and CONFIG_BMP are defined. > > Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar > --- > V5: > - Remove obj-y+= read.o. > > V4: > - No change. > > V3 (patch introduced): > - Rule to compile common/bmp. > > common/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/common/Makefile b/common/Makefile > index 3a6ca337e0..c87bb2e78b 100644 > --- a/common/Makefile > +++ b/common/Makefile > @@ -45,6 +45,7 @@ endif # !CONFIG_SPL_BUILD > > obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o > obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o > +obj-$(CONFIG_$(SPL_)BMP) += bmp.o > > ifdef CONFIG_SPL_BUILD > ifdef CONFIG_SPL_DFU
Re: [PATCH V5 11/13] common: Enable splash functions at SPL
Hi,
On 03/04/23 13:44, Nikhil M Jain wrote:
> To support splash screen at SPL use CONFIG_IS_ENABLED and CONFIG_VAL. To
support splash screen at both u-boot proper and SPL use xyz macros
to check for video related Kconfigs.
> check for stage specific configs at u-boot proper and SPL.
>
> Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
> at u-boot proper and SPL.
>
> Signed-off-by: Nikhil M Jain
After commit message is updated,
Reviewed-by: Devarsh Thakkar
Regards
Devarsh
> ---
> V5:
> - Replace CONFIG_CMD_BMP with CONFIG_BMP.
>
> V4:
> - No change
>
> V3 (patch introduced):
> - Enable splash functions at SPL
>
> common/bmp.c| 10 +-
> common/splash.c | 10 +-
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/common/bmp.c b/common/bmp.c
> index 540d06e63f..51766b3c21 100644
> --- a/common/bmp.c
> +++ b/common/bmp.c
> @@ -33,7 +33,7 @@
> * Returns NULL if decompression failed, or if the decompressed data
> * didn't contain a valid BMP signature.
> */
> -#ifdef CONFIG_VIDEO_BMP_GZIP
> +#if CONFIG_IS_ENABLED(VIDEO_BMP_GZIP)
> struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
>void **alloc_addr)
> {
> @@ -44,9 +44,9 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
> long *lenp,
> /*
>* Decompress bmp image
>*/
> - len = CONFIG_VIDEO_LOGO_MAX_SIZE;
> + len = CONFIG_VAL(VIDEO_LOGO_MAX_SIZE);
> /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
> - dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
> + dst = malloc(CONFIG_VAL(VIDEO_LOGO_MAX_SIZE) + 3);
> if (!dst) {
> puts("Error: malloc in gunzip failed!\n");
> return NULL;
> @@ -55,12 +55,12 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
> long *lenp,
> /* align to 32-bit-aligned-address + 2 */
> bmp = dst + 2;
>
> - if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
> + if (gunzip(bmp, CONFIG_VAL(VIDEO_LOGO_MAX_SIZE), map_sysmem(addr, 0),
> &len)) {
> free(dst);
> return NULL;
> }
> - if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
> + if (len == CONFIG_VAL(VIDEO_LOGO_MAX_SIZE))
> puts("Image could be truncated (increase
> CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
>
> /*
> diff --git a/common/splash.c b/common/splash.c
> index 4bc54b1bf9..a4e68b7042 100644
> --- a/common/splash.c
> +++ b/common/splash.c
> @@ -89,14 +89,14 @@ static inline int splash_video_logo_load(void) { return
> -ENOSYS; }
>
> __weak int splash_screen_prepare(void)
> {
> - if (IS_ENABLED(CONFIG_SPLASH_SOURCE))
> + if (CONFIG_IS_ENABLED(SPLASH_SOURCE))
> return splash_source_load(default_splash_locations,
> ARRAY_SIZE(default_splash_locations));
>
> return splash_video_logo_load();
> }
>
> -#ifdef CONFIG_SPLASH_SCREEN_ALIGN
> +#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
> void splash_get_pos(int *x, int *y)
> {
> char *s = env_get("splashpos");
> @@ -119,7 +119,7 @@ void splash_get_pos(int *x, int *y)
> }
> #endif /* CONFIG_SPLASH_SCREEN_ALIGN */
>
> -#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
> +#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
>
> #ifdef CONFIG_VIDEO_LOGO
> #include
> @@ -159,7 +159,7 @@ void splash_display_banner(void)
> * Common function to show a splash image if env("splashimage") is set.
> * For additional details please refer to doc/README.splashprepare.
> */
> -#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
> +#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
> int splash_display(void)
> {
> ulong addr;
> @@ -183,7 +183,7 @@ int splash_display(void)
> if (x || y)
> goto end;
>
> -#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
> +#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
> splash_display_banner();
> #endif
> end:
Re: [PATCH V5 12/13] include: Enable video related global data variable and splash at SPL
Hi,
On 03/04/23 13:44, Nikhil M Jain wrote:
> To include video related global data variables and splash functions at
> SPL, use CONFIG_IS_ENABLED.
s/at SPL/at both SPL and u-boot proper
>
> Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
> at u-boot proper and SPL.
>
> Signed-off-by: Nikhil M Jain
After above change,
Reviewed-by: Devarsh Thakkar
Regards
Devarsh
> ---
> V5:
> - Replace CONFIG_CMD_BMP with CONFIG_BMP.
>
> V4:
> - No change.
>
> V3 (patch introduced):
> - Include video related global data variables.
> - Include splash display functions.
>
> include/asm-generic/global_data.h | 4 ++--
> include/splash.h | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/include/asm-generic/global_data.h
> b/include/asm-generic/global_data.h
> index 987fb66c17..65bf8df1e5 100644
> --- a/include/asm-generic/global_data.h
> +++ b/include/asm-generic/global_data.h
> @@ -68,7 +68,7 @@ struct global_data {
>* @mem_clk: memory clock rate in Hz
>*/
> unsigned long mem_clk;
> -#if defined(CONFIG_VIDEO)
> +#if CONFIG_IS_ENABLED(VIDEO)
> /**
>* @fb_base: base address of frame buffer memory
>*/
> @@ -359,7 +359,7 @@ struct global_data {
>*/
> struct membuff console_in;
> #endif
> -#ifdef CONFIG_VIDEO
> +#if CONFIG_IS_ENABLED(VIDEO)
> /**
>* @video_top: top of video frame buffer area
>*/
> diff --git a/include/splash.h b/include/splash.h
> index 33e45e6941..b6a100ffc3 100644
> --- a/include/splash.h
> +++ b/include/splash.h
> @@ -49,7 +49,7 @@ struct splash_location {
> char *ubivol; /* UBI volume-name for ubifsmount */
> };
>
> -#ifdef CONFIG_SPLASH_SOURCE
> +#if CONFIG_IS_ENABLED(SPLASH_SOURCE)
> int splash_source_load(struct splash_location *locations, uint size);
> #else
> static inline int splash_source_load(struct splash_location *locations,
> @@ -61,13 +61,13 @@ static inline int splash_source_load(struct
> splash_location *locations,
>
> int splash_screen_prepare(void);
>
> -#ifdef CONFIG_SPLASH_SCREEN_ALIGN
> +#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
> void splash_get_pos(int *x, int *y);
> #else
> static inline void splash_get_pos(int *x, int *y) { }
> #endif
>
> -#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
> +#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
> int splash_display(void);
> #else
> static inline int splash_display(void)
[PATCH v2 0/5] board: verdin-imx8mp: ddr updates
From: Marcel Ziswiler This series contains the following DDR updates: - update ddrc config for different lpddr4 memories - fix lpddr4 refresh timing - update lpddr4 configuration and training - compact slight different lpddr4 configuration - change prints in spl_dram_init function Changes in v2: - Use puts rather than printf in the SPL as suggested by Fabio. Thanks! Emanuele Ghidoli (5): board: verdin-imx8mp: update ddrc config for different lpddr4 memories board: verdin-imx8mp: fix lpddr4 refresh timing board: verdin-imx8mp: update lpddr4 configuration and training board: verdin-imx8mp: compact slight different lpddr4 configuration board: verdin-imx8mp: change prints in spl_dram_init function board/toradex/verdin-imx8mp/lpddr4_timing.c | 423 board/toradex/verdin-imx8mp/lpddr4_timing.h | 11 + board/toradex/verdin-imx8mp/spl.c | 19 +- 3 files changed, 106 insertions(+), 347 deletions(-) create mode 100644 board/toradex/verdin-imx8mp/lpddr4_timing.h -- 2.36.1
[PATCH v2 1/5] board: verdin-imx8mp: update ddrc config for different lpddr4 memories
From: Emanuele Ghidoli
Add support to Verdin IMX8MP V1.1B SKU which uses
MT53E1G32D2FW-046 WT:B memory.
Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on
Verdin IMX8MP V1.0A it has 16 row addresses instead of 17.
In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a
4 GB/rank memory.
Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it
is possible to have a single configuration working with both memories:
- Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16
- New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16
With this change the memory space from the host processor is contiguous
for both the configurations and the correct memory size is computed
using get_ram_size() at runtime.
Support for single rank memories still works thanks to the fact
dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank
memories.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
board/toradex/verdin-imx8mp/lpddr4_timing.c | 4 ++--
board/toradex/verdin-imx8mp/spl.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c
b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 3e00d9b51e1..314b74e7df2 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -55,13 +55,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
{ 0x3d400108, 0x9121c1c },
- { 0x3d400200, 0x18 },
+ { 0x3d400200, 0x17 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
- { 0x3d40021c, 0xf07 },
+ { 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x430 },
diff --git a/board/toradex/verdin-imx8mp/spl.c
b/board/toradex/verdin-imx8mp/spl.c
index ea99e370850..7b383cc0d53 100644
--- a/board/toradex/verdin-imx8mp/spl.c
+++ b/board/toradex/verdin-imx8mp/spl.c
@@ -34,11 +34,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_dram_init(void)
{
/*
-* try configuring for quad die, dual rank aka 8 GB falling back to
-* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
+* Try configuring for dual rank memory falling back to single rank
*/
if (ddr_init(&dram_timing)) {
- printf("Quad die, dual rank failed, attempting dual die, single
rank configuration.\n");
+ printf("Dual rank failed, attempting single rank
configuration.\n");
ddr_init(&dram_timing2);
}
}
--
2.36.1
[PATCH v2 2/5] board: verdin-imx8mp: fix lpddr4 refresh timing
From: Emanuele Ghidoli
Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with
current and futures memories.
Fixes: 2bc2f817cea7 ("board: toradex: add verdin imx8m plus support")
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
board/toradex/verdin-imx8mp/lpddr4_timing.c | 24 ++---
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c
b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 314b74e7df2..58278d2150a 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -21,7 +21,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40, 0xa3080020 },
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
+ { 0x3d400064, 0x7a017c },
{ 0x3d400070, 0x61027f10 },
{ 0x3d400074, 0x7b0 },
{ 0x3d4000d0, 0xc00307a3 },
@@ -39,7 +39,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40011c, 0x501 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe12 },
- { 0x3d400138, 0x120 },
+ { 0x3d400138, 0x184 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
@@ -77,7 +77,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402020, 0x1001 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc001c },
+ { 0x3d402064, 0xc0026 },
{ 0x3d4020dc, 0x84 },
{ 0x3d4020e0, 0x33 },
{ 0x3d4020e8, 0x660048 },
@@ -92,7 +92,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40211c, 0x301 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa12 },
- { 0x3d402138, 0x1d },
+ { 0x3d402138, 0x27 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
@@ -102,7 +102,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x30007 },
+ { 0x3d403064, 0x3000a },
{ 0x3d4030dc, 0x84 },
{ 0x3d4030e0, 0x33 },
{ 0x3d4030e8, 0x660048 },
@@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40311c, 0x301 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa12 },
- { 0x3d403138, 0x8 },
+ { 0x3d403138, 0xa },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
@@ -1841,7 +1841,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d40, 0xa1080020 },
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
+ { 0x3d400064, 0x7a017c },
{ 0x3d400070, 0x61027f10 },
{ 0x3d400074, 0x7b0 },
{ 0x3d4000d0, 0xc00307a3 },
@@ -1859,7 +1859,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d40011c, 0x501 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe12 },
- { 0x3d400138, 0x120 },
+ { 0x3d400138, 0x184 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
@@ -1897,7 +1897,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d402020, 0x1001 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc001c },
+ { 0x3d402064, 0xc0026 },
{ 0x3d4020dc, 0x84 },
{ 0x3d4020e0, 0x33 },
{ 0x3d4020e8, 0x660048 },
@@ -1912,7 +1912,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d40211c, 0x301 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa12 },
- { 0x3d402138, 0x1d },
+ { 0x3d402138, 0x27 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
@@ -1922,7 +1922,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x30007 },
+ { 0x3d403064, 0x3000a },
{ 0x3d4030dc, 0x84 },
{ 0x3d4030e0, 0x33 },
{ 0x3d4030e8, 0x660048 },
@@ -1937,7 +1937,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d40311c, 0x301 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa12 },
- { 0x3d403138, 0x8 },
+ { 0x3d403138, 0xa },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
--
2.36.1
[PATCH v2 4/5] board: verdin-imx8mp: compact slight different lpddr4 configuration
From: Emanuele Ghidoli
Deduplicate similar DDRC configurations and LPDDR4 training patterns
by patching a single configuration.
The aim is to reduce the SPL memory footprint and simplify maintenance
of lpddr4_timing.c
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
board/toradex/verdin-imx8mp/lpddr4_timing.c | 380
board/toradex/verdin-imx8mp/lpddr4_timing.h | 11 +
board/toradex/verdin-imx8mp/spl.c | 6 +-
3 files changed, 75 insertions(+), 322 deletions(-)
create mode 100644 board/toradex/verdin-imx8mp/lpddr4_timing.h
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c
b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 4f0bbe6ce16..29ea31e1461 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -13,6 +13,33 @@
#include
#include
+#include "lpddr4_timing.h"
+
+struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
+ { 0x3d40, 0xa1080020},
+ { 0x3d400200, 0x1f},
+ { 0x3d40021c, 0xf07}
+};
+
+struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
@@ -1835,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
},
};
-struct dram_cfg_param ddr_ddrc_cfg2[] = {
- /** Initialize DDRC registers **/
- { 0x3d400304, 0x1 },
- { 0x3d400030, 0x1 },
- { 0x3d40, 0xa1080020 },
- { 0x3d400020, 0x1303 },
- { 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a017c },
- { 0x3d400070, 0x7027f90 },
- { 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc00307a3 },
- { 0x3d4000d4, 0xc5 },
- { 0x3d4000dc, 0xf4003f },
- { 0x3d4000e0, 0x33 },
- { 0x3d4000e8, 0x660048 },
- { 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x8083f },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x12040a12 },
- { 0x3d400114, 0x2050f0f },
- { 0x3d400118, 0x1010009 },
- { 0x3d40011c, 0x502 },
- { 0x3d400130, 0x20800 },
- { 0x3d400134, 0xe12 },
- { 0x3d400138, 0x184 },
- { 0x3d400144, 0xc80064 },
- { 0x3d400180, 0x3e8001e },
- { 0x3d400184, 0x3207a12 },
- { 0x3d400188, 0x0 },
- { 0x3d400190, 0x49f820e },
- { 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1f0e },
- { 0x3d4001a0, 0xe0400018 },
- { 0x3d4001a4, 0xdf00e4 },
- { 0x3d4001a8, 0x8000 },
- { 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
- { 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0x799 },
- { 0x3d400108, 0x9121b1c },
- { 0x3d400200, 0x1f },
- { 0x3d400208, 0x0 },
- { 0x3d40020c, 0x0 },
- { 0x3d400210, 0x1f1f },
- { 0x3d400204, 0x80808 },
- { 0x3d400214, 0x7070707 },
- { 0x3d400218, 0x7070707 },
- { 0x3d40021c, 0xf07 },
- { 0x3d400250, 0x1705 },
- { 0x3d400254, 0x2c },
- { 0x3d40025c, 0x430 },
- { 0x3d400264, 0x900093e7 },
- { 0x3d40026c, 0x2005574 },
- { 0x3d400400, 0x111 },
- { 0x3d400404, 0x72ff },
- { 0x3d400408, 0x72ff },
- { 0x3d400494, 0x2100e07 },
- { 0x3d400498, 0x620096 },
- { 0x3d40049c, 0x1100e07 },
- { 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1001 },
- { 0x3d402024, 0x30d400 },
- { 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc0026 },
- { 0x3d4020dc, 0x84 },
- { 0x3d4020e0, 0x33 },
- { 0x3d4020e8, 0x660048 },
- { 0x3d4020ec, 0x160048 },
- { 0x3d402100, 0xa040305 },
- { 0x3d402104, 0x30407 },
- { 0x3d402108, 0x203060b },
- { 0x3d40210c, 0x505000 },
- { 0x3d402110, 0x2040202 },
- { 0x3d402114, 0x2030202 },
- { 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x302 },
- { 0x3d402130, 0x20300 },
- { 0x3d402134, 0xa12 },
- { 0x3d402138, 0x27 },
- { 0x3d402144, 0x14000a },
- { 0x3d402180, 0x640004 },
- { 0x3d402190, 0x3818200 },
- { 0x3d402194, 0x80303 },
- { 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0x599 },
- { 0x3d403020, 0x1001 },
- { 0x3d403024, 0xc3500 },
- { 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x3000a },
- { 0x3d4030dc, 0x84 },
- { 0x3d4030e0, 0x33 },
- { 0x3d4030e8, 0x660048 },
- { 0x3d4030ec, 0x160048 },
- { 0x3d403100, 0xa010102 },
- { 0x3d403104, 0x30404 },
- { 0x3d403108, 0x203060b },
- { 0x3d40310c, 0x50
[PATCH v2 5/5] board: verdin-imx8mp: change prints in spl_dram_init function
From: Emanuele Ghidoli
change prints to show which DDR configuration (single/dual rank) is used
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Marcel Ziswiler
---
Changes in v2:
- Use puts rather than printf in the SPL as suggested by Fabio. Thanks!
board/toradex/verdin-imx8mp/spl.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/board/toradex/verdin-imx8mp/spl.c
b/board/toradex/verdin-imx8mp/spl.c
index ab5bcbc0929..73729a42b45 100644
--- a/board/toradex/verdin-imx8mp/spl.c
+++ b/board/toradex/verdin-imx8mp/spl.c
@@ -35,11 +35,17 @@ void spl_dram_init(void)
/*
* Try configuring for dual rank memory falling back to single rank
*/
- if (ddr_init(&dram_timing)) {
- printf("Dual rank failed, attempting single rank
configuration.\n");
- lpddr4_single_rank_training_patch();
- ddr_init(&dram_timing);
+ if (!ddr_init(&dram_timing)) {
+ puts("DDR configured as dual rank\n");
+ return;
}
+
+ lpddr4_single_rank_training_patch();
+ if (!ddr_init(&dram_timing)) {
+ puts("DDR configured as single rank\n");
+ return;
+ }
+ puts("DDR configuration failed\n");
}
void spl_board_init(void)
--
2.36.1
[PATCH v2 3/5] board: verdin-imx8mp: update lpddr4 configuration and training
From: Emanuele Ghidoli
Update LPDDR4 configuration and training using updated spreadsheet and
tools from NXP using data from previous spreadsheet and verified
toward datasheet:
- MX8M_Plus_LPDDR4_RPA_v9.xlsx
- mscale_ddr_tool_v3.30.exe
From:
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467
Some register values differ due to these fixes/modifications:
- corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4)
- corrected ECC related items, none of which affect normal operation
when ECC is not enabled
- corrected formula for calculation of tRTP in cell D122
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
board/toradex/verdin-imx8mp/lpddr4_timing.c | 49 +++--
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c
b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 58278d2150a..4f0bbe6ce16 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -22,8 +22,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a017c },
- { 0x3d400070, 0x61027f10 },
- { 0x3d400074, 0x7b0 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc5 },
{ 0x3d4000dc, 0xf4003f },
@@ -31,12 +31,12 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x807bf },
+ { 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe12 },
{ 0x3d400138, 0x184 },
@@ -53,9 +53,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x9121c1c },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
@@ -89,7 +90,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa12 },
{ 0x3d402138, 0x27 },
@@ -98,7 +99,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
@@ -114,7 +115,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa12 },
{ 0x3d403138, 0xa },
@@ -123,7 +124,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -1700,15 +1701,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x7d },
+ { 0x2000b, 0x465 },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0xc },
+ { 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
{ 0x12000d, 0xfa },
{ 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
+ { 0x22000b, 0x1c },
{ 0x22000c, 0x6 },
{ 0x22000d, 0x3e },
{ 0x22000e, 0x10 },
@@ -1842,8 +1843,8 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a017c },
- { 0x3d400070, 0x61027f10 },
- { 0x3d400074, 0x7b0 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc5 },
{ 0x3d4000dc, 0xf4003f },
@@ -1851,12 +1852,12 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x807bf },
+ { 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
Pull request: please pull u-boot-imx/
Hi Tom, a fix for current release, please pull from u-boot-imx, thanks ! The following changes since commit 565681e596381b5b6db59cf06931e698f2d829e5: imx6sx-udoo-neo-basic: Introduce the u-boot.dtsi (2023-03-28 10:58:16 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20230403 for you to fetch changes up to d8aba36d741c01b1e1ea60f3bbbc33ae05fa2505: configs: imx8mn_bsh_smm_s2: remove console from bootargs (2023-03-31 10:51:14 +0200) Fixes for 2023.04 -- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15831 - fix for imx8mn_bsh_smm_s2 Dario Binacchi (1): configs: imx8mn_bsh_smm_s2: remove console from bootargs include/configs/imx8mn_bsh_smm_s2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Best regards, Stefano -- = DENX Software Engineering GmbH,Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: [PATCH 2/2] pico-imx6: Pass the mmc alias to fix boot regression
Hi Tom and Stefano,
On Wed, Mar 29, 2023 at 7:25 PM wrote:
>
> > Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
> >
> > After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
> > synchronise device trees with linux"), the aliases node is gone as
> > the upstream version does not have it.
> >
> > This causes a boot regression in which the eMMC card cannot be found
> > anymore.
> >
> > Fix it by passing the alias node in the u-boot.dtsi file to
> > restore the original behaviour where the eMMC (esdhc3) was
> > mapped to mmc0.
> >
> > Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux")
> > Signed-off-by: Fabio Estevam
> Applied to u-boot-imx, next, thanks !
Since this one fixes a boot regression, could it be applied to 2023.04?
Thanks
[PATCH] arm64: interrupts: print FAR_ELx on sync exceptions
Default synchronous exceptions handler prints only esr and register
dump. Sometimes it requiers to see an address which caused exceptions
to understand what's going on
ARM ARM in section D13.2.41 states that FAR_EL2 will contain meanfull
value in case of ESR.EC holds 0x20, 0x21, 0x24, 0x25, 0x22, 0x34 or
0x35. Same applies for EL1.
This patch adds function whivh determine current EL, gets correct FAR
register and prints it on panic.
Signed-off-by: Pavel Skripkin
---
arch/arm/lib/interrupts_64.c | 38 +++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index 2e091415a4..125dc0bb39 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -37,6 +37,40 @@ static void show_efi_loaded_images(struct pt_regs *regs)
efi_print_image_infos((void *)regs->elr);
}
+static void dump_far(unsigned long esr)
+{
+ unsigned long el, far;
+
+ switch ((esr >> 26) & 0b11) {
+ case 0x20:
+ case 0x21:
+ case 0x24:
+ case 0x25:
+ case 0x22:
+ case 0x34:
+ case 0x35:
+ break;
+ default:
+ return;
+ }
+
+ asm("mrs%0, CurrentEl": "=r" (el));
+
+ switch (el >> 2) {
+ case 1:
+ asm("mrs%0, FAR_EL1": "=r" (far));
+ break;
+ case 2:
+ asm("mrs%0, FAR_EL2": "=r" (far));
+ break;
+ default:
+ /* don't print anything to make output pretty */
+ return;
+ }
+
+ printf(", far 0x%lx", far);
+}
+
static void dump_instr(struct pt_regs *regs)
{
u32 *addr = (u32 *)(regs->elr & ~3UL);
@@ -165,7 +199,9 @@ void do_sync(struct pt_regs *pt_regs)
smh_emulate_trap(pt_regs))
return;
efi_restore_gd();
- printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr);
+ printf("\"Synchronous Abort\" handler, esr 0x%08lx", pt_regs->esr);
+ dump_far(pt_regs->esr);
+ printf("\n");
show_regs(pt_regs);
show_efi_loaded_images(pt_regs);
panic("Resetting CPU ...\n");
--
2.39.2
rk3399 issue: no DMA in Linux with mainline TF-A and U-Boot SPL
Hello Kever, on a rk3399, booting current U-Boot SPL with mainline TF-A leads to missing DMA (and no sound) on Linux. However, when using rockchip its so called mini-loader (rk3399_miniloader_v1.26.bin) and their BL31 (rk3399_bl31_v1.35.elf) to boot, DMA works perfectly fine. Tested on a custom rk3399 board and on ROCK Pi4. Attached to this mail are two boot logs with some debug prints: - good_amba_log.txt (DMA works) - no_amba_log.txt (no DMA device) The main difference I can spot between the two logs is that on Linux (drivers/amba/bus.c) AMBA_CID (0xb105f00d) cannot be found. Instead, only some CORESIGHT_CIDs (presumably for debugging) and four 0x CIDs are detected. As a result, the "PL330 DMAC-241330" driver does not load. My theory is that DMA needs to be allowed somewhere in the undocumented syscon- registers, similar to what U-Boot is already doing for eMMC in arch_cpu_init() (arch/arm/mach-rockchip/rk3399/rk3399.c). Any ideas? Or maybe I'm just missing some configuration? Since multiple software projects are involved (TF-A, OP-TEE, U-Boot, Linux), I Cc'ed a bit. Thanks -- Christoph DDR Version 1.27 20211018 In soft reset SRX channel 0 CS = 0 MR0=0xB8 MR4=0x2 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0x38 MR4=0x2 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! change freq to 416MHz 0,1 Channel 0: LPDDR4,416MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: LPDDR4,416MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride channel 0 CS = 0 MR0=0xB8 MR4=0x2 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0x38 MR4=0x2 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! channel 0, cs 0, advanced training done channel 1, cs 0, advanced training done channel 0, cs 0, dq 3 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 4 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 5 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 6 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 7 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 8 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 10 RISK!!! read vref 27% no find pass-eye channel 0, cs 0, dq 11 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 12 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 13 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 14 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 15 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 16 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 17 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 18 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 19 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 20 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 21 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 23 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 24 RISK!!! read vref 27% no find pass-eye channel 0, cs 0, dq 25 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 26 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 27 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 28 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 29 RISK!!! TdiVW_total violate spec channel 0, cs 0, dq 31 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 1 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 2 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 8 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 12 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 13 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 14 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 16 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 17 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 18 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 19 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 20 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 21 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 22 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 23 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 24 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 25 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 26 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 27 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 28 RISK!!! TdiVW_total violate spec channel 1, cs 0, dq 29 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 30 RISK!!! read vref 27% no find pass-eye channel 1, cs 0, dq 31 RISK!!! TdiVW_total violate spec change freq to 856MHz 1,0 ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x3281F281, stride = 0x9 ddr_set_rate to 328MHZ ddr_set_rate to 666MHZ ddr_set_rate to 416MH
[PATCH] riscv: Correct a comment in io.h
Replace NDS32 with RISC-V in the comments. Signed-off-by: Bin Meng --- arch/riscv/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 220266e76f..b16e6dfa37 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -180,7 +180,7 @@ static inline u64 readq(const volatile void __iomem *addr) * IO port access primitives * - * - * The NDS32 doesn't have special IO access instructions just like ARM; + * The RISC-V doesn't have special IO access instructions just like ARM; * all IO is memory mapped. * Note that these are defined to perform little endian accesses * only. Their primary purpose is to access PCI and ISA peripherals. -- 2.25.1
[PATCH] boot: vbe_simple: Fix vbe_simple_read_bootflow() dependency
vbe_simple_read_bootflow() calls vbe_simple_read_bootflow_fw()
which is only available when BOOTMETH_VBE_SIMPLE_FW is on.
Signed-off-by: Bin Meng
---
boot/vbe_simple.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c
index 59676d8613..12682abd39 100644
--- a/boot/vbe_simple.c
+++ b/boot/vbe_simple.c
@@ -148,11 +148,13 @@ static int vbe_simple_read_bootflow(struct udevice *dev,
struct bootflow *bflow)
{
int ret;
- if (vbe_phase() == VBE_PHASE_FIRMWARE) {
- ret = vbe_simple_read_bootflow_fw(dev, bflow);
- if (ret)
- return log_msg_ret("fw", ret);
- return 0;
+ if (CONFIG_IS_ENABLED(BOOTMETH_VBE_SIMPLE_FW)) {
+ if (vbe_phase() == VBE_PHASE_FIRMWARE) {
+ ret = vbe_simple_read_bootflow_fw(dev, bflow);
+ if (ret)
+ return log_msg_ret("fw", ret);
+ return 0;
+ }
}
return -EINVAL;
--
2.25.1
Re: [PATCH v2 0/5] enable DMA and CPSW nodes for am62ax SoC family
Bryan, On 03/04/23 3:06 am, Bryan Brattlof wrote: > Hello again everyone! > > This patch series syncs TI's am62ax device tree files with what has been > merged in the v6.3-rc4 of the Linux Kernel. This series will also enable > YMODEM support to make automated testing (which uses the UART boot > method to load the bootloaders) > > Thanks for reviewing > ~Bryan > > Changed from v1: [0] > > o Rebased on top of -next branch > o dropped 'u-boot,dm-spl' for the new 'bootph-pre-ram' properties > > [0] https://lore.kernel.org/u-boot/20230327184035.2128786-1...@ti.com/ > > Bryan Brattlof (4): > arm: dts: sync am62ax dtbs with linux v6.3-rc4 > arm: dts: add DMA and CPSW nodes for uboot > configs: enable net features for am62ax > configs: am62ax: enable ymodem support for a53 spl > > Vignesh Raghavendra (1): > dma: ti: k3-udma: Introduce DMA support for the am62ax > > arch/arm/dts/k3-am62a-main.dtsi | 365 ++ > arch/arm/dts/k3-am62a-mcu.dtsi| 51 > arch/arm/dts/k3-am62a-wakeup.dtsi | 2 +- > arch/arm/dts/k3-am62a7-r5-sk.dts | 8 + > arch/arm/dts/k3-am62a7-sk-u-boot.dtsi | 26 +- > arch/arm/dts/k3-am62a7-sk.dts | 70 + > arch/arm/dts/k3-am62a7.dtsi | 1 + > configs/am62ax_evm_a53_defconfig | 7 +- > drivers/dma/ti/Makefile | 1 + > drivers/dma/ti/k3-psil-am62a.c| 196 ++ > drivers/dma/ti/k3-psil-priv.h | 1 + > drivers/dma/ti/k3-psil.c | 2 + > 12 files changed, 727 insertions(+), 3 deletions(-) > create mode 100644 drivers/dma/ti/k3-psil-am62a.c > > > base-commit: 942ac73afc37fb98695af4489ea1549c21615a5e Acked-by: Ravi Gunasekaran -- Regards, Ravi
Binman for RK35xx
Hi! Trying to build mainline U-Boot for Rockchip RK3568-based board (Forlinx RK3568), but I think it;s can be reproduced on all RK35 chips. The main problem is that BL32 (AKA OP-TEE) is provided by Roch-Chips as a pre-compiled blob and binman fails to implement that scenario. Used .dtsi file and binman verbose output provided in attachments. Do am I done something wrong or it can be considered as bug? Can someone assist? Thanks in advance Igor /home/gosha/u-boot/tools/binman/binman -D --toolpath ./tools -v5 build -u -d u-boot.dtb -O . -m -I . -I /home/gosha/u-boot -I /home/gosha/u-boot/board/forlinx/ok3568-c -I arch/arm/dts -a of-list="rk3568-ok3568-c" -a atf-bl31-path=/home/gosha/ff3588/rk3588/rkbin/bin/rk35/rk3568_bl31_v1.36.elf -a tee-os-path= -a opensbi-path= -a default-dt="rk3568-ok3568-c" -a scp-path= -a rockchip-tpl-path=/home/gosha/ff3588/rk3588/rkbin/bin/rk35/rk3568_ddr_1560MHz_v1.15.bin -a spl-bss-pad= -a tpl-bss-pad=1 -a spl-dtb=y -a tpl-dtb= -a pre-load-key-path= Using input directories ['.', '/home/gosha/u-boot', '/home/gosha/u-boot/board/forlinx/ok3568-c', 'arch/arm/dts'] Using output directory '.' Processing entry args: of-list = rk3568-ok3568-c atf-bl31-path = /home/gosha/ff3588/rk3588/rkbin/bin/rk35/rk3568_bl31_v1.36.elf tee-os-path = opensbi-path = default-dt = rk3568-ok3568-c scp-path = rockchip-tpl-path = /home/gosha/ff3588/rk3588/rkbin/bin/rk35/rk3568_ddr_1560MHz_v1.15.bin spl-bss-pad = tpl-bss-pad = 1 spl-dtb = y tpl-dtb = pre-load-key-path = Processing entry args done bintool: mkimage -d /home/gosha/ff3588/rk3588/rkbin/bin/rk35/rk3568_ddr_1560MHz_v1.15.bin:./spl/u-boot-spl.bin -n rk3568 -T rksd ./idbloader.img Image Type: Rockchip RK35 boot image Init Data Size: 59392 bytes Boot Data Size: 104448 bytes Node '/binman/simple-bin/mkimage': Packing: offset=None, size=None, content_size=28800 Node '/binman/simple-bin/mkimage':- packed: offset=0x0, size=0x28800, content_size=0x28800, next_offset=28800 Node '/binman/simple-bin/fit/images/u-boot/u-boot-nodtb': Packing: offset=None, size=None, content_size=a1e00 Node '/binman/simple-bin/fit/images/u-boot/u-boot-nodtb':- packed: offset=0x0, size=0xa1e00, content_size=0xa1e00, next_offset=a1e00 Node '/binman/simple-bin/fit/images/u-boot/u-boot-nodtb': GetData: size 0xa1e00 Node '/binman/simple-bin/fit/images/u-boot': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/u-boot': GetData: 1 entries, total size 0xa1e00 Node '/binman/simple-bin/fit': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/u-boot': Packing: offset=None, size=0xa1e00, content_size=a1e00 Node '/binman/simple-bin/fit/images/u-boot':- packed: offset=0x0, size=0xa1e00, content_size=0xa1e00, next_offset=a1e00 Node '/binman/simple-bin/fit/images/@atf-SEQ/atf-bl31': Packing: offset=None, size=None, content_size=623c8 Node '/binman/simple-bin/fit/images/@atf-SEQ/atf-bl31':- packed: offset=0x0, size=0x623c8, content_size=0x623c8, next_offset=623c8 Node '/binman/simple-bin/fit/images/@atf-SEQ/atf-bl31': GetData: size 0x623c8 Node '/binman/simple-bin/fit/images/@atf-SEQ': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/@atf-SEQ': GetData: 1 entries, total size 0x623c8 Node '/binman/simple-bin/fit': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/@atf-SEQ': Packing: offset=None, size=0x623c8, content_size=623c8 Node '/binman/simple-bin/fit/images/@atf-SEQ':- packed: offset=0xa1e00, size=0x623c8, content_size=0x623c8, next_offset=1041c8 Node '/binman/simple-bin/fit/images/optee/blob-ext': Packing: offset=None, size=None, content_size=6f998 Node '/binman/simple-bin/fit/images/optee/blob-ext':- packed: offset=0x0, size=0x6f998, content_size=0x6f998, next_offset=6f998 Node '/binman/simple-bin/fit/images/optee/blob-ext': GetData: size 0x6f998 Node '/binman/simple-bin/fit/images/optee': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/optee': GetData: 1 entries, total size 0x6f998 Node '/binman/simple-bin/fit': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/optee': Packing: offset=None, size=0x6f998, content_size=6f998 Node '/binman/simple-bin/fit/images/optee':- packed: offset=0x1041c8, size=0x6f998, content_size=0x6f998, next_offset=173b60 Node '/binman/simple-bin/fit/images/@fdt-SEQ': GetData: 0 entries, total size 0x0 Node '/binman/simple-bin/fit': GetPaddedDataForEntry: size None Node '/binman/simple-bin/fit/images/@fdt-SEQ': Packing: offset=None, size=0x0, content_size=0 Node '/binman/simple-bin/fit/images/@fdt-SEQ':- packed: offset=0x173b60, size=0x0, content_size=0x0, next_offset=173b60 Node '/binman/simple-bin/fit/images/u-boot/u-boot-nodtb': GetData: size 0xa1e00 Node '/binman/simple-bin/fit/images/u-boot': GetPaddedDataForEntry: size 0xa1e00
Re: rk3399 issue: no DMA in Linux with mainline TF-A and U-Boot SPL
On Mon, Apr 03, 2023 at 12:11:40PM +0200, Christoph Fritz wrote: > > > > The ARM PL330 DMA driver in kernel only relate to: > > > > - DTS kernel used, can be check in /proc/device-tree/ > > > > - kernel driver which should mach the compatible name. > > drivers/dma/pl330.c needs also a successfully matched amba, but this > fails when using mainline TF-A and U-Boot SPL. > > I'm using the same kernel and devicetree on both tests, the only thing > changed is TF-A and U-Boot SPL vs mini-loader and rk3399_bl31. > > > This driver should has nothing to do with U-Boot SPL or TF-A, because we > > don't have any special setting for PL330 in loader stage. > > It is drivers/amba/bus.c, which is unable to find an AMBA_CID on the > ARM bus. The DMA driver not loading is just a symptom of this issue. That brings up the obvious question: why is it unable to find the AMBA CID? Is that because some resource needed to read it hasn't been enabled yet? If the AMBA CID is not accessible, presumably the rest of the PL330 also isn't accessible, so even if we could bind the driver, it still wouldn't work? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Re: Binman for RK35xx
> From: > Date: Mon, 3 Apr 2023 12:27:36 +0300 > > Hi! > >Trying to build mainline U-Boot for Rockchip RK3568-based board (Forlinx > RK3568), but I think it;s can be reproduced on all RK35 chips. The main > problem is that BL32 (AKA OP-TEE) is provided by Roch-Chips as a > pre-compiled blob and binman fails to implement that scenario. Used .dtsi > file and binman verbose output provided in attachments. Do am I done > something wrong or it can be considered as bug? Can someone assist? What do you need OP_TEE for? Many of us consider less blobs a good thing and simply live without OP-TEE. Cheers, Mark
Re: Binman for RK35xx
On Mon, Apr 3, 2023 at 2:30 PM Mark Kettenis wrote: > > > From: > > Date: Mon, 3 Apr 2023 12:27:36 +0300 > > > > Hi! > > > >Trying to build mainline U-Boot for Rockchip RK3568-based board (Forlinx > > RK3568), but I think it;s can be reproduced on all RK35 chips. The main > > problem is that BL32 (AKA OP-TEE) is provided by Roch-Chips as a > > pre-compiled blob and binman fails to implement that scenario. Used .dtsi > > file and binman verbose output provided in attachments. Do am I done > > something wrong or it can be considered as bug? Can someone assist? > > What do you need OP_TEE for? Many of us consider less blobs a good > thing and simply live without OP-TEE. I think it's a moot point, OP_TEE is useful for a number of things, and it should be an option for those that wish to use it.
[PATCH 1/2] firmware: zynqmp: Mask expected and show unexpected warning
From: Stefan Herbrechtsmeier
Mask the expected and show the unexpected warning "No permission to
change config object" for NODE_OCM_BANK_0 because this node is used to
detect if further zynqmp_pmufw_node function calls should be skipped.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/firmware/firmware-zynqmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index dc8e3ad2b9..8435b58ef9 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -251,7 +251,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj,
size_t size)
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
- if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) {
+ if (((u32 *)cfg_obj)[NODE_ID_LOCATION] != NODE_OCM_BANK_0) {
printf("PMUFW: No permission to change config
object\n");
return err;
}
--
2.30.2
Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
Geschäftsführer: Dr. Timo Berger, Volker Bibelhausen, Dr. Sebastian Durst,
André Sombecki;
USt-ID-Nr. DE124599660
[PATCH 2/2] firmware: zynqmp: Remove extraordinary return value
From: Stefan Herbrechtsmeier
Return a common -EACCES error value instead of a positive private error
value XST_PM_NO_ACCESS (2002) in zynqmp_pmufw_load_config_object
function if the config object is not loadable to simplify the error
checking.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/firmware/firmware-zynqmp.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index 8435b58ef9..399958eea3 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -82,7 +82,7 @@ int zynqmp_pmufw_node(u32 id)
ret = zynqmp_pmufw_load_config_object(xpm_configobject,
sizeof(xpm_configobject));
- if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
+ if (ret == -EACCES && id == NODE_OCM_BANK_0)
skip_config = true;
return 0;
@@ -235,8 +235,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const
u32 id)
*
* @cfg_obj: Pointer to the configuration object
* @size:Size of @cfg_obj in bytes
- * Return: 0 on success otherwise negative errno. If the config object
- * is not loadable returns positive errno XST_PM_NO_ACCESS(2002)
+ * Return: 0 on success otherwise negative errno.
*/
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
{
@@ -251,10 +250,8 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj,
size_t size)
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
- if (((u32 *)cfg_obj)[NODE_ID_LOCATION] != NODE_OCM_BANK_0) {
+ if (((u32 *)cfg_obj)[NODE_ID_LOCATION] != NODE_OCM_BANK_0)
printf("PMUFW: No permission to change config
object\n");
- return err;
- }
return -EACCES;
}
--
2.30.2
Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
Geschäftsführer: Dr. Timo Berger, Volker Bibelhausen, Dr. Sebastian Durst,
André Sombecki;
USt-ID-Nr. DE124599660
[PATCH v2 1/2] common: cli_hush: Restore clear local variable support
From: Stefan Herbrechtsmeier
The u-boot hush shell doesn’t support the unset command to clear a
variable and therefore an empty value ("c=") should be a valid value
for the set_local_var function to clear the variable. This partial
reverts commit aa722529635c ("common: cli_hush: avoid dead code") and
only checks for a `=` in the string. Additionally explicit call the
unset_local_var function to remove the variable if the value is empty.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2:
- Use `!var` instead of `var == NULL`
common/cli_hush.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 1ad7a509df..171069f5f4 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -2171,12 +2171,18 @@ int set_local_var(const char *s, int flg_export)
* NAME=VALUE format. So the first order of business is to
* split 's' on the '=' into 'name' and 'value' */
value = strchr(name, '=');
- if (value == NULL || *(value + 1) == 0) {
+ if (!value) {
free(name);
return -1;
}
*value++ = 0;
+ if (!*value) {
+ unset_local_var(name);
+ free(name);
+ return 0;
+ }
+
for(cur = top_vars; cur; cur = cur->next) {
if(strcmp(cur->name, name)==0)
break;
--
2.30.2
Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
Geschäftsführer: Dr. Timo Berger, Volker Bibelhausen, Dr. Sebastian Durst,
André Sombecki;
USt-ID-Nr. DE124599660
[PATCH v2 2/2] test: hush_if_test: Add hush variable test
From: Stefan Herbrechtsmeier
Add a test for the hush shell variable assignment and clear.
Signed-off-by: Stefan Herbrechtsmeier
---
(no changes since v1)
test/py/tests/test_hush_if_test.py | 13 +
1 file changed, 13 insertions(+)
diff --git a/test/py/tests/test_hush_if_test.py
b/test/py/tests/test_hush_if_test.py
index 37c1608bb2..3b4b6fcaf4 100644
--- a/test/py/tests/test_hush_if_test.py
+++ b/test/py/tests/test_hush_if_test.py
@@ -182,3 +182,16 @@ def test_hush_if_test_host_file_exists(u_boot_console):
expr = 'test -e hostfs - ' + test_file
exec_hush_if(u_boot_console, expr, False)
+
+def test_hush_var(u_boot_console):
+"""Test the set and unset of variables"""
+u_boot_console.run_command('ut_var_nonexistent=')
+u_boot_console.run_command('ut_var_exists=1')
+u_boot_console.run_command('ut_var_unset=1')
+exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True)
+exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False)
+exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', False)
+exec_hush_if(u_boot_console, 'ut_var_unset=', True)
+exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', True)
+u_boot_console.run_command('ut_var_exists=')
+u_boot_console.run_command('ut_var_unset=')
--
2.30.2
Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
Geschäftsführer: Dr. Timo Berger, Volker Bibelhausen, Dr. Sebastian Durst,
André Sombecki;
USt-ID-Nr. DE124599660
Re: rk3399 issue: no DMA in Linux with mainline TF-A and U-Boot SPL
On Mon, 2023-04-03 at 14:17 +0100, Russell King (Oracle) wrote: > On Mon, Apr 03, 2023 at 12:11:40PM +0200, Christoph Fritz wrote: > > > > > > The ARM PL330 DMA driver in kernel only relate to: > > > > > > - DTS kernel used, can be check in /proc/device-tree/ > > > > > > - kernel driver which should mach the compatible name. > > > > drivers/dma/pl330.c needs also a successfully matched amba, but this > > fails when using mainline TF-A and U-Boot SPL. > > > > I'm using the same kernel and devicetree on both tests, the only thing > > changed is TF-A and U-Boot SPL vs mini-loader and rk3399_bl31. > > > > > This driver should has nothing to do with U-Boot SPL or TF-A, because we > > > don't have any special setting for PL330 in loader stage. > > > > It is drivers/amba/bus.c, which is unable to find an AMBA_CID on the > > ARM bus. The DMA driver not loading is just a symptom of this issue. > > That brings up the obvious question: why is it unable to find the AMBA > CID? Is that because some resource needed to read it hasn't been > enabled yet? That's my guess too, and that's why I'm asking Kever from Rockchip. To me, it seems that their closed-source BL31 and/or mini-loader is enabling something that is missing in upstream TF-A and/or U-Boot SPL. On top of that, the registers responsible for that are undocumented. But I could be wrong, and it's possible that I'm missing something else. Maybe dumping the syscon-registers and comparing them might help, but as far as I can see, it's a bit of an effort because they require special treatment to be accessed. > If the AMBA CID is not accessible, presumably the rest of > the PL330 also isn't accessible, so even if we could bind the driver, > it still wouldn't work? The PL330 driver attempted to probe, but was deferred due to a missing AMBA_CID. It's in the bootlog that I attached in my first email in this thread. Thanks -- Christoph
Re: Binman for RK35xx
On 2023-04-03 15:33, Peter Robinson wrote: > On Mon, Apr 3, 2023 at 2:30 PM Mark Kettenis wrote: >> >>> From: >>> Date: Mon, 3 Apr 2023 12:27:36 +0300 >>> >>> Hi! >>> >>>Trying to build mainline U-Boot for Rockchip RK3568-based board (Forlinx >>> RK3568), but I think it;s can be reproduced on all RK35 chips. The main >>> problem is that BL32 (AKA OP-TEE) is provided by Roch-Chips as a >>> pre-compiled blob and binman fails to implement that scenario. Used .dtsi >>> file and binman verbose output provided in attachments. Do am I done >>> something wrong or it can be considered as bug? Can someone assist? >> >> What do you need OP_TEE for? Many of us consider less blobs a good >> thing and simply live without OP-TEE. > > I think it's a moot point, OP_TEE is useful for a number of things, > and it should be an option for those that wish to use it. Your issue seem to be that your optee node is placed after the dynamic @atf-SEQ node, try place the optee node before the @atf-SEQ node. Trying to use the common rockchip-u-boot.dtsi and TEE env var result in the following: binman: Node '/binman/simple-bin/fit': subnode 'images/@tee-SEQ': Failed to read ELF file: Magic number does not match And I assume you are using a custom binman node because of such error? Adding support for the rockchip bl31.bin blob format to binman and use the common rockchip-u-boot.dtsi would be the proper way to fix this. Regards, Jonas
Re: [PATCH v2 0/5] board: verdin-imx8mp: ddr updates
Hi Marcel, On Mon, Apr 3, 2023 at 9:02 AM Marcel Ziswiler wrote: > > From: Marcel Ziswiler > > > This series contains the following DDR updates: > > - update ddrc config for different lpddr4 memories > - fix lpddr4 refresh timing > - update lpddr4 configuration and training > - compact slight different lpddr4 configuration > - change prints in spl_dram_init function > > Changes in v2: > - Use puts rather than printf in the SPL as suggested by Fabio. Thanks! For the whole series: Reviewed-by: Fabio Estevam
Re: [PATCH v5 3/8] bootstd: Support booting EFI where multiple options exist
On Mon, Apr 03, 2023 at 12:56:49PM +0300, Ilias Apalodimas wrote: > On Sat, Apr 01, 2023 at 07:31:49PM +1300, Simon Glass wrote: > > Hi Tom, > > > > On Sat, 1 Apr 2023 at 07:02, Tom Rini wrote: > > > > > > On Fri, Mar 31, 2023 at 10:25:56AM +1300, Simon Glass wrote: > > > > > > > The current EFI implementation has a strange quirk where it watches > > > > loaded files and uses the last-loaded file to determine the device that > > > > is being booted from. > > > > > > > > This is confusing with bootstd, where multiple options may exist. Even > > > > loading a device tree will cause it to go wrong. There is no API for > > > > passing this information, since the only entry into booting an EFI image > > > > is the 'bootefi' command. > > > > > > > > To work around this, call efi_set_bootdev() for EFI images, if possible, > > > > just before booting. > > > > > > > > Signed-off-by: Simon Glass > > > > > > Shouldn't this all be a simple wrapper around the EFI Standard > > > BootDeviceOrder or whatever that's called? > > > > I think you are referring to boot manager, which isn't used here. This > > is replicating the existing distroboot functionality in standard boot. > > The distroboot functionality *was* trying to behave like the EFI spec > expects the bootmanager to behave. Unfortunately I haven't had time to > review the distroboot patches closely, but back when this started, my point > was that EFI doesn't need anything. Whenever the EFI flow is added bootstd > should 'just' call the bootmanager. Yes, this. We're trying make things cleaner overall, so the EFI portion of bootstd distro boot should just be "call EFI bootmanager" as that has a well defined standard way to specify what devices to try in what order. -- Tom signature.asc Description: PGP signature
Re: Pull request: please pull u-boot-imx/
On Mon, Apr 03, 2023 at 02:12:51PM +0200, Stefano Babic wrote: > Hi Tom, > > a fix for current release, please pull from u-boot-imx, thanks ! > > > The following changes since commit 565681e596381b5b6db59cf06931e698f2d829e5: > > imx6sx-udoo-neo-basic: Introduce the u-boot.dtsi (2023-03-28 10:58:16 > -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git > tags/u-boot-imx-20230403 > > for you to fetch changes up to d8aba36d741c01b1e1ea60f3bbbc33ae05fa2505: > > configs: imx8mn_bsh_smm_s2: remove console from bootargs (2023-03-31 > 10:51:14 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] pico-imx6: Pass the mmc alias to fix boot regression
On Mon, Apr 03, 2023 at 09:25:11AM -0300, Fabio Estevam wrote:
> Hi Tom and Stefano,
>
> On Wed, Mar 29, 2023 at 7:25 PM wrote:
> >
> > > Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
> > >
> > > After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
> > > synchronise device trees with linux"), the aliases node is gone as
> > > the upstream version does not have it.
> > >
> > > This causes a boot regression in which the eMMC card cannot be found
> > > anymore.
> > >
> > > Fix it by passing the alias node in the u-boot.dtsi file to
> > > restore the original behaviour where the eMMC (esdhc3) was
> > > mapped to mmc0.
> > >
> > > Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with
> > > linux")
> > > Signed-off-by: Fabio Estevam
> > Applied to u-boot-imx, next, thanks !
>
> Since this one fixes a boot regression, could it be applied to 2023.04?
I have cherry-picked this to master.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v5 8/8] bootstd: Enable BOOTSTD_DEFAULTS by default
On Sat, Apr 01, 2023 at 07:31:56PM +1300, Simon Glass wrote: > Hi Tom, > > On Sat, 1 Apr 2023 at 07:00, Tom Rini wrote: > > > > On Fri, Mar 31, 2023 at 10:26:01AM +1300, Simon Glass wrote: > > > > > This is needed to enable the boot command used to start standard boot. > > > Enable it by default. This brings in quite a few features, mostly in > > > common with DISTRO_DEFAULTS > > > > > > Exclude boards which have what looks like a custom boot command: > > > > > >git grep CONFIG_BOOTCOM configs/* |grep -v distro_bootcmd | > > >sed -n 's/configs\/\(.*\)_defconfig.*/\1/p' > > > > > > Disable this option for boards which don't have enough space. > > > > > > Disable CONFIG_ENV_VARS_UBOOT_CONFIG for some Xilinx boards which have > > > a very small environment. Disable BOOTSTD_DEFAULTS for smartweb since > > > it is too close to its limit. > > > > > > Signed-off-by: Simon Glass > > > > I wasn't clear, sorry. What I want to see first is a standalone patch > > that disables BOOTSTD on platforms that have their own custom bootcmd, > > that is not just a more complex wrapper around distro_bootcmd (those > > platforms will require more work to convert, but won't be impacted by > > BOOTSTD_DEFAULTS being default). It needs to be on its own so it can be > > reviewed. Thanks. > > Oh OK, I was wondering how it could be standard if it was just "standard" as in default/regular, not "standard" as in rigidly defined by external specification. > disabling BOOTSTD_DEFAULTS... I will give it a crack. I wonder if this > is the same set which doesn't enable DISTRO_DEFAULTS? The ones which do things around "run distro_bootcmd" ? No, probably not. But the ones which have unexplained large size growth? Likely yes. -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 1/3] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
On 2023-04-03 13:28, Eugen Hristev wrote:
> On 4/2/23 14:00, Jonas Karlman wrote:
>> Hi Eugen,
>>
>> On 2023-03-31 11:40, Eugen Hristev wrote:
>>> Add USB 2.0 host nodes and PHYs.
>>>
>>> Co-developed-by: William Wu
>>> Signed-off-by: William Wu
>>> Signed-off-by: Eugen Hristev
>>> ---
>>> Changes in v2,v3:
>>> - none
>>>
>>> arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169
>>> 1 file changed, 169 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>>> b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>>> index 2386edf90deb..e1d240baf35d 100644
>>> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>>> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>>> @@ -4,6 +4,9 @@
>>>*/
>>>
>>> #include "rk3588-u-boot.dtsi"
>>> +#include
>>> +#include
>>> +#include
>>>
>>> / {
>>> aliases {
>>> @@ -13,6 +16,105 @@
>>> chosen {
>>> u-boot,spl-boot-order = &sdmmc;
>>> };
>>> +
>>> + vcc5v0_host: vcc5v0-host-regulator {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "vcc5v0_host";
>>> + regulator-min-microvolt = <500>;
>>> + regulator-max-microvolt = <500>;
>>> + enable-active-high;
>>> + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&vcc5v0_host_en>;
>>> + vin-supply = <&vcc5v0_sys>;
>>> + };
>>> +
>>> + usb_host0_ehci: usb@fc80 {
>>> + compatible = "generic-ehci";
>>> + reg = <0x0 0xfc80 0x0 0x4>;
>>> + interrupts = ;
>>> + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
>>> + clock-names = "usbhost", "arbiter";
>>> + power-domains = <&power RK3588_PD_USB>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + usb_host0_ohci: usb@fc84 {
>>> + compatible = "generic-ohci";
>>> + reg = <0x0 0xfc84 0x0 0x4>;
>>> + interrupts = ;
>>> + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
>>> + clock-names = "usbhost", "arbiter";
>>> + power-domains = <&power RK3588_PD_USB>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + usb_host1_ehci: usb@fc88 {
>>> + compatible = "generic-ehci";
>>> + reg = <0x0 0xfc88 0x0 0x4>;
>>> + interrupts = ;
>>> + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
>>> + clock-names = "usbhost", "arbiter";
>>> + power-domains = <&power RK3588_PD_USB>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + usb_host1_ohci: usb@fc8c {
>>> + compatible = "generic-ohci";
>>> + reg = <0x0 0xfc8c 0x0 0x4>;
>>> + interrupts = ;
>>> + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
>>> + clock-names = "usbhost", "arbiter";
>>> + power-domains = <&power RK3588_PD_USB>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + usb2phy2_grf: syscon@fd5d8000 {
>>> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>>> +"simple-mfd";
>>> + reg = <0x0 0xfd5d8000 0x0 0x4000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + u2phy2: usb2-phy@8000 {
>>> + compatible = "rockchip,rk3588-usb2phy";
>>> + reg = <0x8000 0x10>;
>>> + interrupts = ;
>>> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
>>> + clock-names = "phyclk";
>>> + #clock-cells = <0>;
>>> + status = "disabled";
>>> +
>>> + u2phy2_host: host-port {
>>> + #phy-cells = <0>;
>>> + status = "disabled";
>>> + };
>>> + };
>>> + };
>>> +
>>> + usb2phy3_grf: syscon@fd5dc000 {
>>> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>>> +"simple-mfd";
>>> + reg = <0x0 0xfd5dc000 0x0 0x4000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + u2phy3: usb2-phy@c000 {
>>> + compatible = "rockchip,rk3588-usb2phy";
>>> + reg = <0xc000 0x10>;
>>> + interrupts = ;
>>> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
>>> + clock-names = "phyclk";
>>> + #clock-cells = <0>;
>>> + status = "disabled";
>>> +
>>> + u2phy3_host: host-port {
>>> + #phy-cells = <0>;
>>> + status = "disabled";
>>> + };
>>> + };
>>> + };
>>
>> Most of these nodes could be added to the soc u-boot dtsi and not the
>> board specific file. Also wondering if some of the reset and cloc
Re: [PATCH v2] disk: Use a helper function to reduce duplication
On Mon, Apr 03, 2023 at 09:06:13AM +0900, AKASHI Takahiro wrote: > Hi Tom, > > On Fri, Mar 31, 2023 at 10:17:03AM -0400, Tom Rini wrote: > > On Mon, Mar 20, 2023 at 08:29:57AM +1300, Simon Glass wrote: > > > > > Reduce the duplicated code slightly by using a helper function to handle > > > the common code. > > > > > > This reduces the code size very slightly. > > > > > > Signed-off-by: Simon Glass > > > > Applied to u-boot/next, thanks! > > I think I said nak against this patch. > https://lists.denx.de/pipermail/u-boot/2023-March/512677.html Ah I missed that, sorry, reverting. -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 3/8] bootstd: Support booting EFI where multiple options exist
Am 3. April 2023 16:17:42 MESZ schrieb Tom Rini : >On Mon, Apr 03, 2023 at 12:56:49PM +0300, Ilias Apalodimas wrote: >> On Sat, Apr 01, 2023 at 07:31:49PM +1300, Simon Glass wrote: >> > Hi Tom, >> > >> > On Sat, 1 Apr 2023 at 07:02, Tom Rini wrote: >> > > >> > > On Fri, Mar 31, 2023 at 10:25:56AM +1300, Simon Glass wrote: >> > > >> > > > The current EFI implementation has a strange quirk where it watches >> > > > loaded files and uses the last-loaded file to determine the device that >> > > > is being booted from. >> > > > >> > > > This is confusing with bootstd, where multiple options may exist. Even >> > > > loading a device tree will cause it to go wrong. There is no API for >> > > > passing this information, since the only entry into booting an EFI >> > > > image >> > > > is the 'bootefi' command. >> > > > >> > > > To work around this, call efi_set_bootdev() for EFI images, if >> > > > possible, >> > > > just before booting. >> > > > >> > > > Signed-off-by: Simon Glass >> > > >> > > Shouldn't this all be a simple wrapper around the EFI Standard >> > > BootDeviceOrder or whatever that's called? >> > >> > I think you are referring to boot manager, which isn't used here. This >> > is replicating the existing distroboot functionality in standard boot. >> >> The distroboot functionality *was* trying to behave like the EFI spec >> expects the bootmanager to behave. Unfortunately I haven't had time to >> review the distroboot patches closely, but back when this started, my point >> was that EFI doesn't need anything. Whenever the EFI flow is added bootstd >> should 'just' call the bootmanager. Distroboot used to load the devicetree from a default location too. This makes good sense on many boards but poses a problem for secure boot. @Ilias, we need to evaluate this. Regards Heinrich > >Yes, this. We're trying make things cleaner overall, so the EFI portion >of bootstd distro boot should just be "call EFI bootmanager" as that has >a well defined standard way to specify what devices to try in what >order. >
Re: [PATCH v2 1/3] cmd: pci: Add command to set MPS of all PCIe devices
Thank you Tom! Stephen Carlson -Original Message- From: Tom Rini Sent: Friday, March 31, 2023 7:17 AM To: stcar...@linux.microsoft.com Cc: u-boot@lists.denx.de Subject: [EXTERNAL] Re: [PATCH v2 1/3] cmd: pci: Add command to set MPS of all PCIe devices On Fri, Mar 10, 2023 at 11:07:13AM -0800, stcar...@linux.microsoft.com wrote: From: Stephen Carlson Enable tuning of the PCI Express MPS (Maximum Payload Size) of each device. The Maximum Read Request Size is not altered. The SAFE method uses the largest MPS value supported by all devices in the system for each device. This method is the same algorithm as used by Linux pci=pcie_bus_safe. The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which allows hot plug of devices later that might only support the minimum size, and ensures compatibility of DMA between two devices on the bus. Signed-off-by: Stephen Carlson Applied to u-boot/next, thanks! -- Tom
[PATCH] arm: dts: k3-j721e-sk-u-boot: fix boot on j721e SK
From: Sinthu Raja
J721e SK has been broken since at least March 2022.
The main-navss and mcu-navss nodes were renamed and this caused the
A72 SPL to fail early in the boot even before the serial port was
enabled. Fix this.
A later patch series between v2022.07 and v2022.10 additionally broke
boot on this board by introducing hbmc nodes which are not present on
this board. The right fix is to disable these by default in the SOC
dtsi file, but for now we can also disable them in the u-boot dtsi.
With both these fixed, we can now boot the j721e SK board fully from
mainline u-boot.
Fixes: 58d61fb5a77ef ("arm: dts: k3-j721e-sk: Add initial A72 specific dts
support")
Fixes: 297daac43afb9 ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller
node")
Reported-by: Anand Gadiyar
Signed-off-by: Sinthu Raja
[gadi...@ti.com: update commit description]
Signed-off-by: Anand Gadiyar
Cc: Bryan Brattlof
---
Hi Tom, we'd really love to see this make it to 2023.04 - Bryan and I
spent a whole week narrowing it down, and this gets the board working
again. Thanks!
- Anand and Bryan and Sinthu
arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 2d65e2db42..f529e7032a 100644
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -33,7 +33,7 @@
&cbass_main{
u-boot,dm-spl;
- main_navss {
+ main_navss: bus@3000 {
u-boot,dm-spl;
};
};
@@ -49,7 +49,7 @@
u-boot,dm-spl;
};
- mcu-navss {
+ mcu_navss: bus@2838 {
u-boot,dm-spl;
ringacc@2b80 {
@@ -237,6 +237,10 @@
u-boot,dm-spl;
};
+&hbmc {
+ status = "disabled";
+};
+
&ospi0 {
u-boot,dm-spl;
--
2.34.1
[PATCH 1/1] test: move unit tests into a sub-menu
The main configuration menu should not contain detail settings. Signed-off-by: Heinrich Schuchardt --- test/Kconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/test/Kconfig b/test/Kconfig index 465028265b..6e859fb7d0 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -3,7 +3,9 @@ config POST help See doc/README.POST for more details -menuconfig UNIT_TEST +menu "Unit tests" + +config UNIT_TEST bool "Unit tests" help Select this to compile in unit tests for various parts of @@ -107,3 +109,5 @@ source "test/env/Kconfig" source "test/lib/Kconfig" source "test/optee/Kconfig" source "test/overlay/Kconfig" + +endmenu -- 2.39.2
[PATCH 1/1] common: static fdt_simplefb_enable_existing_node()
Function fdt_simplefb_enable_existing_node() should be static as it is not
used outside common/fdt_simplefb.c.
Signed-off-by: Heinrich Schuchardt
---
common/fdt_simplefb.c | 8 +++-
include/fdt_simplefb.h | 1 -
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c
index 282c34fe0b..069ced75a7 100644
--- a/common/fdt_simplefb.c
+++ b/common/fdt_simplefb.c
@@ -71,7 +71,13 @@ int fdt_simplefb_add_node(void *blob)
return fdt_simplefb_configure_node(blob, off);
}
-int fdt_simplefb_enable_existing_node(void *blob)
+/**
+ * fdt_simplefb_enable_existing_node() - enable simple-framebuffer DT node
+ *
+ * @blob: device-tree
+ * Return: 0 on success, non-zero otherwise
+ */
+static int fdt_simplefb_enable_existing_node(void *blob)
{
int off;
diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h
index 41cd740ac0..af93e3be63 100644
--- a/include/fdt_simplefb.h
+++ b/include/fdt_simplefb.h
@@ -9,6 +9,5 @@
#ifndef _FDT_SIMPLEFB_H_
#define _FDT_SIMPLEFB_H_
int fdt_simplefb_add_node(void *blob);
-int fdt_simplefb_enable_existing_node(void *blob);
int fdt_simplefb_enable_and_mem_rsv(void *blob);
#endif
--
2.39.2
[PATCH 0/2] Add support for Qualcomm QUSB2 USB PHY driver
Enable support for HighSpeed QUSB2 PHY transceiver for USB controllers on Qualcomm chips. This patchset adds driver support for the high-speed PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on Qualcomm Snapdragon SOCs like SM6115 and SDM845. Bhupesh Sharma (2): dt-bindings: phy: Import phy-qcom-qusb2.h phy: Add Qualcomm QUSB2 USB PHY driver drivers/phy/qcom/Kconfig | 7 + drivers/phy/qcom/Makefile| 1 + drivers/phy/qcom/phy-qcom-qusb2.c| 423 +++ include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++ 4 files changed, 468 insertions(+) create mode 100644 drivers/phy/qcom/phy-qcom-qusb2.c create mode 100644 include/dt-bindings/phy/phy-qcom-qusb2.h -- 2.38.1
[PATCH 1/2] dt-bindings: phy: Import phy-qcom-qusb2.h
Import phy-qcom-qusb2.h from Linux to allow standard macros to be used for Qualcomm QUSB2 PHY ids. Signed-off-by: Bhupesh Sharma --- include/dt-bindings/phy/phy-qcom-qusb2.h | 37 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/phy/phy-qcom-qusb2.h diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h new file mode 100644 index 00..5c5e4d800c --- /dev/null +++ b/include/dt-bindings/phy/phy-qcom-qusb2.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ +#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ + +/* PHY HSTX TRIM bit values (24mA to 15mA) */ +#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 +#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 +#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 +#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 +#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 +#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 +#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 +#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 +#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 +#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 +#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa +#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb +#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc +#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd +#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe +#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf + +/* PHY PREEMPHASIS bit values */ +#define QUSB2_V2_PREEMPHASIS_NONE 0 +#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 +#define QUSB2_V2_PREEMPHASIS_10_PERCENT2 +#define QUSB2_V2_PREEMPHASIS_15_PERCENT3 + +/* PHY PREEMPHASIS-WIDTH bit values */ +#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT0 +#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT1 + +#endif -- 2.38.1
[PATCH 2/2] phy: Add Qualcomm QUSB2 USB PHY driver
Several Qualcomm SoCs support QUSB2 USB PHY (for e.g. SM6115 and SDM845 - the corresponding boards being QRB4210-RB2 and Dragonboard845c-RB3). Add PHY driver for the same. Using this driver, the USB Hub connected on board on RB2, can be successfully enumerated via '> usb start'. Signed-off-by: Bhupesh Sharma --- drivers/phy/qcom/Kconfig | 7 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-qusb2.c | 423 ++ 3 files changed, 431 insertions(+) create mode 100644 drivers/phy/qcom/phy-qcom-qusb2.c diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805..361dfb6e11 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -12,6 +12,13 @@ config PHY_QCOM_IPQ4019_USB help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QUSB2 + tristate "Qualcomm USB QUSB2 PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 2113f178c0..f6af985666 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c new file mode 100644 index 00..eab02ed652 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define QUSB2PHY_PLL 0x0 +#define QUSB2PHY_PLL_TEST 0x04 +#define CLK_REF_SELBIT(7) + +#define QUSB2PHY_PLL_TUNE 0x08 +#define QUSB2PHY_PLL_USER_CTL1 0x0c +#define QUSB2PHY_PLL_USER_CTL2 0x10 +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c +#define QUSB2PHY_PLL_PWR_CTRL 0x18 + +/* QUSB2PHY_PLL_STATUS register bits */ +#define PLL_LOCKED BIT(5) + +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + +/* QUSB2PHY_PORT_POWERDOWN register bits */ +#define CLAMP_N_EN BIT(5) +#define FREEZIO_N BIT(1) +#define POWER_DOWN BIT(0) + +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + +#define QUSB2PHY_REFCLK_ENABLE BIT(0) + +#define PHY_CLK_SCHEME_SEL BIT(0) + +/* QUSB2PHY_INTR_CTRL register bits */ +#define DMSE_INTR_HIGH_SEL BIT(4) +#define DPSE_INTR_HIGH_SEL BIT(3) +#define CHG_DET_INTR_ENBIT(2) +#define DMSE_INTR_EN BIT(1) +#define DPSE_INTR_EN BIT(0) + +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ +#define CORE_PLL_EN_FROM_RESET BIT(4) +#define CORE_RESET BIT(5) +#define CORE_RESET_MUX BIT(6) + +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASKGENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT0x4 +#define PREEMPH_WIDTH_HALF_BIT BIT(2) +#define PREEMPHASIS_EN_MASKGENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_10x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_20x198 +#define QUSB2P
Re: Please pull u-boot-dm/next
On Mon, Apr 03, 2023 at 09:35:59AM +1200, Simon Glass wrote: > Hi Tom, > > This is for the -next branch. > > https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/15866 > > > The following changes since commit 942ac73afc37fb98695af4489ea1549c21615a5e: > > Merge tag 'u-boot-imx-next-20230331' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next > (2023-03-31 12:50:34 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-dm.git tags/dm-next-3apr23 > > for you to fetch changes up to 00be5197e8423b8b71744ad0e3f2753d4be0132b: > > test: Run the VPL tests with 'make check' (2023-04-03 06:53:53 +1200) > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: dts: k3-j721e-sk-u-boot: fix boot on j721e SK
On Mon, Apr 03, 2023 at 12:03:12PM -0500, Anand Gadiyar wrote:
> From: Sinthu Raja
>
> J721e SK has been broken since at least March 2022.
>
> The main-navss and mcu-navss nodes were renamed and this caused the
> A72 SPL to fail early in the boot even before the serial port was
> enabled. Fix this.
>
> A later patch series between v2022.07 and v2022.10 additionally broke
> boot on this board by introducing hbmc nodes which are not present on
> this board. The right fix is to disable these by default in the SOC
> dtsi file, but for now we can also disable them in the u-boot dtsi.
>
> With both these fixed, we can now boot the j721e SK board fully from
> mainline u-boot.
>
> Fixes: 58d61fb5a77ef ("arm: dts: k3-j721e-sk: Add initial A72 specific dts
> support")
> Fixes: 297daac43afb9 ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller
> node")
> Reported-by: Anand Gadiyar
> Signed-off-by: Sinthu Raja
> [gadi...@ti.com: update commit description]
> Signed-off-by: Anand Gadiyar
> Cc: Bryan Brattlof
Applied to u-boot/master, thanks!
--
Tom
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Description: PGP signature
[ANN] U-Boot v2023.04 released
Hey all, It's release day and so here's v2023.04. Aside from some very last minute regression fixes (of which the regressions were not last minute), things have been fairly quiet. I do want to ask that moving forward people please base new changes on top of -next once -next is open. While we won't likely have something like the bootph- tag change again soon, a lot of new platforms and so forth that got posted will need either a respin or a fixup by the custodian before being merged. In terms of a changelog, git log --merges v2023.04-rc5..v2023.04 contains what I've pulled since the last RC or: git log --merges v2023.01..v2023.04 for changes since the last full release. As always, more details in pull requests (or the tags referenced by them) will result in more details here. The merge window is formally open again, and I'll be merging in next shortly. v2023.07 is scheduled for July 3rd, 2023 and the merge window will close and -rc1 will be released on the 24th of April, and then the next window will open with -rc2, two weeks later. And since it's a slight change to the norm, I'm saying now that v2024.04 will be released Tuesday, April 2nd, 2024 as I refuse to make a real release on April First. Can't make myself do it. Thanks all! -- Tom signature.asc Description: PGP signature
[PATCH 01/17] mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode
Set High Speed Enable bit for MMC High Speed (52MHz) mode.
Fixes: f12341a95295 ("mmc: sdhci: Fix HISPD bit handling")
Signed-off-by: Jonas Karlman
---
drivers/mmc/sdhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index c6b250b9a1b5..1389c18533fe 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -682,6 +682,7 @@ static int sdhci_set_ios(struct mmc *mmc)
if (!no_hispd_bit) {
if (mmc->selected_mode == MMC_HS ||
mmc->selected_mode == SD_HS ||
+ mmc->selected_mode == MMC_HS_52 ||
mmc->selected_mode == MMC_DDR_52 ||
mmc->selected_mode == MMC_HS_200 ||
mmc->selected_mode == MMC_HS_400 ||
--
2.40.0
[PATCH 00/17] rockchip: eMMC fixes for RK3568 and support for RK3588
This series fixes eMMC HS400 modes on RK3568 and add support for RK3588. It has been tested with rock-3a-rk3568/rock5b-rk3588 defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 && mmc info && mmc read 1000 2000 1 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) All reads have reported OK, prior to this some of these modes worked and others failed. Patch 1-2 fixes an issue with high-speed bit and uhs speed mode field. Patch 3-6 refactors the rk3568 driver to use set_clock and config_dll ops, so that clocks and regs are changed when output clock is disabled. Patch 7-10 continues refactoring and simplification of the driver. Patch 11-12 updates tap and delay values to fix HS400 modes on RK3568. Patch 13-15 adds support for RK3588 to driver and device tree. Patch 16-17 adds workarounds needed to use PIO mode in SPL to successfully load TF-A into SRAM when booting from eMMC on RK3588. Note that this series does not include any change to defconfigs to enable HS200/HS400/HS400ES modes. This series require working pinctrl, see [1]. A copy of this series and its dependencies can be found at [2]. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230315153215.389809-1-eugen.hris...@collabora.com/ [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-emmc-v1 Jonas Karlman (16): mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode mmc: rockchip_sdhci: Fix use of device private data mmc: rockchip_sdhci: Remove unneeded emmc_phy_init ops mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_ops mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops mmc: rockchip_sdhci: Refactor execute tuning error handling mmc: rockchip_sdhci: Update speed mode controls in set_ios_post mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe ops mmc: rockchip_sdhci: Rearrange and simplify used regs and flags mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568 rockchip: rk3568-rock-3a: Enable support for more eMMC modes mmc: rockchip_sdhci: Add support for RK3588 rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support mmc: rockchip_sdhci: Limit number of blocks read in a single command Peter Geis (1): mmc: sdhci: Allow disabling of SDMA in SPL arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 8 + arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 12 +- arch/arm/dts/rk3588s-u-boot.dtsi| 4 + configs/rock5b-rk3588_defconfig | 1 + drivers/clk/rockchip/clk_rk3588.c | 2 + drivers/mmc/Kconfig | 8 + drivers/mmc/rockchip_sdhci.c| 314 ++-- drivers/mmc/sdhci.c | 13 +- 8 files changed, 221 insertions(+), 141 deletions(-) -- 2.40.0
[PATCH 02/17] mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.
Fixes: d1c0a2200afb ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS
timings")
Signed-off-by: Jonas Karlman
---
drivers/mmc/sdhci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 1389c18533fe..86f81f5dfaf3 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -518,6 +518,10 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
reg &= ~SDHCI_CTRL_UHS_MASK;
switch (mmc->selected_mode) {
+ case UHS_SDR25:
+ case MMC_HS:
+ reg |= SDHCI_CTRL_UHS_SDR25;
+ break;
case UHS_SDR50:
case MMC_HS_52:
reg |= SDHCI_CTRL_UHS_SDR50;
--
2.40.0
[PATCH 03/17] mmc: rockchip_sdhci: Fix use of device private data
The device private data is misused in rockchip_sdhci_of_to_plat and
rockchip_sdhci_execute_tuning.
In these functions dev_get_priv is assigned to struct sdhci_host:
struct sdhci_host *host = dev_get_priv(dev);
Instead, the sdhci host should refer to host in struct rockchip_sdhc:
struct rockchip_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
Because host is the first member in struct rockchip_sdhc this is not a
real problem, lets fix it anyway and also use priv name consistently.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index e1409dd2c749..ae28840f6081 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -450,7 +450,8 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host
*host)
static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
- struct sdhci_host *host = dev_get_priv(mmc->dev);
+ struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
+ struct sdhci_host *host = &priv->host;
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
struct mmc_cmd cmd;
u32 ctrl, blk_size;
@@ -531,9 +532,9 @@ static int rockchip_sdhci_probe(struct udevice *dev)
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
- struct rockchip_sdhc *prv = dev_get_priv(dev);
+ struct rockchip_sdhc *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
- struct sdhci_host *host = &prv->host;
+ struct sdhci_host *host = &priv->host;
struct clk clk;
int ret;
@@ -547,8 +548,8 @@ static int rockchip_sdhci_probe(struct udevice *dev)
printf("%s fail to get clk\n", __func__);
}
- prv->emmc_clk = clk;
- prv->dev = dev;
+ priv->emmc_clk = clk;
+ priv->dev = dev;
if (data->get_phy) {
ret = data->get_phy(dev);
@@ -566,7 +567,7 @@ static int rockchip_sdhci_probe(struct udevice *dev)
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
host->mmc = &plat->mmc;
- host->mmc->priv = &prv->host;
+ host->mmc->priv = &priv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
@@ -580,8 +581,9 @@ static int rockchip_sdhci_probe(struct udevice *dev)
static int rockchip_sdhci_of_to_plat(struct udevice *dev)
{
struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
- struct sdhci_host *host = dev_get_priv(dev);
+ struct rockchip_sdhc *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ struct sdhci_host *host = &priv->host;
int ret;
host->name = dev->name;
--
2.40.0
[PATCH 04/17] mmc: rockchip_sdhci: Remove unneeded emmc_phy_init ops
Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit 2321a991bbb5 ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 26 --
1 file changed, 26 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index ae28840f6081..2a30974df501 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -112,7 +112,6 @@ struct rockchip_sdhc {
};
struct sdhci_data {
- int (*emmc_phy_init)(struct udevice *dev);
int (*get_phy)(struct udevice *dev);
/**
@@ -154,11 +153,6 @@ struct sdhci_data {
int (*set_enhanced_strobe)(struct sdhci_host *host);
};
-static int rk3399_emmc_phy_init(struct udevice *dev)
-{
- return 0;
-}
-
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
{
u32 caldone, dllrdy, freqsel;
@@ -294,18 +288,6 @@ static int rk3399_sdhci_set_ios_post(struct sdhci_host
*host)
return 0;
}
-static int rk3568_emmc_phy_init(struct udevice *dev)
-{
- struct rockchip_sdhc *prv = dev_get_priv(dev);
- struct sdhci_host *host = &prv->host;
- u32 extra;
-
- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
-
- return 0;
-}
-
static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int
clock)
{
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
@@ -557,12 +539,6 @@ static int rockchip_sdhci_probe(struct udevice *dev)
return ret;
}
- if (data->emmc_phy_init) {
- ret = data->emmc_phy_init(dev);
- if (ret)
- return ret;
- }
-
host->ops = &rockchip_sdhci_ops;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
@@ -605,7 +581,6 @@ static int rockchip_sdhci_bind(struct udevice *dev)
static const struct sdhci_data rk3399_data = {
.get_phy = rk3399_emmc_get_phy,
- .emmc_phy_init = rk3399_emmc_phy_init,
.set_control_reg = rk3399_sdhci_set_control_reg,
.set_ios_post = rk3399_sdhci_set_ios_post,
.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
@@ -613,7 +588,6 @@ static const struct sdhci_data rk3399_data = {
static const struct sdhci_data rk3568_data = {
.get_phy = rk3568_emmc_get_phy,
- .emmc_phy_init = rk3568_emmc_phy_init,
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
};
--
2.40.0
[PATCH 08/17] mmc: rockchip_sdhci: Update speed mode controls in set_ios_post
Refactor set_ios_post ops to correctly set UHS Speed Select field values
according to TRM. Also set or unset Enhanced Strobe Enable bit and
eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit
was never unset after switching to HS400ES mode.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 68 ++--
1 file changed, 42 insertions(+), 26 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index e56043fce88e..8e29430a483e 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -372,20 +372,6 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
{
- struct mmc *mmc = host->mmc;
- u32 vendor;
- int reg;
-
- reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
- + DWCMSHC_EMMC_CONTROL;
-
- vendor = sdhci_readl(host, reg);
- if (mmc->selected_mode == MMC_HS_400_ES)
- vendor |= DWCMSHC_ENHANCED_STROBE;
- else
- vendor &= ~DWCMSHC_ENHANCED_STROBE;
- sdhci_writel(host, vendor, reg);
-
return 0;
}
@@ -394,21 +380,51 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host
*host)
struct mmc *mmc = host->mmc;
u32 reg, vendor_reg;
- if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode ==
MMC_HS_400_ES) {
- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- reg &= ~SDHCI_CTRL_UHS_MASK;
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_UHS_MASK;
+
+ switch (mmc->selected_mode) {
+ case UHS_SDR25:
+ case MMC_HS:
+ case MMC_HS_52:
+ reg |= SDHCI_CTRL_UHS_SDR25;
+ break;
+ case UHS_SDR50:
+ reg |= SDHCI_CTRL_UHS_SDR50;
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ reg |= SDHCI_CTRL_UHS_DDR50;
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ case MMC_HS_400:
+ case MMC_HS_400_ES:
reg |= DWCMSHC_CTRL_HS400;
- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ break;
+ default:
+ reg |= SDHCI_CTRL_UHS_SDR12;
+ }
+
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
- vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) &
DWCMSHC_AREA1_MASK)
-+ DWCMSHC_EMMC_CONTROL;
- /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
- reg = sdhci_readw(host, vendor_reg);
+ vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) &
DWCMSHC_AREA1_MASK)
++ DWCMSHC_EMMC_CONTROL;
+ reg = sdhci_readw(host, vendor_reg);
+
+ if (IS_MMC(mmc))
reg |= DWCMSHC_CARD_IS_EMMC;
- sdhci_writew(host, reg, vendor_reg);
- } else {
- sdhci_set_uhs_timing(host);
- }
+ else
+ reg &= ~DWCMSHC_CARD_IS_EMMC;
+
+ if (mmc->selected_mode == MMC_HS_400_ES)
+ reg |= DWCMSHC_ENHANCED_STROBE;
+ else
+ reg &= ~DWCMSHC_ENHANCED_STROBE;
+
+ sdhci_writew(host, reg, vendor_reg);
return 0;
}
--
2.40.0
[PATCH 05/17] mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_ops
Add support for the set_clock and config_dll sdhci_ops. Use of these ops
will allow configuration of DLL while the output clock is disabled.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 2a30974df501..bc9838ac7c45 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -139,6 +139,9 @@ struct sdhci_data {
*/
int (*set_ios_post)(struct sdhci_host *host);
+ void (*set_clock)(struct sdhci_host *host, u32 div);
+ int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
+
/**
* set_enhanced_strobe() - Set HS400 Enhanced Strobe config
*
@@ -430,6 +433,15 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host
*host)
return 0;
}
+static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div)
+{
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
+ struct sdhci_data *data = (struct sdhci_data
*)dev_get_driver_data(priv->dev);
+
+ if (data->set_clock)
+ data->set_clock(host, div);
+}
+
static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
@@ -491,6 +503,17 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
return ret;
}
+static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool
enable)
+{
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
+ struct sdhci_data *data = (struct sdhci_data
*)dev_get_driver_data(priv->dev);
+
+ if (data->config_dll)
+ return data->config_dll(host, clock, enable);
+
+ return 0;
+}
+
static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
{
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
@@ -503,9 +526,11 @@ static int rockchip_sdhci_set_enhanced_strobe(struct
sdhci_host *host)
}
static struct sdhci_ops rockchip_sdhci_ops = {
- .set_ios_post = rockchip_sdhci_set_ios_post,
- .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
.set_control_reg = rockchip_sdhci_set_control_reg,
+ .set_ios_post = rockchip_sdhci_set_ios_post,
+ .set_clock = rockchip_sdhci_set_clock,
+ .platform_execute_tuning = rockchip_sdhci_execute_tuning,
+ .config_dll = rockchip_sdhci_config_dll,
.set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
};
--
2.40.0
[PATCH 07/17] mmc: rockchip_sdhci: Refactor execute tuning error handling
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there
is an error. Also skip enable of interrupt signaling and remove a delay,
a delay is already happening in sdhci_send_command.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 35 +++
1 file changed, 11 insertions(+), 24 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index fdf48f4066c9..e56043fce88e 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -449,17 +449,16 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
struct mmc_cmd cmd;
u32 ctrl, blk_size;
- int ret = 0;
+ int ret;
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
- if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width
== 8)
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
@@ -469,36 +468,24 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
cmd.cmdarg = 0;
do {
- if (tuning_loop_counter-- == 0)
- break;
-
- mmc_send_cmd(mmc, &cmd, NULL);
-
- if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
- /*
-* For tuning command, do not do busy loop. As tuning
-* is happening (CLK-DATA latching for setup/hold time
-* requirements), give time to complete
-*/
- udelay(1);
-
+ ret = mmc_send_cmd(mmc, &cmd, NULL);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ret || tuning_loop_counter-- == 0)
+ break;
} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
- if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
- printf("%s:Tuning failed\n", __func__);
- ret = -EIO;
- }
+ if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ if (!ret)
+ ret = -EIO;
+ printf("%s: Tuning failed: %d\n", __func__, ret);
- if (tuning_loop_counter < 0) {
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
- sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
+ ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
}
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
SDHCI_INT_ENABLE);
- /* Mask all sdhci interrupt sources */
- sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
return ret;
}
--
2.40.0
[PATCH 06/17] mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops
Change to configure clock and DLL in set_clock and config_dll ops
instead of in the set_ios_post ops.
With this change the output clock is turned off while configuring DLL
parameters, according to the design recommendations.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index bc9838ac7c45..fdf48f4066c9 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -291,18 +291,24 @@ static int rk3399_sdhci_set_ios_post(struct sdhci_host
*host)
return 0;
}
-static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int
clock)
+static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div)
{
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
+ struct mmc *mmc = host->mmc;
+ ulong rate;
+
+ rate = clk_set_rate(&priv->emmc_clk, mmc->clock);
+ if (IS_ERR_VALUE(rate))
+ printf("%s: Set clock rate failed: %ld\n", __func__,
(long)rate);
+}
+
+static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool
enable)
+{
int val, ret;
u32 extra;
- if (clock > host->max_clk)
- clock = host->max_clk;
- if (clock)
- clk_set_rate(&priv->emmc_clk, clock);
-
- sdhci_set_clock(host->mmc, clock);
+ if (!enable)
+ return 0;
if (clock >= 100 * MHz) {
/* reset DLL */
@@ -386,14 +392,8 @@ static int rk3568_sdhci_set_enhanced_strobe(struct
sdhci_host *host)
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
- uint clock = mmc->tran_speed;
u32 reg, vendor_reg;
- if (!clock)
- clock = mmc->clock;
-
- rk3568_sdhci_emmc_set_clock(host, clock);
-
if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode ==
MMC_HS_400_ES) {
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
@@ -614,6 +614,8 @@ static const struct sdhci_data rk3399_data = {
static const struct sdhci_data rk3568_data = {
.get_phy = rk3568_emmc_get_phy,
.set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
.set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
};
--
2.40.0
[PATCH 12/17] rockchip: rk3568-rock-3a: Enable support for more eMMC modes
Add supported mmc modes to rk3568-rock-3a device tree.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 04bbb01b5d51..1b3cae1b0d96 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -13,6 +13,14 @@
};
};
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
&sdmmc2 {
status = "disabled";
};
--
2.40.0
[PATCH 13/17] mmc: rockchip_sdhci: Add support for RK3588
Add support for RK3588 to the sdhci driver. RK3588 has the inverter flag
in TXCLK reg instead of RXCLK and also make use of a new CMDOUT reg.
Add and use a quirks field to support such quirks.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 62 ++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 12a616d3dfb8..9178bc00b6b8 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -56,6 +56,7 @@
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
#define DWCMSHC_EMMC_DLL_TXCLK 0x808
#define DWCMSHC_EMMC_DLL_STRBIN0x80c
+#define DWCMSHC_EMMC_DLL_CMDOUT0x810
#define DWCMSHC_EMMC_DLL_STATUS0 0x840
#define DWCMSHC_EMMC_DLL_STATUS1 0x844
#define DWCMSHC_EMMC_DLL_START BIT(0)
@@ -70,18 +71,28 @@
#define DLL_RXCLK_NO_INVERTER BIT(29)
#define DLL_RXCLK_ORI_GATE BIT(31)
#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
+#define DLL_TXCLK_TAPNUM_90_DEGREES0x9
#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
+#define DLL_TXCLK_NO_INVERTER BIT(29)
#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
#define DLL_STRBIN_DELAY_NUM_OFFSET16
#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x10
+#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
+#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
+#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
+#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
+#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
#define DLL_LOCK_WO_TMOUT(x) \
x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
#define ROCKCHIP_MAX_CLKS 3
+#define QUIRK_INVERTER_FLAG_IN_RXCLK BIT(0)
+#define QUIRK_HAS_DLL_CMDOUT BIT(1)
+
struct rockchip_sdhc_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -99,6 +110,7 @@ struct rockchip_sdhc {
void *base;
struct rockchip_emmc_phy *phy;
struct clk emmc_clk;
+ u8 txclk_tapnum;
};
struct sdhci_data {
@@ -144,6 +156,8 @@ struct sdhci_data {
* Return: 0 if successful, -ve on error
*/
int (*set_enhanced_strobe)(struct sdhci_host *host);
+
+ u32 quirks;
};
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -294,6 +308,10 @@ static void rk3568_sdhci_set_clock(struct sdhci_host
*host, u32 div)
static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool
enable)
{
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc,
host);
+ struct sdhci_data *data = (struct sdhci_data
*)dev_get_driver_data(priv->dev);
+ struct mmc *mmc = host->mmc;
+ u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
int val, ret;
u32 extra;
@@ -318,12 +336,33 @@ static int rk3568_sdhci_config_dll(struct sdhci_host
*host, u32 clock, bool enab
if (ret)
return ret;
- extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_NO_INVERTER;
+ extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
+ if (data->quirks & QUIRK_INVERTER_FLAG_IN_RXCLK)
+ extra |= DLL_RXCLK_NO_INVERTER;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES)
+ txclk_tapnum = priv->txclk_tapnum;
+
+ if ((data->quirks & QUIRK_HAS_DLL_CMDOUT) &&
+ (mmc->selected_mode == MMC_HS_400 ||
+mmc->selected_mode == MMC_HS_400_ES)) {
+ txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
+
+ extra = DLL_CMDOUT_SRC_CLK_NEG |
+ DLL_CMDOUT_BOTH_CLK_EDGE |
+ DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_CMDOUT_TAPNUM_90_DEGREES |
+ DLL_CMDOUT_TAPNUM_FROM_SW;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
+ }
+
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_TXCLK_TAPNUM_DEFAULT |
- DLL_TXCLK_TAPNUM_FROM_SW;
+ DLL_TXCLK_TAPNUM_FROM_SW |
+ DLL_TXCLK_NO_INVERTER |
+ txclk_tapnum;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
@@ -339,6 +378,8 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host,
u32 clock, bool enab
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXC
[PATCH 11/17] mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568
Adjust tap number for transmit clock, tap number and delay number for strobe input to fix HS400 modes on RK3568. New values have been picked from vendor kernel and u-boot and have successfully been tested with rock-3a-rk3568_defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 && mmc info && mmc read 1000 2000 1 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) Signed-off-by: Jonas Karlman --- drivers/mmc/rockchip_sdhci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index bcf65e091741..12a616d3dfb8 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -69,13 +69,13 @@ #define DWCMSHC_EMMC_DLL_DLYENABIT(27) #define DLL_RXCLK_NO_INVERTER BIT(29) #define DLL_RXCLK_ORI_GATE BIT(31) -#define DLL_TXCLK_TAPNUM_DEFAULT 0xA +#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) -#define DLL_STRBIN_TAPNUM_DEFAULT 0x8 +#define DLL_STRBIN_TAPNUM_DEFAULT 0x4 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) #define DLL_STRBIN_DELAY_NUM_OFFSET16 -#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 +#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x10 #define DLL_LOCK_WO_TMOUT(x) \ x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ -- 2.40.0
[PATCH 09/17] mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe ops
Remove empty implementations of get_phy and set_enhanced_strobe ops.
Change driver set_enhanced_strobe to return 0 in order to allow missing
implementation of the ops.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 8e29430a483e..9716fbb54dd4 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -365,16 +365,6 @@ static int rk3568_sdhci_config_dll(struct sdhci_host
*host, u32 clock, bool enab
return 0;
}
-static int rk3568_emmc_get_phy(struct udevice *dev)
-{
- return 0;
-}
-
-static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
-{
- return 0;
-}
-
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
@@ -525,7 +515,7 @@ static int rockchip_sdhci_set_enhanced_strobe(struct
sdhci_host *host)
if (data->set_enhanced_strobe)
return data->set_enhanced_strobe(host);
- return -ENOTSUPP;
+ return 0;
}
static struct sdhci_ops rockchip_sdhci_ops = {
@@ -615,11 +605,9 @@ static const struct sdhci_data rk3399_data = {
};
static const struct sdhci_data rk3568_data = {
- .get_phy = rk3568_emmc_get_phy,
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
.config_dll = rk3568_sdhci_config_dll,
- .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
};
static const struct udevice_id sdhci_ids[] = {
--
2.40.0
[PATCH 15/17] clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman --- drivers/clk/rockchip/clk_rk3588.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 41e31b61a55b..d0cc19b47883 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1553,6 +1553,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) case DCLK_DECOM: rate = rk3588_mmc_get_clk(priv, clk->id); break; + case TMCLK_EMMC: case TCLK_WDT0: rate = OSC_HZ; break; @@ -1702,6 +1703,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) case DCLK_DECOM: ret = rk3588_mmc_set_clk(priv, clk->id, rate); break; + case TMCLK_EMMC: case TCLK_WDT0: ret = OSC_HZ; break; -- 2.40.0
[PATCH 10/17] mmc: rockchip_sdhci: Rearrange and simplify used regs and flags
This rearrange and remove duplicate defines to make the code cleaner.
There is no need to read vendor area1 and use an offset each time, it is
easier and clearer to just use the reg offset defined in TRM, same as
the other vendor regs.
This also removes use of the misspelled const for the RK3588 CMDOUT reg,
it will be re-added when support for RK3588 is introduced.
Signed-off-by: Jonas Karlman
---
drivers/mmc/rockchip_sdhci.c | 40
1 file changed, 13 insertions(+), 27 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 9716fbb54dd4..bcf65e091741 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -47,46 +47,36 @@
#define ARASAN_VENDOR_REGISTER 0x78
#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
-/* DWC IP vendor area 1 pointer */
-#define DWCMSHC_P_VENDOR_AREA1 0xe8
-#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
-/* Offset inside the vendor area 1 */
-#define DWCMSHC_EMMC_CONTROL 0x2c
+/* Rockchip specific Registers */
+#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
#define DWCMSHC_CARD_IS_EMMC BIT(0)
#define DWCMSHC_ENHANCED_STROBEBIT(8)
-
-/* Rockchip specific Registers */
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESETBIT(1)
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
#define DWCMSHC_EMMC_DLL_TXCLK 0x808
#define DWCMSHC_EMMC_DLL_STRBIN0x80c
-#define DECMSHC_EMMC_DLL_CMDOUT0x810
#define DWCMSHC_EMMC_DLL_STATUS0 0x840
#define DWCMSHC_EMMC_DLL_STATUS1 0x844
#define DWCMSHC_EMMC_DLL_START BIT(0)
-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
+#define DWCMSHC_EMMC_DLL_LOCKEDBIT(8)
+#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
#define DWCMSHC_EMMC_DLL_START_POINT 16
#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
#define DWCMSHC_EMMC_DLL_INC_VALUE 2
#define DWCMSHC_EMMC_DLL_INC 8
#define DWCMSHC_EMMC_DLL_BYPASSBIT(24)
#define DWCMSHC_EMMC_DLL_DLYENABIT(27)
+#define DLL_RXCLK_NO_INVERTER BIT(29)
+#define DLL_RXCLK_ORI_GATE BIT(31)
#define DLL_TXCLK_TAPNUM_DEFAULT 0xA
-
+#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
#define DLL_STRBIN_DELAY_NUM_OFFSET16
#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
-#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
-#define DWCMSHC_EMMC_DLL_LOCKEDBIT(8)
-#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
-#define DLL_RXCLK_NO_INVERTER 1
-#define DLL_RXCLK_INVERTER 0
-#define DLL_RXCLK_ORI_GATE BIT(31)
-#define DWCMSHC_ENHANCED_STROBEBIT(8)
#define DLL_LOCK_WO_TMOUT(x) \
x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
@@ -328,8 +318,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host,
u32 clock, bool enab
if (ret)
return ret;
- extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_NO_INVERTER;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
@@ -346,10 +335,9 @@ static int rk3568_sdhci_config_dll(struct sdhci_host
*host, u32 clock, bool enab
* Disable DLL and reset both of sample and drive clock.
* The bypass bit and start bit need to be set if DLL is not
locked.
*/
- sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS |
DWCMSHC_EMMC_DLL_START,
-DWCMSHC_EMMC_DLL_CTRL);
+ extra = DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
- sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
/*
* Before switching to hs400es mode, the driver will enable
@@ -368,7 +356,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host,
u32 clock, bool enab
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
- u32 reg, vendor_reg;
+ u32 reg;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
@@ -400,9 +388,7 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host
*host)
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
- vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) &
DWCMSHC_AREA1_MASK)
-+ DWCMSHC_EMMC_CONT
[PATCH 14/17] rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported
mmc modes and pinctrl.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 12 ++--
arch/arm/dts/rk3588s-u-boot.dtsi| 4
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 4c6f0311d6a1..85075bf435f9 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,11 +7,11 @@
/ {
aliases {
- mmc0 = &sdmmc;
+ mmc1 = &sdmmc;
};
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
@@ -19,3 +19,11 @@
bus-width = <4>;
status = "okay";
};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe
&emmc_rstnout>;
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 65960fa50adc..65d0ba9c68d2 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -59,6 +59,10 @@
u-boot,spl-fifo-mode;
};
+&sdhci {
+ u-boot,dm-spl;
+};
+
&uart2 {
clock-frequency = <2400>;
u-boot,dm-spl;
--
2.40.0
