Re: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller base address
> From: Bin Meng [mailto:bmeng...@gmail.com] > Sent: Tuesday, August 18, 2020 4:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller > base address > > From: Bin Meng > > At present fdtdec_get_addr() is used to get L2 cache controller base > address. This only works for a fixed #address-cells and #size-cells. > Change to use fdtdec_get_addr_size_auto_parent() instead. > > Signed-off-by: Bin Meng > --- > > arch/riscv/cpu/fu540/cache.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Rick Chen
Re: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit
> From: Bin Meng [mailto:bmeng...@gmail.com] > Sent: Tuesday, August 18, 2020 4:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit > > From: Bin Meng > > priv->info.size is of type 'size_t' but the length modifier is l. > Fix this by casting priv->info.size. Note 'z' cannot be used as > the modifier as SPL does not support that. > > Signed-off-by: Bin Meng > --- > > drivers/ram/sifive/fu540_ddr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen
RE: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
> -Original Message-
> From: Pali Rohár
> Sent: Wednesday, August 19, 2020 16:57
> To: Stefan Roese ; Kostya Porotchkin
> Cc: u-boot@lists.denx.de
> Subject: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT
> compatible with Linux kernel DT
>
> External Email
>
> --
> Change active-high to active-low and change DT property name from reset-
> gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver
> in
> Linux kernel.
>
> Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
> ---
> arch/arm/dts/armada-3720-db.dts | 2 +-
> arch/arm/dts/armada-3720-espressobin.dts | 2 +- arch/arm/dts/armada-
> 3720-turris-mox.dts | 2 +-
> drivers/pci/pci-aardvark.c | 6 +++---
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-
> db.dts index 1b219c423b..1b1b66b94d 100644
> --- a/arch/arm/dts/armada-3720-db.dts
> +++ b/arch/arm/dts/armada-3720-db.dts
> @@ -159,6 +159,6 @@
> &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie_pins>;
> - reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
> status = "okay";
> };
> diff --git a/arch/arm/dts/armada-3720-espressobin.dts
> b/arch/arm/dts/armada-3720-espressobin.dts
> index 84e2c2adba..f10a953ec5 100644
> --- a/arch/arm/dts/armada-3720-espressobin.dts
> +++ b/arch/arm/dts/armada-3720-espressobin.dts
> @@ -145,6 +145,6 @@
> &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie_pins>;
> - reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
> status = "okay";
> };
> diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
> b/arch/arm/dts/armada-3720-turris-mox.dts
> index 0f0a6ce65d..974270cc8c 100644
> --- a/arch/arm/dts/armada-3720-turris-mox.dts
> +++ b/arch/arm/dts/armada-3720-turris-mox.dts
> @@ -172,6 +172,6 @@
> &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie_pins>;
> - reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
> status = "disabled";
> };
> diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index
> 711b930d0f..5b3f23c184 100644
> --- a/drivers/pci/pci-aardvark.c
> +++ b/drivers/pci/pci-aardvark.c
> @@ -616,7 +616,7 @@ static int pcie_advk_probe(struct udevice *dev) #if
> CONFIG_IS_ENABLED(DM_GPIO)
> struct gpio_desc reset_gpio;
>
> - gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
> + gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio,
>GPIOD_IS_OUT);
> /*
>* Issue reset to add-in card through the dedicated GPIO.
> @@ -633,9 +633,9 @@ static int pcie_advk_probe(struct udevice *dev)
>*/
> if (dm_gpio_is_valid(&reset_gpio)) {
> dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
> - dm_gpio_set_value(&reset_gpio, 0);
> - mdelay(200);
> dm_gpio_set_value(&reset_gpio, 1);
> + mdelay(200);
> + dm_gpio_set_value(&reset_gpio, 0);
> }
> #else
> dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
> --
> 2.20.1
Re: [PATCH v2 1/7] riscv: Rework riscv timer driver to only support S-mode
On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote: > > The riscv-timer driver currently serves as a shim for several riscv timer > drivers. This is not too desirable because it bypasses the usual timer > selection via the driver model. There is no easy way to specify an > alternate timing driver, or have the tick rate depend on the cpu's > configured frequency. The timer drivers also do not have device structs, > and so have to rely on storing parameters in gd_t. Lastly, there is no > initialization call, so driver init is done in the same function which > reads the time. This can result in confusing error messages. To a user, it > looks like the driver failed when trying to read the time, whereas it may > have failed while initializing. > > This patch removes the shim functionality from the riscv-timer driver, and > has it instead implement the former rdtime.c timer driver. This is because > existing u-boot users who pass in a device tree (e.g. qemu) do not create a > timer device for S-mode u-boot. The existing behavior of creating the > riscv-timer device in the riscv cpu driver must be kept. The actual reading > of the CSRs has been redone in the style of Linux's get_cycles64. > > Signed-off-by: Sean Anderson > --- > > Changes in v2: > - Remove RISCV_RDTIME KConfig option > > arch/riscv/Kconfig | 8 > arch/riscv/lib/Makefile | 1 - > arch/riscv/lib/rdtime.c | 38 > drivers/timer/Kconfig | 6 +++--- > drivers/timer/riscv_timer.c | 39 +++-- > 5 files changed, 23 insertions(+), 69 deletions(-) > delete mode 100644 arch/riscv/lib/rdtime.c > Reviewed-by: Bin Meng
Re: [PATCH v2 2/7] riscv: Rework Andes PLMT as a UCLASS_TIMER driver
On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote:
>
> This converts the PLMT driver from the riscv-specific timer interface to be
> a DM-based UCLASS_TIMER driver.
>
> Signed-off-by: Sean Anderson
> ---
> This patch builds but has NOT been tested.
>
> (no changes since v1)
>
> arch/riscv/Kconfig | 4 ---
> arch/riscv/dts/ae350_32.dts | 1 +
> arch/riscv/dts/ae350_64.dts | 1 +
> arch/riscv/include/asm/global_data.h | 3 --
> arch/riscv/lib/andes_plmt.c | 42 +---
> 5 files changed, 22 insertions(+), 29 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 21e6690f4d..d9155b9bab 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -177,10 +177,6 @@ config ANDES_PLIC
> config ANDES_PLMT
> bool
> depends on RISCV_MMODE || SPL_RISCV_MMODE
> - select REGMAP
> - select SYSCON
> - select SPL_REGMAP if SPL
> - select SPL_SYSCON if SPL
> help
> The Andes PLMT block holds memory-mapped mtime register
> associated with timer tick.
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> index 3f8525fe56..afcb9cfbbf 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -162,6 +162,7 @@
> &CPU2_intc 7
> &CPU3_intc 7>;
> reg = <0xe600 0x10>;
> + clock-frequency = <6000>;
Why not use /cpus/timebase-frequency directly?
> };
> };
>
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> index 482c707503..1c37879049 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -162,6 +162,7 @@
> &CPU2_intc 7
> &CPU3_intc 7>;
> reg = <0x0 0xe600 0x0 0x10>;
> + clock-frequency = <6000>;
> };
> };
>
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index 2eb14815bc..0dec5e669e 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -24,9 +24,6 @@ struct arch_global_data {
> #ifdef CONFIG_ANDES_PLIC
> void __iomem *plic; /* plic base address */
> #endif
> -#ifdef CONFIG_ANDES_PLMT
> - void __iomem *plmt; /* plmt base address */
> -#endif
> #if CONFIG_IS_ENABLED(SMP)
> struct ipi_data ipi[CONFIG_NR_CPUS];
> #endif
> diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> index a7e90ca992..b0245d0b52 100644
> --- a/arch/riscv/lib/andes_plmt.c
> +++ b/arch/riscv/lib/andes_plmt.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2019, Rick Chen
> + * Copyright (C) 2020, Sean Anderson
> *
> * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> * The PLMT block holds memory-mapped mtime register
> @@ -9,46 +10,43 @@
>
> #include
> #include
> -#include
> -#include
> +#include
> #include
> -#include
> #include
>
> /* mtime register */
> #define MTIME_REG(base)((ulong)(base))
>
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define PLMT_BASE_GET(void)\
> - do {\
> - long *ret; \
> - \
> - if (!gd->arch.plmt) { \
> - ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> - if (IS_ERR(ret))\
> - return PTR_ERR(ret);\
> - gd->arch.plmt = ret;\
> - } \
> - } while (0)
> -
> -int riscv_get_time(u64 *time)
> +static int andes_plmt_get_count(struct udevice *dev, u64 *count)
> {
> - PLMT_BASE_GET();
> + *count = readq((void __iomem *)MTIME_REG(dev->priv));
>
> - *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> + return 0;
> +}
> +
> +static const struct timer_ops andes_plmt_ops = {
> + .get_count = andes_plmt_get_count,
> +};
> +
> +static int andes_plmt_probe(struct udevice *dev)
> +{
> + dev->priv = dev_read_addr_ptr(dev);
> + if (!dev->priv)
> + return -EINVAL;
>
> return 0;
> }
>
> static const struct udevice_id andes_plmt_ids[] = {
> - { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
RISCV_SYSCON_PLMT should be removed from
arch/riscv/include/asm/syscon.h to make this patch complete.
> + { .compatible = "riscv,plmt0" },
> {
Re: [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
On Thursday 20 August 2020 07:02:18 Stefan Roese wrote: > Can't you just use "mtdparts=" kernel cmdline parameter instead to pass > the MTD layout to the kernel? Maybe it is possible too, I have not tried it. I thought that more common is to update DTS file by uboot when loading kernel as it is already done e.g. for ethernet MAC address on Espressobin. Also I see that uboot has function fdt_fixup_mtdparts() via CONFIG_FDT_FIXUP_PARTITIONS option which do this, but uses uboot MTD code which IIRC cannot initialize SPI NOR. Anyway, updating DTS has advantage that it is not needed to update existing boot scripts for OS. There are more distributions for Espressobin which have own boot scripts stored on SD card for loading kernel. And therefore to use command line parameters it would be needed to update all of them. And I see there another problem. For specifying size of mtd partitions in command line, it is required to know offsets of those partitions. And e.g. uboot env partition depends on CONFIG_ENV_OFFSET option which is not available for uboot boot script code. But if you have other idea, I'm open to also other solutions.
Re: [PATCH v2 3/7] riscv: Clean up initialization in Andes PLIC
On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote: > > This merges the PLIC initialization code from two functions into one. > > Signed-off-by: Sean Anderson > --- > This patch builds but has NOT been tested. > > (no changes since v1) > > arch/riscv/lib/andes_plic.c | 58 - > 1 file changed, 25 insertions(+), 33 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
On Thursday 20 August 2020 07:05:58 Stefan Roese wrote:
> On 19.08.20 15:57, Pali Rohár wrote:
> > This change ensures that PCIe card is put into reset state when U-Boot
> > stops using it.
> >
> > DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
> > prior booting Linux kernel.
> >
> > Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
> > prior initializing it. If it does not issue reset then some PCIe cards
> > (specially Compex WiFi cards) are not detected at all.
> >
> > Putting PCIe card into reset state prior booting Linux kernel would ensure
> > that card would be properly reset at time when Linux kernel starts
> > initializing pci-aardvark driver.
> >
> > Signed-off-by: Pali Rohár
> > ---
> > drivers/pci/pci-aardvark.c | 27 +--
> > 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
> > index 5b3f23c184..8996be5309 100644
> > --- a/drivers/pci/pci-aardvark.c
> > +++ b/drivers/pci/pci-aardvark.c
> > @@ -148,6 +148,9 @@ struct pcie_advk {
> > void *base;
> > intfirst_busno;
> > struct udevice *dev;
> > +#if CONFIG_IS_ENABLED(DM_GPIO)
> > + struct gpio_desc reset_gpio;
> > +#endif
> > };
>
> Adding more #ifdef's is not recommended. Can't you "depend" this driver
> on DM_GPIO in Kconfig instead? Are there any used that don't support
> DM_GPIO right now?
I'm not sure if this dependency is what people want. CCing Simon.
In past Simon created commit bcee8d6764f9215f16b393a35581000178633254
where described that want to build SPL without GPIO uclass support.
> > static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
> > @@ -614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
> > struct pcie_advk *pcie = dev_get_priv(dev);
> > #if CONFIG_IS_ENABLED(DM_GPIO)
>
> If you change the driver to rely on DM_GPIO, then please also remove all
> other #ifdef's with DM_GPIO.
>
> Thanks,
> Stefan
>
> > - struct gpio_desc reset_gpio;
> > -
> > - gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio,
> > + gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
> > GPIOD_IS_OUT);
> > /*
> > * Issue reset to add-in card through the dedicated GPIO.
> > @@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
> > * possible before PCIe PHY initialization. Moreover, the PCIe
> > * clock should be gated as well.
> > */
> > - if (dm_gpio_is_valid(&reset_gpio)) {
> > + if (dm_gpio_is_valid(&pcie->reset_gpio)) {
> > dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
> > - dm_gpio_set_value(&reset_gpio, 1);
> > + dm_gpio_set_value(&pcie->reset_gpio, 1);
> > mdelay(200);
> > - dm_gpio_set_value(&reset_gpio, 0);
> > + dm_gpio_set_value(&pcie->reset_gpio, 0);
> > }
> > #else
> > dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
> > @@ -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
> > return pcie_advk_setup_hw(pcie);
> > }
> > +static int pcie_advk_remove(struct udevice *dev)
> > +{
> > +#if CONFIG_IS_ENABLED(DM_GPIO)
> > + struct pcie_advk *pcie = dev_get_priv(dev);
> > +
> > + if (dm_gpio_is_valid(&pcie->reset_gpio))
> > + dm_gpio_set_value(&pcie->reset_gpio, 1);
> > +#endif /* DM_GPIO */
> > +
> > + return 0;
> > +}
> > +
> > /**
> >* pcie_advk_ofdata_to_platdata() - Translate from DT to device state
> >*
> > @@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
> > .ops= &pcie_advk_ops,
> > .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
> > .probe = pcie_advk_probe,
> > + .remove = pcie_advk_remove,
> > + .flags = DM_FLAG_OS_PREPARE,
> > .priv_auto_alloc_size = sizeof(struct pcie_advk),
> > };
> >
>
>
> Viele Grüße,
> Stefan
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver
On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote:
>
> This converts the clint driver from the riscv-specific interface to be a
> DM-based UCLASS_TIMER driver. We also need to re-add the initialization for
> IPI back into the SPL code. This was previously implicitly done when the
> timer was initialized. In addition, the SiFive DDR driver previously
> implicitly depended on the CLINT to select REGMAP.
>
> Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
> the SiFive CLINT is part of the device tree passed in by qemu. This device
> tree doesn't have a clocks or clock-frequency property on clint, so we need
> to fall back on the timebase-frequency property. Perhaps in the future we
> can get a clock-frequency property added to the qemu dtb.
>
> Signed-off-by: Sean Anderson
> ---
> This patch builds but has only been tested on the K210 and QEMU. It has NOT
> been tested on a HiFive.
>
> (no changes since v1)
>
> arch/riscv/Kconfig| 4 --
> arch/riscv/lib/sifive_clint.c | 87 +++
> common/spl/spl_opensbi.c | 5 ++
> drivers/ram/sifive/Kconfig| 2 +
> 4 files changed, 64 insertions(+), 34 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index d9155b9bab..aaa3b833a5 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -155,10 +155,6 @@ config 64BIT
> config SIFIVE_CLINT
> bool
> depends on RISCV_MMODE || SPL_RISCV_MMODE
> - select REGMAP
> - select SYSCON
> - select SPL_REGMAP if SPL
> - select SPL_SYSCON if SPL
> help
> The SiFive CLINT block holds memory-mapped control and status
> registers
> associated with software and timer interrupts.
> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
> index b9a2c649cc..3345a17ad2 100644
> --- a/arch/riscv/lib/sifive_clint.c
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -8,9 +8,9 @@
> */
>
> #include
> +#include
> #include
> -#include
> -#include
> +#include
> #include
> #include
> #include
> @@ -24,35 +24,19 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int riscv_get_time(u64 *time)
> -{
> - /* ensure timer register base has a sane value */
> - riscv_init_ipi();
> -
> - *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
> -
> - return 0;
> -}
> -
> -int riscv_set_timecmp(int hart, u64 cmp)
> -{
> - /* ensure timer register base has a sane value */
> - riscv_init_ipi();
> -
> - writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
> -
> - return 0;
> -}
> -
> int riscv_init_ipi(void)
> {
> - if (!gd->arch.clint) {
> - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
> + int ret;
> + struct udevice *dev;
>
> - if (IS_ERR(ret))
> - return PTR_ERR(ret);
> - gd->arch.clint = ret;
> - }
> + ret = uclass_get_device_by_driver(UCLASS_TIMER,
> + DM_GET_DRIVER(sifive_clint), &dev);
> + if (ret)
> + return ret;
> +
> + gd->arch.clint = dev_read_addr_ptr(dev);
> + if (!gd->arch.clint)
> + return -EINVAL;
>
> return 0;
> }
> @@ -78,14 +62,57 @@ int riscv_get_ipi(int hart, int *pending)
> return 0;
> }
>
> +static int sifive_clint_get_count(struct udevice *dev, u64 *count)
> +{
> + *count = readq((void __iomem *)MTIME_REG(dev->priv));
> +
> + return 0;
> +}
> +
> +static const struct timer_ops sifive_clint_ops = {
> + .get_count = sifive_clint_get_count,
> +};
> +
> +static int sifive_clint_probe(struct udevice *dev)
> +{
> + int ret;
> + ofnode cpu;
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + u32 rate;
> +
> + dev->priv = dev_read_addr_ptr(dev);
> + if (!dev->priv)
> + return -EINVAL;
> +
> + /* Did we get our clock rate from the device tree? */
> + if (uc_priv->clock_rate)
> + return 0;
> +
> + /* Fall back to timebase-frequency */
> + cpu = ofnode_path("/cpus");
> + if (!ofnode_valid(cpu))
> + return -EINVAL;
> +
> + ret = ofnode_read_u32(cpu, "timebase-frequency", &rate);
> + if (ret)
> + return ret;
> +
> + log_warning("missing clocks or clock-frequency property, falling back
> on timebase-frequency\n");
> + uc_priv->clock_rate = rate;
> +
> + return 0;
> +}
> +
> static const struct udevice_id sifive_clint_ids[] = {
> - { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
RISCV_SYSCON_CLINT should be removed from syscon.h
> + { .compatible = "riscv,clint0" },
> { }
> };
>
> U_BOOT_DRIVER(sifive_clint) = {
> .name = "sifive_clint",
> - .id = UCLASS_SYSCON,
> + .id = UCLASS_TIMER,
> .of_match = sifive_cl
Re: [PATCH v2 0/7] riscv: Clean up timer drivers
Hi Sean, On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote: > > This series cleans up the timer drivers in RISC-V and converts them to DM. > > This series depends on [1]. This series needs to be tested! I have only tested > it on QEMU and the K210. Notably, this means that the HiFive and anything > Andes > is completely untested. CI for this series is located at [2]. > > [1] https://patchwork.ozlabs.org/project/uboot/list/?series=190862 > [2] https://dev.azure.com/seanga2/u-boot/_build/results?buildId=4 > > Changes in v2: > - Remove RISCV_RDTIME KConfig option > - Split Kendryte binding changes into their own commit > - Fix SiFive CLINT not getting tick-rate from rtcclk This series does not apply to u-boot/master. Please rebase. Regards, Bin
Re: [PATCH v2 6/7] riscv: Update Kendryte device tree for new CLINT driver
On Wed, Jul 29, 2020 at 5:57 PM Sean Anderson wrote:
>
> AFAIK because the K210 clock driver does not come up until after
> relocation, the clint will always use the clock-frequency parameter.
> Ideally, it should update itself after relocation to take into account the
> actual CPU frequency.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v2:
> - New
>
> arch/riscv/dts/k210.dtsi | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
> index 2546c7d4e0..2698a33a5c 100644
> --- a/arch/riscv/dts/k210.dtsi
> +++ b/arch/riscv/dts/k210.dtsi
> @@ -17,6 +17,8 @@
> compatible = "kendryte,k210";
>
> aliases {
> + cpu0 = &cpu0;
> + cpu1 = &cpu1;
> dma0 = &dmac0;
> gpio0 = &gpio0;
> gpio1 = &gpio1_0;
> @@ -126,14 +128,15 @@
> read-only;
> };
>
> - clint0: interrupt-controller@200 {
> + clint0: clint@200 {
> #interrupt-cells = <1>;
> compatible = "kendryte,k210-clint", "riscv,clint0";
> reg = <0x200 0xC000>;
> - interrupt-controller;
Why is this property dropped?
> interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> <&cpu1_intc 3>, <&cpu1_intc 7>;
> - clocks = <&sysclk K210_CLK_CPU>;
> + clocks = <&sysclk K210_CLK_CLINT>;
> + /* sysclk is only available post-relocation */
> + clock-frequency = <780>;
> };
>
> plic0: interrupt-controller@C00 {
> --
Regards,
Bin
Re: [PATCH] xilinx: Enable preboot feature for ZynqMP and Versal
st 19. 8. 2020 v 9:39 odesílatel Michal Simek napsal: > > Enable preboot functionality for ZynqMP and Versal platforms. > > Signed-off-by: Michal Simek > --- > > configs/xilinx_versal_virt_defconfig | 1 + > configs/xilinx_zynqmp_virt_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/xilinx_versal_virt_defconfig > b/configs/xilinx_versal_virt_defconfig > index 5075cf2f688a..49138278f1ef 100644 > --- a/configs/xilinx_versal_virt_defconfig > +++ b/configs/xilinx_versal_virt_defconfig > @@ -9,6 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y > CONFIG_FIT=y > CONFIG_FIT_VERBOSE=y > CONFIG_BOOTDELAY=5 > +CONFIG_USE_PREBOOT=y > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_BOARD_EARLY_INIT_R=y > CONFIG_SYS_PROMPT="Versal> " > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index cf07df8145cc..7ed88ae09403 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -15,6 +15,7 @@ CONFIG_FIT=y > CONFIG_FIT_VERBOSE=y > CONFIG_SPL_LOAD_FIT=y > CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 > +CONFIG_USE_PREBOOT=y > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_BOARD_EARLY_INIT_F=y > CONFIG_BOARD_EARLY_INIT_R=y > -- > 2.28.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers
čt 13. 8. 2020 v 14:35 odesílatel Michal Simek napsal: > > Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in > PL and vice versa. That's why change dependencies and do not limit enabling > just for some platforms. > > Signed-off-by: Michal Simek > --- > > drivers/gpio/Kconfig | 4 ++-- > drivers/i2c/Kconfig | 2 +- > drivers/mmc/Kconfig | 1 - > drivers/net/Kconfig | 6 +++--- > 4 files changed, 6 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 11e9a17f9729..202fcc6f4759 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -381,8 +381,8 @@ config MVEBU_GPIO > > config ZYNQ_GPIO > bool "Zynq GPIO driver" > - depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) > - default y > + depends on DM_GPIO > + default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL > help > Supports GPIO access on Zynq SoC. > > diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig > index dec6dc9dfa4d..8ae54e1e93b0 100644 > --- a/drivers/i2c/Kconfig > +++ b/drivers/i2c/Kconfig > @@ -88,7 +88,7 @@ config SYS_I2C_FSL > > config SYS_I2C_CADENCE > tristate "Cadence I2C Controller" > - depends on DM_I2C && (ARCH_ZYNQ || ARM64) > + depends on DM_I2C > help > Say yes here to select Cadence I2C Host Controller. This controller > is > e.g. used by Xilinx Zynq. > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig > index 556b3ac48978..c29d1ea680ef 100644 > --- a/drivers/mmc/Kconfig > +++ b/drivers/mmc/Kconfig > @@ -653,7 +653,6 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK > > config MMC_SDHCI_ZYNQ > bool "Arasan SDHCI controller support" > - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL > depends on DM_MMC && OF_CONTROL && BLK > depends on MMC_SDHCI > help > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index ecd779d979e4..039f9fb05899 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -519,7 +519,7 @@ config TULIP > This driver supports DEC DC2114x Fast ethernet chips. > > config XILINX_AXIEMAC > - depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) > + depends on DM_ETH > select PHYLIB > select MII > bool "Xilinx AXI Ethernet" > @@ -527,7 +527,7 @@ config XILINX_AXIEMAC > This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. > > config XILINX_EMACLITE > - depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS) > + depends on DM_ETH > select PHYLIB > select MII > bool "Xilinx Ethernetlite" > @@ -535,7 +535,7 @@ config XILINX_EMACLITE > This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. > > config ZYNQ_GEM > - depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) > + depends on DM_ETH > select PHYLIB > bool "Xilinx Ethernet GEM" > help > -- > 2.28.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
On 20.08.20 09:43, Pali Rohár wrote:
On Thursday 20 August 2020 07:05:58 Stefan Roese wrote:
On 19.08.20 15:57, Pali Rohár wrote:
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
Adding more #ifdef's is not recommended. Can't you "depend" this driver
on DM_GPIO in Kconfig instead? Are there any used that don't support
DM_GPIO right now?
I'm not sure if this dependency is what people want. CCing Simon.
In past Simon created commit bcee8d6764f9215f16b393a35581000178633254
where described that want to build SPL without GPIO uclass support.
Is this PCI driver ever built into SPL?
Thanks,
Stefan
Re: [PATCH v3] i2c: eeprom: Use reg property instead of offset and size
st 22. 7. 2020 v 12:14 odesílatel Michal Simek napsal:
>
> Remove adhoc dt binding for fixed-partition definition for i2c eeprom.
> fixed-partition are using reg property instead of offset/size pair.
>
> Signed-off-by: Michal Simek
> ---
>
> Changes in v3:
> - Add test for sandbox
> - Fix issues related to OF_TRANSLATE
> - Remove address/size cells from parent because of OF_TRANSLATE
>
> Changes in v2:
> - Bootcount tested on zynqmp zcu104
> - Add missing address/size cells
> - Use dev_read_addr_size_index
> - Check parameters
>
> Just build tested - ge_bx50v3_defconfig
> Tested on zcu104
>
> ---
> arch/arm/dts/imx53-ppd-uboot.dtsi| 12 ++--
> arch/arm/dts/imx6q-bx50v3-uboot.dtsi | 10 +-
> arch/sandbox/dts/test.dts| 13 +
> configs/sandbox_defconfig| 1 +
> drivers/misc/i2c_eeprom.c| 15 ---
> test/dm/bootcount.c | 8
> 6 files changed, 41 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi
> b/arch/arm/dts/imx53-ppd-uboot.dtsi
> index d38a1bc264c9..d61b7cb87642 100644
> --- a/arch/arm/dts/imx53-ppd-uboot.dtsi
> +++ b/arch/arm/dts/imx53-ppd-uboot.dtsi
> @@ -24,15 +24,15 @@
> &eeprom {
> partitions {
> compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
>
> - vpd {
> - offset = <0>;
> - size = <1022>;
> + vpd@0 {
> + reg = <0 1022>;
> };
>
> - bootcount: bootcount {
> - offset = <1022>;
> - size = <2>;
> + bootcount: bootcount@1022 {
> + reg = <1022 2>;
> };
> };
> };
> diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
> b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
> index df446e0ed149..01321cab781b 100644
> --- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
> +++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
> @@ -23,15 +23,15 @@
> &eeprom {
> partitions {
> compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
>
> - vpd {
> - offset = <0>;
> - size = <1022>;
> + vpd@0 {
> + reg = <0 1022>;
> };
>
> bootcount: bootcount {
> - offset = <1022>;
> - size = <2>;
> + reg = <1022 2>;
> };
> };
> };
> diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
> index 1b33cd4c0878..19522a9e4778 100644
> --- a/arch/sandbox/dts/test.dts
> +++ b/arch/sandbox/dts/test.dts
> @@ -403,6 +403,14 @@
> reg = <0x2c>;
> compatible = "i2c-eeprom";
> sandbox,emul = <&emul_eeprom>;
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bootcount_i2c: bootcount@10 {
> + reg = <10 2>;
> + };
> + };
> };
>
> rtc_0: rtc@43 {
> @@ -450,6 +458,11 @@
> offset = <0x13>;
> };
>
> + bootcount {
> + compatible = "u-boot,bootcount-i2c-eeprom";
> + i2c-eeprom = <&bootcount_i2c>;
> + };
> +
> adc@0 {
> compatible = "sandbox,adc";
> vdd-supply = <&buck2>;
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index 6059d668af77..320e564eb8e7 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -106,6 +106,7 @@ CONFIG_AXI_SANDBOX=y
> CONFIG_BOOTCOUNT_LIMIT=y
> CONFIG_DM_BOOTCOUNT=y
> CONFIG_DM_BOOTCOUNT_RTC=y
> +CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
> CONFIG_CLK=y
> CONFIG_CLK_COMPOSITE_CCF=y
> CONFIG_SANDBOX_CLK_CCF=y
> diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
> index 45c34d388c8a..3651ba4871ef 100644
> --- a/drivers/misc/i2c_eeprom.c
> +++ b/drivers/misc/i2c_eeprom.c
> @@ -301,19 +301,20 @@ static int i2c_eeprom_partition_probe(struct udevice
> *dev)
> static int i2c_eeprom_partition_ofdata_to_platdata(struct udevice *dev)
> {
> struct i2c_eeprom_partition *priv = dev_get_priv(dev);
> - u32 offset, size;
> + u32 reg[2];
> int ret;
>
> - ret = dev_read_u32(dev, "offset", &offset);
> + ret = dev_read_u32_array(dev, "reg", reg, 2);
> if (ret)
> return ret;
>
> - ret = dev_read_u32(dev, "size", &size);
> - if (ret)
> - return ret;
> + if (!reg[1])
> + return
Re: [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
On Thursday 20 August 2020 09:48:17 Stefan Roese wrote:
> On 20.08.20 09:43, Pali Rohár wrote:
> > On Thursday 20 August 2020 07:05:58 Stefan Roese wrote:
> > > On 19.08.20 15:57, Pali Rohár wrote:
> > > > This change ensures that PCIe card is put into reset state when U-Boot
> > > > stops using it.
> > > >
> > > > DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
> > > > prior booting Linux kernel.
> > > >
> > > > Linux kernel pci-aardvark driver needs to reset PCIe card via PERST#
> > > > signal
> > > > prior initializing it. If it does not issue reset then some PCIe cards
> > > > (specially Compex WiFi cards) are not detected at all.
> > > >
> > > > Putting PCIe card into reset state prior booting Linux kernel would
> > > > ensure
> > > > that card would be properly reset at time when Linux kernel starts
> > > > initializing pci-aardvark driver.
> > > >
> > > > Signed-off-by: Pali Rohár
> > > > ---
> > > >drivers/pci/pci-aardvark.c | 27 +--
> > > >1 file changed, 21 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
> > > > index 5b3f23c184..8996be5309 100644
> > > > --- a/drivers/pci/pci-aardvark.c
> > > > +++ b/drivers/pci/pci-aardvark.c
> > > > @@ -148,6 +148,9 @@ struct pcie_advk {
> > > > void *base;
> > > > intfirst_busno;
> > > > struct udevice *dev;
> > > > +#if CONFIG_IS_ENABLED(DM_GPIO)
> > > > + struct gpio_desc reset_gpio;
> > > > +#endif
> > > >};
> > >
> > > Adding more #ifdef's is not recommended. Can't you "depend" this driver
> > > on DM_GPIO in Kconfig instead? Are there any used that don't support
> > > DM_GPIO right now?
> >
> > I'm not sure if this dependency is what people want. CCing Simon.
> >
> > In past Simon created commit bcee8d6764f9215f16b393a35581000178633254
> > where described that want to build SPL without GPIO uclass support.
>
> Is this PCI driver ever built into SPL?
SPL is not used for Espressobin and Turris MOX. But I'm not sure for
other boards. Maybe Simon could provide more information about it.
Basically I added GPIO handling in aardvark driver as it was used on
other place.
Re: [PATCH] xilinx: Fix xlnx,mio_bank property
pá 24. 7. 2020 v 9:01 odesílatel Michal Simek napsal:
>
> s/xlnx,mio_bank/xlnx,mio-bank/g
>
> DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
> also driver itself.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 2 +-
> arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 2 +-
> arch/arm/dts/versal-mini-emmc0.dts| 2 +-
> arch/arm/dts/versal-mini-emmc1.dts| 2 +-
> arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +-
> arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +-
> arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4 ++--
> arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 4 ++--
> arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 4 ++--
> arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 4 ++--
> arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 4 ++--
> arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 ++--
> arch/arm/dts/zynqmp-zcu100-revC.dts | 4 ++--
> arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +-
> arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +-
> drivers/mmc/zynq_sdhci.c | 2 +-
> 23 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> index ac641ff1a582..85ab9e9e29ab 100644
> --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> @@ -51,7 +51,7 @@
> /* microSD card slot */
> &sdhci1 {
> status = "okay";
> - xlnx,mio_bank = <1>;
> + xlnx,mio-bank = <1>;
> clock-frequency = <18000>;
> max-frequency = <5000>;
> no-1-8-v;
> diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> index b635db649f43..cbcb290a5c83 100644
> --- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> +++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> @@ -51,6 +51,6 @@
> /* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
> &sdhci0 {
> status = "okay";
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> clock-frequency = <18000>;
> };
> diff --git a/arch/arm/dts/versal-mini-emmc0.dts
> b/arch/arm/dts/versal-mini-emmc0.dts
> index 7f57d232b7f9..7826a282134b 100644
> --- a/arch/arm/dts/versal-mini-emmc0.dts
> +++ b/arch/arm/dts/versal-mini-emmc0.dts
> @@ -43,7 +43,7 @@
> clocks = <&clk25 &clk25>;
> xlnx,device_id = <0>;
> no-1-8-v;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> #stream-id-cells = <1>;
> };
> };
> diff --git a/arch/arm/dts/versal-mini-emmc1.dts
> b/arch/arm/dts/versal-mini-emmc1.dts
> index 4e0758f61893..2f28f856a6a3 100644
> --- a/arch/arm/dts/versal-mini-emmc1.dts
> +++ b/arch/arm/dts/versal-mini-emmc1.dts
> @@ -43,7 +43,7 @@
> clocks = <&clk25 &clk25>;
> xlnx,device_id = <1>;
> no-1-8-v;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> #stream-id-cells = <1>;
> };
> };
> diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> index c260411d7571..a8bbb14f6cd1 100644
> --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> @@ -131,7 +131,7 @@
> status = "okay";
> no-1-8-v;
> disable-wp;
> - xlnx,mio_bank = <1>;
> + xlnx,mio-bank = <1>;
> };
>
> &gem0 {
> diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> index 09da60b10072..9468dc574fd8 100644
> --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> @@ -70,7 +70,7 @@
> non-removable;
> disable-wp;
> bus-width = <8>;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> };
>
> &uart0 { /* uart0 MIO38-39 */
> diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA
Re: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
Hi Kosta,
this one as well please. ;)
Thanks,
Stefan
On 19.08.20 19:31, Kostya Porotchkin wrote:
From: Pali Rohár
Sent: Wednesday, August 19, 2020 16:57
To: Stefan Roese; Kostya Porotchkin
Cc: u-boot@lists.denx.de
Subject: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when
unloading driver
External Email
--
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_GPIO)
- struct gpio_desc reset_gpio;
-
- gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
* possible before PCIe PHY initialization. Moreover, the PCIe
* clock should be gated as well.
*/
- if (dm_gpio_is_valid(&reset_gpio)) {
+ if (dm_gpio_is_valid(&pcie->reset_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(&reset_gpio, 1);
+ dm_gpio_set_value(&pcie->reset_gpio, 1);
mdelay(200);
- dm_gpio_set_value(&reset_gpio, 0);
+ dm_gpio_set_value(&pcie->reset_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
@@ -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
return pcie_advk_setup_hw(pcie);
}
+static int pcie_advk_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(&pcie->reset_gpio))
+ dm_gpio_set_value(&pcie->reset_gpio, 1);
+#endif /* DM_GPIO */
+
+ return 0;
+}
+
/**
* pcie_advk_ofdata_to_platdata() - Translate from DT to device state
*
@@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
.ops= &pcie_advk_ops,
.ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
.probe = pcie_advk_probe,
+ .remove = pcie_advk_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.priv_auto_alloc_size = sizeof(struct pcie_advk),
};
--
2.20.1
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] mmc: zynq: Fix default value for xlnx,mio-bank
pá 24. 7. 2020 v 9:03 odesílatel Michal Simek napsal: > > DT binding is saying that default value is 0 not -1 that's why fix it. > > Signed-off-by: Michal Simek > --- > > Depends on https://lists.denx.de/pipermail/u-boot/2020-July/421231.html > --- > drivers/mmc/zynq_sdhci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c > index 6505527616d1..e9381b949307 100644 > --- a/drivers/mmc/zynq_sdhci.c > +++ b/drivers/mmc/zynq_sdhci.c > @@ -276,7 +276,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice > *dev) > return PTR_ERR(priv->host->ioaddr); > > priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); > - priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", -1); > + priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0); > > return 0; > } > -- > 2.27.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 0/8] xilinx: zynqmp: Silicon name cleanup
st 5. 8. 2020 v 13:23 odesílatel Michal Simek napsal: > > Hi, > > This patch series is intended to cleanup the functions used to get > the silicon name for ZynqMPSoC devices. It make use the firmware driver > rather than SMC call and impements more understandable agorithm to > compute the device name. > > Thanks, > Ibai/Michal > > > Ibai Erkiaga (7): > xilinx: zynqmp: synchronize firmware call return payload > xilinx: zynqmp: merge firmware calls for EL2 and EL3 > xilinx: zynqmp: get chip ID using firmware driver > xilinx: zynqmp: get chip ID at EL3 > xilinx: zynqmp: remove chip_id function Applied all above. > xilinx: zynqmp: refactor silicon name function This one needs to be fixed that's why not applied. > xilinx: zynqmp: fix incorrect map not align with IPI HW Applied this one > > Michal Simek (1): > xilinx: zynqmp: Remove one static variable It depends on the patch above that's why it is not applied. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: versal: Enable i2c misc eeprom driver
st 5. 8. 2020 v 14:00 odesílatel Michal Simek napsal: > > Enable this driver to be able to work with i2c based eeproms on Versal. > > Signed-off-by: Michal Simek > --- > > configs/xilinx_versal_virt_defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/configs/xilinx_versal_virt_defconfig > b/configs/xilinx_versal_virt_defconfig > index 5075cf2f688a..e034c001f8f9 100644 > --- a/configs/xilinx_versal_virt_defconfig > +++ b/configs/xilinx_versal_virt_defconfig > @@ -43,6 +43,9 @@ CONFIG_FPGA_VERSALPL=y > CONFIG_DM_I2C=y > CONFIG_SYS_I2C_CADENCE=y > CONFIG_MISC=y > +CONFIG_I2C_EEPROM=y > +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 > +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 > CONFIG_MMC_IO_VOLTAGE=y > CONFIG_MMC_UHS_SUPPORT=y > CONFIG_MMC_HS400_SUPPORT=y > -- > 2.27.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: Add support for ENV_VARS_UBOOT_RUNTIME_CONFIG
st 5. 8. 2020 v 14:01 odesílatel Michal Simek napsal:
>
> Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG to enable/disable updating
> variables with run time information.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/Kconfig | 3 +++
> board/xilinx/versal/board.c | 3 +++
> board/xilinx/zynq/board.c| 8
> board/xilinx/zynqmp/zynqmp.c | 3 +++
> 4 files changed, 17 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 156698f23d48..7e54288ad789 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1075,6 +1075,7 @@ config ARCH_VERSAL
> select DM_SERIAL
> select OF_CONTROL
> imply BOARD_LATE_INIT
> + imply ENV_VARS_UBOOT_RUNTIME_CONFIG
>
> config ARCH_VF610
> bool "Freescale Vybrid"
> @@ -1110,6 +,7 @@ config ARCH_ZYNQ
> imply CMD_CLK
> imply CMD_DM
> imply CMD_SPL
> + imply ENV_VARS_UBOOT_RUNTIME_CONFIG
> imply FAT_WRITE
>
> config ARCH_ZYNQMP_R5
> @@ -1149,6 +1151,7 @@ config ARCH_ZYNQMP
> select ZYNQMP_IPI
> imply BOARD_LATE_INIT
> imply CMD_DM
> + imply ENV_VARS_UBOOT_RUNTIME_CONFIG
> imply FAT_WRITE
> imply MP
> imply DM_USB_GADGET
> diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
> index 3dc7044b213e..a5ca4ca87401 100644
> --- a/board/xilinx/versal/board.c
> +++ b/board/xilinx/versal/board.c
> @@ -116,6 +116,9 @@ int board_late_init(void)
> return 0;
> }
>
> + if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
> + return 0;
> +
> bootmode = versal_get_bootmode();
>
> puts("Bootmode: ");
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> index 2164eac8d518..f98497eb73d6 100644
> --- a/board/xilinx/zynq/board.c
> +++ b/board/xilinx/zynq/board.c
> @@ -33,6 +33,14 @@ int board_late_init(void)
> char *new_targets;
> char *env_targets;
>
> + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
> + debug("Saved variables - Skipping\n");
> + return 0;
> + }
> +
> + if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
> + return 0;
> +
> switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
> case ZYNQ_BM_QSPI:
> mode = "qspi";
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index e8ea3c5a4975..de25f804fcd7 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -521,6 +521,9 @@ int board_late_init(void)
> return 0;
> }
>
> + if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
> + return 0;
> +
> ret = set_fdtfile();
> if (ret)
> return ret;
> --
> 2.27.0
>
Applied with adding missing log.h to zynq/board.c
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: Change logic around zynq_board_read_rom_ethaddr()
st 5. 8. 2020 v 14:02 odesílatel Michal Simek napsal:
>
> There is no reason to build private function when
> CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET is not defined. There is already weak
> function which handles default case properly.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/common/board.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
> index 3bca3a25a97b..0782d08ee3fe 100644
> --- a/board/xilinx/common/board.c
> +++ b/board/xilinx/common/board.c
> @@ -13,11 +13,10 @@
> #include
> #include "board.h"
>
> +#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
> int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
> {
> int ret = -EINVAL;
> -
> -#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
> struct udevice *dev;
> ofnode eeprom;
>
> @@ -37,10 +36,10 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
> debug("%s: I2C EEPROM MAC address read failed\n", __func__);
> else
> debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
> -#endif
>
> return ret;
> }
> +#endif
>
> #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
> void *board_fdt_blob_setup(void)
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 0/4] xilinx: common: Fix fdt/initrd_high and bootm_* variables
st 12. 8. 2020 v 12:42 odesílatel Michal Simek napsal: > > Hi, > > this series is removing fdt/initrd_high variables and tune bootm_size run > time setup to match needs from Linux kernel. > > Thanks, > Michal > > > Michal Simek (4): > xilinx: common: Get rid of fdt_high variable > xilinx: common: Get rid of initrd_high variable setup > xilinx: common: Check return value from variable setup > xilinx: common: Change bootm_size variable setting > > board/xilinx/common/board.c | 17 ++--- > include/configs/xilinx_versal.h | 1 - > include/configs/xilinx_zynqmp.h | 1 - > include/configs/zynq-common.h | 1 - > 4 files changed, 10 insertions(+), 10 deletions(-) > > -- > 2.28.0 > Applied all. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
On 20.08.20 09:52, Pali Rohár wrote:
On Thursday 20 August 2020 09:48:17 Stefan Roese wrote:
On 20.08.20 09:43, Pali Rohár wrote:
On Thursday 20 August 2020 07:05:58 Stefan Roese wrote:
On 19.08.20 15:57, Pali Rohár wrote:
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
Adding more #ifdef's is not recommended. Can't you "depend" this driver
on DM_GPIO in Kconfig instead? Are there any used that don't support
DM_GPIO right now?
I'm not sure if this dependency is what people want. CCing Simon.
In past Simon created commit bcee8d6764f9215f16b393a35581000178633254
where described that want to build SPL without GPIO uclass support.
Is this PCI driver ever built into SPL?
SPL is not used for Espressobin and Turris MOX. But I'm not sure for
other boards. Maybe Simon could provide more information about it.
AFAIK (I did not work on Armada for quite some time), only 32bit
Armada uses SPL. All 64bit Aramda 37xx / 7xxx / 8xxx do not use
SPL.
Basically I added GPIO handling in aardvark driver as it was used on
other place.
I understand.
I suggest to "depend" this driver on DM_GPIO and include the GPIO code
without any #ifdef's. And please run a world-build (buildman, Travis...)
to see, if nothing breaks.
Thanks,
Stefan
Re: [PATCH] clk: versal: Move pm_query_id out of clock driver
pá 24. 7. 2020 v 14:26 odesílatel Michal Simek napsal:
>
> There is no reason to have firmware specific structure in clock driver.
> Move it to generic location and also initialize enum values which is based
> on
> https://lore.kernel.org/linux-arm-kernel/20200318125003.ga2727...@kroah.com/
> recommended way to go to make sure that values guaranteed by compiler.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/clk/clk_versal.c | 17 -
> include/zynqmp_firmware.h | 17 +
> 2 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
> index 6f82b60f04db..d93b860aed35 100644
> --- a/drivers/clk/clk_versal.c
> +++ b/drivers/clk/clk_versal.c
> @@ -68,23 +68,6 @@
> #define CLOCK_NODE_TYPE_DIV4
> #define CLOCK_NODE_TYPE_GATE 6
>
> -enum pm_query_id {
> - PM_QID_INVALID,
> - PM_QID_CLOCK_GET_NAME,
> - PM_QID_CLOCK_GET_TOPOLOGY,
> - PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
> - PM_QID_CLOCK_GET_PARENTS,
> - PM_QID_CLOCK_GET_ATTRIBUTES,
> - PM_QID_PINCTRL_GET_NUM_PINS,
> - PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
> - PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
> - PM_QID_PINCTRL_GET_FUNCTION_NAME,
> - PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
> - PM_QID_PINCTRL_GET_PIN_GROUPS,
> - PM_QID_CLOCK_GET_NUM_CLOCKS,
> - PM_QID_CLOCK_GET_MAX_DIVISOR,
> -};
> -
> enum clk_type {
> CLK_TYPE_OUTPUT,
> CLK_TYPE_EXTERNAL,
> diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
> index 93d771ece26a..98e20a466e24 100644
> --- a/include/zynqmp_firmware.h
> +++ b/include/zynqmp_firmware.h
> @@ -62,6 +62,23 @@ enum pm_api_id {
> PM_API_MAX,
> };
>
> +enum pm_query_id {
> + PM_QID_INVALID = 0,
> + PM_QID_CLOCK_GET_NAME = 1,
> + PM_QID_CLOCK_GET_TOPOLOGY = 2,
> + PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
> + PM_QID_CLOCK_GET_PARENTS = 4,
> + PM_QID_CLOCK_GET_ATTRIBUTES = 5,
> + PM_QID_PINCTRL_GET_NUM_PINS = 6,
> + PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
> + PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
> + PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
> + PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
> + PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
> + PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
> + PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
> +};
> +
> #define PM_SIP_SVC 0xc200
>
> #define ZYNQMP_PM_VERSION_MAJOR 1
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] mmc: sdhci: Enable high speed conditional on the correspnding bit
Hi,
čt 13. 8. 2020 v 12:48 odesílatel Michal Simek napsal:
>
> Hi Peng,
>
> st 29. 7. 2020 v 17:07 odesílatel Michal Simek napsal:
> >
> > Hi,
> >
> > čt 23. 7. 2020 v 6:12 odesílatel Faiz Abbas napsal:
> > >
> > > The capabilities register has a field to indicate whether the host
> > > supports high speed mode or not. Add high speed host_caps based on
> > > this bit instead of enabling it by default.
> > >
> > > Signed-off-by: Faiz Abbas
> > > ---
> > > drivers/mmc/sdhci.c | 5 -
> > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> > > index 16989dcf05..48d639fe93 100644
> > > --- a/drivers/mmc/sdhci.c
> > > +++ b/drivers/mmc/sdhci.c
> > > @@ -866,7 +866,10 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
> > > sdhci_host *host,
> > > if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
> > > cfg->voltages |= host->voltages;
> > >
> > > - cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
> > > + if (caps & SDHCI_CAN_DO_HISPD)
> > > + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
> > > +
> > > + cfg->host_caps |= MMC_MODE_4BIT;
> > >
> > > /* Since Host Controller Version3.0 */
> > > if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
> > > --
> > > 2.17.1
> > >
> >
> > Reviewed-by: Michal Simek
> > Tested-by: Michal Simek (zcu104 with
> > sdhci-caps-mask = <0 0x20>;)
>
> Peng: Can you please take this patch to your tree? Or I will take it.
I applied this patch but I have fixed typo in subject.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] mmc: sdhci: Use upper/lower_32_bits macros
st 29. 7. 2020 v 15:44 odesílatel Michal Simek napsal:
>
> Instead of recasting and shifting use macros which are designed for taking
> upper/lower 32bit value from 64bit variable.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/mmc/sdhci.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index ec6c493fb642..f5fbbacee542 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -749,9 +749,9 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
> sdhci_host *host,
> "sdhci-caps-mask", 0);
> dt_caps = dev_read_u64_default(host->mmc->dev,
>"sdhci-caps", 0);
> - caps = ~(u32)dt_caps_mask &
> + caps = ~lower_32_bits(dt_caps_mask) &
>sdhci_readl(host, SDHCI_CAPABILITIES);
> - caps |= (u32)dt_caps;
> + caps |= lower_32_bits(dt_caps);
> #else
> caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> #endif
> @@ -794,9 +794,9 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
> sdhci_host *host,
> /* Check whether the clock multiplier is supported or not */
> if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
> #if CONFIG_IS_ENABLED(DM_MMC)
> - caps_1 = ~(u32)(dt_caps_mask >> 32) &
> + caps_1 = ~upper_32_bits(dt_caps_mask) &
> sdhci_readl(host, SDHCI_CAPABILITIES_1);
> - caps_1 |= (u32)(dt_caps >> 32);
> + caps_1 |= upper_32_bits(dt_caps);
> #else
> caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
> #endif
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
RE: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
> -Original Message-
> From: Pali Rohár
> Sent: Wednesday, August 19, 2020 16:57
> To: Stefan Roese ; Kostya Porotchkin
> Cc: u-boot@lists.denx.de
> Subject: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when
> unloading driver
>
> External Email
>
> --
> This change ensures that PCIe card is put into reset state when U-Boot stops
> using it.
>
> DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove
> callback prior booting Linux kernel.
>
> Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
> prior initializing it. If it does not issue reset then some PCIe cards
> (specially
> Compex WiFi cards) are not detected at all.
>
> Putting PCIe card into reset state prior booting Linux kernel would ensure
> that card would be properly reset at time when Linux kernel starts
> initializing
> pci-aardvark driver.
>
> Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
> ---
> drivers/pci/pci-aardvark.c | 27 +--
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index
> 5b3f23c184..8996be5309 100644
> --- a/drivers/pci/pci-aardvark.c
> +++ b/drivers/pci/pci-aardvark.c
> @@ -148,6 +148,9 @@ struct pcie_advk {
> void *base;
> intfirst_busno;
> struct udevice *dev;
> +#if CONFIG_IS_ENABLED(DM_GPIO)
> + struct gpio_desc reset_gpio;
> +#endif
> };
>
> static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
> @@ -
> 614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
> struct pcie_advk *pcie = dev_get_priv(dev);
>
> #if CONFIG_IS_ENABLED(DM_GPIO)
> - struct gpio_desc reset_gpio;
> -
> - gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio,
> + gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
>GPIOD_IS_OUT);
> /*
>* Issue reset to add-in card through the dedicated GPIO.
> @@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
>* possible before PCIe PHY initialization. Moreover, the PCIe
>* clock should be gated as well.
>*/
> - if (dm_gpio_is_valid(&reset_gpio)) {
> + if (dm_gpio_is_valid(&pcie->reset_gpio)) {
> dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
> - dm_gpio_set_value(&reset_gpio, 1);
> + dm_gpio_set_value(&pcie->reset_gpio, 1);
> mdelay(200);
> - dm_gpio_set_value(&reset_gpio, 0);
> + dm_gpio_set_value(&pcie->reset_gpio, 0);
> }
> #else
> dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n"); @@
> -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
> return pcie_advk_setup_hw(pcie);
> }
>
> +static int pcie_advk_remove(struct udevice *dev) { #if
> +CONFIG_IS_ENABLED(DM_GPIO)
> + struct pcie_advk *pcie = dev_get_priv(dev);
> +
> + if (dm_gpio_is_valid(&pcie->reset_gpio))
> + dm_gpio_set_value(&pcie->reset_gpio, 1); #endif /*
> DM_GPIO */
> +
> + return 0;
> +}
> +
> /**
> * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
> *
> @@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
> .ops= &pcie_advk_ops,
> .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
> .probe = pcie_advk_probe,
> + .remove = pcie_advk_remove,
> + .flags = DM_FLAG_OS_PREPARE,
> .priv_auto_alloc_size = sizeof(struct pcie_advk),
> };
> --
> 2.20.1
Re: [PATCH v5 11/11] riscv: Add FPIOA and GPIO support for Kendryte K210
Hi Sean > On 8/18/20 11:48 PM, Rick Chen wrote: > > Hi Tom > > > >> This patch adds the necessary configs and docs for FPIOA and GPIO support > >> on the K210. > >> > >> The board does not boot unless CONSOLE_LOGLEVEL is set to a non-default > >> value . It also boots when the tree is dirty (and CONSOLE_LOGLEVEL is not > >> changed). It also boots when changes are made to the device tree and then > >> committed. I don't know why this happens. These breakages only occur after > >> bf2fb81ad3. > >> > >> Signed-off-by: Sean Anderson > >> --- > >> > >> Changes in v5: > >> - Increase CONSOLE_LOGLEVEL to 5 as a hack to get the board booting again > >> - Patch 05/12 "gpio: sifive: Use generic reg read function" has been > >> superseded > >> by commit 2548493ab4. > > > > Would you like to pick up this series, [PATCH v5 00/11] riscv: Add > > FPIOA and GPIO support for Kendryte K210 ? > > Or maybe it is better to figure out what is wrong here and find the > > root cause why it need to Increase CONSOLE_LOGLEVEL to 5 as a hack ? > > As an additional note, *CONFIG_LOGLEVEL (whoops) can also be decreased > for the same effect. In addition, there are several other ways I found > to "fix" this bug (as noted in the commit message). If you would like to > test this out, I have two trees [1, 2] where this series (actually a slightly > earlier version of this series) is applied just before and just after > bf2fb81ad3. The original patch is located at [3]. > > --Sean > > [1] https://github.com/Forty-Bot/u-boot/tree/maix_gpio_good > [2] https://github.com/Forty-Bot/u-boot/tree/maix_gpio_bad > [3] > https://patchwork.ozlabs.org/project/uboot/patch/20200724111225.12513-15-ovidiu.pan...@windriver.com/ I don't have a K210 board for verification. But it is OK to run in AE350 board after applying your series. After check about this commit "common/board_r: Remove initr_serial wrapper", it seem shall not affect anything. It just change to call serial_initialize directly. Only I can think about maybe it is a cache problem. Just like sometime we add a printf, then the problem will be walk around. Thanks, Rick
Re: [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
On 20.08.20 09:40, Pali Rohár wrote: On Thursday 20 August 2020 07:02:18 Stefan Roese wrote: Can't you just use "mtdparts=" kernel cmdline parameter instead to pass the MTD layout to the kernel? Maybe it is possible too, I have not tried it. I thought that more common is to update DTS file by uboot when loading kernel as it is already done e.g. for ethernet MAC address on Espressobin. Updating the MAC address is very common, yes. But passing the MTD partition layout via the mtdparts= cmdline is also very common and used very frequently. From my experience, its the defacto recommended method to pass this info and also easier than generating these DTS lines via some code. Please take a look at the mtdparts U-Boot command and its usage in other targets. Also I see that uboot has function fdt_fixup_mtdparts() via CONFIG_FDT_FIXUP_PARTITIONS option which do this, but uses uboot MTD code which IIRC cannot initialize SPI NOR. Why not? SPI NOR is also integrated into the U-Boot MTD world as well. Please see this GARDENA MT7688 target, which uses SPI NOR & SPI NAND: => mtd list List of MTD devices: * nor0 - type: NOR flash - block size: 0x1000 bytes - min I/O: 0x1 bytes - 0x-0x0080 : "nor0" - 0x-0x000a : "uboot" - 0x000a-0x000b : "uboot_env0" - 0x000b-0x000c : "uboot_env1" - 0x000c-0x000d : "factory" - 0x000d-0x0080 : "unused" * spi-nand0 - device: spi-nand@1 - parent: spi@b00 - driver: spi_nand - type: NAND flash - block size: 0x2 bytes - min I/O: 0x800 bytes - OOB size: 128 bytes - OOB available: 63 bytes - 0x-0x0800 : "spi-nand0" - 0x-0x0800 : "nand" => mtdparts device nor0 , # parts = 5 #: namesizeoffset mask_flags 0: uboot 0x000a 0x 0 1: uboot_env0 0x0001 0x000a 0 2: uboot_env1 0x0001 0x000b 0 3: factory 0x0001 0x000c 0 4: unused 0x0073 0x000d 0 device spi-nand0 , # parts = 1 #: namesizeoffset mask_flags 0: nand0x0800 0x 0 active partition: nor0,0 - (uboot) 0x000a @ 0x defaults: mtdids : spi-nand0=spi0.1,nor0=spi0.0 mtdparts: spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand) Anyway, updating DTS has advantage that it is not needed to update existing boot scripts for OS. There are more distributions for Espressobin which have own boot scripts stored on SD card for loading kernel. And therefore to use command line parameters it would be needed to update all of them. I see. This is an argument I understand. But can't you use the common fdt_fixup_mtdparts() then? And I see there another problem. For specifying size of mtd partitions in command line, it is required to know offsets of those partitions. And e.g. uboot env partition depends on CONFIG_ENV_OFFSET option which is not available for uboot boot script code. But if you have other idea, I'm open to also other solutions. I have not investigated a multi-distribution solution here. Perhaps the common fdt_fixup_mtdparts() is able to handle this? If not, then I won't stop this current patch. I just wanted to point out the more common and more elegant solutions to you. Thanks, Stefan
Re: [PATCH v2 2/9] mips: octeon: Add octeon-model.h header
Hi Daniel, On 19.08.20 16:01, Daniel Schwierzeck wrote: Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese: From: Aaron Williams This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- Changes in v2: - Some unsupported Octeon families removed (only Octeon 2 & 3 supported in general) .../mach-octeon/include/mach/octeon-model.h | 317 ++ 1 file changed, 317 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/octeon-model.h diff --git a/arch/mips/mach-octeon/include/mach/octeon-model.h b/arch/mips/mach-octeon/include/mach/octeon-model.h new file mode 100644 index 00..209e813a2f --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/octeon-model.h @@ -0,0 +1,317 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses this line is superfluous Ok. Will remove in next version (in all files). + */ + +#ifndef __OCTEON_MODEL_H__ +#define __OCTEON_MODEL_H__ + +/* NOTE: These must match what is checked in common-config.mk */ +/* Defines to represent the different versions of Octeon. */ + +/* + * IMPORTANT: When the default pass is updated for an Octeon Model, + * the corresponding change must also be made in the oct-sim script. + */ + +/* + * The defines below should be used with the OCTEON_IS_MODEL() macro to + * determine what model of chip the software is running on. Models ending + * in 'XX' match multiple models (families), while specific models match only + * that model. If a pass (revision) is specified, then only that revision + * will be matched. Care should be taken when checking for both specific + * models and families that the specific models are checked for first. + * While these defines are similar to the processor ID, they are not intended + * to be used by anything other that the OCTEON_IS_MODEL framework, and + * the values are subject to change at anytime without notice. + * + * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* macros + * should be used outside of this file. All other macros are for internal + * use only, and may change without notice. + */ should be just one multi-line comment block Okay. I'll move all comments into one comment block. Thanks, Stefan + +#define OCTEON_FAMILY_MASK 0x0000 +#define OCTEON_PRID_MASK 0x00ff + +/* Flag bits in top byte */ +/* Ignores revision in model checks */ +#define OM_IGNORE_REVISION0x0100 +/* Check submodels */ +#define OM_CHECK_SUBMODEL 0x0200 +/* Match all models previous than the one specified */ +#define OM_MATCH_PREVIOUS_MODELS 0x0400 +/* Ignores the minor revison on newer parts */ +#define OM_IGNORE_MINOR_REVISION 0x0800 +#define OM_FLAG_MASK 0xff00 + +/* Match all cn5XXX Octeon models. */ +#define OM_MATCH_5XXX_FAMILY_MODELS 0x2000 +/* Match all cn6XXX Octeon models. */ +#define OM_MATCH_6XXX_FAMILY_MODELS 0x4000 +/* Match all cnf7XXX Octeon models. */ +#define OM_MATCH_F7XXX_FAMILY_MODELS0x8000 +/* Match all cn7XXX Octeon models. */ +#define OM_MATCH_7XXX_FAMILY_MODELS 0x1000 +#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \ +OM_MATCH_6XXX_FAMILY_MODELS | \ +OM_MATCH_F7XXX_FAMILY_MODELS | \ +OM_MATCH_7XXX_FAMILY_MODELS) + +/* + * CN7XXX models with new revision encoding + */ + +#define OCTEON_CNF75XX_PASS1_0 0x000d9800 +#define OCTEON_CNF75XX_PASS1_2 0x000d9802 +#define OCTEON_CNF75XX_PASS1_3 0x000d9803 +#define OCTEON_CNF75XX (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF75XX_PASS1_X \ + (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN73XX_PASS1_0 0x000d9700 +#define OCTEON_CN73XX_PASS1_1 0x000d9701 +#define OCTEON_CN73XX_PASS1_2 0x000d9702 +#define OCTEON_CN73XX_PASS1_3 0x000d9703 +#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN73XX_PASS1_X \ + (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN72XX OCTEON_CN73XX + +#define OCTEON_CN23XX OCTEON_CN73XX +#define OCTEON_CN23XX_PASS1_2 OCTEON_CN73XX_PASS1_2 +#define OCTEON_CN23XX_PASS1_3 OCTEON_CN73XX_PASS1_3 + +#define OCTEON_CN70XX_PASS1_0 0x000d9600 +#define OCTEON_CN70XX_PASS1_1 0x000d9601 +#define OCTEON_CN70XX_PASS1_2 0x000d9602 + +#define OCTEON_CN70XX_PASS2_0 0x000d9608 + +#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN70XX_PASS1_X \ + (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN70XX
Re: [PATCH 5/9] xhci-ring.c: Add the poll_pend state to properly abort transactions
Hi Jason,
On Sat, Jul 25, 2020 at 5:51 AM Jason Wessel wrote:
>
> xhci_trl_tx and xhchi_bulk_tx can be called synchronously by other
> drivers such as the usb storage or network, while the keyboard driver
> exclusively uses the polling mode.
>
Could you provide more details as to when this will fail?
> And pending polling transactions must be aborted before switching
> modes to avoid corrupting the state of the controller.
>
> Signed-off-by: Jason Wessel
> ---
> drivers/usb/host/xhci-ring.c | 86 +---
> 1 file changed, 70 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> index b7b2e16410..d6339f4f0a 100644
> --- a/drivers/usb/host/xhci-ring.c
> +++ b/drivers/usb/host/xhci-ring.c
> @@ -24,6 +24,12 @@
>
> #include
>
> +static void *last_bulk_tx_buf;
> +static struct usb_device *poll_last_udev;
> +int poll_last_ep_index;
> +static unsigned long bulk_tx_poll_ts;
> +static bool poll_pend;
Should these variables go into struct xhci_ctrl? What happens if 2
controllers are sending data?
> +
> /**
> * Is this TRB a link TRB or was the last TRB the last TRB in this event ring
> * segment? I.e. would the updated event TRB pointer step off the end of the
> @@ -549,19 +555,8 @@ static void record_transfer_result(struct usb_device
> *udev,
> }
> }
>
> -/ Bulk and Control transfer methods /
> -/**
> - * Queues up the BULK Request
> - *
> - * @param udev pointer to the USB device structure
> - * @param pipe contains the DIR_IN or OUT , devnum
> - * @param length length of the buffer
> - * @param buffer buffer to be read/written based on the request
> - * @param nonblock when true do not block waiting for response
> - * @return returns 0 if successful else -1 on failure
> - */
> -int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
> - int length, void *buffer, bool nonblock)
> +static int _xhci_bulk_tx_queue(struct usb_device *udev, unsigned long pipe,
> + int length, void *buffer)
> {
> int num_trbs = 0;
> struct xhci_generic_trb *start_trb;
> @@ -575,7 +570,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
> struct xhci_virt_device *virt_dev;
> struct xhci_ep_ctx *ep_ctx;
> struct xhci_ring *ring; /* EP transfer ring */
> - union xhci_trb *event;
>
> int running_total, trb_buff_len;
> unsigned int total_packet_count;
> @@ -719,20 +713,73 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
> } while (running_total < length);
>
> giveback_first_trb(udev, ep_index, start_cycle, start_trb);
> + return 0;
> +}
>
> +/ Bulk and Control transfer methods /
> +/**
> + * Queues up the BULK Request
> + *
> + * @param udev pointer to the USB device structure
> + * @param pipe contains the DIR_IN or OUT , devnum
> + * @param length length of the buffer
> + * @param buffer buffer to be read/written based on the request
> + * @param nonblock when true do not block waiting for response
> + * @return returns 0 if successful else -1 on failure
> + */
> +int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
> +int length, void *buffer, bool nonblock)
> +{
> + u32 field;
> + int ret;
> + union xhci_trb *event;
> + struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
> + int ep_index = usb_pipe_ep_index(pipe);
> +
> + if (poll_pend) {
> + /*
> +* Abort a pending poll operation if it should have
> +* timed out, or if this is a different buffer from a
> +* separate request
> +*/
> + if (get_timer(bulk_tx_poll_ts) > XHCI_TIMEOUT ||
> + last_bulk_tx_buf != buffer || poll_last_udev != udev ||
> + ep_index != poll_last_ep_index) {
> + abort_td(poll_last_udev, poll_last_ep_index);
> + poll_last_udev->status = USB_ST_NAK_REC; /* closest
> thing to a timeout */
> + poll_last_udev->act_len = 0;
> + poll_pend = false;
> + }
> + } /* No else here because poll_pend might have changed above */
> + if (!poll_pend) {
> + last_bulk_tx_buf = buffer;
> + ret = _xhci_bulk_tx_queue(udev, pipe, length, buffer);
> + if (ret)
> + return ret;
> + }
> event = xhci_wait_for_event(ctrl, TRB_TRANSFER, nonblock);
> if (!event) {
> - if (nonblock)
> + if (nonblock) {
> + if (!poll_pend) {
> + /* Start the timer */
> + bulk_tx_poll_ts = get_timer(0);
> + poll_last_udev = udev;
> +
Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Hello, Am 19.08.20 um 21:54 schrieb Ralph Siemsen: > On Wed, Aug 19, 2020 at 09:28:39PM +0200, Marek Vasut wrote: >> >> Is the F2SDRAM port enabled in your case ? > > Is there a way I can check this via software? Unfortunately I do not > have access to Quartus/Qsys files, nor the person who did the design. Looking to the U-Boot driver "drivers/net/altera_tse.c" tells me, that it maps system memory for the SGDMA controller in its probe function. I found the Altera SoC Triple Speed Ethernet Design Example at [1]. And yes, it seems to use F2SDRAM as well. [1] https://rocketboards.org/foswiki/Projects/AlteraSoCTripleSpeedEthernetDesignExample Wolfgang
Re: [PATCH v2 1/8] usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()
On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote: > > On MIPS platforms, mapping of the base address is needed. This patch > switches from dev_get_addr() to dev_remap_addr() to get the mapped base > address of the xHCI controller. > > Signed-off-by: Stefan Roese > Cc: Bin Meng > Cc: Marek Vasut > --- > > (no changes since v1) > > drivers/usb/host/xhci-dwc3.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH v2 4/9] mips: octeon: Add octeon_ddr.h header
Hi Daniel,
On 19.08.20 16:07, Daniel Schwierzeck wrote:
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
From: Aaron Williams
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
Changes in v2:
- Use readq/writeq in cvmx_read64_uint64/cvmx_write64_uint64 instead of
readl/writel
.../mach-octeon/include/mach/octeon_ddr.h | 988 ++
1 file changed, 988 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/octeon_ddr.h
diff --git a/arch/mips/mach-octeon/include/mach/octeon_ddr.h
b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
new file mode 100644
index 00..630231a191
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
@@ -0,0 +1,988 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
this line is superfluous
Yes, will remove.
+ */
+
+#ifndef __OCTEON_DDR_H_
+#define __OCTEON_DDR_H_
+
+#include
+#include
+#include
+#include
+#include
don't pull unneeded headers. Especially avoid common.h in new code.
I'll drop "common.h" and will check the other headers as well.
+#include
+#include
+
+/* Mapping is done starting from 0x11800.8000 */
+#define CVMX_L2C_CTL 0x0080
+#define CVMX_L2C_BIG_CTL 0x00800030
+#define CVMX_L2C_TADX_INT(i) (0x00a00028 + (((i) & 7) * 0x4))
+#define CVMX_L2C_MCIX_INT(i) (0x00c00028 + (((i) & 3) * 0x4))
+
+/* Some "external" (non-LMC) registers */
+#define CVMX_IPD_CLK_COUNT 0x00014F000338
+#define CVMX_FPA_CLK_COUNT 0x000128F0
+
+#define CVMX_NODE_MEM_SHIFT40
+
+#define DDR_INTERFACE_MAX 4
+
+/* Private data struct */
+struct ddr_priv {
+ void __iomem *lmc_base;
+ void __iomem *l2c_base;
+
+ bool ddr_clock_initialized[DDR_INTERFACE_MAX];
+ bool ddr_memory_preserved;
+ u32 flags;
+
+ struct ram_info info;
+};
+
+/* Short cut to convert a number to megabytes */
+#define MB(X) ((u64)(X) * (u64)(1024 * 1024))
+
+#define octeon_is_cpuid(x) (__OCTEON_IS_MODEL_COMPILE__(x, read_c0_prid()))
+
+#define strtoull simple_strtoull
+
+/* Access LMC registers */
+static inline u64 lmc_rd(struct ddr_priv *priv, u64 addr)
+{
+ return ioread64(priv->lmc_base + addr);
+}
+
+static inline void lmc_wr(struct ddr_priv *priv, u64 addr, u64 val)
+{
+ iowrite64(val, priv->lmc_base + addr);
+}
+
+/* Access L2C registers */
+static inline u64 l2c_rd(struct ddr_priv *priv, u64 addr)
+{
+ return ioread64(priv->l2c_base + addr);
+}
+
+static inline void l2c_wr(struct ddr_priv *priv, u64 addr, u64 val)
+{
+ iowrite64(val, priv->l2c_base + addr);
+}
+
+/* Access other CSR registers not located inside the LMC address space */
+static inline u64 csr_rd(u64 addr)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(addr, 0x100);
+ return ioread64(base);
+}
+
+static inline void csr_wr(u64 addr, u64 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(addr, 0x100);
+ return iowrite64(val, base);
+}
+
+/* "Normal" access, without any offsets and/or mapping */
+static inline u64 cvmx_read64_uint64(u64 addr)
+{
+ return readq((void *)addr);
+}
+
+static inline void cvmx_write64_uint64(u64 addr, u64 val)
+{
+ writeq(val, (void *)addr);
+}
+
+/* Failsafe mode */
+#define FLAG_FAILSAFE_MODE 0x01000
+/* Note that the DDR clock initialized flags must be contiguous */
+/* Clock for DDR 0 initialized */
+#define FLAG_DDR0_CLK_INITIALIZED 0x02000
+/* Clock for DDR 1 initialized */
+#define FLAG_DDR1_CLK_INITIALIZED 0x04000
+/* Clock for DDR 2 initialized */
+#define FLAG_DDR2_CLK_INITIALIZED 0x08000
+/* Clock for DDR 3 initialized */
+#define FLAG_DDR3_CLK_INITIALIZED 0x1
+/* Loaded into RAM externally */
+#define FLAG_RAM_RESIDENT 0x2
+/* Verbose DDR information */
+#define FLAG_DDR_VERBOSE 0x4
+/* Check env. for DDR variables */
+#define FLAG_DDR_DEBUG 0x8
+#define FLAG_DDR_TRACE_INIT0x10
+#define FLAG_MEMORY_PRESERVED 0x20
+#define FLAG_DFM_VERBOSE 0x40
+#define FLAG_DFM_TRACE_INIT0x80
+/* DFM memory clock initialized */
+#define FLAG_DFM_CLK_INITIALIZED 0x100
+/* EEPROM clock descr. missing */
+#define FLAG_CLOCK_DESC_MISSING0x200
+/* EEPROM board descr. missing */
+#define FLAG_BOARD_DESC_MISSING0x400
+#define FLAG_DDR_PROMPT0x800
+
+#ifndef DDR_NO_DEBUG
+static inline int ddr_verbose(struct ddr_priv *priv)
+{
+ return !!(priv->flags & FLAG_DDR_VERBOSE);
+}
+
+static inline char *ddr_getenv_debug(struct ddr_priv *priv, char *name)
+{
+ if (priv->flags & FLAG_FAILSAFE
Re: [PATCH v3] board: armltd: Add support for Total Compute platform
On 12/08/2020 16:34, Tom Rini wrote: On Wed, Aug 12, 2020 at 04:12:53PM +0100, Usama Arif wrote: Total Compute is based on ARM architecture and has the following features enabled in u-boot: - PL011 UART - PL180 MMC - NOR Flash - FIT image with Signature - AVB Signed-off-by: Usama Arif Reviewed-by: Tom Rini Hi, Thanks for the review! I am not completely sure about the review cycle in u-boot and just wanted to check if there was something required from my side to get this patch as well as patch [1/2] (avb: Make AVB independent of fastboot) merged in u-boot/master? Thanks, Usama
Re: [PATCH v5 11/11] riscv: Add FPIOA and GPIO support for Kendryte K210
Hi Sean > Hi Sean > > > On 8/18/20 11:48 PM, Rick Chen wrote: > > > Hi Tom > > > > > >> This patch adds the necessary configs and docs for FPIOA and GPIO support > > >> on the K210. > > >> > > >> The board does not boot unless CONSOLE_LOGLEVEL is set to a non-default > > >> value . It also boots when the tree is dirty (and CONSOLE_LOGLEVEL is not > > >> changed). It also boots when changes are made to the device tree and then > > >> committed. I don't know why this happens. These breakages only occur > > >> after > > >> bf2fb81ad3. > > >> > > >> Signed-off-by: Sean Anderson > > >> --- > > >> > > >> Changes in v5: > > >> - Increase CONSOLE_LOGLEVEL to 5 as a hack to get the board booting again > > >> - Patch 05/12 "gpio: sifive: Use generic reg read function" has been > > >> superseded > > >> by commit 2548493ab4. > > > > > > Would you like to pick up this series, [PATCH v5 00/11] riscv: Add > > > FPIOA and GPIO support for Kendryte K210 ? > > > Or maybe it is better to figure out what is wrong here and find the > > > root cause why it need to Increase CONSOLE_LOGLEVEL to 5 as a hack ? > > > > As an additional note, *CONFIG_LOGLEVEL (whoops) can also be decreased > > for the same effect. In addition, there are several other ways I found > > to "fix" this bug (as noted in the commit message). If you would like to > > test this out, I have two trees [1, 2] where this series (actually a > > slightly > > earlier version of this series) is applied just before and just after > > bf2fb81ad3. The original patch is located at [3]. > > > > --Sean > > > > [1] https://github.com/Forty-Bot/u-boot/tree/maix_gpio_good > > [2] https://github.com/Forty-Bot/u-boot/tree/maix_gpio_bad > > [3] > > https://patchwork.ozlabs.org/project/uboot/patch/20200724111225.12513-15-ovidiu.pan...@windriver.com/ > > I don't have a K210 board for verification. > But it is OK to run in AE350 board after applying your series. > > After check about this commit "common/board_r: Remove initr_serial > wrapper", it seem shall not affect anything. > It just change to call serial_initialize directly. > Only I can think about maybe it is a cache problem. > Just like sometime we add a printf, then the problem will be walk around. Can you dig in to find the root cause ? For code stability, it is better not to have any unknown issue. Yo can dirty hack and work around currently, but it may crash again after several commits. Thanks, Rick > > Thanks, > Rick
Re: [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
On Thursday 20 August 2020 10:17:55 Stefan Roese wrote: > On 20.08.20 09:40, Pali Rohár wrote: > > On Thursday 20 August 2020 07:02:18 Stefan Roese wrote: > > > Can't you just use "mtdparts=" kernel cmdline parameter instead to pass > > > the MTD layout to the kernel? > > > > Maybe it is possible too, I have not tried it. > > > > I thought that more common is to update DTS file by uboot when loading > > kernel as it is already done e.g. for ethernet MAC address on > > Espressobin. > > Updating the MAC address is very common, yes. But passing the > MTD partition layout via the mtdparts= cmdline is also very > common and used very frequently. From my experience, its the > defacto recommended method to pass this info and also easier than > generating these DTS lines via some code. > > Please take a look at the mtdparts U-Boot command and its usage > in other targets. > > > Also I see that uboot has function fdt_fixup_mtdparts() via > > CONFIG_FDT_FIXUP_PARTITIONS option which do this, but uses uboot MTD > > code which IIRC cannot initialize SPI NOR. > > Why not? I had an impression that U-Boot does not support. > SPI NOR is also integrated into the U-Boot MTD world as > well. Please see this GARDENA MT7688 target, which uses SPI NOR & > SPI NAND: Ok, I'm going to look at it. > > Anyway, updating DTS has advantage that it is not needed to update > > existing boot scripts for OS. There are more distributions for > > Espressobin which have own boot scripts stored on SD card for loading > > kernel. And therefore to use command line parameters it would be needed > > to update all of them. > > I see. This is an argument I understand. But can't you use the common > fdt_fixup_mtdparts() then? > > > And I see there another problem. For specifying size of mtd partitions > > in command line, it is required to know offsets of those partitions. And > > e.g. uboot env partition depends on CONFIG_ENV_OFFSET option which is > > not available for uboot boot script code. > > > > But if you have other idea, I'm open to also other solutions. > > I have not investigated a multi-distribution solution here. Perhaps > the common fdt_fixup_mtdparts() is able to handle this? In case U-Boot would see MTD SPI partitions, then fdt_fixup_mtdparts() should work.
Re: [PATCH v2 2/8] usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Hi Stefan, On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote: > > Octeon uses mapped addresses for virtual and physical memory. Its not nits: It's > that easy to calculate the resulting addresses here. So lets remove let's > this BUG_ON() completely, as its not really helpful. it's > > Please also note, that BUG_ON() is not recommended any more in the Linux > kernel. > > Signed-off-by: Stefan Roese > Cc: Bin Meng > Cc: Marek Vasut > > --- > > Changes in v2: > - Completely remove BUG_ON() for this trans_event.buffer check > - Reword commit text > > drivers/usb/host/xhci-ring.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c > index 092ed6eaf1..fd15f39906 100644 > --- a/drivers/usb/host/xhci-ring.c > +++ b/drivers/usb/host/xhci-ring.c > @@ -726,8 +726,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long > pipe, > > BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); > BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); > - BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) - Does phys_to_virt() not work on MIPS? > - buffer > (size_t)length); > > record_transfer_result(udev, event, length); > xhci_acknowledge_event(ctrl); > -- Regards, Bin
Re: [PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
Hi Stefan,
On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote:
>
> This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
nits: It's
> mainly from the Linux code.
>
> Signed-off-by: Stefan Roese
> Cc: Bin Meng
> Cc: Marek Vasut
> ---
>
> (no changes since v1)
>
> drivers/usb/host/Kconfig| 9 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/dwc3-octeon-glue.c | 396
> 3 files changed, 406 insertions(+)
> create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 1c374a7bd8..d71c12d888 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
> SoCs, which includes Armada8K, Armada3700 and other Armada
> family SoCs.
>
> +config USB_XHCI_OCTEON
> + bool "Support for Marvell Octeon family on-chip xHCI USB controller"
> + depends on ARCH_OCTEON
> + default y
> + help
> + Enables support for the on-chip xHCI controller on Marvell Octeon
> + family SoCs. This is a driver for the dwc3 to provide the glue logic
> + to configure the controller.
> +
> config USB_XHCI_PCI
> bool "Support for PCI-based xHCI USB controller"
> depends on DM_USB
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 29d4f87e38..a12e8f2702 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
> +obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
>
> # designware
> obj-$(CONFIG_USB_DWC2) += dwc2.o
> diff --git a/drivers/usb/host/dwc3-octeon-glue.c
> b/drivers/usb/host/dwc3-octeon-glue.c
> new file mode 100644
> index 00..7b1ca7ee33
> --- /dev/null
> +++ b/drivers/usb/host/dwc3-octeon-glue.c
> @@ -0,0 +1,396 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Octeon family DWC3 specific glue layer
> + *
> + * Copyright (C) 2020 Stefan Roese
> + *
> + * The lowlevel init code is based on the Linux driver octeon-usb.c by
nits: low-level
> + * David Daney , which is:
> + * Copyright (C) 2010-2017 Cavium Networks
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
> +#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
> +((i) & 31) * 8 - 8 * 16)
> +
> +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
> +#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
> +
> +#define UCTL_CTL_UCTL_RST BIT_ULL(0)
> +#define UCTL_CTL_UAHC_RST BIT_ULL(1)
> +#define UCTL_CTL_UPHY_RST BIT_ULL(2)
> +#define UCTL_CTL_DRD_MODE BIT_ULL(3)
> +#define UCTL_CTL_SCLK_EN BIT_ULL(4)
> +#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
> +#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
> +#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
> +#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
> +#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
> +#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
> +#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
> +#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
> +#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
> +#define UCTL_CTL_SSC_ENBIT_ULL(59)
> +#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
> +
> +#define UCTL_HOST_CFG 0xe0
> +#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
> +#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
> +
> +#define UCTL_SHIM_CFG 0xe8
> +#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
> +#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
> +
> +#define OCTEON_H_CLKDIV_SEL8
> +#define OCTEON_MIN_H_CLK_RATE 15000
> +#define OCTEON_MAX_H_CLK_RATE 3
> +
> +static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
> +
> +static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
> +{
> + u64 uctl_host_cfg;
> + u64 gpio_bit;
> + u32 gpio_pwr[3];
> + int gpio, len, power_active_low;
> + const struct device_node *node = dev_np(dev);
> + int index = ((u64)base >> 24) & 1;
> + void __iomem *gpio_bit_cfg;
> +
> + if (of_find_property(node, "power", &len)) {
> + if (len == 12) {
> + dev_read_u32_array(dev, "power", gpio_pwr, 3);
> + power_active_low = gpio_pwr[2] & 0x01;
> + gpio = gpio_pwr[1];
> +
Re: [PATCH v2 7/8] mips: octeon: Add USB DT nodes
Hi Stefan,
On Thu, Aug 20, 2020 at 1:37 PM Stefan Roese wrote:
>
> Add the USB device tree nodes to the Octeon dts/dtsi files.
>
> Signed-off-by: Stefan Roese
> ---
>
> (no changes since v1)
>
> arch/mips/dts/mrvl,cn73xx.dtsi| 58 +++
> arch/mips/dts/mrvl,octeon-ebb7304.dts | 22 ++
> 2 files changed, 80 insertions(+)
>
> diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
> index 44a5a03014..1865849fe8 100644
> --- a/arch/mips/dts/mrvl,cn73xx.dtsi
> +++ b/arch/mips/dts/mrvl,cn73xx.dtsi
> @@ -143,5 +143,63 @@
> spi-max-frequency = <2500>;
> clocks = <&clk OCTEON_CLK_IO>;
> };
> +
> + /* USB 0 */
> + usb0: uctl@118006800 {
> + compatible = "cavium,octeon-7130-usb-uctl";
> + reg = <0x11800 0x6800 0x0 0x100>;
> + ranges; /* Direct mapping */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + /* Only 100MHz allowed */
> + refclk-frequency = <1>;
> + /* Only "dlmc_ref_clk0" is supported for 73xx */
> + refclk-type-ss = "dlmc_ref_clk0";
> + /* Only "dlmc_ref_clk0" is supported for 73xx */
> + refclk-type-hs = "dlmc_ref_clk0";
> +
> + /* Power is specified by three parts:
nits: please use the following multi-line comment format, and fix this
globally in this patch
/*
*
*/
> +* 1) GPIO handle (must be &gpio)
> +* 2) GPIO pin number
> +* 3) Active high (0) or active low (1)
> +*/
> + xhci@16800 {
> + compatible =
> "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
> + reg = <0x16800 0x 0x10 0x0>;
> + interrupts = <0x68080 4>; /* UAHC_IMAN, level
> */
> + maximum-speed = "super-speed";
> + dr_mode = "host";
> + snps,dis_u3_susphy_quirk;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + };
> + };
> +
> + /* USB 1 */
> + usb1: uctl@118006900 {
> + compatible = "cavium,octeon-7130-usb-uctl";
> + reg = <0x11800 0x6900 0x0 0x100>;
> + ranges; /* Direct mapping */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + /* 50MHz, 100MHz and 125MHz allowed */
> + refclk-frequency = <1>;
> + /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
> + refclk-type-ss = "dlmc_ref_clk0";
> + /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or
> "pll_ref_clk" */
> + refclk-type-hs = "dlmc_ref_clk0";
> +
> + /* Power is specified by three parts:
> +* 1) GPIO handle (must be &gpio)
> +* 2) GPIO pin number
> +* 3) Active high (0) or active low (1)
> +*/
> + xhci@16900 {
> + compatible =
> "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
> + reg = <0x16900 0x 0x10 0x0>;
> + interrupts = <0x69080 4>; /* UAHC_IMAN, level
> */
> + dr_mode = "host";
> + };
> + };
> };
> };
> diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
> b/arch/mips/dts/mrvl,octeon-ebb7304.dts
> index 6b2e5e84bc..cd576db478 100644
> --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
> +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
> @@ -113,3 +113,25 @@
> reg = <0>;
> };
> };
> +
> +/* USB 0 */
> +&usb0 {
> + status = "okay";
> + /* Power is specified by three parts:
> +* 1) GPIO handle (must be &gpio)
> +* 2) GPIO pin number
> +* 3) Active high (0) or active low (1)
> +*/
> + power = <&gpio 20 0>;
> +};
> +
> +/* USB 1 */
> +&usb1 {
> + status = "okay";
> + /* Power is specified by three parts:
> +* 1) GPIO handle (must be &gpio)
> +* 2) GPIO pin number
> +* 3) Active high (0) or active low (1)
> +*/
> + power = <&gpio 21 0>;
> +};
Otherwise,
Reviewed-by: Bin Meng
Regards,
Bin
Re: [PATCH v7 01/10] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
On Thu, Aug 20, 2020 at 12:45 PM Stefan Roese wrote:
>
> Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
> commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
> CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
> It makes no sense to still carry code that is guarded with
> "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
> all these unreferenced code paths.
>
> Signed-off-by: Stefan Roese
> Reviewed-by: Pali Rohár
> Reviewed-by: Andy Shevchenko
>
> ---
>
> (no changes since v5)
>
> Changes in v5:
> - Add Reviewed-by tag from Pali & Andy
> - Move "bd" assignment as suggested by Andy
>
> Changes in v4:
> - Only remove dead code with CONFIG_NR_DRAM_BANKS always defined
>
> arch/x86/cpu/broadwell/cpu_from_spl.c | 2 --
> board/xilinx/zynqmp/zynqmp.c | 2 --
> cmd/bdinfo.c | 2 --
> common/board_f.c | 7 +-
> common/image.c| 3 +--
> common/init/handoff.c | 33 +++
> drivers/pci/pci-uclass.c | 18 ++-
> include/asm-generic/u-boot.h | 2 --
> include/handoff.h | 2 --
> lib/fdtdec.c | 5
> lib/lmb.c | 9 ++--
> 11 files changed, 19 insertions(+), 66 deletions(-)
>
Reviewed-by: Bin Meng
Re: [PATCH v7 03/10] board_f: Add default values for bi_dram[] in dram_init_banksize()
Hi Stefan,
On Thu, Aug 20, 2020 at 12:45 PM Stefan Roese wrote:
>
> Remove the bi_memstart / bi_memsize assignment in setup_bdinfo() and
> make sure, that bd_dram[] is always configured in the weak default
> implementation of dram_init_banksize(), when CONFIG_SYS_SDRAM_BASE is
> not set.
>
> Signed-off-by: Stefan Roese
> Reviewed-by: Ovidiu Panait
>
> ---
>
> Changes in v7:
> - Add Reviewe-by tag from Ovidiu
>
> Changes in v6:
> - Simplify dram_init_banksize() even more as suggested by Daniel
>
> Changes in v4:
> - New patch
>
> common/board_f.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/common/board_f.c b/common/board_f.c
> index d1f0f9af08..8a43df97e4 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -237,10 +237,8 @@ static int show_dram_config(void)
>
> __weak int dram_init_banksize(void)
> {
> -#if defined(CONFIG_SYS_SDRAM_BASE)
> - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
After this change, I guess CONFIG_SYS_SDRAM_BASE can be dropped in
board's config.h now?
> + gd->bd->bi_dram[0].start = gd->ram_base;
> gd->bd->bi_dram[0].size = get_effective_memsize();
> -#endif
>
> return 0;
> }
> @@ -602,9 +600,6 @@ int setup_bdinfo(void)
> {
> struct bd_info *bd = gd->bd;
>
> - bd->bi_memstart = gd->ram_base; /* start of memory */
> - bd->bi_memsize = gd->ram_size; /* size in bytes */
> -
> if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
> bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
> bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
> --
Regards,
Bin
Re: [PATCH v7 03/10] board_f: Add default values for bi_dram[] in dram_init_banksize()
Hi Bin,
On 20.08.20 11:22, Bin Meng wrote:
Hi Stefan,
On Thu, Aug 20, 2020 at 12:45 PM Stefan Roese wrote:
Remove the bi_memstart / bi_memsize assignment in setup_bdinfo() and
make sure, that bd_dram[] is always configured in the weak default
implementation of dram_init_banksize(), when CONFIG_SYS_SDRAM_BASE is
not set.
Signed-off-by: Stefan Roese
Reviewed-by: Ovidiu Panait
---
Changes in v7:
- Add Reviewe-by tag from Ovidiu
Changes in v6:
- Simplify dram_init_banksize() even more as suggested by Daniel
Changes in v4:
- New patch
common/board_f.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index d1f0f9af08..8a43df97e4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -237,10 +237,8 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_SYS_SDRAM_BASE)
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
After this change, I guess CONFIG_SYS_SDRAM_BASE can be dropped in
board's config.h now?
No. Its still referenced in many other places, e.g.:
static int setup_dest_addr(void)
{
...
#ifdef CONFIG_SYS_SDRAM_BASE
gd->ram_base = CONFIG_SYS_SDRAM_BASE;
#endif
Please see Daniel's explanation for this change here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg380426.html
Thanks,
Stefan
[PATCH 1/2] rockchip: rk3188: Fix the code support for SPL_LED
Fix the build error for the wrong code when CONFIG_SPL_LED is enabled.
Signed-off-by: Kever Yang
---
arch/arm/mach-rockchip/rk3188/rk3188.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c
b/arch/arm/mach-rockchip/rk3188/rk3188.c
index 1b2f4a4757..222953ab94 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -105,6 +106,7 @@ int rk_board_late_init(void)
}
#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
@@ -120,7 +122,7 @@ static int setup_led(void)
debug("%s: get=%d\n", __func__, ret);
return ret;
}
- ret = led_set_on(dev, 1);
+ ret = led_set_state(dev, LEDST_ON);
if (ret)
return ret;
#endif
--
2.25.1
[PATCH 2/2] rockchip: firefly-rk3288: Fix the code support for SPL_LED
Fix the build error for the wrong code when CONFIG_SPL_LED is enabled.
Signed-off-by: Kever Yang
---
board/firefly/firefly-rk3288/firefly-rk3288.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c
b/board/firefly/firefly-rk3288/firefly-rk3288.c
index 1965985a0f..bd8a32cf7b 100644
--- a/board/firefly/firefly-rk3288/firefly-rk3288.c
+++ b/board/firefly/firefly-rk3288/firefly-rk3288.c
@@ -5,9 +5,11 @@
#include
#include
+#include
#include
#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
@@ -23,7 +25,7 @@ static int setup_led(void)
debug("%s: get=%d\n", __func__, ret);
return ret;
}
- ret = led_set_on(dev, 1);
+ ret = led_set_state(dev, LEDST_ON);
if (ret)
return ret;
#endif
--
2.25.1
Re: [PATCH v2 5/9] ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
Hi Daniel,
On 19.08.20 16:30, Daniel Schwierzeck wrote:
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
From: Aaron Williams
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.
Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
Changes in v2:
- Don't re-init after relocation
- Some unsupported Octeon families removed (only Octeon 2 & 3 supported
in general)
drivers/ram/octeon/octeon_ddr.c | 2730 +++
1 file changed, 2730 insertions(+)
create mode 100644 drivers/ram/octeon/octeon_ddr.c
some general notes:
- there are still some C++ style comments
Yes. Please see my comment from "[PATCH v2 4/9] mips: octeon: Add
octeon_ddr.h header" on this.
- there are a lot of non-static functions, are them really used in
other source files and why?
This separation into multiple files is historical. One reason for this
split is, that the file "octeon3_lmc.c" will not be not used by all
Octeon versions. It will be replaced (Makefile switch) by a different
driver file for other Octeon SoC's - once we get to supporting these.
Of course you can split the code into
multiple files but this file is the driver entrypoint and shouldn't
export anything
I'm not sure, if I understand this logic fully. You want me to split
this file again, so that it only includes the (DM) driver entrypoint?
What's the reasoning for this?
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
new file mode 100644
index 00..0b347b61fd
--- /dev/null
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -0,0 +1,2730 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
this line is superfluous
Removed.
+ */
+
+#include
try to avoid common.h in new code
Yes, sorry. I should have remembered this. But these changes started
before "common.h" got deprecated. I'll check all DDR files for this.
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
do Octeon ARM and MIPS share the same DDR3/4 memory controller? If yes,
would this driver support both archs and would ARM provide an own
version of octeon_ddr.h?
No. The DDR3/4 code is *only* used by the "older" MIPS Octeon II/III.
The ARM Octeon TX variants have the DDR init code integrated in the
other binaries, like TF-A. So no code for newer SoC will even be
integrated into this code base.
+static int octeon_ddr_probe(struct udevice *dev)
+{
+ struct ddr_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args l2c_node;
+ struct ddr_conf *ddr_conf_ptr;
+ u32 ddr_conf_valid_mask = 0;
+ u32 measured_ddr_hertz = 0;
+ int conf_table_count;
+ int def_ddr_freq;
+ u32 mem_mbytes = 0;
+ u32 ddr_hertz;
+ u32 ddr_ref_hertz;
+ int alt_refclk;
+ const char *eptr;
+ fdt_addr_t addr;
+ u64 *ptr;
+ u64 val;
+ int ret;
+ int i;
+
+ /* Don't try to re-init the DDR controller after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ /*
+* Dummy read all local variables into cache, so that they are
+* locked in cache when the DDR code runs with flushes etc enabled
+*/
+ ptr = (u64 *)_end;
+ for (i = 0; i < (0x10 / sizeof(u64)); i++)
+ val = readq(ptr++);
+
+ /*
+* The base addresses of LMC and L2C are read from the DT. This
+* makes it possible to use the DDR init code without the need
+* of the "node" variable, describing on which node to access. The
+* node number is already included implicitly in the base addresses
+* read from the DT this way.
+*/
+
+ /* Get LMC base address */
+ priv->lmc_base = dev_remap_addr(dev);
+ debug("%s: lmc_base=%p\n", __func__, priv->lmc_base);
+
+ /* Get L2C base address */
+ ret = dev_read_phandle_with_args(dev, "l2c-handle", NULL, 0, 0,
+&l2c_node);
+ if (ret) {
+ printf("Can't access L2C node!\n");
+ return -ENODEV;
+ }
+
+ addr = ofnode_get_addr(l2c_node.node);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("Can't access L2C node!\n");
+ return -ENODEV;
+ }
+
+ priv->l2c_base = map_physmem(addr, 0, MAP_NOCACHE);
+ debug("%s: l2c_base=%p\n", __func__, priv->l2c_base);
why not dev_remap_addr()?
I'm not sure, how I can access the "udev" necessary for this for the
L2C DT node:
l2c: l2c@118008000 {
#address-cells = <1>;
#size-cells = <0>;
Re: [PATCH v1 01/15] x86: Introduce USE_EARLY_BOARD_INIT option
On Thu, Aug 06, 2020 at 05:54:24PM +0300, Andy Shevchenko wrote: > Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. ... > +#ifdef USE_EARLY_BOARD_INIT And here I missed CONFIG_ prefix... I'll fix this in v2. > /* >* Critical early platform init - generally not used, we prefer init >* to happen later when we have a console, in case something goes > @@ -96,6 +97,8 @@ _start: > jmp early_board_init > .globl early_board_init_ret > early_board_init_ret: > +#endif -- With Best Regards, Andy Shevchenko
Re: [PATCH 3/5] board: xen: Remove CONFIG_CMD_RUN define as it is set on by default in Kconfig
Hi, st 19. 8. 2020 v 14:43 odesílatel Anastasiia Lukianenko napsal: > > From: Anastasiia Lukianenko You really need to write something here. > > Signed-off-by: Anastasiia Lukianenko > --- > configs/xenguest_arm64_defconfig | 1 - > include/configs/xenguest_arm64.h | 2 -- > 2 files changed, 3 deletions(-) > > diff --git a/configs/xenguest_arm64_defconfig > b/configs/xenguest_arm64_defconfig > index 46473c251d..1a85166ff5 100644 > --- a/configs/xenguest_arm64_defconfig > +++ b/configs/xenguest_arm64_defconfig > @@ -17,7 +17,6 @@ CONFIG_CMD_ELF=n > CONFIG_CMD_EXT4=y > CONFIG_CMD_FAT=y > CONFIG_CMD_GO=n > -CONFIG_CMD_RUN=n I have seen one message where you got a recommendation to use savedefconfig. That's why please use it. All these options =n are just wrong. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH v3 00/11] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622>
From: Frank Wunderlich This series adds Mediatek AHCI driver, makes neccessary phy modifications creates new dts for bananapi-r64 (because it's a bit different to rfb) and adds all DTS nodes to get SATA and USB working on mt7622 and mt7623 they are based on top of this: Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888 and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331 v2->v3: - fixed code style suggested by sam v1->v2: - made register of phy optional for tphy v1 and remove it in dts Frank Wunderlich (11): arm: dts: mt7622: add SATA reset constants phy: mtk-tphy: add PHY_TYPE_SATA phy: mtk-tphy: make shared reg optional for v1 reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add watchdog-reboot node for mt7622 arm: dts: add dts for Bananapi-R64 arm: dts: mt7622: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes arch/arm/dts/Makefile| 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 92 ++ arch/arm/dts/mt7623.dtsi | 46 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 128 + drivers/clk/mediatek/clk-mt7622.c| 56 ++ drivers/phy/phy-mtk-tphy.c | 110 ++- include/dt-bindings/reset/mt7629-reset.h | 5 +- 12 files changed, 690 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts create mode 100644 drivers/ata/mtk_ahci.c -- 2.25.1
[PATCH v3 03/11] phy: mtk-tphy: make shared reg optional for v1
From: Frank Wunderlich
make the shared reg optional when version is v1 for sata
Suggested-by: Chunfeng Yun
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
drivers/phy/phy-mtk-tphy.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 326227a30d..3d7b9cd2b1 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -698,11 +698,10 @@ static int mtk_tphy_probe(struct udevice *dev)
tphy->dev = dev;
tphy->version = dev_get_driver_data(dev);
- /* v1 has shared banks */
+ /* v1 has shared banks for usb/pcie mode, */
+ /* but not for sata mode */
if (tphy->version == MTK_TPHY_V1) {
tphy->sif_base = dev_read_addr_ptr(dev);
- if (!tphy->sif_base)
- return -ENOENT;
}
dev_for_each_subnode(subnode, dev) {
--
2.25.1
[PATCH v3 04/11] reset: add basic reset controller for pciesys
From: Frank Wunderlich
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index bd86b5b974..d53ed69189 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
}
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+// PCIESYS uses in linux also 0x34 = ETHSYS reset controller
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
static int mt7622_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
.id = UCLASS_CLK,
.of_match = mt7622_pciesys_compat,
.probe = mt7622_pciesys_probe,
+ .bind = mt7622_pciesys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
--
2.25.1
[PATCH v3 06/11] clk: mt7622: add needed clocks for ssusb-node
From: Frank Wunderlich
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index d53ed69189..0246149107 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift,\
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
.xtal2_rate = 25 * MHZ,
@@ -599,7 +622,6 @@ static int mt7622_pciesys_bind(struct udevice *dev)
int ret = 0;
if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
-// PCIESYS uses in linux also 0x34 = ETHSYS reset controller
ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
debug("Warning: failed to bind reset controller\n");
@@ -631,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
}
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7622_apmixed_compat[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" },
{ }
@@ -671,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
{ }
};
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ssusbsys" },
+ { }
+};
+
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7622-mcucfg",
.id = UCLASS_SYSCON,
@@ -747,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7622-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ssusbsys_compat,
+ .probe = mt7622_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--
2.25.1
[PATCH v3 02/11] phy: mtk-tphy: add PHY_TYPE_SATA
From: Frank Wunderlich
add support for PHY_TYPE_SATA to Mediateks TPHY driver
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
drivers/phy/phy-mtk-tphy.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 1e65c24356..326227a30d 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -175,6 +175,65 @@
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSKGENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSKGENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION20x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSKGENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION90x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x) (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL10x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL40x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL60x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL10x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSKGENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL40xd8
+#define RG_CDR_BIRLTD0_GEN1_MSKGENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL50xdc
+#define RG_CDR_BIRLTD0_GEN3_MSKGENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
enum mtk_phy_version {
MTK_TPHY_V1 = 1,
MTK_TPHY_V2,
@@ -372,6 +431,45 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
udelay(3000);
}
+static void sata_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
+ RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
+ RG_CDR_BIRLTR_GEN1_VAL(0x6) |
+ RG_CDR_BC_GEN1_VAL(0x1a));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
+ RG_CDR_BIRLTD0_GEN1_MSK,
+ RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
+ RG_CDR_BIRLTD0_GEN3_MSK,
+ RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
+ RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
+ RG_CDR_BICLTR_GEN1_VAL(0x0c) |
+ RG_CDR_BR_GEN2_VAL(0x07));
+ clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
+ RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
+ RG_CDR_BICLTD0_GEN1_VAL(0x08) |
+ RG_CDR_BICLTD1_GEN1_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
+ RG_LOCK_CNT_SEL_MSK,
+ RG_LOCK_CNT_SEL_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
+ RG_T2_MIN_MSK | RG_TG_MIN_MSK |
+ RG_T2_MAX_MSK | RG_TG_MAX_MSK,
+ RG_T2_MIN_VAL(0
[PATCH v3 01/11] arm: dts: mt7622: add SATA reset constants
From: Frank Wunderlich add reset constants used for SATA to header file Signed-off-by: Frank Wunderlich --- include/dt-bindings/reset/mt7629-reset.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h index 8f1634f7a6..311a5cb3d0 100644 --- a/include/dt-bindings/reset/mt7629-reset.h +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -6,7 +6,10 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* PCIe Subsystem resets */ +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST15 #define PCIE1_CORE_RST 19 #define PCIE1_MMIO_RST 20 #define PCIE1_HRST 21 -- 2.25.1
[PATCH v3 05/11] ahci: mediatek: add ahci driver
From: Frank Wunderlich
add AHCI driver ported from linux
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c
Signed-off-by: Frank Wunderlich
---
drivers/ata/Kconfig| 8 +++
drivers/ata/Makefile | 1 +
drivers/ata/mtk_ahci.c | 128 +
3 files changed, 137 insertions(+)
create mode 100644 drivers/ata/mtk_ahci.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index d8c9756c2a..f2f8275aec 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -130,4 +130,12 @@ config AHCI_MVEBU
onboard AHCI SATA.
If unsure, say N.
+
+config MTK_AHCI
+ bool "Enable Mediatek AHCI driver support"
+ depends on AHCI
+ help
+ Enable this driver to support Sata devices through
+ Mediatek AHCI controller (e.g. MT7622).
+
endmenu
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a69edb10f7..98fb480700 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
+obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
new file mode 100644
index 00..4ad260a5bb
--- /dev/null
+++ b/drivers/ata/mtk_ahci.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTK SATA platform driver
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Ryder Lee
+ * Author: Frank Wunderlich
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYS_CFG0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_ENBIT(31)
+
+struct mtk_ahci_priv {
+ void *base;
+
+ struct ahci_uc_priv ahci_priv;
+ struct regmap *mode;
+ struct reset_ctl_bulk rst_bulk;
+};
+
+static int mtk_ahci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int mtk_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_remap_addr_index(dev, 0);
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
+ struct udevice *dev)
+{
+ struct mtk_ahci_priv *plat = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+
+ /* enable SATA function if needed */
+ if (fdt_get_property(fdt, dev_of_offset(dev),
+"mediatek,phy-mode", NULL)) {
+ plat->mode = syscon_regmap_lookup_by_phandle(dev,
+ "mediatek,phy-mode");
+ if (IS_ERR(plat->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(plat->mode);
+ }
+ regmap_update_bits(plat->mode, SYS_CFG,
+ SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
+ }
+
+ ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map);
+ return 0;
+}
+
+static int mtk_ahci_probe(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+ int ret;
+ struct phy phy;
+
+ ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(dev, &priv->rst_bulk);
+ if (!ret) {
+ reset_assert_bulk(&priv->rst_bulk);
+ reset_deassert_bulk(&priv->rst_bulk);
+ } else {
+ dev_err(dev, "Failed to get reset: %d\n", ret);
+ }
+
+ ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
+ if (ret) {
+ pr_err("can't get the phy from DT\n");
+ return ret;
+ }
+
+ ret = generic_phy_init(&phy);
+ if (ret) {
+ pr_err("unable to initialize the sata phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ pr_err("unable to power on the sata phy\n");
+ return ret;
+ }
+
+ return ahci_probe_scsi(dev, (ulong)priv->base);
+}
+
+static const struct udevice_id mtk_ahci_ids[] = {
+ { .compatible = "mediatek,mtk-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_ahci) = {
+ .name = "mtk_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = mtk_ahci_ids,
+ .bind = mtk_ahci_bind,
+ .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata,
+ .ops= &scsi_ops,
+ .probe = mtk_ahci_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv),
+};
--
2.25.1
[PATCH v3 11/11] arm: dts: mt7623: add USB nodes
From: Frank Wunderlich
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
arch/arm/dts/mt7623.dtsi | 46
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +
2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 0452889ef8..b5a802552b 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -352,6 +352,52 @@
};
};
+ usb1: usb@1a1c {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a1c 0x1000>, <0x1a1c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a1c4000 {
+ compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
+
+ reg = <0x1a1c4000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0x1a1c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0x1a1c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ };
+ };
+
+ usb2: usb@1a24 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a24 0x1000>, <0x1a244700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
u3phy2: usb-phy@1a244000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index bcedcf20f1..ef07369627 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
+
+&usb1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
--
2.25.1
[PATCH v3 09/11] arm: dts: mt7622: add sata- and asm_sel nodes
From: Frank Wunderlich
asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++
arch/arm/dts/mt7622.dtsi | 31
2 files changed, 40 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 768f15bc2c..c36ec8f8d0 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -204,3 +204,12 @@
full-duplex;
};
};
+
+&gpio {
+ /*gpio 90 for setting mode to sata*/
+ asm_sel {
+ gpio-hog;
+ gpios = <90 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index fec071643e..6b4260407e 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt7622";
@@ -270,6 +271,36 @@
};
};
+ sata: sata@1a20 {
+ compatible = "mediatek,mtk-ahci";
+ reg = <0x1a20 0x1100>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ ports-implemented = <0x1>;
+ phys = <&sata_port PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ status = "okay";
+ };
+
+ sata_phy: sata-phy@1a243000 {
+ compatible = "mediatek,generic-tphy-v1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ sata_port: sata-phy@1a243000 {
+ reg = <0x1a243000 0x0100>;
+ clocks = <&topckgen CLK_TOP_ETH_500M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
[PATCH v3 07/11] arm: dts: add watchdog-reboot node for mt7622
From: Frank Wunderlich
adding a wdt-reboot node to mt7622 dtsi
Signed-off-by: Frank Wunderlich
---
arch/arm/dts/mt7622.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index d0783bc9ff..fec071643e 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -142,6 +142,11 @@
reg = <0x10212000 0x800>;
};
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&watchdog>;
+ };
+
gic: interrupt-controller@1030 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.25.1
[PATCH v3 08/11] arm: dts: add dts for Bananapi-R64
From: Frank Wunderlich
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support
Signed-off-by: Frank Wunderlich
---
v1->v2:
- changed name
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 206 +++
2 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8ecf63e988..ff0e76f808 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -959,6 +959,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
+ mt7622-bananapi-bpi-r64.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
new file mode 100644
index 00..768f15bc2c
--- /dev/null
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt7622-u-boot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mt7622-bpi-r64";
+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ aliases {
+ spi0 = &snfi;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x4000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&pinctrl {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ pwm_pins: pwm1 {
+ mux {
+ function = "pwm";
+ groups = "pwm_ch1_0" ;
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+*/
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+* DAT2, DAT3, CMD, CLK for SD respectively.
+*/
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up
[PATCH v3 10/11] arm: dts: mt7622: add USB nodes
From: Frank Wunderlich
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
v1->v2:
- remove clk25m as it's not needed
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8
arch/arm/dts/mt7622-rfb.dts | 8
arch/arm/dts/mt7622.dtsi | 56
3 files changed, 72 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index c36ec8f8d0..7cd581cf7d 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -213,3 +213,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 317fc78abd..ef7d0f0270 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -222,3 +222,11 @@
full-duplex;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 6b4260407e..5a4dab185f 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -192,6 +192,14 @@
status = "disabled";
};
+ ssusbsys: ssusbsys@1a00 {
+ compatible = "mediatek,mt7622-ssusbsys",
+"syscon";
+ reg = <0x1a00 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -301,6 +309,54 @@
};
};
+ ssusb: usb@1a0c {
+ compatible = "mediatek,mt7622-xhci",
+"mediatek,mtk-xhci";
+ reg = <0x1a0c 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = ;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+<&ssusbsys CLK_SSUSB_REF_EN>,
+<&ssusbsys CLK_SSUSB_MCU_EN>,
+<&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy@1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+"mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
[PATCH v2 03/15] x86: congatec: conga-qeval20-qa3-e3845: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Stefan Roese --- v2: added Rb tag(s) board/congatec/conga-qeval20-qa3-e3845/Makefile | 2 +- board/congatec/conga-qeval20-qa3-e3845/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/congatec/conga-qeval20-qa3-e3845/start.S diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile index 2f04828a27f2..451a4fcd6c4d 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Makefile +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Google, Inc -obj-y += conga-qeval20-qa3.o start.o +obj-y += conga-qeval20-qa3.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/congatec/conga-qeval20-qa3-e3845/start.S b/board/congatec/conga-qeval20-qa3-e3845/start.S deleted file mode 100644 index 65d1f7e96150.. --- a/board/congatec/conga-qeval20-qa3-e3845/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Google, Inc - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 01/15] x86: Introduce USE_EARLY_BOARD_INIT option
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. Cc: George McCollister Signed-off-by: Andy Shevchenko Reviewed-by: Stefan Roese Reviewed-by: Aiden Park --- v2: added Rb tag(s), appended CONFIG prefix when use the option in the code arch/x86/Kconfig | 3 +++ arch/x86/cpu/start.S | 3 +++ board/google/chromebook_coral/Kconfig | 1 + board/google/chromebook_link/Kconfig | 1 + board/google/chromebook_samus/Kconfig | 1 + 5 files changed, 9 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a34b108fffa6..76276c602745 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -203,6 +203,9 @@ config SPL_X86_32BIT_INIT help This is enabled when 32-bit init is in SPL +config USE_EARLY_BOARD_INIT + bool + config RESET_SEG_START hex depends on X86_RESET_VECTOR diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 4ad515ce0856..3b6ed37bc07e 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -88,6 +88,7 @@ _start: /* Clear the interrupt vectors */ lidtblank_idt_ptr +#ifdef CONFIG_USE_EARLY_BOARD_INIT /* * Critical early platform init - generally not used, we prefer init * to happen later when we have a console, in case something goes @@ -96,6 +97,8 @@ _start: jmp early_board_init .globl early_board_init_ret early_board_init_ret: +#endif + post_code(POST_START) /* Initialise Cache-As-RAM */ diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig index 940bee89b0b6..27671958e146 100644 --- a/board/google/chromebook_coral/Kconfig +++ b/board/google/chromebook_coral/Kconfig @@ -18,6 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT select INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 944716d002c9..dd29ddf694be 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index 90c23cba1bed..9f66d7998870 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -19,6 +19,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT select INTEL_BROADWELL select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 -- 2.28.0
[PATCH v2 06/15] x86: efi: efi-x86_payload: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/efi/efi-x86_payload/Makefile | 2 +- board/efi/efi-x86_payload/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/efi/efi-x86_payload/start.S diff --git a/board/efi/efi-x86_payload/Makefile b/board/efi/efi-x86_payload/Makefile index 00ef69534d00..a4ebc85aa5b3 100644 --- a/board/efi/efi-x86_payload/Makefile +++ b/board/efi/efi-x86_payload/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2018, Bin Meng -obj-y += start.o payload.o +obj-y += payload.o diff --git a/board/efi/efi-x86_payload/start.S b/board/efi/efi-x86_payload/start.S deleted file mode 100644 index f7eaa7cb12a9.. --- a/board/efi/efi-x86_payload/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 05/15] x86: dfi: dfi-bt700: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Stefan Roese --- v2: added Rb tag(s) board/dfi/dfi-bt700/Makefile | 2 +- board/dfi/dfi-bt700/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/dfi/dfi-bt700/start.S diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile index 99cf357b701f..50d88f295458 100644 --- a/board/dfi/dfi-bt700/Makefile +++ b/board/dfi/dfi-bt700/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Google, Inc -obj-y += dfi-bt700.o start.o +obj-y += dfi-bt700.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/dfi/dfi-bt700/start.S b/board/dfi/dfi-bt700/start.S deleted file mode 100644 index 65d1f7e96150.. --- a/board/dfi/dfi-bt700/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Google, Inc - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 02/15] x86: advantech: som-db5800-som-6867: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Cc: George McCollister Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/advantech/som-db5800-som-6867/Makefile | 2 +- board/advantech/som-db5800-som-6867/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/advantech/som-db5800-som-6867/start.S diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile index 0524766bb718..7975547f4109 100644 --- a/board/advantech/som-db5800-som-6867/Makefile +++ b/board/advantech/som-db5800-som-6867/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Google, Inc -obj-y += som-db5800-som-6867.o start.o +obj-y += som-db5800-som-6867.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S deleted file mode 100644 index 65d1f7e96150.. --- a/board/advantech/som-db5800-som-6867/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Google, Inc - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 11/15] x86: intel: edison: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/edison/Makefile | 2 +- board/intel/edison/start.S | 12 2 files changed, 1 insertion(+), 13 deletions(-) delete mode 100644 board/intel/edison/start.S diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile index eed8d65eb661..1eaf7ca7f8e2 100644 --- a/board/intel/edison/Makefile +++ b/board/intel/edison/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += start.o edison.o +obj-y += edison.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/edison/start.S b/board/intel/edison/start.S deleted file mode 100644 index aa702622d48c.. --- a/board/intel/edison/start.S +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.r...@gmail.com. - */ - -/* board early intialization */ -.globl early_board_init -early_board_init: - /* No 32-bit board specific initialisation */ - jmp early_board_init_ret -- 2.28.0
[PATCH v2 04/15] x86: coreboot: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/coreboot/coreboot/Makefile | 2 +- board/coreboot/coreboot/start.S | 12 2 files changed, 1 insertion(+), 13 deletions(-) delete mode 100644 board/coreboot/coreboot/start.S diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 8db7cc62f309..d292b7032c23 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -10,4 +10,4 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, dan...@omicron.se. -obj-y += start.o coreboot.o +obj-y += coreboot.o diff --git a/board/coreboot/coreboot/start.S b/board/coreboot/coreboot/start.S deleted file mode 100644 index aa702622d48c.. --- a/board/coreboot/coreboot/start.S +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.r...@gmail.com. - */ - -/* board early intialization */ -.globl early_board_init -early_board_init: - /* No 32-bit board specific initialisation */ - jmp early_board_init_ret -- 2.28.0
[PATCH v2 15/15] x86: qemu: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/emulation/qemu-x86/Makefile | 2 -- board/emulation/qemu-x86/start.S | 8 2 files changed, 10 deletions(-) delete mode 100644 board/emulation/qemu-x86/start.S diff --git a/board/emulation/qemu-x86/Makefile b/board/emulation/qemu-x86/Makefile index 782e298b74ce..5af8d31d5840 100644 --- a/board/emulation/qemu-x86/Makefile +++ b/board/emulation/qemu-x86/Makefile @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2015, Bin Meng - -obj-y += start.o diff --git a/board/emulation/qemu-x86/start.S b/board/emulation/qemu-x86/start.S deleted file mode 100644 index e4bde561b20d.. --- a/board/emulation/qemu-x86/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 10/15] x86: intel: crownbay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/crownbay/Makefile | 2 +- board/intel/crownbay/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/crownbay/start.S diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile index b52c69aeaa1b..6abd3eeb5540 100644 --- a/board/intel/crownbay/Makefile +++ b/board/intel/crownbay/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2014, Bin Meng -obj-y += crownbay.o start.o +obj-y += crownbay.o diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S deleted file mode 100644 index 7faa7d05fae4.. --- a/board/intel/crownbay/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 07/15] x86: intel: bayleybay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/bayleybay/Makefile | 2 +- board/intel/bayleybay/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/bayleybay/start.S diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile index e0553f146248..d19447184a6e 100644 --- a/board/intel/bayleybay/Makefile +++ b/board/intel/bayleybay/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Bin Meng -obj-y += bayleybay.o start.o +obj-y += bayleybay.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/bayleybay/start.S b/board/intel/bayleybay/start.S deleted file mode 100644 index e4bde561b20d.. --- a/board/intel/bayleybay/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 12/15] x86: intel: galileo: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/galileo/Makefile | 2 +- board/intel/galileo/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/galileo/start.S diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile index e8f58bff9aca..4130bb023656 100644 --- a/board/intel/galileo/Makefile +++ b/board/intel/galileo/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Bin Meng -obj-y += galileo.o start.o +obj-y += galileo.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/galileo/start.S b/board/intel/galileo/start.S deleted file mode 100644 index e4bde561b20d.. --- a/board/intel/galileo/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 09/15] x86: intel: cougarcanyon2: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/cougarcanyon2/Makefile | 2 +- board/intel/cougarcanyon2/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/cougarcanyon2/start.S diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile index 75cc508f4ec0..13b19ae65389 100644 --- a/board/intel/cougarcanyon2/Makefile +++ b/board/intel/cougarcanyon2/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2016, Bin Meng -obj-y += cougarcanyon2.o start.o +obj-y += cougarcanyon2.o diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S deleted file mode 100644 index 8521800921e4.. --- a/board/intel/cougarcanyon2/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 13/15] x86: intel: minnowmax: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/minnowmax/Makefile | 2 +- board/intel/minnowmax/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/minnowmax/start.S diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile index 989344df1c91..d339b5ad0a54 100644 --- a/board/intel/minnowmax/Makefile +++ b/board/intel/minnowmax/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2015, Google, Inc -obj-y += minnowmax.o start.o +obj-y += minnowmax.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S deleted file mode 100644 index 65d1f7e96150.. --- a/board/intel/minnowmax/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Google, Inc - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 14/15] x86: intel: slimbootloader: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass Reviewed-by: Aiden Park --- v2: added Rb tag(s) board/intel/slimbootloader/Makefile | 2 +- board/intel/slimbootloader/start.S | 9 - 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 board/intel/slimbootloader/start.S diff --git a/board/intel/slimbootloader/Makefile b/board/intel/slimbootloader/Makefile index fd8fa98a8d39..50330cc6e5db 100644 --- a/board/intel/slimbootloader/Makefile +++ b/board/intel/slimbootloader/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2019 Intel Corporation -obj-y += start.o slimbootloader.o +obj-y += slimbootloader.o diff --git a/board/intel/slimbootloader/start.S b/board/intel/slimbootloader/start.S deleted file mode 100644 index 5c3f3df09eb0.. --- a/board/intel/slimbootloader/start.S +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Intel Corporation - */ - -/* board early initialization */ -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
[PATCH v2 08/15] x86: intel: cherryhill: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used by the build system, so simply drop the rule from it. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- v2: added Rb tag(s) board/intel/cherryhill/Makefile | 2 +- board/intel/cherryhill/start.S | 8 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 board/intel/cherryhill/start.S diff --git a/board/intel/cherryhill/Makefile b/board/intel/cherryhill/Makefile index b09581a9195e..ff6e14836a11 100644 --- a/board/intel/cherryhill/Makefile +++ b/board/intel/cherryhill/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2017, Bin Meng -obj-y += cherryhill.o start.o +obj-y += cherryhill.o diff --git a/board/intel/cherryhill/start.S b/board/intel/cherryhill/start.S deleted file mode 100644 index 2e3e7f840944.. --- a/board/intel/cherryhill/start.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng - */ - -.globl early_board_init -early_board_init: - jmp early_board_init_ret -- 2.28.0
Re: [PATCH v2 6/7] riscv: Update Kendryte device tree for new CLINT driver
On 8/20/20 3:45 AM, Bin Meng wrote:
> On Wed, Jul 29, 2020 at 5:57 PM Sean Anderson wrote:
>>
>> AFAIK because the K210 clock driver does not come up until after
>> relocation, the clint will always use the clock-frequency parameter.
>> Ideally, it should update itself after relocation to take into account the
>> actual CPU frequency.
>>
>> Signed-off-by: Sean Anderson
>> ---
>>
>> Changes in v2:
>> - New
>>
>> arch/riscv/dts/k210.dtsi | 9 ++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
>> index 2546c7d4e0..2698a33a5c 100644
>> --- a/arch/riscv/dts/k210.dtsi
>> +++ b/arch/riscv/dts/k210.dtsi
>> @@ -17,6 +17,8 @@
>> compatible = "kendryte,k210";
>>
>> aliases {
>> + cpu0 = &cpu0;
>> + cpu1 = &cpu1;
>> dma0 = &dmac0;
>> gpio0 = &gpio0;
>> gpio1 = &gpio1_0;
>> @@ -126,14 +128,15 @@
>> read-only;
>> };
>>
>> - clint0: interrupt-controller@200 {
>> + clint0: clint@200 {
>> #interrupt-cells = <1>;
>> compatible = "kendryte,k210-clint", "riscv,clint0";
>> reg = <0x200 0xC000>;
>> - interrupt-controller;
>
> Why is this property dropped?
Because the clint is not an interrupt-controller. That is, no other
devices have an interrupt which is controlled by the clint.
>
>> interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
>> <&cpu1_intc 3>, <&cpu1_intc 7>;
>> - clocks = <&sysclk K210_CLK_CPU>;
>> + clocks = <&sysclk K210_CLK_CLINT>;
>> + /* sysclk is only available post-relocation */
>> + clock-frequency = <780>;
>> };
>>
>> plic0: interrupt-controller@C00 {
>> --
>
> Regards,
> Bin
>
Re: [PATCH v2 2/7] riscv: Rework Andes PLMT as a UCLASS_TIMER driver
On 8/20/20 3:40 AM, Bin Meng wrote:
> On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote:
>>
>> This converts the PLMT driver from the riscv-specific timer interface to be
>> a DM-based UCLASS_TIMER driver.
>>
>> Signed-off-by: Sean Anderson
>> ---
>> This patch builds but has NOT been tested.
>>
>> (no changes since v1)
>>
>> arch/riscv/Kconfig | 4 ---
>> arch/riscv/dts/ae350_32.dts | 1 +
>> arch/riscv/dts/ae350_64.dts | 1 +
>> arch/riscv/include/asm/global_data.h | 3 --
>> arch/riscv/lib/andes_plmt.c | 42 +---
>> 5 files changed, 22 insertions(+), 29 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 21e6690f4d..d9155b9bab 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -177,10 +177,6 @@ config ANDES_PLIC
>> config ANDES_PLMT
>> bool
>> depends on RISCV_MMODE || SPL_RISCV_MMODE
>> - select REGMAP
>> - select SYSCON
>> - select SPL_REGMAP if SPL
>> - select SPL_SYSCON if SPL
>> help
>> The Andes PLMT block holds memory-mapped mtime register
>> associated with timer tick.
>> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
>> index 3f8525fe56..afcb9cfbbf 100644
>> --- a/arch/riscv/dts/ae350_32.dts
>> +++ b/arch/riscv/dts/ae350_32.dts
>> @@ -162,6 +162,7 @@
>> &CPU2_intc 7
>> &CPU3_intc 7>;
>> reg = <0xe600 0x10>;
>> + clock-frequency = <6000>;
>
> Why not use /cpus/timebase-frequency directly?
I touched on this in the discussion for the previous version of the
sifive clint patch.
> I prefer [using clock-frequency/clocks] for two reasons. First,
> properties which affect a device should be located near its binding in
> the device tree. Using timebase-frequency only really makes sense
> when the cpu itself is the timer device. This is the case when we read
> the time from a CSR, but not when there is a separate device. Second,
> it lets the device use the clock subsystem which adds flexibility. If
> the device is configured for a different clock speed, the timer can
> adjust itself.
Only the first reason applies to the andes plmt, but I think it is good
for consistency to move the property here as well.
>> };
>> };
>>
>> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
>> index 482c707503..1c37879049 100644
>> --- a/arch/riscv/dts/ae350_64.dts
>> +++ b/arch/riscv/dts/ae350_64.dts
>> @@ -162,6 +162,7 @@
>> &CPU2_intc 7
>> &CPU3_intc 7>;
>> reg = <0x0 0xe600 0x0 0x10>;
>> + clock-frequency = <6000>;
>> };
>> };
>>
>> diff --git a/arch/riscv/include/asm/global_data.h
>> b/arch/riscv/include/asm/global_data.h
>> index 2eb14815bc..0dec5e669e 100644
>> --- a/arch/riscv/include/asm/global_data.h
>> +++ b/arch/riscv/include/asm/global_data.h
>> @@ -24,9 +24,6 @@ struct arch_global_data {
>> #ifdef CONFIG_ANDES_PLIC
>> void __iomem *plic; /* plic base address */
>> #endif
>> -#ifdef CONFIG_ANDES_PLMT
>> - void __iomem *plmt; /* plmt base address */
>> -#endif
>> #if CONFIG_IS_ENABLED(SMP)
>> struct ipi_data ipi[CONFIG_NR_CPUS];
>> #endif
>> diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
>> index a7e90ca992..b0245d0b52 100644
>> --- a/arch/riscv/lib/andes_plmt.c
>> +++ b/arch/riscv/lib/andes_plmt.c
>> @@ -1,6 +1,7 @@
>> // SPDX-License-Identifier: GPL-2.0+
>> /*
>> * Copyright (C) 2019, Rick Chen
>> + * Copyright (C) 2020, Sean Anderson
>> *
>> * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
>> * The PLMT block holds memory-mapped mtime register
>> @@ -9,46 +10,43 @@
>>
>> #include
>> #include
>> -#include
>> -#include
>> +#include
>> #include
>> -#include
>> #include
>>
>> /* mtime register */
>> #define MTIME_REG(base)((ulong)(base))
>>
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> -#define PLMT_BASE_GET(void)\
>> - do {\
>> - long *ret; \
>> - \
>> - if (!gd->arch.plmt) { \
>> - ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
>> - if (IS_ERR(ret))\
>> - return PTR_ERR(ret);\
>> - gd->arch.plmt = ret;\
>> - } \
>> - } while (0)
>>
Re: [PATCH v2 2/8] usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Hi Bin, On 20.08.20 10:58, Bin Meng wrote: Hi Stefan, On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote: Octeon uses mapped addresses for virtual and physical memory. Its not nits: It's that easy to calculate the resulting addresses here. So lets remove let's this BUG_ON() completely, as its not really helpful. it's Will change in next version. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: Stefan Roese Cc: Bin Meng Cc: Marek Vasut --- Changes in v2: - Completely remove BUG_ON() for this trans_event.buffer check - Reword commit text drivers/usb/host/xhci-ring.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6eaf1..fd15f39906 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -726,8 +726,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); - BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) - Does phys_to_virt() not work on MIPS? It does. But the calculation of the resulting address grew quite frustratingly complex AFAIR (it's been a while, when I created this patch). To sum it up, the resulting expression was unreadable because of the multiple de-references. It seemed "better" to drop this check completely. Especially since Linux (checkpatch) moves away from BUG() statements. I also tried to find this check in the Linux xHCI driver and failed. Thanks, Stefan
Re: [PATCH v2 4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver
On 8/20/20 3:43 AM, Bin Meng wrote:
> On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson wrote:
>>
>> This converts the clint driver from the riscv-specific interface to be a
>> DM-based UCLASS_TIMER driver. We also need to re-add the initialization for
>> IPI back into the SPL code. This was previously implicitly done when the
>> timer was initialized. In addition, the SiFive DDR driver previously
>> implicitly depended on the CLINT to select REGMAP.
>>
>> Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
>> the SiFive CLINT is part of the device tree passed in by qemu. This device
>> tree doesn't have a clocks or clock-frequency property on clint, so we need
>> to fall back on the timebase-frequency property. Perhaps in the future we
>> can get a clock-frequency property added to the qemu dtb.
>>
>> Signed-off-by: Sean Anderson
>> ---
>> This patch builds but has only been tested on the K210 and QEMU. It has NOT
>> been tested on a HiFive.
>>
>> (no changes since v1)
>>
>> arch/riscv/Kconfig| 4 --
>> arch/riscv/lib/sifive_clint.c | 87 +++
>> common/spl/spl_opensbi.c | 5 ++
>> drivers/ram/sifive/Kconfig| 2 +
>> 4 files changed, 64 insertions(+), 34 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index d9155b9bab..aaa3b833a5 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -155,10 +155,6 @@ config 64BIT
>> config SIFIVE_CLINT
>> bool
>> depends on RISCV_MMODE || SPL_RISCV_MMODE
>> - select REGMAP
>> - select SYSCON
>> - select SPL_REGMAP if SPL
>> - select SPL_SYSCON if SPL
>> help
>> The SiFive CLINT block holds memory-mapped control and status
>> registers
>> associated with software and timer interrupts.
>> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
>> index b9a2c649cc..3345a17ad2 100644
>> --- a/arch/riscv/lib/sifive_clint.c
>> +++ b/arch/riscv/lib/sifive_clint.c
>> @@ -8,9 +8,9 @@
>> */
>>
>> #include
>> +#include
>> #include
>> -#include
>> -#include
>> +#include
>> #include
>> #include
>> #include
>> @@ -24,35 +24,19 @@
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -int riscv_get_time(u64 *time)
>> -{
>> - /* ensure timer register base has a sane value */
>> - riscv_init_ipi();
>> -
>> - *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
>> -
>> - return 0;
>> -}
>> -
>> -int riscv_set_timecmp(int hart, u64 cmp)
>> -{
>> - /* ensure timer register base has a sane value */
>> - riscv_init_ipi();
>> -
>> - writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
>> -
>> - return 0;
>> -}
>> -
>> int riscv_init_ipi(void)
>> {
>> - if (!gd->arch.clint) {
>> - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
>> + int ret;
>> + struct udevice *dev;
>>
>> - if (IS_ERR(ret))
>> - return PTR_ERR(ret);
>> - gd->arch.clint = ret;
>> - }
>> + ret = uclass_get_device_by_driver(UCLASS_TIMER,
>> + DM_GET_DRIVER(sifive_clint), &dev);
>> + if (ret)
>> + return ret;
>> +
>> + gd->arch.clint = dev_read_addr_ptr(dev);
>> + if (!gd->arch.clint)
>> + return -EINVAL;
>>
>> return 0;
>> }
>> @@ -78,14 +62,57 @@ int riscv_get_ipi(int hart, int *pending)
>> return 0;
>> }
>>
>> +static int sifive_clint_get_count(struct udevice *dev, u64 *count)
>> +{
>> + *count = readq((void __iomem *)MTIME_REG(dev->priv));
>> +
>> + return 0;
>> +}
>> +
>> +static const struct timer_ops sifive_clint_ops = {
>> + .get_count = sifive_clint_get_count,
>> +};
>> +
>> +static int sifive_clint_probe(struct udevice *dev)
>> +{
>> + int ret;
>> + ofnode cpu;
>> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>> + u32 rate;
>> +
>> + dev->priv = dev_read_addr_ptr(dev);
>> + if (!dev->priv)
>> + return -EINVAL;
>> +
>> + /* Did we get our clock rate from the device tree? */
>> + if (uc_priv->clock_rate)
>> + return 0;
>> +
>> + /* Fall back to timebase-frequency */
>> + cpu = ofnode_path("/cpus");
>> + if (!ofnode_valid(cpu))
>> + return -EINVAL;
>> +
>> + ret = ofnode_read_u32(cpu, "timebase-frequency", &rate);
>> + if (ret)
>> + return ret;
>> +
>> + log_warning("missing clocks or clock-frequency property, falling
>> back on timebase-frequency\n");
>> + uc_priv->clock_rate = rate;
>> +
>> + return 0;
>> +}
>> +
>> static const struct udevice_id sifive_clint_ids[] = {
>> - { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
>
> RISCV_SYSCON_CLINT should be removed from syscon.h
This can't be removed because the IPI driver still depends on it.
>> +
Re: [PATCH v2 7/8] mips: octeon: Add USB DT nodes
Hi Bin,
On 20.08.20 11:09, Bin Meng wrote:
Hi Stefan,
On Thu, Aug 20, 2020 at 1:37 PM Stefan Roese wrote:
Add the USB device tree nodes to the Octeon dts/dtsi files.
Signed-off-by: Stefan Roese
---
(no changes since v1)
arch/mips/dts/mrvl,cn73xx.dtsi| 58 +++
arch/mips/dts/mrvl,octeon-ebb7304.dts | 22 ++
2 files changed, 80 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 44a5a03014..1865849fe8 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -143,5 +143,63 @@
spi-max-frequency = <2500>;
clocks = <&clk OCTEON_CLK_IO>;
};
+
+ /* USB 0 */
+ usb0: uctl@118006800 {
+ compatible = "cavium,octeon-7130-usb-uctl";
+ reg = <0x11800 0x6800 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /* Only 100MHz allowed */
+ refclk-frequency = <1>;
+ /* Only "dlmc_ref_clk0" is supported for 73xx */
+ refclk-type-ss = "dlmc_ref_clk0";
+ /* Only "dlmc_ref_clk0" is supported for 73xx */
+ refclk-type-hs = "dlmc_ref_clk0";
+
+ /* Power is specified by three parts:
nits: please use the following multi-line comment format, and fix this
globally in this patch
Ok.
/*
*
*/
+* 1) GPIO handle (must be &gpio)
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ xhci@16800 {
+ compatible =
"cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
+ reg = <0x16800 0x 0x10 0x0>;
+ interrupts = <0x68080 4>; /* UAHC_IMAN, level */
+ maximum-speed = "super-speed";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ };
+ };
+
+ /* USB 1 */
+ usb1: uctl@118006900 {
+ compatible = "cavium,octeon-7130-usb-uctl";
+ reg = <0x11800 0x6900 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /* 50MHz, 100MHz and 125MHz allowed */
+ refclk-frequency = <1>;
+ /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
+ refclk-type-ss = "dlmc_ref_clk0";
+ /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or
"pll_ref_clk" */
+ refclk-type-hs = "dlmc_ref_clk0";
+
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be &gpio)
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ xhci@16900 {
+ compatible =
"cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
+ reg = <0x16900 0x 0x10 0x0>;
+ interrupts = <0x69080 4>; /* UAHC_IMAN, level */
+ dr_mode = "host";
+ };
+ };
};
};
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 6b2e5e84bc..cd576db478 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -113,3 +113,25 @@
reg = <0>;
};
};
+
+/* USB 0 */
+&usb0 {
+ status = "okay";
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be &gpio)
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ power = <&gpio 20 0>;
+};
+
+/* USB 1 */
+&usb1 {
+ status = "okay";
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be &gpio)
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ power = <&gpio 21 0>;
+};
Otherwise,
Reviewed-by: Bin Meng
Thanks,
Stefan
[PATCH v4 1/1] cmd: provide command sbi
Provide a command to display information about the SBI implementation.
The output might look like:
=> sbi
SBI 0.2
OpenSBI
Extensions:
sbi_set_timer
sbi_console_putchar
sbi_console_getchar
sbi_clear_ipi
sbi_send_ipi
sbi_remote_fence_i
sbi_remote_sfence_vma
sbi_remote_sfence_vma_asid
sbi_shutdown
SBI Base Functionality
Timer Extension
IPI Extension
RFENCE Extension
Hart State Management Extension
The command can be used to construct a unit test checking that the
communication with the SEE is working.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Atish Patra
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
v4:
only show command name 'sbi' as short description in Kconfig menu
as suggested by Bin
v3:
add dependency on CONFIG_SBI_V02
use lower case for sbi in Kconfig
v2:
provide a non-blank long help text
---
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/lib/sbi.c | 36
cmd/Kconfig | 6 +++
cmd/riscv/Makefile | 1 +
cmd/riscv/sbi.c | 82
5 files changed, 127 insertions(+)
create mode 100644 cmd/riscv/sbi.c
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 08e1ac0c0e..53ca316180 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
*hart_mask,
unsigned long asid);
#endif
void sbi_set_timer(uint64_t stime_value);
+long sbi_get_spec_version(void);
+int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 8fbc23839d..920889ed13 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)
#endif
}
+/**
+ * sbi_get_spec_version() - get current SBI specification version
+ *
+ * Return: version id
+ */
+long sbi_get_spec_version(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+
+/**
+ * sbi_get_impl_id() - get SBI implementation ID
+ *
+ * Return: implementation ID
+ */
+int sbi_get_impl_id(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+
/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9ad511aa17..8feeb0ddb0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
help
Read system EEPROM data block in ONIE Tlvinfo format from SPL.
+config CMD_SBI
+ bool "sbi"
+ depends on RISCV_SMODE && SBI_V02
+ help
+ Display information about the SBI implementation.
+
endmenu
menu "Boot commands"
diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile
index 24df023ece..1e6ac364e3 100644
--- a/cmd/riscv/Makefile
+++ b/cmd/riscv/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_CMD_EXCEPTION) += exception.o
+obj-$(CONFIG_CMD_SBI) += sbi.o
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
new file mode 100644
index 00..7c9151f436
--- /dev/null
+++ b/cmd/riscv/sbi.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'sbi' command displays information about the SBI implementation.
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt
+ */
+
+#include
+#include
+#include
+
+struct sbi_ext {
+ const u32 id;
+ const char *name;
+};
+
+static struct sbi_ext extensions[] = {
+ { 0x, "sbi_set_timer" },
+ { 0x0001, "sbi_console_putchar" },
+ { 0x0002, "sbi_console_getchar" },
+ { 0x0003, "sbi_clear_ipi" },
+ { 0x0004, "sbi_send_ipi" },
+ { 0x0005, "sbi_remote_fence_i" },
+ { 0x0006, "sbi_remote_sfence_vma" },
+ { 0x0007, "sbi_remote_sfence_vma_asid" },
+ { 0x0008, "sbi_shutdown" },
+ { 0x0010, "SBI Base Functionality" },
+ { 0x54494D45, "Timer Extension" },
+ { 0x00735049, "IPI Extension" },
+ { 0x52464E43, "RFENCE Extension" },
+ { 0x0048534D, "Hart State Management Extension" },
+};
+
+static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int i;
+ long ret;
+
+ ret = sbi_get_spec_version();
+ if (ret >= 0)
+ printf("SBI %ld.%ld\n", ret >> 24, ret & 0xff);
+ ret = sbi_get_impl_id();
+ if (ret >= 0) {
+ switch (ret) {
+
Aw: [PATCH v3 04/11] reset: add basic reset controller for pciesys
> Gesendet: Donnerstag, 20. August 2020 um 11:55 Uhr
> Von: "Frank Wunderlich"
> +static int mt7622_pciesys_bind(struct udevice *dev)
> +{
> + int ret = 0;
> +
> + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
> +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller
sorry, squashed change to wrong commit...will fix it soon
> + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
> + if (ret)
> + debug("Warning: failed to bind reset controller\n");
> + }
> +
> + return ret;
> +}
[PATCH 1/1] efi_selftest: add a test for ResetSystem()
The unit test will reset the system by calling the ResetSystem() runtime
service before ExitBootServices().
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/Makefile | 1 +
lib/efi_selftest/efi_selftest_reset.c | 50 +++
2 files changed, 51 insertions(+)
create mode 100644 lib/efi_selftest/efi_selftest_reset.c
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 45ce6859b8..85fe8e1216 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -31,6 +31,7 @@ efi_selftest_mem.o \
efi_selftest_memory.o \
efi_selftest_open_protocol.o \
efi_selftest_register_notify.o \
+efi_selftest_reset.o \
efi_selftest_set_virtual_address_map.o \
efi_selftest_textinput.o \
efi_selftest_textinputex.o \
diff --git a/lib/efi_selftest/efi_selftest_reset.c
b/lib/efi_selftest/efi_selftest_reset.c
new file mode 100644
index 00..a4b985d21b
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_reset.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_reset
+ *
+ * Copyright (c) 2020 Heinrich Schuchardt
+ *
+ * This test checks the following service at boot time:
+ * ResetSystem()
+ */
+
+#include
+
+static struct efi_runtime_services *runtime;
+
+/*
+ * Setup unit test.
+ *
+ * @handle:handle of the loaded image
+ * @systable: system table
+ * @return:EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+const struct efi_system_table *systable)
+{
+ runtime = systable->runtime;
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return:EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ u16 reset_data[] = L"Reset by selftest";
+
+ runtime->reset_system(EFI_RESET_COLD, EFI_SUCCESS,
+ sizeof(reset_data), reset_data);
+ efi_st_error("Reset failed.\n");
+ return EFI_ST_FAILURE;
+}
+
+EFI_UNIT_TEST(reset) = {
+ .name = "reset system",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .on_request = true,
+};
--
2.28.0
[PATCH v4 01/11] arm: dts: mt7622: add SATA reset constants
From: Frank Wunderlich add reset constants used for SATA to header file Signed-off-by: Frank Wunderlich --- include/dt-bindings/reset/mt7629-reset.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h index 8f1634f7a6..311a5cb3d0 100644 --- a/include/dt-bindings/reset/mt7629-reset.h +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -6,7 +6,10 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* PCIe Subsystem resets */ +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST15 #define PCIE1_CORE_RST 19 #define PCIE1_MMIO_RST 20 #define PCIE1_HRST 21 -- 2.25.1
[PATCH v4 02/11] phy: mtk-tphy: add PHY_TYPE_SATA
From: Frank Wunderlich
add support for PHY_TYPE_SATA to Mediateks TPHY driver
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
drivers/phy/phy-mtk-tphy.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 1e65c24356..326227a30d 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -175,6 +175,65 @@
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSKGENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSKGENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION20x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSKGENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION90x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x) (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL10x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL40x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL60x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL10x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSKGENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL40xd8
+#define RG_CDR_BIRLTD0_GEN1_MSKGENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL50xdc
+#define RG_CDR_BIRLTD0_GEN3_MSKGENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
enum mtk_phy_version {
MTK_TPHY_V1 = 1,
MTK_TPHY_V2,
@@ -372,6 +431,45 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
udelay(3000);
}
+static void sata_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
+ RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
+ RG_CDR_BIRLTR_GEN1_VAL(0x6) |
+ RG_CDR_BC_GEN1_VAL(0x1a));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
+ RG_CDR_BIRLTD0_GEN1_MSK,
+ RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
+ RG_CDR_BIRLTD0_GEN3_MSK,
+ RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
+ RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
+ RG_CDR_BICLTR_GEN1_VAL(0x0c) |
+ RG_CDR_BR_GEN2_VAL(0x07));
+ clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
+ RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
+ RG_CDR_BICLTD0_GEN1_VAL(0x08) |
+ RG_CDR_BICLTD1_GEN1_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
+ RG_LOCK_CNT_SEL_MSK,
+ RG_LOCK_CNT_SEL_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
+ RG_T2_MIN_MSK | RG_TG_MIN_MSK |
+ RG_T2_MAX_MSK | RG_TG_MAX_MSK,
+ RG_T2_MIN_VAL(0
[PATCH v4 00/11] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622>
From: Frank Wunderlich This series adds Mediatek AHCI driver, makes neccessary phy modifications creates new dts for bananapi-r64 (because it's a bit different to rfb) and adds all DTS nodes to get SATA and USB working on mt7622 and mt7623 they are based on top of this: Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888 and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331 v3->v4: - fix wrong squashing of pciesys-comment v2->v3: - fixed code style suggested by sam v1->v2: - made register of phy optional for tphy v1 and remove it in dts Frank Wunderlich (11): arm: dts: mt7622: add SATA reset constants phy: mtk-tphy: add PHY_TYPE_SATA phy: mtk-tphy: make shared reg optional for v1 reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add watchdog-reboot node for mt7622 arm: dts: add dts for Bananapi-R64 arm: dts: mt7622: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes arch/arm/dts/Makefile| 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 92 ++ arch/arm/dts/mt7623.dtsi | 46 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 128 + drivers/clk/mediatek/clk-mt7622.c| 56 ++ drivers/phy/phy-mtk-tphy.c | 110 ++- include/dt-bindings/reset/mt7629-reset.h | 5 +- 12 files changed, 690 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts create mode 100644 drivers/ata/mtk_ahci.c -- 2.25.1
[PATCH v4 06/11] clk: mt7622: add needed clocks for ssusb-node
From: Frank Wunderlich
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 42 +++
1 file changed, 42 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index a1a35f72a3..0246149107 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift,\
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
.xtal2_rate = 25 * MHZ,
@@ -630,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
}
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7622_apmixed_compat[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" },
{ }
@@ -670,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
{ }
};
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ssusbsys" },
+ { }
+};
+
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7622-mcucfg",
.id = UCLASS_SYSCON,
@@ -746,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7622-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ssusbsys_compat,
+ .probe = mt7622_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--
2.25.1
[PATCH v4 07/11] arm: dts: add watchdog-reboot node for mt7622
From: Frank Wunderlich
adding a wdt-reboot node to mt7622 dtsi
Signed-off-by: Frank Wunderlich
---
arch/arm/dts/mt7622.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index d0783bc9ff..fec071643e 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -142,6 +142,11 @@
reg = <0x10212000 0x800>;
};
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&watchdog>;
+ };
+
gic: interrupt-controller@1030 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.25.1
[PATCH v4 03/11] phy: mtk-tphy: make shared reg optional for v1
From: Frank Wunderlich
make the shared reg optional when version is v1 for sata
Suggested-by: Chunfeng Yun
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
drivers/phy/phy-mtk-tphy.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 326227a30d..3d7b9cd2b1 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -698,11 +698,10 @@ static int mtk_tphy_probe(struct udevice *dev)
tphy->dev = dev;
tphy->version = dev_get_driver_data(dev);
- /* v1 has shared banks */
+ /* v1 has shared banks for usb/pcie mode, */
+ /* but not for sata mode */
if (tphy->version == MTK_TPHY_V1) {
tphy->sif_base = dev_read_addr_ptr(dev);
- if (!tphy->sif_base)
- return -ENOENT;
}
dev_for_each_subnode(subnode, dev) {
--
2.25.1
[PATCH v4 04/11] reset: add basic reset controller for pciesys
From: Frank Wunderlich
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index bd86b5b974..a1a35f72a3 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -594,6 +594,19 @@ static int mt7622_pciesys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
}
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
static int mt7622_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -710,6 +723,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
.id = UCLASS_CLK,
.of_match = mt7622_pciesys_compat,
.probe = mt7622_pciesys_probe,
+ .bind = mt7622_pciesys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
--
2.25.1
[PATCH v4 05/11] ahci: mediatek: add ahci driver
From: Frank Wunderlich
add AHCI driver ported from linux
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c
Signed-off-by: Frank Wunderlich
---
drivers/ata/Kconfig| 8 +++
drivers/ata/Makefile | 1 +
drivers/ata/mtk_ahci.c | 128 +
3 files changed, 137 insertions(+)
create mode 100644 drivers/ata/mtk_ahci.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index d8c9756c2a..f2f8275aec 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -130,4 +130,12 @@ config AHCI_MVEBU
onboard AHCI SATA.
If unsure, say N.
+
+config MTK_AHCI
+ bool "Enable Mediatek AHCI driver support"
+ depends on AHCI
+ help
+ Enable this driver to support Sata devices through
+ Mediatek AHCI controller (e.g. MT7622).
+
endmenu
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a69edb10f7..98fb480700 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
+obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
new file mode 100644
index 00..4ad260a5bb
--- /dev/null
+++ b/drivers/ata/mtk_ahci.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTK SATA platform driver
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Ryder Lee
+ * Author: Frank Wunderlich
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYS_CFG0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_ENBIT(31)
+
+struct mtk_ahci_priv {
+ void *base;
+
+ struct ahci_uc_priv ahci_priv;
+ struct regmap *mode;
+ struct reset_ctl_bulk rst_bulk;
+};
+
+static int mtk_ahci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int mtk_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_remap_addr_index(dev, 0);
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
+ struct udevice *dev)
+{
+ struct mtk_ahci_priv *plat = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+
+ /* enable SATA function if needed */
+ if (fdt_get_property(fdt, dev_of_offset(dev),
+"mediatek,phy-mode", NULL)) {
+ plat->mode = syscon_regmap_lookup_by_phandle(dev,
+ "mediatek,phy-mode");
+ if (IS_ERR(plat->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(plat->mode);
+ }
+ regmap_update_bits(plat->mode, SYS_CFG,
+ SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
+ }
+
+ ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map);
+ return 0;
+}
+
+static int mtk_ahci_probe(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+ int ret;
+ struct phy phy;
+
+ ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(dev, &priv->rst_bulk);
+ if (!ret) {
+ reset_assert_bulk(&priv->rst_bulk);
+ reset_deassert_bulk(&priv->rst_bulk);
+ } else {
+ dev_err(dev, "Failed to get reset: %d\n", ret);
+ }
+
+ ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
+ if (ret) {
+ pr_err("can't get the phy from DT\n");
+ return ret;
+ }
+
+ ret = generic_phy_init(&phy);
+ if (ret) {
+ pr_err("unable to initialize the sata phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ pr_err("unable to power on the sata phy\n");
+ return ret;
+ }
+
+ return ahci_probe_scsi(dev, (ulong)priv->base);
+}
+
+static const struct udevice_id mtk_ahci_ids[] = {
+ { .compatible = "mediatek,mtk-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_ahci) = {
+ .name = "mtk_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = mtk_ahci_ids,
+ .bind = mtk_ahci_bind,
+ .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata,
+ .ops= &scsi_ops,
+ .probe = mtk_ahci_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv),
+};
--
2.25.1
[PATCH v4 08/11] arm: dts: add dts for Bananapi-R64
From: Frank Wunderlich
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support
Signed-off-by: Frank Wunderlich
---
v1->v2:
- changed name
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 206 +++
2 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8ecf63e988..ff0e76f808 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -959,6 +959,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
+ mt7622-bananapi-bpi-r64.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
new file mode 100644
index 00..768f15bc2c
--- /dev/null
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt7622-u-boot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mt7622-bpi-r64";
+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ aliases {
+ spi0 = &snfi;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x4000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&pinctrl {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ pwm_pins: pwm1 {
+ mux {
+ function = "pwm";
+ groups = "pwm_ch1_0" ;
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+*/
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+* DAT2, DAT3, CMD, CLK for SD respectively.
+*/
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up
[PATCH v4 11/11] arm: dts: mt7623: add USB nodes
From: Frank Wunderlich
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
arch/arm/dts/mt7623.dtsi | 46
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +
2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 0452889ef8..b5a802552b 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -352,6 +352,52 @@
};
};
+ usb1: usb@1a1c {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a1c 0x1000>, <0x1a1c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a1c4000 {
+ compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
+
+ reg = <0x1a1c4000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0x1a1c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0x1a1c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ };
+ };
+
+ usb2: usb@1a24 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a24 0x1000>, <0x1a244700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
u3phy2: usb-phy@1a244000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index bcedcf20f1..ef07369627 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
+
+&usb1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
--
2.25.1
[PATCH v4 10/11] arm: dts: mt7622: add USB nodes
From: Frank Wunderlich
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
v1->v2:
- remove clk25m as it's not needed
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8
arch/arm/dts/mt7622-rfb.dts | 8
arch/arm/dts/mt7622.dtsi | 56
3 files changed, 72 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index c36ec8f8d0..7cd581cf7d 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -213,3 +213,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 317fc78abd..ef7d0f0270 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -222,3 +222,11 @@
full-duplex;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 6b4260407e..5a4dab185f 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -192,6 +192,14 @@
status = "disabled";
};
+ ssusbsys: ssusbsys@1a00 {
+ compatible = "mediatek,mt7622-ssusbsys",
+"syscon";
+ reg = <0x1a00 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -301,6 +309,54 @@
};
};
+ ssusb: usb@1a0c {
+ compatible = "mediatek,mt7622-xhci",
+"mediatek,mtk-xhci";
+ reg = <0x1a0c 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = ;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+<&ssusbsys CLK_SSUSB_REF_EN>,
+<&ssusbsys CLK_SSUSB_MCU_EN>,
+<&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy@1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+"mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
[PATCH v4 09/11] arm: dts: mt7622: add sata- and asm_sel nodes
From: Frank Wunderlich
asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++
arch/arm/dts/mt7622.dtsi | 31
2 files changed, 40 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 768f15bc2c..c36ec8f8d0 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -204,3 +204,12 @@
full-duplex;
};
};
+
+&gpio {
+ /*gpio 90 for setting mode to sata*/
+ asm_sel {
+ gpio-hog;
+ gpios = <90 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index fec071643e..6b4260407e 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt7622";
@@ -270,6 +271,36 @@
};
};
+ sata: sata@1a20 {
+ compatible = "mediatek,mtk-ahci";
+ reg = <0x1a20 0x1100>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ ports-implemented = <0x1>;
+ phys = <&sata_port PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ status = "okay";
+ };
+
+ sata_phy: sata-phy@1a243000 {
+ compatible = "mediatek,generic-tphy-v1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ sata_port: sata-phy@1a243000 {
+ reg = <0x1a243000 0x0100>;
+ clocks = <&topckgen CLK_TOP_ETH_500M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
[PATCH v7 00/10] Remove CONFIG_NR_DRAM_BANKS option and bi_memstart/memsize from bd_info
This patchset is an extension of the previous single patch "CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined". With a split into separate patches, its hopefully easier to understand, what is changed. The earlier patch versions tried a simple search and replace of the bi_memstart / bi_memsize values with bi_dram[].start/.size. This did not work. This patchset now removes some of the assignments and changes in most cases to gd->ram_base/ram_size instead, which seems a better choice. Successful Azure build report: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=38&view=results Thanks, Stefan Changes in v7: - Add Reviewe-by tag from Ovidiu - Reword commit text as suggested by Wolfgang - Add Reviewe-by tag from Ovidiu - Add Reviewe-by tag from Ovidiu - Add Reviewe-by tag from Ovidiu Changes in v6: - Simplify dram_init_banksize() even more as suggested by Daniel Changes in v5: - Add Reviewed-by tag from Pali & Andy - Move "bd" assignment as suggested by Andy - Use PHYSADDR() for xtensa, as the bi_memstart value was originally defined this way - New patch to fix the failing "test.py xtfpga" CI test - Add Tested-by tag from Oleksandr & Michael Changes in v4: - Only remove dead code with CONFIG_NR_DRAM_BANKS always defined - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch Stefan Roese (10): CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined image: Use gd->ram_base/_size in env_get_bootm_size() board_f: Add default values for bi_dram[] in dram_init_banksize() global: Move from bi_memstart/memsize -> gd->ram_base/ram_size xtensa: Remove arch_setup_bdinfo() xtensa: Remove local no-op dram_init_banksize() video: cfb_console.c: Use bi_dram[] values on all platforms powerpc: Remove bi_memstart & bi_memsize assignments in spl.c cmd: bdinfo: Remove print of superseeded bi_memstart / bi_memsize values asm-generic/u-boot.h: Remove bi_memstart & bi_memsize from bd_info api/api_platform-mips.c | 3 +-- api/api_platform-powerpc.c| 2 +- arch/mips/lib/boot.c | 2 +- arch/mips/lib/bootm.c | 2 +- arch/powerpc/cpu/mpc83xx/fdt.c| 2 +- arch/powerpc/cpu/mpc83xx/traps.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c| 4 ++-- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc86xx/fdt.c| 4 +++- arch/powerpc/cpu/mpc86xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xx/fdt.c | 2 +- arch/powerpc/lib/bootm.c | 4 ++-- arch/x86/cpu/broadwell/cpu_from_spl.c | 2 -- arch/xtensa/lib/Makefile | 2 +- arch/xtensa/lib/bdinfo.c | 22 -- arch/xtensa/lib/bootm.c | 5 ++-- board/Arcturus/ucp1020/spl.c | 2 -- board/cadence/xtfpga/xtfpga.c | 5 board/freescale/p1010rdb/spl.c| 2 -- board/freescale/p1_p2_rdb_pc/spl.c| 2 -- board/freescale/t102xrdb/spl.c| 2 -- board/freescale/t104xrdb/spl.c| 2 -- board/freescale/t208xqds/spl.c| 2 -- board/freescale/t208xrdb/spl.c| 2 -- board/freescale/t4rdb/spl.c | 2 -- board/xilinx/zynqmp/zynqmp.c | 2 -- cmd/bdinfo.c | 10 cmd/bedbug.c | 2 +- common/board_f.c | 12 +- common/image.c| 10 ++-- common/init/handoff.c | 33 +++ drivers/pci/pci-uclass.c | 18 ++- drivers/video/cfb_console.c | 8 +-- include/asm-generic/u-boot.h | 4 include/handoff.h | 2 -- lib/fdtdec.c | 5 lib/lmb.c | 9 ++-- 37 files changed, 41 insertions(+), 157 deletions(-) delete mode 100644 arch/xtensa/lib/bdinfo.c -- 2.28.0
[PATCH] board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support
Add support PHYTEC phyCORE-i.MX8MM SOM.
Supported features:
- 2GB LPDDR4 RAM
- 1x 1Gbit Ethernet
- eMMC
- external SD
- debug UART3
- watchdog
- i2c eeprom
Signed-off-by: Teresa Remmet
---
arch/arm/dts/Makefile|1 +
arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 100 ++
arch/arm/dts/phycore-imx8mm.dts | 259
arch/arm/mach-imx/imx8m/Kconfig |6 +
board/phytec/phycore_imx8mm/Kconfig | 12 +
board/phytec/phycore_imx8mm/MAINTAINERS |9 +
board/phytec/phycore_imx8mm/Makefile | 11 +
board/phytec/phycore_imx8mm/lpddr4_timing.c | 1846 ++
board/phytec/phycore_imx8mm/phycore-imx8mm.c | 53 +
board/phytec/phycore_imx8mm/spl.c| 128 ++
configs/phycore-imx8mm_defconfig | 103 ++
include/configs/phycore_imx8mm.h | 131 ++
12 files changed, 2659 insertions(+)
create mode 100644 arch/arm/dts/phycore-imx8mm-u-boot.dtsi
create mode 100644 arch/arm/dts/phycore-imx8mm.dts
create mode 100644 board/phytec/phycore_imx8mm/Kconfig
create mode 100644 board/phytec/phycore_imx8mm/MAINTAINERS
create mode 100644 board/phytec/phycore_imx8mm/Makefile
create mode 100644 board/phytec/phycore_imx8mm/lpddr4_timing.c
create mode 100644 board/phytec/phycore_imx8mm/phycore-imx8mm.c
create mode 100644 board/phytec/phycore_imx8mm/spl.c
create mode 100644 configs/phycore-imx8mm_defconfig
create mode 100644 include/configs/phycore_imx8mm.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7e29b9096b93..d72037ae4d7d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-verdin.dtb \
+ phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
new file mode 100644
index ..fc0fa22d1bb4
--- /dev/null
+++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts
new file mode 100644
index ..c46d3c72ced9
--- /dev/null
+++ b/arch/arm/dts/phycore-imx8mm.dts
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet
+ */
+
+/dts-v1/;
+
+#include
+#include "imx8mm.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX8MM";
+ compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
+
+ chosen {
+ stdout-patch = &uart3;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+/* ethernet */
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ ti,rx-internal-de
RE: [PATCH] arm: dts: fix ast2500-evb inclusion for correct target
Hi > -Original Message- > From: Thirupathaiah Annapureddy [mailto:thir...@linux.microsoft.com] > Sent: Thursday, August 20, 2020 8:16 AM > To: u-boot@lists.denx.de > Cc: Maxim Sloyko ; Marek Vasut ; > ChiaWei Wang ; Ryan Chen > > Subject: Re: [PATCH] arm: dts: fix ast2500-evb inclusion for correct target > > Adding Ryan and Chiawei to the list. > > On 8/17/2020 5:53 PM, Thirupathaiah Annapureddy wrote: > > Include ast2500-evb.dtb for CONFIG_TARGET_EVB_AST2500 instead of for > > all aspeed targets. There should not have to many Kconfig for ASPEED platform. I prefer use following to build all all ASPEED platform. Like following. dtb-$(CONFIG_ARCH_ASPEED) += \ ast2400-evb.dtb \ ast2500-evb.dtb \ ast2600a0-evb.dtb \ ast2600a0-ncsi.dtb \ ast2600a1-evb.dtb \ ast2600a1-ncsi.dtb \ ast2600-fpga.dtb \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb > > > > Signed-off-by: Thirupathaiah Annapureddy > --- > > arch/arm/dts/Makefile | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > > 7e29b9096b..d019f26983 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ > > > > dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb > > > > -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb > > +dtb-$(CONFIG_TARGET_EVB_AST2500) += ast2500-evb.dtb > > > > dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb > > > >
