[PATCH 1/1] efi_loader: document efi_save_gd(), efi_restore_gd()
Provide function descriptions for efi_save_gd() and efi_restore_gd().
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_boottime.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0b16554ba2..d49145fc76 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -104,7 +104,15 @@ int __efi_exit_check(void)
return ret;
}
-/* Called from do_bootefi_exec() */
+/**
+ * efi_save_gd() - save global data register
+ *
+ * On the ARM architecture gd is mapped to a fixed register (r9 or x18).
+ * As this register may be overwritten by an EFI payload we save it here
+ * and restore it on every callback entered.
+ *
+ * This function is called after relocation from initr_reloc_global_data().
+ */
void efi_save_gd(void)
{
#ifdef CONFIG_ARM
@@ -112,10 +120,12 @@ void efi_save_gd(void)
#endif
}
-/*
- * Special case handler for error/abort that just forces things back to u-boot
- * world so we can dump out an abort message, without any care about returning
- * back to UEFI world.
+/**
+ * efi_restore_gd() - restore global data register
+ *
+ * On the ARM architecture gd is mapped to a fixed register (r9 or x18).
+ * Restore it after returning from the UEFI world to the value saved via
+ * efi_save_gd().
*/
void efi_restore_gd(void)
{
--
2.27.0
[PATCH 1/1] efi_loader: returning form UEFI FIT images
Do not reset the board when returning from an UEFI FIT image.
For failed UEFI binary we already print the return status in efi_run_image.
Remove duplicate output.
Signed-off-by: Heinrich Schuchardt
---
common/bootm_os.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 55296483f7..8b4397693a 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -542,15 +542,14 @@ static int do_bootm_efi(int flag, int argc, char *const
argv[],
images->ep);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+ /* We expect to return */
+ images->os.type = IH_TYPE_STANDALONE;
+
image_buf = map_sysmem(images->ep, images->os.image_len);
efi_ret = efi_run_image(image_buf, images->os.image_len);
- if (efi_ret != EFI_SUCCESS) {
- printf("## Failed to run EFI image: r = %lu\n",
- efi_ret & ~EFI_ERROR_MASK);
+ if (efi_ret != EFI_SUCCESS)
return 1;
- }
-
return 0;
}
#endif
--
2.27.0
[PATCH 1/1] ls1088ardb :Set CONFIG_SYS_BOARD to ls1088ardb
From: Jaiprakash Singh Env variable board and board_name set to CONFIG_SYS_BOARD Signed-off-by: Jaiprakash Singh --- include/configs/ls1088ardb.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 815449f..650ffa3 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -319,6 +319,8 @@ #endif /* CONFIG_TFABOOT */ #undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "ls1088ardb" #ifdef CONFIG_TFABOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "BOARD=ls1088ardb\0"\ -- 2.7.4
Re: [PATCH 1/3] phy: Add Rockchip PCIe PHY driver
On 2020/7/10 上午2:11, Jagan Teki wrote:
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile| 1 +
drivers/phy/rockchip/phy-rockchip-pcie.c | 271 +++
3 files changed, 279 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-pcie.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 84cc7c876d..2318e71f35 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2
help
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
+config PHY_ROCKCHIP_PCIE
+ bool "Rockchip PCIe PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip PCIe PHY.
+
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
depends on ARCH_ROCKCHIP
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 95b2f8a3c0..44049154f9 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,4 +4,5 @@
#
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_PCIE)+= phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c
b/drivers/phy/rockchip/phy-rockchip-pcie.c
new file mode 100644
index 00..83928cffe0
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: (GPL-2.0-only)
+/*
+ * Rockchip PCIe PHY driver
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) 2016 Shawn Lin
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define PHY_MAX_LANE_NUM 4
+#define PHY_CFG_DATA_SHIFT7
+#define PHY_CFG_ADDR_SHIFT1
+#define PHY_CFG_DATA_MASK 0xf
+#define PHY_CFG_ADDR_MASK 0x3f
+#define PHY_CFG_RD_MASK 0x3ff
+#define PHY_CFG_WR_ENABLE 1
+#define PHY_CFG_WR_DISABLE1
+#define PHY_CFG_WR_SHIFT 0
+#define PHY_CFG_WR_MASK 1
+#define PHY_CFG_PLL_LOCK 0x10
+#define PHY_CFG_CLK_TEST 0x10
+#define PHY_CFG_CLK_SCC 0x12
+#define PHY_CFG_SEPE_RATE BIT(3)
+#define PHY_CFG_PLL_100M BIT(3)
+#define PHY_PLL_LOCKEDBIT(9)
+#define PHY_PLL_OUTPUTBIT(10)
+#define PHY_LANE_RX_DET_SHIFT 11
+#define PHY_LANE_RX_DET_TH0x1
+#define PHY_LANE_IDLE_OFF 0x1
+#define PHY_LANE_IDLE_MASK0x1
+#define PHY_LANE_IDLE_A_SHIFT 3
+#define PHY_LANE_IDLE_B_SHIFT 4
+#define PHY_LANE_IDLE_C_SHIFT 5
+#define PHY_LANE_IDLE_D_SHIFT 6
+
+struct rockchip_pcie_phy_data {
+ unsigned int pcie_conf;
+ unsigned int pcie_status;
+ unsigned int pcie_laneoff;
+};
+
+struct rockchip_pcie_phy {
+ void *reg_base;
+ struct clk refclk;
+ struct reset_ctl phy_rst;
+ const struct rockchip_pcie_phy_data *data;
+};
+
+static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
+{
+ u32 reg;
+
+ reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
+ reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+}
+
+static int rockchip_pcie_phy_power_on(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret = 0;
+ u32 reg, status;
+
+ ret = reset_deassert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_laneof
Re: [PATCH 2/3] pci: rockchip: Switch to generic-phy
On 2020/7/10 上午2:11, Jagan Teki wrote:
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pci/Kconfig | 1 +
drivers/pci/pcie_rockchip.c | 20 ++--
drivers/pci/pcie_rockchip.h | 5 +
3 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d8c22aacf..58ca673e4b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -200,6 +200,7 @@ config PCIE_MEDIATEK
config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"
select DM_PCI
+ select PHY_ROCKCHIP_PCIE
default y if ROCKCHIP_RK3399
help
Say Y here if you want to enable PCIe controller support on
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 0edc2464a8..ce573aa4b4 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie
*priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
- struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
- ret = ops->init(phy);
+ ret = generic_phy_init(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
goto err_exit_phy;
@@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = ops->power_on(phy);
+ ret = generic_phy_power_on(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
goto err_power_off_phy;
@@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return 0;
err_power_off_phy:
- ops->power_off(phy);
+ generic_phy_power_off(&priv->pcie_phy);
err_exit_phy:
- ops->exit(phy);
+ generic_phy_exit(&priv->pcie_phy);
return ret;
}
@@ -443,6 +441,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return ret;
}
+ ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -460,10 +464,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
if (ret)
return ret;
- ret = rockchip_pcie_phy_get(dev);
- if (ret)
- return ret;
-
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
return ret;
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
index 845d5059e1..6d20d5232d 100644
--- a/drivers/pci/pcie_rockchip.h
+++ b/drivers/pci/pcie_rockchip.h
@@ -9,6 +9,8 @@
*
*/
+#include
+
#define HIWORD_UPDATE(mask, val)(((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -126,6 +128,9 @@ struct rockchip_pcie {
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
};
int rockchip_pcie_phy_get(struct udevice *dev);
Re: [PATCH 3/3] pci: rockchip: Drop legacy PHY driver
On 2020/7/10 上午2:11, Jagan Teki wrote:
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pci/Makefile| 2 +-
drivers/pci/pcie_rockchip.c | 75 +++-
drivers/pci/pcie_rockchip.h | 146 ---
drivers/pci/pcie_rockchip_phy.c | 205
4 files changed, 74 insertions(+), 354 deletions(-)
delete mode 100644 drivers/pci/pcie_rockchip.h
delete mode 100644 drivers/pci/pcie_rockchip_phy.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 955351c5c2..493e9354dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index ce573aa4b4..04609f1296 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -25,10 +26,80 @@
#include
#include
-#include "pcie_rockchip.h"
-
DECLARE_GLOBAL_DATA_PTR;
+#define HIWORD_UPDATE(mask, val)(((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x) x) >> 1) & 3) << 4)
+#define PCIE_CLIENT_BASE0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
+#define PCIE_CLIENT_BASIC_STATUS1 0x0048
+#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
+#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
+#define PCIE_LINK_UP(x) \
+ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE0x80
+#define PCIE_LM_BASE 0x90
+#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
+#define PCIE_LM_VENDOR_ROCKCHIP0x1d87
+#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
+#define PCIE_LM_RCBARPIE BIT(19)
+#define PCIE_LM_RCBARPIS BIT(20)
+#define PCIE_RC_BASE 0xa0
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
+#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
+#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
+#define PCIE_ATR_BASE 0xc0
+#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
+#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
+#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
+#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
+#define PCIE_ATR_HDR_MEM 0x2
+#define PCIE_ATR_HDR_IO0x6
+#define PCIE_ATR_HDR_CFG_TYPE0 0xa
+#define PCIE_ATR_HDR_CFG_TYPE1 0xb
+#define PCIE_ATR_HDR_RID BIT(23)
+
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
+#define PCIE_ATR_OB_REGION_SIZE(1 * 1024 * 1024)
+
+struct rockchip_pcie {
+ fdt_addr_t axi_base;
+ fdt_addr_t apb_base;
+ int first_busno;
+ struct udevice *dev;
+
+ /* resets */
+ struct reset_ctl core_rst;
+ struct reset_ctl mgmt_rst;
+ struct reset_ctl mgmt_sticky_rst;
+ struct reset_ctl pipe_rst;
+ struct reset_ctl pm_rst;
+ struct reset_ctl pclk_rst;
+ struct reset_ctl aclk_rst;
+
+ /* gpio */
+ struct gpio_desc ep_gpio;
+
+ /* vpcie regulators */
+ struct udevice *vpcie12v;
+ struct udevice *vpcie3v3;
+ struct udevice *vpcie1v8;
+ struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
+};
+
static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
{
unsigned int bus = PCI_BUS(bdf);
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
deleted file mode 100644
index 6d20d5232d..00
--- a/drivers/pci/pcie_rockchip.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Rockchip PCIe Headers
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020
Re: [PATCH v4 3/4] rtc: rk8xx: Add base support for the RK808 PMIC RTC
Hi Jagan,
On 2020/7/10 下午11:50, Jagan Teki wrote:
From: Suniel Mahesh
Rockchip RK808 PMIC provides an integrated RTC module. It is
commonly used with Rockchip SoCs. Add basic support to access
date and time.
Signed-off-by: Jagan Teki
---
Change for v4:
- rebase
- style fixes
- warning fixes
Seems like the change request by Elaine in previous version does not
update ?
Thanks,
- Kever
drivers/rtc/Kconfig | 8 ++
drivers/rtc/Makefile| 1 +
drivers/rtc/rk808-rtc.c | 173
3 files changed, 182 insertions(+)
create mode 100644 drivers/rtc/rk808-rtc.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 59e2fc44ba..a754d1b4f1 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -75,6 +75,14 @@ config RTC_ISL1208
This driver supports reading and writing the RTC/calendar and detects
total power failures.
+config RTC_RK808
+ bool "Enable Rockchip RK8XX RTC driver"
+depends on DM_RTC && PMIC_RK8XX
+ default y
+ help
+ Basic support for Rockchip RK808 PMIC Real Time Clock devices for
+ time and date.
+
config RTC_RV3029
bool "Enable RV3029 driver"
depends on DM_RTC
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 12eb449583..63e2c3413d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
obj-$(CONFIG_RTC_PCF2127) += pcf2127.o
obj-$(CONFIG_RTC_PL031) += pl031.o
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
+obj-$(CONFIG_RTC_RK808) += rk808-rtc.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
obj-$(CONFIG_RTC_RV3029) += rv3029.o
obj-$(CONFIG_RTC_RV8803) += rv8803.o
diff --git a/drivers/rtc/rk808-rtc.c b/drivers/rtc/rk808-rtc.c
new file mode 100644
index 00..50cca4dd4b
--- /dev/null
+++ b/drivers/rtc/rk808-rtc.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RTC driver for Rockchip RK808 PMIC.
+ *
+ * Copyright (C) 2020 Amarula Solutions(India).
+ * Suniel Mahesh
+ *
+ * Based on code from Linux kernel:
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Chris Zhong
+ * Author: Zhang Qing
+ *
+ * Date & Time support (no alarms and interrupts)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* RTC_CTRL_REG bitfields */
+#define BIT_RTC_CTRL_REG_STOP_RTC_MBIT(0)
+
+/* RK808 has a shadowed register for saving a "frozen" RTC time.
+ * When user setting "GET_TIME" to 1, the time will save in this shadowed
+ * register. If set "READSEL" to 1, user read rtc time register, actually
+ * get the time of that moment. If we need the real time, clr this bit.
+ */
+
+#define BIT_RTC_CTRL_REG_RTC_GET_TIME BIT(6)
+#define BIT_RTC_CTRL_REG_RTC_READSEL_M BIT(7)
+#define RTC_STATUS_MASK0xFE
+
+#define SECONDS_REG_MSK0x7F
+#define MINUTES_REG_MAK0x7F
+#define HOURS_REG_MSK 0x3F
+#define DAYS_REG_MSK 0x3F
+#define MONTHS_REG_MSK 0x1F
+#define YEARS_REG_MSK 0xFF
+#define WEEKS_REG_MSK 0x7
+
+/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
+
+#define NUM_TIME_REGS (REG_WEEKS - REG_SECONDS + 1)
+
+static int rk808_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ u8 rtc_data[NUM_TIME_REGS];
+
+ debug("RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday,
+ tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ rtc_data[0] = bin2bcd(tm->tm_sec);
+ rtc_data[1] = bin2bcd(tm->tm_min);
+ rtc_data[2] = bin2bcd(tm->tm_hour);
+ rtc_data[3] = bin2bcd(tm->tm_mday);
+ rtc_data[4] = bin2bcd(tm->tm_mon);
+ rtc_data[5] = bin2bcd(tm->tm_year - 2000);
+ rtc_data[6] = bin2bcd(tm->tm_wday);
+
+ /* Stop RTC while updating the RTC registers */
+ pmic_clrsetbits(dev->parent, REG_RTC_CTRL, 0,
+ BIT_RTC_CTRL_REG_STOP_RTC_M);
+ pmic_write(dev->parent, REG_SECONDS, rtc_data, NUM_TIME_REGS);
+
+ /* Start RTC again */
+ pmic_clrsetbits(dev->parent, REG_RTC_CTRL,
+ BIT_RTC_CTRL_REG_STOP_RTC_M, 0);
+
+ return 0;
+}
+
+static int rk808_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ u8 rtc_data[NUM_TIME_REGS];
+
+ /* Force an update of the shadowed registers right now */
+ pmic_clrsetbits(dev->parent, REG_RTC_CTRL, 0,
+ BIT_RTC_CTRL_REG_RTC_GET_TIME);
+
+ /*
+* After we set the GET_TIME bit, the rtc time can't be read
+* immediately. So we should wait up to 31.25 us, about one cycle of
+* 32khz. If we clear the GET_TIME bit here, the time of i2c transfer
+* certa
Re: [PATCH 1/3] ram: rk3399: Drop debug stride in driver
On 2020/7/14 上午4:06, Jagan Teki wrote:
stride debug is already present in sdram_common.c via
RAM_ROCKCHIP_DEBUG.
So, drop the redundant debug stride code in rk3399 driver.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/ram/rockchip/sdram_rk3399.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 60a1ab8b51..d2f3fde236 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2875,31 +2875,6 @@ static unsigned char calculate_stride(struct
rk3399_sdram_params *params)
if (stride == (-1))
goto error;
}
- switch (stride) {
- case 0xc:
- printf("128B stride\n");
- break;
- case 5:
- case 9:
- case 0xd:
- case 0x11:
- case 0x19:
- printf("256B stride\n");
- break;
- case 0xa:
- case 0xe:
- case 0x12:
- printf("512B stride\n");
- break;
- case 0xf:
- printf("4K stride\n");
- break;
- case 0x1f:
- printf("32MB + 256B stride\n");
- break;
- default:
- printf("no stride\n");
- }
sdram_print_stride(stride);
Re: [PATCH 2/3] ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUG
On 2020/7/14 上午4:06, Jagan Teki wrote:
Right now all these debug statements are printing on the
console to make sure proper dram initialization happens.
Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful
and work like before since the RAM_ROCKCHIP_DEBUG is by
default yet.
No functionality changes.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/ram/rockchip/sdram_rk3399.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index d2f3fde236..670925420d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2551,8 +2551,10 @@ static int lpddr4_set_rate(struct dram_info *dram,
lpddr4_set_ctl(dram, params, ctl_fn,
dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
- printf("%s: change freq to %d mhz %d, %d\n", __func__,
- dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+ printf("%s: change freq to %d mhz %d, %d\n", __func__,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+ ctl_fn, phy_fn);
}
return 0;
@@ -2966,8 +2968,10 @@ static int sdram_init(struct dram_info *dram,
params->base.num_channels++;
}
- printf("Channel ");
- printf(channel ? "1: " : "0: ");
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+ printf("Channel ");
+ printf(channel ? "1: " : "0: ");
+ }
if (channel == 0)
set_ddr_stride(dram->pmusgrf, 0x17);
Re: [PATCH 3/3] roc-rk3399-pc: Disable RAM_ROCKCHIP_DEBUG
On 2020/7/14 上午4:06, Jagan Teki wrote: Disable ram rockchip debug driver for roc-rk3399-pc boards since we have verified ram in many instances with respective U-Boot versions. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index f15dddc684..c87a8568fc 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -53,6 +53,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=150 diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 9ffde7f960..601f5c6ae1 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -50,6 +50,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=150
Re: [PATCH v5 2/5] rockchip: Don't clear the reset status reg
On 2020/7/14 下午5:32, Jagan Teki wrote:
reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.
Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.
However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v5:
- new patch
arch/arm/include/asm/arch-rockchip/cru.h | 1 -
arch/arm/mach-rockchip/cpu-info.c| 6 --
2 files changed, 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
index 5eb17f9d55..d2057cb738 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -26,7 +26,6 @@ enum {
SND_GLB_TSADC_RST_ST= BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
- GLB_RST_ST_MASK = GENMASK(5, 0),
};
#define MHz 100
diff --git a/arch/arm/mach-rockchip/cpu-info.c
b/arch/arm/mach-rockchip/cpu-info.c
index 21ca9dedce..bb5a198039 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -47,12 +47,6 @@ static char *get_reset_cause(void)
*/
env_set("reset_reason", cause);
- /*
-* Clear glb_rst_st, so we can determine the last reset cause
-* for following resets.
-*/
- rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
-
return cause;
}
Re: [PATCH v5 1/5] roc-rk3399-pc: Move leds setup in SPL
On 2020/7/14 下午5:32, Jagan Teki wrote:
roc-rk3399-pc has some specific requirements to support LEDS,
environment. board detection and etc prior to U-Boot proper.
So as of now SPL would be a better stage for these custom board
requirements to support unlike TPL. Adding few of these custom
requirements like LEDS in TPL would require extra code pulling
and also the size of TPL can grow.
So, this patch moves the leds code from TPL into SPL after relocation.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v5
- drop tpl.c file
- update the code in board file
arch/arm/mach-rockchip/tpl.c| 7
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 36 +++--
configs/roc-pc-mezzanine-rk3399_defconfig | 2 +-
configs/roc-pc-rk3399_defconfig | 2 +-
4 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 88f80b05a9..cc908e1b0e 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -43,18 +43,11 @@ __weak void rockchip_stimer_init(void)
TIMER_CONTROL_REG);
}
-__weak int board_early_init_f(void)
-{
- return 0;
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
- board_early_init_f();
-
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
/*
* Debug UART can be used from here if required:
diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
index 7c3a803654..4db3dd739c 100644
--- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
+++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
@@ -6,14 +6,24 @@
#include
#include
#include
-#include
-#include
#include
-#include
+#include
+
#include
-#ifndef CONFIG_SPL_BUILD
-int board_early_init_f(void)
+#define GPIO0_BASE 0xff72
+
+static int led_setup(void)
+{
+ struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
+
+ /* Turn on red LED, indicating full power mode */
+ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
+
+ return 0;
+}
+
+static int roc_pc_early_init_f(void)
{
struct udevice *regulator;
int ret;
@@ -30,19 +40,11 @@ int board_early_init_f(void)
out:
return 0;
}
-#endif
-
-#if defined(CONFIG_TPL_BUILD)
-
-#define GPIO0_BASE 0xff72
int board_early_init_f(void)
{
- struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
-
- /* Turn on red LED, indicating full power mode */
- spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
-
- return 0;
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return led_setup();
+ else
+ return roc_pc_early_init_f();
}
-#endif
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig
b/configs/roc-pc-mezzanine-rk3399_defconfig
index c87a8568fc..15d511741f 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -21,7 +22,6 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 601f5c6ae1..2a6d0d22c8 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -21,7 +22,6 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
Re: [PATCH v5 3/5] rockchip: Separate the reset cause from display cpuinfo
On 2020/7/14 下午5:32, Jagan Teki wrote:
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed.
Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.
So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.
Tested-by: Suniel Mahesh
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v5:
- update Makefile
arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
arch/arm/mach-rockchip/Makefile | 5 -
arch/arm/mach-rockchip/cpu-info.c| 20
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
index d2057cb738..13ea4aba8e 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -30,4 +30,6 @@ enum {
#define MHz 100
+char *get_reset_cause(void);
+
#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5b38526fe0..121f23a563 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -22,11 +22,14 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
+ifeq ($(CONFIG_TPL_BUILD),)
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
+endif
+
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
diff --git a/arch/arm/mach-rockchip/cpu-info.c
b/arch/arm/mach-rockchip/cpu-info.c
index bb5a198039..d0f030109f 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -13,7 +13,7 @@
#include
#include
-static char *get_reset_cause(void)
+char *get_reset_cause(void)
{
struct rockchip_cru *cru = rockchip_get_cru();
char *cause = NULL;
@@ -41,21 +41,25 @@ static char *get_reset_cause(void)
cause = "unknown reset";
}
- /**
-* reset_reason env is used by rk3288, due to special use case
-* to figure it the boot behavior. so keep this as it is.
-*/
- env_set("reset_reason", cause);
-
return cause;
}
+#if CONFIG_IS_ENABLED(DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
+ char *cause = get_reset_cause();
+
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
- printf("Reset cause: %s\n", get_reset_cause());
+ printf("Reset cause: %s\n", cause);
+
+ /**
+* reset_reason env is used by rk3288, due to special use case
+* to figure it the boot behavior. so keep this as it is.
+*/
+ env_set("reset_reason", cause);
/* TODO print operating temparature and clock */
return 0;
}
+#endif
Re: [PATCH v5 4/5] rockchip: spl: Move board_early_init_f after cpu timer
Hi Jagan,
On 2020/7/14 下午5:32, Jagan Teki wrote:
Custom board_early_init_f not only deal with simple gpio
configuration but also have a possibility to access clocks
to process any clock related operations like checking reset
cause state and etc.
So, call it once the rockchip timer initialization done instead
of calling first place of board_init_f which doesn't have any
rockchip init code before.
This specific concern was tested with checking reset reason
via board_early_init_f, which indeed require a clk probe.
board_early_init_f() is suppose to run at very beginning before
the spl framework is init, so I don't agree this move.
I think the led setup code definitely should go to spl_board_init().
As I said before, the setup_led should be the common feature,
so I think you can have a copy of setup_led() in rk3399.c as a weak
common function, and if roc-rk3399-pc is really special, then you
can have its own implementation.
Note that the spl_board_init in SPL is already very early stage in
system init, should be enough for your case, you can do a test for
the led_setup() in board_early_init_f() after this patch and in
spl_board_init(), they should be very close.
Thanks,
- Kever
Signed-off-by: Jagan Teki
---
Changes for v5:
- new patch
arch/arm/mach-rockchip/spl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index cddf4fd3d5..082828de66 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -122,8 +122,6 @@ void board_init_f(ulong dummy)
debug("\nspl:debug uart enabled in %s\n", __func__);
#endif
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
printf("spl_early_init() failed: %d\n", ret);
@@ -137,6 +135,9 @@ void board_init_f(ulong dummy)
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
#endif
+
+ board_early_init_f();
+
#if !defined(CONFIG_TPL) || defined(CONFIG_SPL_RAM)
debug("\nspl:init dram\n");
ret = dram_init();
Re: [PATCH v2] gpio: octeon_gpio: Add GPIO controller driver for Octeon
> From: Suneel Garapati > > Add support for GPIO controllers found on Octeon II/III and Octeon TX > TX2 SoC platforms. > > Signed-off-by: Aaron Williams > Signed-off-by: Suneel Garapati > Signed-off-by: Stefan Roese > Cc: Simon Glass > Cc: Daniel Schwierzeck > Cc: Aaron Williams > Cc: Chandrakala Chavva > --- > v2 (Stefan): > - Removed #ifdef's for Octeon vs OcteonTX/TX2 completely > The differentiation is now made via driver data / compatible > string > > RFC -> v1 (Stefan) > - Separated this patch from the OcteonTX/TX2 RFC patch series into a > single patch. This is useful, as the upcoming MIPS Octeon support will > use this GPIO driver. > - Added MIPS Octeon II/III support (big endian). Rename driver and its > function names from "octeontx" to "octeon" to better match all Octeon > platforms. > - Moved from union to defines / bitmasks. This makes the driver usage > on little- and big-endian platforms much easier. > - Used clrbits_64() instead of clrbits_le64() and friends to support > usage on little- and big-endian systems > - Removed dev->req_seq assignment > - Enhanced Kconfig text > - Rewrote GPIO_BIT macro > - Dropped many macros to calculate the registers offsets and implemented > simple functions for this (easier to read) > - Used GENMASK_ULL and FIELD_GET helpers > - Minor cosmetic changes (dropped brackets etc) > - Reword commit text and subject > > drivers/gpio/Kconfig | 10 ++ > drivers/gpio/Makefile | 1 + > drivers/gpio/octeon_gpio.c | 253 + > 3 files changed, 264 insertions(+) > create mode 100644 drivers/gpio/octeon_gpio.c > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index d87f6cc105..451896f400 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -316,6 +316,16 @@ config PIC32_GPIO > help > Say yes here to support Microchip PIC32 GPIOs. > > +config OCTEON_GPIO > + bool "Octeon II/III/TX/TX2 GPIO driver" > + depends on DM_GPIO && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) > + default y > + help > + Add support for the Marvell Octeon GPIO driver. This is used with > + various Octeon parts such as Octeon II/III and OcteonTX/TX2. > + Octeon II/III has 32 GPIOs (count defined via DT) and OcteonTX/TX2 > + has 64 GPIOs (count defined via internal register). > + found another issue: drivers/gpio/octeon_gpio.c: In function 'octeon_gpio_probe': drivers/gpio/octeon_gpio.c:189:16: warning: implicit declaration of function 'dm_pci_map_bar'; did you mean 'pci_map_bar'? [-Wimplicit- function-declaration] 189 | priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, |^~ |pci_map_bar drivers/gpio/octeon_gpio.c:189:14: warning: assignment to 'void *' from 'int' makes pointer from integer without a cast [-Wint-conversion] 189 | priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, | ^ due to the dependency on DM_PCI you need to express this in Kconfig with "depends on DM_PCI ...". Alternatively you need to wrap the PCI specific code with a "#ifdef CONFIG_DM_PCI" as the DM_PCI specific function prototypes in pci.h are also wrapped with "#ifdef CONFIG_DM_PCI". The former option will build and link DM PCI code which is not used and therefore bloats the U-Boot binary. I guess the choice mainly depends on whether you'll add a PCI host controller driver for Octeon MIPS64 in the future and can live with the extra but unused PCI code until then. > config STM32_GPIO > bool "ST STM32 GPIO driver" > depends on DM_GPIO && (ARCH_STM32 || ARCH_STM32MP) > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 7638259007..eb6364adb4 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -58,6 +58,7 @@ obj-$(CONFIG_HIKEY_GPIO)+= hi6220_gpio.o > obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o > obj-$(CONFIG_IMX_RGPIO2P)+= imx_rgpio2p.o > obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o > +obj-$(CONFIG_OCTEON_GPIO)+= octeon_gpio.o > obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o > obj-$(CONFIG_MSM_GPIO) += msm_gpio.o > obj-$(CONFIG_$(SPL_)PCF8575_GPIO)+= pcf8575_gpio.o > diff --git a/drivers/gpio/octeon_gpio.c b/drivers/gpio/octeon_gpio.c > new file mode 100644 > index 00..d7ac9a1910 > --- /dev/null > +++ b/drivers/gpio/octeon_gpio.c > @@ -0,0 +1,253 @@ > +// SPDX-License-Identifier:GPL-2.0 > +/* > + * Copyright (C) 2018 Marvell International Ltd. > + * > + * (C) Copyright 2011 > + * eInfochips Ltd. > + * Written-by: Ajay Bhargav > + * > + * (C) Copyright 2010 > + * Marvell Semiconductor > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include don't use common.h anymore. Also some headers are unused. I can build the driver with: #include #include #include #include #include #i
Re: [PATCH v3 6/6] roc-rk3399-pc: Update ENV offset, size
On 2020/7/18 上午11:20, Kever Yang wrote: On 2020/7/7 下午9:50, Jagan Teki wrote: Adjust the ENV offset, size to fit into all images on 16MB flash. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Applied to u-boot-rockchip master for this patch set, thanks. Thanks, - Kever --- Changes for v3: - fix configs configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++-- configs/roc-pc-rk3399_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index b2c370cc59..f15dddc684 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0020 -CONFIG_ENV_SIZE=0x6000 -CONFIG_ENV_OFFSET=0x46 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_ROCKCHIP_RK3399=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 588d03952a..9ffde7f960 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0020 -CONFIG_ENV_SIZE=0x6000 -CONFIG_ENV_OFFSET=0x46 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_ROCKCHIP_RK3399=y
Re: [PATCH 0/3] rockchip: rk3328: Add SPI support
On 2020/7/9 上午5:57, Johannes Krottmayer wrote: This patch series adds support for the RK3328 SPI controller. Johannes Krottmayer (3): drivers: clk: rockchip: clk_rk3328: Add SPI support drivers: spi: rk_spi: Add support for RK3328 ARM: dts: rk3328: Add SPI support arch/arm/dts/rk3328-u-boot.dtsi | 5 + drivers/clk/rockchip/clk_rk3328.c | 31 +++ drivers/spi/rk_spi.c | 2 ++ 3 files changed, 38 insertions(+) Applied to u-boot-rockchip master for this patch set, thanks.
Re: [PATCH 0/2] PINE64 Rock64 board: Add SPI Flash support
On 2020/7/9 上午6:50, Johannes Krottmayer wrote: This patch series adds SPI Flash support for the PINE64 Rock64 board. Tested with the version 2.0 of the board. Johannes Krottmayer (2): ARM: dts: rk3328-rock64: Add SPI Flash support configs: rock64-rk3328_defconfig: Add SPI Flash support arch/arm/dts/rk3328-rock64-u-boot.dtsi | 6 ++ configs/rock64-rk3328_defconfig| 2 ++ 2 files changed, 8 insertions(+) Applied to u-boot-rockchip master for this patch set, thanks.
Re: [PATCH] rockchip: sdram: fix dram_init_banksize
On 2020/7/18 上午11:13, Kever Yang wrote:
Hi Alex,
Tanks for your fix.
On 2020/7/15 上午7:03, Alex Bee wrote:
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board
if CONFIG_SPL_OPTEE is set. This is troublesome when booting a
linux kernel since this size will be injected in FDT of the kernel.
gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE)
must not be taken into consideration for calculation of second bank
size, since this offset is already included in calculation of "top".
After applying this patch 992 MB (1024 MB - 32 MB reserved for
optee-os) is correctly calculated and has also been verified on
2 GB boards.
Signed-off-by: Alex Bee
Reviewed-by: Kever Yang
Applied to u-boot-rockchip master for this patch set, thanks.
Thanks,
- Kever
---
arch/arm/mach-rockchip/sdram.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/sdram.c
b/arch/arm/mach-rockchip/sdram.c
index 24fe6cc8f0..4c637b7767 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -56,16 +56,14 @@ int dram_init_banksize(void)
- CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + top - gd->bd->bi_dram[1].start;
+ gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x840;
/* Reserve 32M for OPTEE with TA */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x200;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + top - gd->bd->bi_dram[1].start;
+ gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
[PATCH v2 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,
-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.
Signed-off-by: Rayagonda Kokatanur
---
Changes from v1:
-Address review comments from Tom Rini,
Fix build warning messages.
arch/arm/lib/gic-v3-its.c | 73 +++
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..5057cc5421 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -15,6 +16,48 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ */
+struct gic_v3_its_priv {
+ u32 gicd_base;
+ u32 gicr_base;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_IRQ,
+ DM_GET_DRIVER(arm_gic_v3_its), &dev);
+ if (ret) {
+ pr_err("%s: failed to get %s irq device\n", __func__,
+ DM_GET_DRIVER(arm_gic_v3_its)->name);
+ return ret;
+ }
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicd_base = addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICR address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicr_base = addr;
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
@@ -23,15 +66,18 @@ static u32 lpi_id_bits;
*/
int gic_lpi_tables_init(u64 base, u32 num_redist)
{
+ struct gic_v3_its_priv priv;
u32 gicd_typer;
u64 val;
u64 tmp;
int i;
u64 redist_lpi_base;
- u64 pend_base = GICR_BASE + GICR_PENDBASER;
+ u64 pend_base;
- gicd_typer = readl(GICD_BASE + GICD_TYPER);
+ if (gic_v3_its_get_gic_addr(&priv))
+ return -EINVAL;
+ gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
pr_err("GIC implementation does not support LPI's\n");
@@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
- if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ if ((readl((uintptr_t)(priv.gicr_base + offset))) &
GICR_CTLR_ENABLE_LPIS) {
pr_err("Re-Distributor %d LPI is already enabled\n",
i);
@@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq(val, (GICR_BASE + GICR_PROPBASER));
- tmp = readl(GICR_BASE + GICR_PROPBASER);
+ writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+ tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_NC;
- writeq(val, (GICR_BASE + GICR_PROPBASER));
+ writeq(val,
+ (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
}
}
redist_lpi_base = base + LPI_PROPBASE_SZ;
+ pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
@@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
/* Enable LPI for the redistributor */
- writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ writel(GICR_CTLR_ENABLE_LPIS,
+ (uintptr_t)(priv.gicr_base + offset));
}
return 0;
}
+static const struct udevice_id gic_v3_its_ids[] = {
+ { .compatible = "arm,gic-v3" },
+ {}
+};
+
+U_BOOT_DRIVER(arm_gic_v3_its) = {
+ .name
[PATCH v2 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get gic details like GICD, GICR base address, max number of redistributors and git lpi address. Changes from v1: -Address review comments from Tom Rini, Fix build warning messages. Rayagonda Kokatanur (2): arch: arm: use dt and UCLASS_IRQ to get gic details arch: arm: use dt and UCLASS_SYSCON to get gic lpi details arch/arm/Kconfig | 2 + arch/arm/include/asm/gic-v3.h | 4 +- arch/arm/lib/gic-v3-its.c | 136 ++ 3 files changed, 126 insertions(+), 16 deletions(-) -- 2.17.1
[PATCH v2 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur
---
arch/arm/Kconfig | 2 ++
arch/arm/include/asm/gic-v3.h | 4 +--
arch/arm/lib/gic-v3-its.c | 63 +++
3 files changed, 60 insertions(+), 9 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f115fcdcc4..2fd20fc648 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
config GIC_V3_ITS
bool "ARM GICV3 ITS"
+ select REGMAP
+ select SYSCON
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 5057cc5421..5e82bdf568 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,6 +4,8 @@
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -16,15 +18,22 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS 8
+
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
u32 gicd_base;
u32 gicr_base;
+ u32 lpi_base;
+ u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
@@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
*priv)
return 0;
}
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+ struct regmap *regmap;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(gic_lpi_syscon), &dev);
+ if (ret) {
+ pr_err("%s: failed to get %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(dev);
+ if (!regmap) {
+ pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return -ENODEV;
+ }
+ priv->lpi_base = regmap->ranges[0].start;
+
+ priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
+ MAX_GIC_REDISTRIBUTORS);
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
- * base: Configuration table address
- * num_redist: number of redistributors
*/
-int gic_lpi_tables_init(u64 base, u32 num_redist)
+int gic_lpi_tables_init(void)
{
struct gic_v3_its_priv priv;
u32 gicd_typer;
@@ -77,6 +112,9 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
if (gic_v3_its_get_gic_addr(&priv))
return -EINVAL;
+ if (gic_v3_its_get_gic_lpi_addr(&priv))
+ return -EINVAL;
+
gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
@@ -89,7 +127,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
* Once the LPI table is enabled, can not program the
* LPI configuration tables again, unless the GIC is reset.
*/
- for (i = 0; i < num_redist; i++) {
+ for (i = 0; i < priv.num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
if ((readl((uintptr_t)(priv.gicr_base + offset))) &
@@ -105,7 +143,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
ITS_MAX_LPI_NRBITS);
/* Set PropBase */
- val = (base |
+ val = (priv.lpi_base |
GICR_PROPBASER_INNERSHAREABLE |
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
@@ -122,10 +160,10 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
}
- redist_lpi_base = base + LPI_PROPBASE_SZ;
+
am654_sdhci: mmc fail to send stop cmd
Hi all,
on one device with one specific SD-card (possibly an aging one), I'm
seeing frequent "mmc fail to send stop cmd" messages, followed by read
errors when loading kernel and dtb. -ETIMEDOUT is returned by
mmd_send_cmd. However, I can always resolve this by simply retrying the
stop command like this:
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f36d11ddc8..9019d9f2ed 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -406,7 +406,11 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst,
lbaint_t start,
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
pr_err("mmc fail to send stop cmd\n");
#endif
- return 0;
+ pr_err("retrying...\n");
+ if (mmc_send_cmd(mmc, &cmd, NULL)) {
+ pr_err("failed again\n");
+ return 0;
+ }
}
}
Hardware is our IOT2050, baseline is today's master (1c4b5038afcc) with
board-enabling and a bunch of patches from your tree [1]. However,
already 4d6da10ce611 exposes the problem.
What could cause this?
Jan
[1] https://github.com/siemens/u-boot/commits/jan/iot2050
[PATCH] rockchip: rk3399: Add default env to support compressed krenel Image
Add default kernel_comp_addr_r and kernel_comp_size to support boot from compressed kernel Image, this space is temporarily used during decompress according to README.distro. Signed-off-by: Kever Yang --- include/configs/rk3399_common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e63ebb14f7..4121d5edc4 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -53,7 +53,9 @@ "pxefile_addr_r=0x0060\0" \ "fdt_addr_r=0x01f0\0" \ "kernel_addr_r=0x0208\0" \ - "ramdisk_addr_r=0x0600\0" + "ramdisk_addr_r=0x0600\0" \ + "kernel_comp_addr_r=0x0800\0" \ + "kernel_comp_size=0x200\0" #ifndef ROCKCHIP_DEVICE_SETTINGS #define ROCKCHIP_DEVICE_SETTINGS -- 2.17.1
Re: rk3399: boot from compressed Image
Hi Yuanhao, Thanks for your good suggestion, could you take a try for this: https://patchwork.ozlabs.org/project/uboot/patch/20200718144823.7997-1-kever.y...@rock-chips.com/ Thanks, - Kever On 2020/6/22 上午10:30, Tian Yuanhao wrote: Hello, booti now supports booting from compressed Image. See 414c34ed555b8ce5c260cf641261ecf45beca251. Would you please add kernel_comp_addr_r and kernel_comp_size to rk3399_common.h, so that people can use compressed Image (e.g. Image.gz) in extlinux.conf. Thanks, Yuanhao
Re: [PATCH v2 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Hi Simon, On Sat, Jul 18, 2020 at 8:14 PM Rayagonda Kokatanur wrote: > > Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get > gic details like GICD, GICR base address, max number of redistributors > and git lpi address. > > Changes from v1: > -Address review comments from Tom Rini, > Fix build warning messages. > > Rayagonda Kokatanur (2): > arch: arm: use dt and UCLASS_IRQ to get gic details > arch: arm: use dt and UCLASS_SYSCON to get gic lpi details > > arch/arm/Kconfig | 2 + > arch/arm/include/asm/gic-v3.h | 4 +- > arch/arm/lib/gic-v3-its.c | 136 ++ > 3 files changed, 126 insertions(+), 16 deletions(-) Request you to please review these patches. These are required for other board file patches to build. Best regards, Rayagonda > > > -- > 2.17.1 >
[PULL] u-boot-mips
Hi Tom, please pull MIPS updates for 2020.10. This contains initial but very basic support for Marvell Octeon MIPS64 SoC's along with some small refactorings in start.S to prepare for Octeon. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/pipelines/4105 The following changes since commit 1c4b5038afcc7cdb1064713f65571da05aa0de0e: Merge branch '2020-07-17-misc-fixes' (2020-07-17 16:08:54 -0400) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-mips.git tags/mips-pull-2020-07-18 for you to fetch changes up to 5fef24c912a44a08ab644aa16ceb5a435491f9d9: mips: octeon: Add minimal Octeon 3 EBB7304 EVK support (2020-07-18 15:47:50 +0200) - MIPS: refactor cache init and setup in start.S - MIPS: sync asm header files with Linux 5.7 - MIPS: add initial support for Marvell Octeon MIPS64 Aaron Williams (1): mips: octeon: Initial minimal support for the Marvell Octeon SoC Daniel Schwierzeck (8): mips: start.S: remove dead code mips: add KSEG1 wrapper for change_k0_cca mips: refactor disabling of caches mips: add config options for generic cache setup code mips: remove deprecated UNCACHED_SDRAM() macro mips: sync asm/asm.h with Linux 5.7 mips: sync asm/addrspace.h with Linux 5.7 mips: sync asm/mipsregs.h with Linux 5.7 Stefan Roese (11): mips: time: Only compile the weak get_tbclk() when needed mips: traps: Set WG bit in EBase register on Octeon mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usage mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM mips: cache: Make flush_cache() weak to enable overwrite mips: cache: Make invalidate_dcache_range() weak to enable overwrite mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init code sysreset: Add Octeon sysreset driver mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file mips: octeon: use mips_mach_early_init() to copy to L2 cache mips: octeon: Add minimal Octeon 3 EBB7304 EVK support MAINTAINERS |7 + arch/mips/Kconfig | 77 ++ arch/mips/Makefile|3 + arch/mips/cpu/start.S | 31 +- arch/mips/cpu/time.c |2 + arch/mips/dts/Makefile|1 + arch/mips/dts/mrvl,cn73xx.dtsi| 64 ++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++ arch/mips/include/asm/addrspace.h | 27 +- arch/mips/include/asm/asm.h | 130 +-- arch/mips/include/asm/cm.h| 12 + arch/mips/include/asm/compiler.h | 69 ++ arch/mips/include/asm/isa-rev.h | 24 + arch/mips/include/asm/mipsregs.h | 1201 + arch/mips/include/asm/relocs.h|2 +- arch/mips/lib/bootm.c |4 +- arch/mips/lib/cache.c |6 +- arch/mips/lib/cache_init.S| 38 +- arch/mips/lib/reloc.c |7 +- arch/mips/lib/traps.c |4 + arch/mips/mach-octeon/Kconfig | 60 ++ arch/mips/mach-octeon/Makefile| 10 + arch/mips/mach-octeon/cache.c | 24 + arch/mips/mach-octeon/clock.c | 14 + arch/mips/mach-octeon/cpu.c | 66 ++ arch/mips/mach-octeon/dram.c | 28 + arch/mips/mach-octeon/include/ioremap.h | 30 + arch/mips/mach-octeon/include/mach/cavm-reg.h | 17 + arch/mips/mach-octeon/include/mach/clock.h| 12 + arch/mips/mach-octeon/lowlevel_init.S | 69 ++ board/Marvell/octeon_ebb7304/Kconfig | 19 + board/Marvell/octeon_ebb7304/MAINTAINERS |7 + board/Marvell/octeon_ebb7304/Makefile |8 + board/Marvell/octeon_ebb7304/board.c |9 + configs/octeon_ebb7304_defconfig | 38 + drivers/sysreset/Kconfig |7 + drivers/sysreset/Makefile |1 + drivers/sysreset/sysreset_octeon.c| 52 ++ include/configs/octeon_common.h | 19 + include/configs/octeon_ebb7304.h | 20 + scripts/config_whitelist.txt |1 - 41 files changed, 1937 insertions(+), 379 deletions(-) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 arch/mips/include/asm/compiler.h create mode 100644 arch/mips/include/asm/isa-rev.h create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach
Re: [PATCHv2] armv8: MMU: Mark code memory Executable, any other Non-Executable
On Fri, Jun 19, 2020 at 02:53:32PM +0200, marek.bykow...@gmail.com wrote:
> From: Marek Bykowski
>
> If the location the ARM CPU is accessing is executable (translation
> table descriptor Execute-Never attribute bit cleared) then the ARM CPU
> fetches a number of instructions from that location all at the same time.
> For example, Cortex-A57 can source up to 128 bits per fetch depending on
> alignment.
>
> If the CPU mispredicts to the Execute-Never region, it creates the
> memory fault but it actually never uses the instructions mispredicted.
> The CPU branches away elsewhere. So, as long as we program the MMU
> correctly these mispredictions will only affect the performance.
>
> However if we fail programming so and the instruction fetch logic goes
> mispredict to non-instruction memory it may eventually perturb it, eg.
> corrupt the FIFO, or the control registers, load the unified cache
> the data side memory system hits into subsequently.
>
> U-Boot adheres into attributing the device regions to Execute-Never but
> it actually fails doing so for data regions. Data as well as Device Regions
> should be Execute-Never.
>
> This patch enables attributing data memory regions to Non-Executable,
> and code region to Executable, additionally to Read-Only. Read-Only ensures
> the code region is only Readable resulting in Instruction Abort, Permission
> Fault exception on a write.
>
> To use the updated attributes the DDR memory of interest should be
> Non-Executable, it is by default Read-Write Access Permission as well
> with an example as follows:
>
> static struct mm_region axxia_mem_map[] = {
> {
> .virt = 0x0UL, /* DDR */
> .phys = 0x0UL,
> .size = 0x4ULL,
> .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_INNER_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> .virt = AXXIA_CCN_512_BASE,
> .phys = AXXIA_CCN_512_BASE,
> .size = AXXIA_CCN_512_SIZE,
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> .virt = AXI_MMAP_BASE,
> .phys = AXI_MMAP_BASE,
> .size = AXI_MMAP_SIZE,
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> .virt = AXI_PERIPH_BASE,
> .phys = AXI_PERIPH_BASE,
> .size = AXI_PERIPH_SIZE,
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> /* List terminator */
> 0,
> }
> };
>
> add_text_map() routine in cache_v8.c locates then the code region in it and
> modifies its attributes to Executable, Read-Only. The HW Debugger views
> the Memory Map set then as:
>
> EL2N:0x-0x3FD35FFF NP:0x-0x3FD35FFF Normal RW C S XN
> EL2N:0x3FD36000-0x3FD86FFF NP:0x3FD36000-0x3FD86FFF Normal RO C S
> EL2N:0x3FD87000-0x3 NP:0x3FD87000-0x3 Normal RW C S XN
> EL2N:0x4-0x3F
> EL2N:0x40-0x403FFF NP:0x40-0x403FFF Device-nGnRnE RW
> NC XN
> EL2N:0x404000-0x7F
> EL2N:0x80-0x803FFF NP:0x80-0x803FFF Device-nGnRnE RW
> NC XN
> EL2N:0x804000-0x807FFF
> EL2N:0x808000-0x80BFFF NP:0x808000-0x80BFFF Device-nGnRnE RW
> NC XN
> EL2N:0x80C000-0xFF
>
> where:
> C, NC is Cacheable, Non-Cacheable respectively,
> S, NS - Shareable and Non-Shareable,
> XN - Execute-Never, if XN isn't present it is Executable.
>
> Shareability of the Device is always treated as Outer Shareable,
> regardless of the attributes, therefore the Shareability for the Device
> Regions is not mentioned here.
>
> Signed-off-by: Marek Bykowski
> ---
> Patch v1 -> v2:
> I have only changed the description of the commit as incorrectly address
> the Shareability domain there.
>
> arch/arm/cpu/armv8/cache_v8.c| 21 +
> arch/arm/cpu/armv8/u-boot.lds| 6 --
> arch/arm/include/asm/armv8/mmu.h | 6 ++
> arch/arm/lib/sections.c | 1 +
> include/asm-generic/sections.h | 1 +
> 5 files changed, 33 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index c1a08fb4ac..cb25fc0c8a 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -361,6 +362,24 @@ __weak u64 get_page_table_size(void)
> return size;
> }
>
> +__weak void add_text_map(void)
> +{
> + if (!(gd->flags & GD_FLG_RELOC))
> + return;
> +
> + /* Text is always XN=0, read-only region. */
> + struct mm_region text = {
> + .virt = (unsigned long)__image_copy_start,
> + .phys = (unsigned long)__image_copy_start,
> + .size = (unsigned long)__text
Re: [PATCH] rockchip: rk3328: Add SPI support
Hi Kever,
On 18.07.20 at 05:02, Kever Yang wrote:
> Hi Johannes,
>
> Do you have plan to update for this patch?
I think this thread is obsolete. You have already applied
the improved two patch (RK3328, PINE64 Rock64) series
later in a new thread.
Many thanks for the apply.
Kind regards,
Johannes K.
>
> Thanks,
>
> - Kever
>
> On 2020/7/8 下午6:08, Kever Yang wrote:
>> Hi Johannes,
>>
>> The changes look good to me, but you need to split the patch into 3
>> patches:
>>
>> - rk3328 clock driver;
>>
>> - rkspi driver;
>>
>> - rk3328-u-boot.dtsi
>>
>> BTW: the patch no need reply-to previous mail, you can make a new thread.
>>
>> Thanks,
>>
>> - Kever
>>
>> On 2020/7/4 上午2:08, Johannes Krottmayer wrote:
>>> Add U-Boot SPI support for the RK3328
>>>
>>> Signed-off-by: Johannes Krottmayer
>>> Cc: Kever Yang
>>> Cc: Jagan Teki
>>> ---
>>>
>>> It's a initial SPI support. Not sure if "rk3399_spi_params" is also
>>> needed. Probing of the SPI flash devices works. Tested with the
>>> PINE64 Rock64 board.
>>>
>>> Okay?
>>>
>>> arch/arm/dts/rk3328-u-boot.dtsi | 5 +
>>> drivers/clk/rockchip/clk_rk3328.c | 31 +++
>>> drivers/spi/rk_spi.c | 2 ++
>>> 3 files changed, 38 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/rk3328-u-boot.dtsi
>>> b/arch/arm/dts/rk3328-u-boot.dtsi
>>> index c69e13e11e..c980daae99 100644
>>> --- a/arch/arm/dts/rk3328-u-boot.dtsi
>>> +++ b/arch/arm/dts/rk3328-u-boot.dtsi
>>> @@ -7,6 +7,7 @@
>>> aliases {
>>> mmc0 = &emmc;
>>> mmc1 = &sdmmc;
>>> + spi0 = &spi0;
>>> };
>>> chosen {
>>> @@ -66,3 +67,7 @@
>>> &usb20_otg {
>>> hnp-srp-disable;
>>> };
>>> +
>>> +&spi0 {
>>> + u-boot,dm-pre-reloc;
>>> +};
>>> diff --git a/drivers/clk/rockchip/clk_rk3328.c
>>> b/drivers/clk/rockchip/clk_rk3328.c
>>> index 02d3b08efa..bd95ab832b 100644
>>> --- a/drivers/clk/rockchip/clk_rk3328.c
>>> +++ b/drivers/clk/rockchip/clk_rk3328.c
>>> @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct
>>> rk3328_cru *cru, uint hz)
>>> return rk3328_saradc_get_clk(cru);
>>> }
>>> +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
>>> +{
>>> + u32 div, val;
>>> +
>>> + val = readl(&cru->clksel_con[24]);
>>> + div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
>>> +
>>> + return DIV_TO_RATE(OSC_HZ, div);
>>> +}
>>> +
>>> +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
>>> +{
>>> + u32 src_clk_div;
>>> +
>>> + src_clk_div = GPLL_HZ / hz;
>>> + assert(src_clk_div < 128);
>>> +
>>> + rk_clrsetreg(&cru->clksel_con[24],
>>> + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
>>> + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
>>> + (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
>>> +
>>> + return rk3328_spi_get_clk(cru);
>>> +}
>>> +
>>> static ulong rk3328_clk_get_rate(struct clk *clk)
>>> {
>>> struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
>>> @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
>>> case SCLK_SARADC:
>>> rate = rk3328_saradc_get_clk(priv->cru);
>>> break;
>>> + case SCLK_SPI:
>>> + rate = rk3328_spi_get_clk(priv->cru);
>>> + break;
>>> default:
>>> return -ENOENT;
>>> }
>>> @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk,
>>> ulong rate)
>>> case SCLK_SARADC:
>>> ret = rk3328_saradc_set_clk(priv->cru, rate);
>>> break;
>>> + case SCLK_SPI:
>>> + ret = rk3328_spi_set_clk(priv->cru, rate);
>>> + break;
>>> case DCLK_LCDC:
>>> case SCLK_PDM:
>>> case SCLK_RTC32K:
>>> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
>>> index 833cb04922..0495e04945 100644
>>> --- a/drivers/spi/rk_spi.c
>>> +++ b/drivers/spi/rk_spi.c
>>> @@ -545,7 +545,9 @@ const struct rockchip_spi_params
>>> rk3399_spi_params = {
>>> };
>>> static const struct udevice_id rockchip_spi_ids[] = {
>>> + { .compatible = "rockchip,rk3066-spi" },
>>> { .compatible = "rockchip,rk3288-spi" },
>>> + { .compatible = "rockchip,rk3328-spi" },
>>> { .compatible = "rockchip,rk3368-spi",
>>> .data = (ulong)&rk3399_spi_params },
>>> { .compatible = "rockchip,rk3399-spi",
>>
>>
>
>
Re: [PATCH 1/6] Convert CONFIG_SYS_DEVICE_NULLDEV to Kconfig
Hi Simon, On 18.07.2020 06:03, Simon Glass wrote: This converts the following to Kconfig: CONFIG_SYS_DEVICE_NULLDEV Signed-off-by: Simon Glass --- common/Kconfig | 16 configs/M5249EVB_defconfig | 3 ++- configs/colibri_pxa270_defconfig | 2 +- doc/README.silent| 2 +- include/configs/M5249EVB.h | 2 -- include/configs/colibri_pxa270.h | 2 -- scripts/config_whitelist.txt | 1 - 7 files changed, 20 insertions(+), 8 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index 67b3818fde..4d5b3a9cfb 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -634,6 +634,22 @@ config SYS_STDIO_DEREGISTER removed (for example a USB keyboard) then this option can be enabled to ensure this is handled correctly. +config SPL_SYS_STDIO_DEREGISTER + bool "Allow deregistering stdio devices in SPL" + help + Generally there is no need to deregister stdio devices since they + are never deactivated. But if a stdio device is used which can be + removed (for example a USB keyboard) then this option can be + enabled to ensure this is handled correctly. This is very rarely + needed in SPL. + +config SYS_DEVICE_NULLDEV + bool "Enable a null device for stdio" + help + Enable creation of a "nulldev" stdio device. This allows silent + operation of the console by setting stdout to "nulldev". Enable + this to use a serial console under board control. + endmenu menu "Logging" diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 12db389b69..8f8a4a6bad 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -3,7 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFE0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_TARGET_M5249EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_DEVICE_NULLDEV=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTOBOOT is not set @@ -12,7 +14,6 @@ CONFIG_LOOPW=y CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" CONFIG_ENV_ADDR=0xFFE04000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 669b9dfe58..aff7b62639 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" +CONFIG_SYS_DEVICE_NULLDEV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_CMDLINE_EDITING is not set @@ -43,6 +44,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SERIAL=y CONFIG_PXA_SERIAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y Is this deletion intentional? It is not immediately obvious to me how it relates to CONFIG_SYS_DEVICE_NULLDEV getting converted to Kconfig. Reviewed-by: Ovidiu Panait Thanks! Ovidiu # CONFIG_REGEX is not set CONFIG_OF_LIBFDT=y diff --git a/doc/README.silent b/doc/README.silent index 6d90a0ec40..00288e03b0 100644 --- a/doc/README.silent +++ b/doc/README.silent @@ -19,7 +19,7 @@ The following actions are taken if "silent" is set at boot time: - When the console devices have been initialized, "stdout" and "stderr" are set to "nulldev", so subsequent messages are suppressed automatically. Make sure to enable "nulldev" by - #defining CONFIG_SYS_DEVICE_NULLDEV in your board config file. + enabling CONFIG_SYS_DEVICE_NULLDEV in your board defconfig file. - When booting a linux kernel, the "bootargs" are fixed up so that the argument "console=" will be in the command line, no matter how diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index de7132940c..1a1a110765 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -31,8 +31,6 @@ */ #undef CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - #define CONFIG_SYS_LOAD_ADDR 0x20/* default load address */ /* diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 29827f1ee8..3bbef55ec3 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -70,8 +70,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE #endif -#define CONFIG_SYS_DEVICE_NULLDEV 1 - /* * Clock Configuration */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1c7946fb65..2da34a5d23 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2178,7 +2178,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_
[PATCH v5] net: tftp: Add client support for RFC 7440
Add support for RFC 7440: "TFTP Windowsize Option".
This optional feature allows the client and server
to negotiate a window size of consecutive blocks to send as an
alternative for replacing the single-block lockstep schema.
windowsize can be defined statically during compilation by
setting CONFIG_TFTP_WINDOWSIZE, or defined in runtime by
setting an environment variable: "tftpwindowsize"
If not defined, the windowsize is set to 1, meaning that it
behaves as it was never defined.
Choosing the appropriate windowsize depends on the specific
network topology, underlying NIC.
You should test various windowsize scenarios and see which
best work for you.
Setting a windowsize too big can actually decreases performance.
Signed-off-by: Ramon Fried
Reviewed-by: Marek Vasut
---
v2:
* Don't send windowsize option on tftpput, as it's not implemented yet.
* Don't send NACK for every out of order block that arrives, one nack
is enough.
v3:
* Add option CONFIG_TFTP_WINDOWSIZE to kconfig with default 1.
* Fixed some spelling errors.
* Took assignment out of a loop.
* simplified variable increment.
v4:
* send ack for last packet, so the server can finish
the tranfer gracefully and not in timeout.
v5:
* rebase the patch on top of latest tftp changes.
* Fix wraparound issue in tftp_cur_block increment.
* Change strcmp to strcasecmp
README | 5
net/Kconfig | 9 ++
net/tftp.c | 79 -
3 files changed, 86 insertions(+), 7 deletions(-)
diff --git a/README b/README
index 2384966a39..2ebf664848 100644
--- a/README
+++ b/README
@@ -3473,6 +3473,11 @@ List of environment variables (most likely not complete):
downloads succeed with high packet loss rates, or with
unreliable TFTP servers or client hardware.
+ tftpwindowsize - if this is set, the value is used for TFTP's
+ window size as described by RFC 7440.
+ This means the count of blocks we can receive before
+ sending ack to server.
+
vlan - When set to a value < 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
diff --git a/net/Kconfig b/net/Kconfig
index ac6d0cf8a6..7916ae305f 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -49,4 +49,13 @@ config TFTP_BLOCKSIZE
almost-MTU block sizes.
You can also activate CONFIG_IP_DEFRAG to set a larger block.
+config TFTP_WINDOWSIZE
+ int "TFTP window size"
+ default 1
+ help
+ Default TFTP window size.
+ RFC7440 defines an optional window size of transmits,
+ before an ack response is required.
+ The default TFTP implementation implies a window size of 1.
+
endif # if NET
diff --git a/net/tftp.c b/net/tftp.c
index c05b7b5532..84e970bec1 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -5,7 +5,6 @@
* Copyright 2011 Comelit Group SpA,
*Luca Ceresoli
*/
-
#include
#include
#include
@@ -98,6 +97,12 @@ static int tftp_tsize;
/* The number of hashes we printed */
static short tftp_tsize_num_hash;
#endif
+/* The window size negotiated */
+static ushort tftp_windowsize;
+/* Next block to send ack to */
+static ushort tftp_next_ack;
+/* Last nack block we send */
+static ushort tftp_last_nack;
#ifdef CONFIG_CMD_TFTPPUT
/* 1 if writing, else 0 */
static int tftp_put_active;
@@ -138,8 +143,19 @@ static char tftp_filename[MAX_LEN];
* (but those using CONFIG_IP_DEFRAG may want to set a larger block in cfg
file)
*/
+/* When windowsize is defined to 1,
+ * tftp behaves the same way as it was
+ * never declared
+ */
+#ifdef CONFIG_TFTP_WINDOWSIZE
+#define TFTP_WINDOWSIZE CONFIG_TFTP_WINDOWSIZE
+#else
+#define TFTP_WINDOWSIZE 1
+#endif
+
static unsigned short tftp_block_size = TFTP_BLOCK_SIZE;
static unsigned short tftp_block_size_option = CONFIG_TFTP_BLOCKSIZE;
+static unsigned short tftp_window_size_option = TFTP_WINDOWSIZE;
static inline int store_block(int block, uchar *src, unsigned int len)
{
@@ -356,6 +372,14 @@ static void tftp_send(void)
/* try for more effic. blk size */
pkt += sprintf((char *)pkt, "blksize%c%d%c",
0, tftp_block_size_option, 0);
+
+ /* try for more effic. window size.
+* Implemented only for tftp get.
+* Don't bother sending if it's 1
+*/
+ if (tftp_state == STATE_SEND_RRQ && tftp_window_size_option > 1)
+ pkt += sprintf((char *)pkt, "windowsize%c%d%c",
+ 0, tftp_window_size_option, 0);
len = pkt - xp;
break;
@@ -550,7 +574,17 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct
in_addr sip,
(char *)pkt + i + 6, tftp_tsize);
}
#endif
+
[PATCH] ARM: omap3: evm: Complete DM_ETH and DM_USB migrations
This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.
Cc: Tom Rini
Cc: Adam Ford
Signed-off-by: Derald D. Woods
---
arch/arm/mach-omap2/omap3/Kconfig | 3 ++
board/ti/evm/evm.c| 82 +--
configs/omap3_evm_defconfig | 14 --
3 files changed, 23 insertions(+), 76 deletions(-)
diff --git a/arch/arm/mach-omap2/omap3/Kconfig
b/arch/arm/mach-omap2/omap3/Kconfig
index cf11e5707f..0a6eb4cb26 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -61,7 +61,10 @@ config TARGET_OMAP3_EVM
select DM
select DM_GPIO
select DM_SERIAL
+ select OMAP3_GPIO_2
select OMAP3_GPIO_3
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
imply CMD_DM
config TARGET_OMAP3_IGEP00X0
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 193b3eb576..ecbd843676 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -16,7 +16,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -24,20 +23,17 @@
#include
#include
#include
-#include
#include
#include
-#include
#include
#include
-#include
-#include
-#include
#include "evm.h"
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
+#define CONFIG_SMC911X_BASE 0x2C00
+
DECLARE_GLOBAL_DATA_PTR;
static u32 omap3_evm_version;
@@ -49,7 +45,7 @@ u32 get_omap3_evm_rev(void)
static void omap3_evm_get_revision(void)
{
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
/*
* Board revision can be ascertained only by identifying
* the Ethernet chipset.
@@ -70,7 +66,7 @@ static void omap3_evm_get_revision(void)
default:
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
}
-#else /* !CONFIG_CMD_NET */
+#else /* !CONFIG_SMC911X */
#if defined(CONFIG_STATIC_BOARD_REV)
/* Look for static defintion of the board revision */
omap3_evm_version = CONFIG_STATIC_BOARD_REV;
@@ -78,7 +74,7 @@ static void omap3_evm_get_revision(void)
/* Fallback to the default above */
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
#endif /* CONFIG_STATIC_BOARD_REV */
-#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_SMC911X */
}
#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
@@ -155,33 +151,6 @@ void get_board_mem_timings(struct board_sdrc_timings
*timings)
}
#endif /* CONFIG_SPL_BUILD */
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps= 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-#endif /* CONFIG_USB_MUSB_OMAP2PLUS */
-
/*
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
@@ -190,25 +159,18 @@ int misc_init_r(void)
{
twl4030_power_init();
-#ifdef CONFIG_SYS_I2C_OMAP24XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
setup_net_chip();
#endif
omap3_evm_get_revision();
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
reset_net_chip();
#endif
omap_die_id_display();
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
- musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
-#endif
-
-#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
+ !defined(CONFIG_SMC911X)
omap_die_id_usbethaddr();
#endif
return 0;
@@ -225,7 +187,7 @@ void set_muxconf_regs(void)
MUX_EVM();
}
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
@@ -283,33 +245,11 @@ static void reset_net_chip(void)
udelay(1);
gpio_set_value(rst_gpio, 1);
}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_SMC911X)
- env_set("ethaddr", NULL);
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#else
- return 0;
-#endif
-}
-#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_SMC911X */
#if defined(CONFIG_MMC)
-int board_mmc_init(struct
[PATCH v2] ARM: omap3: evm: Complete DM_ETH and DM_USB migrations
This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.
Cc: Tom Rini
Cc: Adam Ford
Signed-off-by: Derald D. Woods
---
Changes for v2:
- Add omitted ethernet node to omap3-evm-u-boot.dtsi
* Based on similar changes found in logicpd-torpedo-35xx-devkit.dtsi
---
arch/arm/dts/omap3-evm-u-boot.dtsi | 10
arch/arm/mach-omap2/omap3/Kconfig | 3 ++
board/ti/evm/evm.c | 82 --
configs/omap3_evm_defconfig| 14 +++--
4 files changed, 33 insertions(+), 76 deletions(-)
diff --git a/arch/arm/dts/omap3-evm-u-boot.dtsi
b/arch/arm/dts/omap3-evm-u-boot.dtsi
index b9e433f873..97a8141c8a 100644
--- a/arch/arm/dts/omap3-evm-u-boot.dtsi
+++ b/arch/arm/dts/omap3-evm-u-boot.dtsi
@@ -11,4 +11,14 @@
chosen {
stdout-path = &uart1;
};
+
+ ethernet@2c00 {
+ compatible = "smsc,lan9221","smsc,lan9115";
+ reg = <0x2c00 0xff>;
+ bank-width = <2>;
+ vddvario-supply = <&vddvario>;
+ vdd33a-supply = <&vdd33a>;
+ reg-io-width = <4>;
+ smsc,save-mac-address;
+ };
};
diff --git a/arch/arm/mach-omap2/omap3/Kconfig
b/arch/arm/mach-omap2/omap3/Kconfig
index cf11e5707f..0a6eb4cb26 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -61,7 +61,10 @@ config TARGET_OMAP3_EVM
select DM
select DM_GPIO
select DM_SERIAL
+ select OMAP3_GPIO_2
select OMAP3_GPIO_3
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
imply CMD_DM
config TARGET_OMAP3_IGEP00X0
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 193b3eb576..ecbd843676 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -16,7 +16,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -24,20 +23,17 @@
#include
#include
#include
-#include
#include
#include
-#include
#include
#include
-#include
-#include
-#include
#include "evm.h"
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
+#define CONFIG_SMC911X_BASE 0x2C00
+
DECLARE_GLOBAL_DATA_PTR;
static u32 omap3_evm_version;
@@ -49,7 +45,7 @@ u32 get_omap3_evm_rev(void)
static void omap3_evm_get_revision(void)
{
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
/*
* Board revision can be ascertained only by identifying
* the Ethernet chipset.
@@ -70,7 +66,7 @@ static void omap3_evm_get_revision(void)
default:
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
}
-#else /* !CONFIG_CMD_NET */
+#else /* !CONFIG_SMC911X */
#if defined(CONFIG_STATIC_BOARD_REV)
/* Look for static defintion of the board revision */
omap3_evm_version = CONFIG_STATIC_BOARD_REV;
@@ -78,7 +74,7 @@ static void omap3_evm_get_revision(void)
/* Fallback to the default above */
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
#endif /* CONFIG_STATIC_BOARD_REV */
-#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_SMC911X */
}
#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
@@ -155,33 +151,6 @@ void get_board_mem_timings(struct board_sdrc_timings
*timings)
}
#endif /* CONFIG_SPL_BUILD */
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps= 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-#endif /* CONFIG_USB_MUSB_OMAP2PLUS */
-
/*
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
@@ -190,25 +159,18 @@ int misc_init_r(void)
{
twl4030_power_init();
-#ifdef CONFIG_SYS_I2C_OMAP24XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
setup_net_chip();
#endif
omap3_evm_get_revision();
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
reset_net_chip();
#endif
omap_die_id_display();
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
- musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
-#endif
-
-#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG
[PATCH v3] ARM: omap3: evm: Complete DM_ETH and DM_USB migrations
This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.
Cc: Tom Rini
Cc: Adam Ford
Signed-off-by: Derald D. Woods
---
Changes for v3:
- Also handle 37xx 'dtsi' variant
- My testing is with the 3530 processor variant
Changes for v2:
- Add omitted ethernet node to omap3-evm-u-boot.dtsi
* Based on similar changes found in logicpd-torpedo-35xx-devkit.dtsi
---
arch/arm/dts/omap3-evm-37xx-u-boot.dtsi | 10 +++
arch/arm/dts/omap3-evm-u-boot.dtsi | 10 +++
arch/arm/mach-omap2/omap3/Kconfig | 3 +
board/ti/evm/evm.c | 82 -
configs/omap3_evm_defconfig | 14 +++--
5 files changed, 43 insertions(+), 76 deletions(-)
diff --git a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi
b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi
index b9e433f873..97a8141c8a 100644
--- a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi
+++ b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi
@@ -11,4 +11,14 @@
chosen {
stdout-path = &uart1;
};
+
+ ethernet@2c00 {
+ compatible = "smsc,lan9221","smsc,lan9115";
+ reg = <0x2c00 0xff>;
+ bank-width = <2>;
+ vddvario-supply = <&vddvario>;
+ vdd33a-supply = <&vdd33a>;
+ reg-io-width = <4>;
+ smsc,save-mac-address;
+ };
};
diff --git a/arch/arm/dts/omap3-evm-u-boot.dtsi
b/arch/arm/dts/omap3-evm-u-boot.dtsi
index b9e433f873..97a8141c8a 100644
--- a/arch/arm/dts/omap3-evm-u-boot.dtsi
+++ b/arch/arm/dts/omap3-evm-u-boot.dtsi
@@ -11,4 +11,14 @@
chosen {
stdout-path = &uart1;
};
+
+ ethernet@2c00 {
+ compatible = "smsc,lan9221","smsc,lan9115";
+ reg = <0x2c00 0xff>;
+ bank-width = <2>;
+ vddvario-supply = <&vddvario>;
+ vdd33a-supply = <&vdd33a>;
+ reg-io-width = <4>;
+ smsc,save-mac-address;
+ };
};
diff --git a/arch/arm/mach-omap2/omap3/Kconfig
b/arch/arm/mach-omap2/omap3/Kconfig
index cf11e5707f..0a6eb4cb26 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -61,7 +61,10 @@ config TARGET_OMAP3_EVM
select DM
select DM_GPIO
select DM_SERIAL
+ select OMAP3_GPIO_2
select OMAP3_GPIO_3
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
imply CMD_DM
config TARGET_OMAP3_IGEP00X0
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 193b3eb576..ecbd843676 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -16,7 +16,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -24,20 +23,17 @@
#include
#include
#include
-#include
#include
#include
-#include
#include
#include
-#include
-#include
-#include
#include "evm.h"
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
+#define CONFIG_SMC911X_BASE 0x2C00
+
DECLARE_GLOBAL_DATA_PTR;
static u32 omap3_evm_version;
@@ -49,7 +45,7 @@ u32 get_omap3_evm_rev(void)
static void omap3_evm_get_revision(void)
{
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SMC911X)
/*
* Board revision can be ascertained only by identifying
* the Ethernet chipset.
@@ -70,7 +66,7 @@ static void omap3_evm_get_revision(void)
default:
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
}
-#else /* !CONFIG_CMD_NET */
+#else /* !CONFIG_SMC911X */
#if defined(CONFIG_STATIC_BOARD_REV)
/* Look for static defintion of the board revision */
omap3_evm_version = CONFIG_STATIC_BOARD_REV;
@@ -78,7 +74,7 @@ static void omap3_evm_get_revision(void)
/* Fallback to the default above */
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
#endif /* CONFIG_STATIC_BOARD_REV */
-#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_SMC911X */
}
#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
@@ -155,33 +151,6 @@ void get_board_mem_timings(struct board_sdrc_timings
*timings)
}
#endif /* CONFIG_SPL_BUILD */
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps= 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
Re: [PATCH v6 0/4] usb: xhci: Load Raspberry Pi 4 VL805's firmware
Hi Nicolas,
On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> loaded explicitly. Earlier versions didn't need that as they where using
> an EEPROM for that purpose. This series takes care of setting up the
> relevant infrastructure and run the firmware loading routine at the
> right moment.
I tried using this patchset to boot from a USB mass storage device on
RPi 4 with 8GB RAM. I updated the EEPROM firmware as well as deployed
the latest GPU firmware (start4.elf/fixup4.dat) from the firmware master
branch. I think with that I have new enough/correct versions.
The RPi 4 successfully boots U-Boot from a mass storage device. However,
U-Boot itself is then not able to access USB. The output always shows
-110 (timeout). It seems that the VL805 controller is not detected on
the PCIe bus. Do you happen to know what I might be missing?
I tried current master (which has your patchset merged) as well as your
vl805 branch on Github.
U-Boot 2020.07-rc4-00036-gdeb48986ee (Jul 19 2020 - 02:29:44 +0200)
DRAM: 7.9 GiB
RPI 4 Model B (0xd03114)
MMC: mmcnr@7e30: 1, emmc2@7e34: 0
Loading Environment from FAT... Card did not respond to voltage select!
In:serial
Out: vidconsole
Err: vidconsole
Net: eth0: genet@7d58
PCIe BRCM: link up, 5.0 Gbps x1 (!SSC)
Device 'pci_0:0.0': seq 0 is in use by 'pcie@7d50'
starting USB...
Bus xhci_pci: probe failed, error -110
No working controllers found
Hit any key to stop autoboot: 0
U-Boot> pci enum
U-Boot> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_
00.00.00 0x14e4 0x2711 Bridge device 0x04
--
Stefan
>
> Note that this builds on top of Sylwester Nawrocki's "USB host support
> for Raspberry Pi 4 board" series.
>
> This also depends on a DT/bindings patch available on the linux-mailing lists:
> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2205783.html
>
> Here is the relevant bit for reference/discussion:
>
> &pcie0 {
>pci@1,0 {
>#address-cells = <3>;
>#size-cells = <2>;
>ranges;
>
>reg = <0 0 0 0 0>;
>
>usb@1,0 {
>reg = <0x1 0 0 0 0>;
>resets = <&reset
> RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
>};
>};
> };
>
> ---
>
> Changes since v5:
> - Properly handle !CONFIG_IS_ENABLED(DM_RESET) in xchi code
>
> Changes since v4:
> - Correct DT PCI topology, I separated the root bridge and controller
>DT nodes
> - Get rid of PCI core patch as not needed with correct DT PCI topology
> - Move reset support to xchi core
>
> Changes since v3:
> - Use reset controller
>
> Changes since v2:
> - Correct comment on patch #1
> - Address Matthias' comments
>
> Changes since v1:
> - Rename function
> - Use callback in xhci-pci.c
>
> Nicolas Saenz Julienne (4):
> arm: rpi: Add function to trigger VL805's firmware load
> reset: Add Raspberry Pi 4 firmware reset controller
> configs: Enable support for reset controllers on RPi4
> usb: xhci: Add reset controller support
>
> arch/arm/mach-bcm283x/include/mach/mbox.h | 13
> arch/arm/mach-bcm283x/include/mach/msg.h | 7 +++
> arch/arm/mach-bcm283x/msg.c | 46 ++
> configs/rpi_4_32b_defconfig | 1 +
> configs/rpi_4_defconfig | 1 +
> configs/rpi_arm64_defconfig | 1 +
> drivers/reset/Kconfig | 10
> drivers/reset/Makefile| 1 +
> drivers/reset/reset-raspberrypi.c | 60 +++
> drivers/usb/host/xhci-mem.c | 2 +
> drivers/usb/host/xhci.c | 33 ++
> .../reset/raspberrypi,firmware-reset.h| 13
> include/usb/xhci.h| 2 +
> 13 files changed, 190 insertions(+)
> create mode 100644 drivers/reset/reset-raspberrypi.c
> create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
