Re: [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support

[Matthias Brugger]

Hi Marek,

On 09/07/2020 08:33, Marek Szyprowski wrote:

Hi Matthias,

On 11.06.2020 10:39, Matthias Brugger wrote:

...
Series looks good to me. The problem is that on RPi4 with 8 GB the USB FW get's
loaded via the RPi FW. Nicolas provided a series which is under review right
now. Without this series the 8 GB RPi4 won't boot. As soon as the series is
ready I'll take all the RPi4 PCI/USB related patches into the next branch.


I've noticed that You took both required patchsets to rpi-next branch.
May I ask for taking this one too?



I didn't forgot that series. The thing is, that it is assigned to Tom in 
patchwork, so I wanted to sync with him, if he is OK that I take the series. He 
provided already his Reviewed-by tags for the parts that I was concerned about.


@Tom, is it OK if I take this series through my rpi-next branch?

Regards,
Matthias

RE: [PATCH v6] ARM: dts: stm32: add seeed studio odyssey-stm32mp157c board

[Patrick DELAUNAY]

Hi Marcin,

> From: Marcin Sloniewski 
> Sent: mercredi 8 juillet 2020 19:56
> 
> This commit adds device tree files supporting SBC from Seeed Studio based on
> STM32MP157C.
> 
> This works with generic stm32mp1 config.
> Right now only booting from SD card is supported.
> 
> Signed-off-by: Marcin Sloniewski 
> ---
> 
> Changes in v6:
> - forgot to add changes in v5 ;(
> 
> Changes in v5:
> - removed description of PLL1 which is now handled by OPP info
> - removed cd-gpio for sdmmc1 since it is not yet supported
> 
> Changes in v4:
> - removed unnecessary pull up on uart4 rx
> 
> Changes in v3:
> - changed name of dts files from odyssey-stm32mp157c...
>   to stm32mp157c-odyssey...
> - removed usbotg node config
> - add new board in dts/Makefile in alphabetical order
> 
> Changes in v2:
> - removed `st,adc_usb_pd` from config since that
>   adc connection is non-existent which caused
>   warning or hang during boot
> 
>  arch/arm/dts/Makefile |   1 +
>  .../dts/stm32mp157c-odyssey-som-u-boot.dtsi   | 125 ++
>  arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 364 ++
>  arch/arm/dts/stm32mp157c-odyssey-u-boot.dtsi  |  58 +++
>  arch/arm/dts/stm32mp157c-odyssey.dts  | 161 
>  5 files changed, 709 insertions(+)
>  create mode 100644 arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157c-odyssey-som.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157c-odyssey-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157c-odyssey.dts
> 

Reviewed-by: Patrick Delaunay 

Thanks

Patrick

Re: [PATCH v2 1/2] spi: Remove unnecessary #ifdefs in header file

[Bin Meng]

On Wed, Jul 8, 2020 at 11:02 PM Simon Glass  wrote:
>
> These prevent use of compile-time checks such as:
>
> if (CONFIG_IS_ENABLED(DM_SPI))
>
> since, for example, if CONFIG_SPL_DM_SPI is not enabled then the
> definitions are not included by spi.h and the C code will not build.
>
> The #ifdefs are unnecessary since there are no conflicts with the pre-DM
> code. In any case we have almost switched over to driver model for SPI.
>
> Drop these #ifdefs from spi.h to fix a build warning on chromebook_coral
> in the following patch.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2:
> - Add an #ifdef around spi_cs_de/activate() as these are static in many 
> drivers
>
>  include/spi.h | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
>

applied to u-boot-x86, thanks!

Re: [PATCH v3 1/2] drivers: tee: broadcom: add optee based bnxt fw load driver

[Rayagonda Kokatanur]

Hi Simon,

On Mon, Jun 29, 2020 at 10:56 PM Simon Glass  wrote:
>
> Hi Rayagonda,
>
> On Sun, 28 Jun 2020 at 21:08, Rayagonda Kokatanur
>  wrote:
> >
> > Hi Simon,
> >
> > On Fri, Jun 26, 2020 at 6:42 AM Simon Glass  wrote:
> > >
> > > Hi Rayagonda,
> > >
> > > On Wed, 10 Jun 2020 at 05:15, Rayagonda Kokatanur
> > >  wrote:
> > > >
> > > > From: Vikas Gupta 
> > > >
> > > > Add optee based bnxt fw load driver.
> > > > bnxt is Broadcom NetXtreme controller Ethernet card.
> > > > This driver is used to load bnxt firmware binary using OpTEE.
> > > >
> > > > Signed-off-by: Vikas Gupta 
> > > > Signed-off-by: Rayagonda Kokatanur 
> > > > ---
> > > > Changes from v2:
> > > >  -Address review comments from Simon,
> > > >   Remove own return code and use standard error code.
> > > >   Take out common lines from different functions and move them
> > > >   into common static function.
> > > >   Remove include  as its not required.
> > > >   Move functions with printf from header file into c file.
> > > >
> > > >  drivers/tee/Kconfig|   1 +
> > > >  drivers/tee/Makefile   |   1 +
> > > >  drivers/tee/broadcom/Kconfig   |   7 ++
> > > >  drivers/tee/broadcom/Makefile  |   3 +
> > > >  drivers/tee/broadcom/chimp_optee.c | 182 +
> > > >  include/broadcom/chimp.h   |  16 +++
> > > >  6 files changed, 210 insertions(+)
> > > >  create mode 100644 drivers/tee/broadcom/Kconfig
> > > >  create mode 100644 drivers/tee/broadcom/Makefile
> > > >  create mode 100644 drivers/tee/broadcom/chimp_optee.c
> > > >  create mode 100644 include/broadcom/chimp.h
> > > >
> > > > diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig
> > > > index 5c0c89043f..5ca5a0836c 100644
> > > > --- a/drivers/tee/Kconfig
> > > > +++ b/drivers/tee/Kconfig
> > > > @@ -29,6 +29,7 @@ config SANDBOX_TEE
> > > >   "avb" commands.
> > > >
> > > >  source "drivers/tee/optee/Kconfig"
> > > > +source "drivers/tee/broadcom/Kconfig"
> > > >
> > > >  endmenu
> > > >
> > > > diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile
> > > > index f72c68c09f..5c8ffdbce8 100644
> > > > --- a/drivers/tee/Makefile
> > > > +++ b/drivers/tee/Makefile
> > > > @@ -3,3 +3,4 @@
> > > >  obj-y += tee-uclass.o
> > > >  obj-$(CONFIG_SANDBOX) += sandbox.o
> > > >  obj-$(CONFIG_OPTEE) += optee/
> > > > +obj-y += broadcom/
> > > > diff --git a/drivers/tee/broadcom/Kconfig b/drivers/tee/broadcom/Kconfig
> > > > new file mode 100644
> > > > index 00..ce95072d4e
> > > > --- /dev/null
> > > > +++ b/drivers/tee/broadcom/Kconfig
> > > > @@ -0,0 +1,7 @@
> > > > +config CHIMP_OPTEE
> > > > +   bool "Enable secure ChiMP firmware loading"
> > > > +   depends on OPTEE
> > > > +   default y
> > > > +   help
> > > > + This driver is used to load bnxt firmware binary using OpTEE.
> > > > + bnxt is Broadcom NetXtreme controller Ethernet card.
> > > > diff --git a/drivers/tee/broadcom/Makefile 
> > > > b/drivers/tee/broadcom/Makefile
> > > > new file mode 100644
> > > > index 00..cb3cef16df
> > > > --- /dev/null
> > > > +++ b/drivers/tee/broadcom/Makefile
> > > > @@ -0,0 +1,3 @@
> > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > +
> > > > +obj-y += chimp_optee.o
> > > > diff --git a/drivers/tee/broadcom/chimp_optee.c 
> > > > b/drivers/tee/broadcom/chimp_optee.c
> > > > new file mode 100644
> > > > index 00..4ca1b59c6a
> > > > --- /dev/null
> > > > +++ b/drivers/tee/broadcom/chimp_optee.c
> > > > @@ -0,0 +1,182 @@
> > > > +// SPDX-License-Identifier: BSD-2-Clause
> > > > +/*
> > > > + * Copyright 2020 Broadcom.
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +
> > > > +#ifdef CONFIG_CHIMP_OPTEE
> > > > +
> > > > +#define CHMIP_BOOT_UUID { 0x6272636D, 0x2019, 0x0716, \
> > > > +  { 0x42, 0x43, 0x4D, 0x5F, 0x53, 0x43, 0x48, 0x49 } }
> > > > +
> > > > +enum {
> > > > +   TEE_CHIMP_FASTBOOT = 0,
> > > > +   TEE_CHIMP_HEALTH_STATUS,
> > > > +   TEE_CHIMP_HANDSHAKE_STATUS,
> > > > +} tee_chmip_cmd;
> > > > +
> > > > +struct bcm_chimp_data {
> > > > +   struct udevice *tee;
> > > > +   u32 session;
> > > > +} chimp_data;
> > > > +
> > > > +static int get_open_session(struct bcm_chimp_data *b_data)
> > > > +{
> > > > +   struct udevice *tee = NULL;
> > > > +
> > > > +   while (!b_data->tee) {
> > > > +   const struct tee_optee_ta_uuid uuid = CHMIP_BOOT_UUID;
> > > > +   struct tee_open_session_arg arg;
> > > > +   int rc;
> > > > +
> > > > +   tee = tee_find_device(tee, NULL, NULL, NULL);
> > > > +   if (!tee)
> > > > +   return -ENODEV;
> > > > +
> > > > +   memset(&arg, 0, sizeof(arg));
> > > > +   tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
> > > > +   rc = tee_open_session(tee, &arg, 0, NULL);
> > > > +   if (!rc) {
> > > > +   b_data->t

[PATCH 01/10] board_f: Introduce arch_setup_bdinfo initcall

[Ovidiu Panait]

Certain architectures (ppc, mips, sh, m68k) use setup board_part1 and
setup_board_part2 calls during pre-relocation init to populate gd->bd
boardinfo fields. This makes the generic init sequence cluttered with
arch-specific ifdefs.

In order to clean these arch-specific sequences from generic init,
introduce arch_setup_bdinfo weak initcall so that everyone can define their
own bdinfo setup routines.

Signed-off-by: Ovidiu Panait 
---

 common/board_f.c |  6 ++
 include/init.h   | 12 
 2 files changed, 18 insertions(+)

diff --git a/common/board_f.c b/common/board_f.c
index dcad551ae4..e597749d2f 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -597,6 +597,11 @@ static int display_new_sp(void)
return 0;
 }
 
+__weak int arch_setup_bdinfo(void)
+{
+   return 0;
+}
+
 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
 static int setup_board_part1(void)
@@ -974,6 +979,7 @@ static const init_fnc_t init_sequence_f[] = {
reserve_stacks,
dram_init_banksize,
show_dram_config,
+   arch_setup_bdinfo,
 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
setup_board_part1,
diff --git a/include/init.h b/include/init.h
index e727031514..ccb766a348 100644
--- a/include/init.h
+++ b/include/init.h
@@ -141,6 +141,18 @@ int arch_reserve_stacks(void);
  */
 int arch_reserve_mmu(void);
 
+/**
+ * arch_setup_bdinfo() - Architecture dependent boardinfo setup
+ *
+ * Architecture-specific routine for populating various boardinfo fields of
+ * gd->bd. It is called during the generic board init sequence.
+ *
+ * If an implementation is not provided, it will just be a nop stub.
+ *
+ * Return: 0 if OK
+ */
+int arch_setup_bdinfo(void);
+
 /**
  * init_cache_f_r() - Turn on the cache in preparation for relocation
  *
-- 
2.17.1

Re: [PATCH 0/6] Add new series Micron SPI NAND devices

[Jagan Teki]

+ Vignesh

On Wed, Jul 8, 2020 at 1:37 AM  wrote:
>
> From: Shivamurthy Shastri 
>
> This patchset is for the new series of Micron SPI NAND devices, and the
> following links are their datasheet.
>
> These devices are already supported in Linux Kernel.
>
> M78A:
> [1] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
> [2] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
>
> M79A:
> [3] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
> [4] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
>
> M70A:
> [5] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
> [6] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
> [7] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
> [8] 
> https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
>
>
> Shivamurthy Shastri (6):
>   mtd: spinand: micron: Generalize the OOB layout structure and function
> names
>   mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
>   mtd: spinand: micron: Add new Micron SPI NAND devices
>   mtd: spinand: micron: identify SPI NAND device with Continuous Read
> mode
>   mtd: spinand: micron: Add M70A series Micron SPI NAND devices
>   mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
> dies

Acked-by: Jagan Teki 

[PATCH 04/10] board_f: sh: Factor out sh-specific bdinfo setup

[Ovidiu Panait]

Factor out sh-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/sh/lib/board.c.

Signed-off-by: Ovidiu Panait 
---

 arch/sh/lib/board.c | 18 ++
 common/board_f.c|  4 ++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index a6a8f07e6f..32e87e742b 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -16,6 +16,24 @@ int dram_init(void)
return 0;
 }
 
+int arch_setup_bdinfo(void)
+{
+   bd_t *bd = gd->bd;
+
+   /*
+* Save local variables to board info struct
+*/
+   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
+   bd->bi_memsize = gd->ram_size;  /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
+#endif
+
+   return 0;
+}
+
 void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
 {
void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r;
diff --git a/common/board_f.c b/common/board_f.c
index 960a9c83db..9bfcd6b236 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -602,7 +602,7 @@ __weak int arch_setup_bdinfo(void)
return 0;
 }
 
-#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
+#if defined(CONFIG_MIPS)
 static int setup_board_part1(void)
 {
bd_t *bd = gd->bd;
@@ -943,7 +943,7 @@ static const init_fnc_t init_sequence_f[] = {
dram_init_banksize,
show_dram_config,
arch_setup_bdinfo,
-#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
+#if defined(CONFIG_MIPS)
setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
 #endif
-- 
2.17.1

[PATCH 05/10] board_f: mips: Factor out mips-specific bdinfo setup

[Ovidiu Panait]

Factor out mips-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/mips/lib/boot.c.

Signed-off-by: Ovidiu Panait 
---

 arch/mips/lib/boot.c | 18 ++
 common/board_f.c | 25 +
 2 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6379..b3a48ce10f 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -9,6 +9,24 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int arch_setup_bdinfo(void)
+{
+   bd_t *bd = gd->bd;
+
+   /*
+* Save local variables to board info struct
+*/
+   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
+   bd->bi_memsize = gd->ram_size;  /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
+#endif
+
+   return 0;
+}
+
 unsigned long do_go_exec(ulong (*entry)(int, char * const []),
 int argc, char * const argv[])
 {
diff --git a/common/board_f.c b/common/board_f.c
index 9bfcd6b236..fd7e6a17ad 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -602,26 +602,6 @@ __weak int arch_setup_bdinfo(void)
return 0;
 }
 
-#if defined(CONFIG_MIPS)
-static int setup_board_part1(void)
-{
-   bd_t *bd = gd->bd;
-
-   /*
-* Save local variables to board info struct
-*/
-   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
-   bd->bi_memsize = gd->ram_size;  /* size in bytes */
-
-#ifdef CONFIG_SYS_SRAM_BASE
-   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
-   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
-#endif
-
-   return 0;
-}
-#endif
-
 #ifdef CONFIG_POST
 static int init_post(void)
 {
@@ -942,11 +922,8 @@ static const init_fnc_t init_sequence_f[] = {
reserve_stacks,
dram_init_banksize,
show_dram_config,
-   arch_setup_bdinfo,
-#if defined(CONFIG_MIPS)
-   setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
-#endif
+   arch_setup_bdinfo,
display_new_sp,
 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
-- 
2.17.1

[PATCH 08/10] common/board_r: Remove initr_serial wrapper

[Ovidiu Panait]

Remove the initr_serial->serial_initialize indirection and call
serial_initialize directly.

Signed-off-by: Ovidiu Panait 
---

 common/board_r.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c
index 5e924322b2..522059c5a5 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -187,12 +187,6 @@ static int initr_reloc_global_data(void)
return 0;
 }
 
-static int initr_serial(void)
-{
-   serial_initialize();
-   return 0;
-}
-
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
 static int initr_trap(void)
 {
@@ -705,7 +699,7 @@ static init_fnc_t init_sequence_r[] = {
 #endif
initr_dm_devices,
stdio_init_tables,
-   initr_serial,
+   serial_initialize,
initr_announce,
 #if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
-- 
2.17.1

[PATCH 03/10] board_f: ppc: Factor out ppc-specific bdinfo setup

[Ovidiu Panait]

Factor out ppc-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/powerpc/lib/bdinfo.c.

Signed-off-by: Ovidiu Panait 
---

 arch/powerpc/lib/bdinfo.c | 42 +++
 common/board_f.c  | 39 ++--
 2 files changed, 44 insertions(+), 37 deletions(-)

diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index d8c64155f0..49635874cf 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -11,6 +11,48 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int arch_setup_bdinfo(void)
+{
+   bd_t *bd = gd->bd;
+
+   /*
+* Save local variables to board info struct
+*/
+   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
+   bd->bi_memsize = gd->ram_size;  /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
+#endif
+
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+   bd->bi_immr_base = CONFIG_SYS_IMMR; /* base  of IMMR register */
+#endif
+
+#if defined(CONFIG_MPC83xx)
+   bd->bi_immrbar = CONFIG_SYS_IMMR;
+#endif
+
+   bd->bi_intfreq = gd->cpu_clk;   /* Internal Freq, in Hz */
+   bd->bi_busfreq = gd->bus_clk;   /* Bus Freq,  in Hz */
+
+#if defined(CONFIG_CPM2)
+   bd->bi_cpmfreq = gd->arch.cpm_clk;
+   bd->bi_brgfreq = gd->arch.brg_clk;
+   bd->bi_sccfreq = gd->arch.scc_clk;
+   bd->bi_vco = gd->arch.vco_out;
+#endif /* CONFIG_CPM2 */
+
+#if defined(CONFIG_EXTRA_CLOCK)
+   bd->bi_inpfreq = gd->arch.inp_clk;  /* input Freq in Hz */
+   bd->bi_vcofreq = gd->arch.vco_clk;  /* vco Freq in Hz */
+   bd->bi_flbfreq = gd->arch.flb_clk;  /* flexbus Freq in Hz */
+#endif
+
+   return 0;
+}
+
 void __weak board_detail(void)
 {
/* Please define board_detail() for your PPC platform */
diff --git a/common/board_f.c b/common/board_f.c
index 7d65879b93..960a9c83db 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -602,8 +602,7 @@ __weak int arch_setup_bdinfo(void)
return 0;
 }
 
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
-   defined(CONFIG_SH)
+#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
 static int setup_board_part1(void)
 {
bd_t *bd = gd->bd;
@@ -619,36 +618,6 @@ static int setup_board_part1(void)
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
 #endif
 
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-   bd->bi_immr_base = CONFIG_SYS_IMMR; /* base  of IMMR register */
-#endif
-#if defined(CONFIG_MPC83xx)
-   bd->bi_immrbar = CONFIG_SYS_IMMR;
-#endif
-
-   return 0;
-}
-#endif
-
-#if defined(CONFIG_PPC)
-static int setup_board_part2(void)
-{
-   bd_t *bd = gd->bd;
-
-   bd->bi_intfreq = gd->cpu_clk;   /* Internal Freq, in Hz */
-   bd->bi_busfreq = gd->bus_clk;   /* Bus Freq,  in Hz */
-#if defined(CONFIG_CPM2)
-   bd->bi_cpmfreq = gd->arch.cpm_clk;
-   bd->bi_brgfreq = gd->arch.brg_clk;
-   bd->bi_sccfreq = gd->arch.scc_clk;
-   bd->bi_vco = gd->arch.vco_out;
-#endif /* CONFIG_CPM2 */
-#if defined(CONFIG_EXTRA_CLOCK)
-   bd->bi_inpfreq = gd->arch.inp_clk;  /* input Freq in Hz */
-   bd->bi_vcofreq = gd->arch.vco_clk;  /* vco Freq in Hz */
-   bd->bi_flbfreq = gd->arch.flb_clk;  /* flexbus Freq in Hz */
-#endif
-
return 0;
 }
 #endif
@@ -974,13 +943,9 @@ static const init_fnc_t init_sequence_f[] = {
dram_init_banksize,
show_dram_config,
arch_setup_bdinfo,
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
-   defined(CONFIG_SH)
+#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
setup_board_part1,
-#endif
-#if defined(CONFIG_PPC)
INIT_FUNC_WATCHDOG_RESET
-   setup_board_part2,
 #endif
display_new_sp,
 #ifdef CONFIG_OF_BOARD_FIXUP
-- 
2.17.1

[PATCH 02/10] board_f: m68k: Factor out m68k-specific bdinfo setup

[Ovidiu Panait]

Factor out m68k-specific bdinfo setup to arch_setup_bdinfo in
arch/m68k/lib/bdinfo.c. Also, use if(IS_ENABLED()) instead of #ifdef where
possible.

Signed-off-by: Ovidiu Panait 
---

 arch/m68k/lib/bdinfo.c | 32 
 common/board_f.c   | 14 --
 2 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 971c47c306..83e367b502 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -11,6 +11,38 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int arch_setup_bdinfo(void)
+{
+   bd_t *bd = gd->bd;
+
+   /*
+* Save local variables to board info struct
+*/
+   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
+   bd->bi_memsize = gd->ram_size;  /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
+#endif
+
+   bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+
+   bd->bi_intfreq = gd->cpu_clk;   /* Internal Freq, in Hz */
+   bd->bi_busfreq = gd->bus_clk;   /* Bus Freq,  in Hz */
+
+   if (IS_ENABLED(CONFIG_PCI))
+   bd->bi_pcifreq = gd->pci_clk;
+
+#if defined(CONFIG_EXTRA_CLOCK)
+   bd->bi_inpfreq = gd->arch.inp_clk;  /* input Freq in Hz */
+   bd->bi_vcofreq = gd->arch.vco_clk;  /* vco Freq in Hz */
+   bd->bi_flbfreq = gd->arch.flb_clk;  /* flexbus Freq in Hz */
+#endif
+
+   return 0;
+}
+
 void arch_print_bdinfo(void)
 {
bd_t *bd = gd->bd;
diff --git a/common/board_f.c b/common/board_f.c
index e597749d2f..7d65879b93 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -602,7 +602,7 @@ __weak int arch_setup_bdinfo(void)
return 0;
 }
 
-#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
 static int setup_board_part1(void)
 {
@@ -622,9 +622,6 @@ static int setup_board_part1(void)
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base  of IMMR register */
 #endif
-#if defined(CONFIG_M68K)
-   bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
-#endif
 #if defined(CONFIG_MPC83xx)
bd->bi_immrbar = CONFIG_SYS_IMMR;
 #endif
@@ -633,7 +630,7 @@ static int setup_board_part1(void)
 }
 #endif
 
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC)
 static int setup_board_part2(void)
 {
bd_t *bd = gd->bd;
@@ -646,9 +643,6 @@ static int setup_board_part2(void)
bd->bi_sccfreq = gd->arch.scc_clk;
bd->bi_vco = gd->arch.vco_out;
 #endif /* CONFIG_CPM2 */
-#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
-   bd->bi_pcifreq = gd->pci_clk;
-#endif
 #if defined(CONFIG_EXTRA_CLOCK)
bd->bi_inpfreq = gd->arch.inp_clk;  /* input Freq in Hz */
bd->bi_vcofreq = gd->arch.vco_clk;  /* vco Freq in Hz */
@@ -980,11 +974,11 @@ static const init_fnc_t init_sequence_f[] = {
dram_init_banksize,
show_dram_config,
arch_setup_bdinfo,
-#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
setup_board_part1,
 #endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC)
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
 #endif
-- 
2.17.1

[PATCH 09/10] blkcache: Extend blkcache_init to cover CONFIG_NEEDS_MANUAL_RELOC

[Ovidiu Panait]

Extend manual relocation of block_cache list pointers to all platforms that
enable CONFIG_NEEDS_MANUAL_RELOC. Remove m68k-specific checks and provide a
single implementation that adds gd->reloc_off to the pre-relocation
pointers.

Cc: Angelo Durgehello 
Signed-off-by: Ovidiu Panait 
---

 common/board_r.c |  2 +-
 drivers/block/blkcache.c | 13 +++--
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c
index 522059c5a5..29d831d5eb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -836,7 +836,7 @@ static init_fnc_t init_sequence_r[] = {
 #if defined(CONFIG_PRAM)
initr_mem,
 #endif
-#if defined(CONFIG_M68K) && defined(CONFIG_BLOCK_CACHE)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
blkcache_init,
 #endif
run_main_loop,
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index b6fc72fe98..d97ee99cf4 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct block_cache_node {
struct list_head lh;
int iftype;
@@ -22,21 +24,20 @@ struct block_cache_node {
char *cache;
 };
 
-#ifndef CONFIG_M68K
 static LIST_HEAD(block_cache);
-#else
-static struct list_head block_cache;
-#endif
 
 static struct block_cache_stats _stats = {
.max_blocks_per_entry = 8,
.max_entries = 32
 };
 
-#ifdef CONFIG_M68K
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 int blkcache_init(void)
 {
-   INIT_LIST_HEAD(&block_cache);
+   struct list_head *head = &block_cache;
+
+   head->next = (uintptr_t)head->next + gd->reloc_off;
+   head->prev = (uintptr_t)head->prev + gd->reloc_off;
 
return 0;
 }
-- 
2.17.1

[PATCH 07/10] drivers: serial: Make serial_initialize return int

[Ovidiu Panait]

serial_initialize is called only during the common init sequence, after
relocation (in common/board_r.c). Because it has a void return value, it
has to wrapped in initr_serial. In order to be able to get rid of this
indirection, make serial_initialize return int.

Remove extern from prototype in order to silence the following checkpatch
warning:
check: extern prototypes should be avoided in .h files

Signed-off-by: Ovidiu Panait 
---

 drivers/serial/serial-uclass.c | 4 ++--
 drivers/serial/serial.c| 4 +++-
 include/serial.h   | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index a0af0e6bfd..0027625ebf 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -170,9 +170,9 @@ int serial_init(void)
 }
 
 /* Called after relocation */
-void serial_initialize(void)
+int serial_initialize(void)
 {
-   serial_init();
+   return serial_init();
 }
 
 static void _serial_putc(struct udevice *dev, char ch)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index da017dc5b3..53358acb81 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -170,7 +170,7 @@ void serial_register(struct serial_device *dev)
  * serial port to the serial core. That serial port is then used as a
  * default output.
  */
-void serial_initialize(void)
+int serial_initialize(void)
 {
atmel_serial_initialize();
mcf_serial_initialize();
@@ -183,6 +183,8 @@ void serial_initialize(void)
mtk_serial_initialize();
 
serial_assign(default_serial_console()->name);
+
+   return 0;
 }
 
 static int serial_stub_start(struct stdio_dev *sdev)
diff --git a/include/serial.h b/include/serial.h
index c590637b1f..6d1e62c677 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -42,10 +42,10 @@ extern struct serial_device eserial5_device;
 extern struct serial_device eserial6_device;
 
 extern void serial_register(struct serial_device *);
-extern void serial_initialize(void);
 extern void serial_stdio_init(void);
 extern int serial_assign(const char *name);
 extern void serial_reinit_all(void);
+int serial_initialize(void);
 
 /* For usbtty */
 #ifdef CONFIG_USB_TTY
-- 
2.17.1

[PATCH 10/10] common/board_r: Move blkcache_init call earlier in the boot sequence

[Ovidiu Panait]

blkcache_init manually relocates blkcache list pointers when
CONFIG_NEEDS_MANUAL_RELOC is enabled. However, it is called very late in
the boot sequence, which could be a problem if previous boot calls execute
blkcache operations with the non-relocated pointers. For example, mmc is
initialized earlier and might call blkcache_invalidate (in
mmc_select_hwpart()) when trying to load the environment from mmc via
env_load().

To fix this issue, move blkcache_init boot call earlier, before mmc gets
initialized.

Cc: Angelo Durgehello 
Signed-off-by: Ovidiu Panait 
---

 common/board_r.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c
index 29d831d5eb..a3c26bb380 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -705,6 +705,9 @@ static init_fnc_t init_sequence_r[] = {
initr_watchdog,
 #endif
INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
+   blkcache_init,
+#endif
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
 #endif
@@ -835,9 +838,6 @@ static init_fnc_t init_sequence_r[] = {
 #endif
 #if defined(CONFIG_PRAM)
initr_mem,
-#endif
-#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
-   blkcache_init,
 #endif
run_main_loop,
 };
-- 
2.17.1

[PATCH 06/10] dm: blk: Use IS_ENABLED() instead of #ifdefs in blk_post_probe

[Ovidiu Panait]

Use IS_ENABLED() instead of #ifdef in blk_post_probe function.

No functional change intended.

Signed-off-by: Ovidiu Panait 
---

 drivers/block/blk-uclass.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index b19375cbc8..b2738f5717 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -644,11 +644,12 @@ int blk_unbind_all(int if_type)
 
 static int blk_post_probe(struct udevice *dev)
 {
-#if defined(CONFIG_PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE)
-   struct blk_desc *desc = dev_get_uclass_platdata(dev);
+   if (IS_ENABLED(CONFIG_PARTITIONS) &&
+   IS_ENABLED(CONFIG_HAVE_BLOCK_DEV)) {
+   struct blk_desc *desc = dev_get_uclass_platdata(dev);
 
-   part_init(desc);
-#endif
+   part_init(desc);
+   }
 
return 0;
 }
-- 
2.17.1

Re: [PATCH v6 00/21] mtd: spi-nor-core: add xSPI Octal DTR support

[Jagan Teki]

On Tue, Jul 7, 2020 at 7:00 PM Vignesh Raghavendra  wrote:
>
> Hi Jagan,
>
> On 15/06/20 9:21 pm, Pratyush Yadav wrote:
> > On 05/06/20 06:14PM, Pratyush Yadav wrote:
> >> Hi,
> >>
> >> This series adds support for octal DTR flashes in the spi-nor framework,
> >> and then adds hooks for the Cypress Semper flash which is an xSPI
> >> compliant Octal DTR flash.
> >>
> >> The Cadence QSPI controller driver is also updated to run in Octal DTR
> >> mode.
> >>
> >> Tested on TI J721e EVM.
> >>
> >> The Travis CI build can be found here [0]. It is from the previous
> >> version, but there is no code change between the two versions.
> >>
> >> [0] https://travis-ci.org/github/prati0100/uboot/builds/694602802
> >
> > Jagan,
> >
> > Do you have any comments for the series? If not, can it please be merged
> > in?
> >
>
> Ping, given that merge window is opening shortly.. Could you take a look
> at this series?

Except for soft reset patches, the rest of them seems okay. Is Linux
support the same way w/o CONFIG options?

Jagan.

[PATCH 03/11] imx8m: add sdhc/nand/ecspi clk api

[peng . fan]

From: Peng Fan 

Current DM CLK is a bit complicated, for simplity, let DM clk only
support enable/disable/get_rate. For the expected rate settings,
we use non-DM clk to do that. Then we could have simple DM clk for
i.MX and could also share between SPL/U-Boot proper.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 66 ++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 0a8208606d..68effbd54f 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -317,6 +317,72 @@ void init_wdog_clk(void)
clock_enable(CCGR_WDOG3, 1);
 }
 
+void init_clk_usdhc(u32 index)
+{
+   /*
+* set usdhc clock root
+* sys pll1 400M
+*/
+   switch (index) {
+   case 0:
+   clock_enable(CCGR_USDHC1, 0);
+   clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+CLK_ROOT_SOURCE_SEL(1));
+   clock_enable(CCGR_USDHC1, 1);
+   return;
+   case 1:
+   clock_enable(CCGR_USDHC2, 0);
+   clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+CLK_ROOT_SOURCE_SEL(1));
+   clock_enable(CCGR_USDHC2, 1);
+   return;
+   case 2:
+   clock_enable(CCGR_USDHC3, 0);
+   clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
+CLK_ROOT_SOURCE_SEL(1));
+   clock_enable(CCGR_USDHC3, 1);
+   return;
+   default:
+   printf("Invalid usdhc index\n");
+   return;
+   }
+}
+
+void init_clk_ecspi(u32 index)
+{
+   switch (index) {
+   case 0:
+   clock_enable(CCGR_ECSPI1, 0);
+   clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+   clock_enable(CCGR_ECSPI1, 1);
+   return;
+   case 1:
+   clock_enable(CCGR_ECSPI2, 0);
+   clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+   clock_enable(CCGR_ECSPI2, 1);
+   case 2:
+   clock_enable(CCGR_ECSPI3, 0);
+   clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+   clock_enable(CCGR_ECSPI3, 1);
+   return;
+   default:
+   printf("Invalid ecspi index\n");
+   return;
+   }
+}
+
+void init_nand_clk(void)
+{
+   /*
+* set rawnand root
+* sys pll1 400M
+*/
+   clock_enable(CCGR_RAWNAND, 0);
+   clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
+   CLK_ROOT_SOURCE_SEL(3) | 
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
+   clock_enable(CCGR_RAWNAND, 1);
+}
+
 int clock_init(void)
 {
u32 val_cfg0;
-- 
2.16.4

[PATCH 04/11] imx8m: add eqos clk

[peng . fan]

From: Peng Fan 

Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the
weak function in driver

Add set_clk_eqos to configure eQoS clk

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 90 ++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 68effbd54f..3610f5b2fc 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -788,6 +788,96 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
 }
 
+#ifdef CONFIG_DWC_ETH_QOS
+int set_clk_eqos(enum enet_freq type)
+{
+   u32 target;
+   u32 enet1_ref;
+
+   switch (type) {
+   case ENET_125MHZ:
+   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+   break;
+   case ENET_50MHZ:
+   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+   break;
+   case ENET_25MHZ:
+   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   /* disable the clock first */
+   clock_enable(CCGR_QOS_ETHENET, 0);
+   clock_enable(CCGR_SDMA2, 0);
+
+   /* set enet axi clock 266Mhz */
+   target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+   clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+   target = CLK_ROOT_ON | enet1_ref |
+CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+   clock_set_target_val(ENET_QOS_CLK_ROOT, target);
+
+   target = CLK_ROOT_ON |
+   ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+   CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+   CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+   clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
+
+   /* enable clock */
+   clock_enable(CCGR_QOS_ETHENET, 1);
+   clock_enable(CCGR_SDMA2, 1);
+
+   return 0;
+}
+
+int imx_eqos_txclk_set_rate(u32 rate)
+{
+   u32 val;
+   u32 eqos_post_div;
+
+   /* disable the clock first */
+   clock_enable(CCGR_QOS_ETHENET, 0);
+   clock_enable(CCGR_SDMA2, 0);
+
+   switch (rate) {
+   case 12500:
+   eqos_post_div = 1;
+   break;
+   case 2500:
+   eqos_post_div = 12500 / 2500;
+   break;
+   case 250:
+   eqos_post_div = 12500 / 250;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
+   val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
+   val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+  CLK_ROOT_POST_DIV(eqos_post_div - 1);
+   clock_set_target_val(ENET_QOS_CLK_ROOT, val);
+
+   /* enable clock */
+   clock_enable(CCGR_QOS_ETHENET, 1);
+   clock_enable(CCGR_SDMA2, 1);
+
+   return 0;
+}
+
+u32 imx_get_eqos_csr_clk(void)
+{
+   return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int set_clk_enet(enum enet_freq type)
 {
-- 
2.16.4

[PATCH 02/11] imx8m: configure NoC clk

[peng . fan]

From: Peng Fan 

Configure NoC clk for better system performance

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 6ab75f0e2c..0a8208606d 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -353,11 +353,24 @@ int clock_init(void)
/* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
 
+   if (is_imx8mn() || is_imx8mp())
+   intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
+   else
+   intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
+
+#ifdef CONFIG_IMX8MP
+   /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk 
to 600Mhz */
+   /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
+   clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(2));
+#else
+   clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(2));
+
/* config GIC to sys_pll2_100m */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
 CLK_ROOT_SOURCE_SEL(3));
clock_enable(CCGR_GIC, 1);
+#endif
 
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 CLK_ROOT_SOURCE_SEL(1));
-- 
2.16.4

[PATCH 00/11] imx8m: soc/clk update

[peng . fan]

From: Peng Fan 

This is to upstream some patches from NXP tree after adapt to U-Boot
upstream.

Added a few APIs that directly touch CCM/PLL register without CLK DM.

I plan to simplify the clk DM part to only keep gate and get rate, so
move complicated set rate out from clk DM with non-DM API.

Peng Fan (9):
  imx8m: configure arm clk sources from PLL
  imx8m: configure NoC clk
  imx8m: add sdhc/nand/ecspi clk api
  imx8m: add eqos clk
  imx8m: workaround ROM serror
  imx8m: power down fused cores
  imx8m: disable nodes before kernel/mfgtool boot for fused part
  clk: imx8m: drop clk settings
  imx8m: Refactor the OPTEE memory removal

Ye Li (2):
  imx8mp: Add fused parts support
  imx8mn/imx8mp: override env_get_offset and env_get_location

 arch/arm/include/asm/arch-imx/cpu.h|   5 +
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 158 +++
 arch/arm/include/asm/mach-imx/sys_proto.h  |   9 +-
 arch/arm/mach-imx/cpu.c|  12 +-
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 299 +++-
 arch/arm/mach-imx/imx8m/soc.c  | 605 -
 board/beacon/imx8mm/imx8mm_beacon.c|  11 -
 board/freescale/imx8mm_evk/imx8mm_evk.c|  11 -
 board/freescale/imx8mn_evk/imx8mn_evk.c|   7 -
 board/freescale/imx8mp_evk/imx8mp_evk.c|  40 --
 board/freescale/imx8mq_evk/imx8mq_evk.c|  11 -
 board/google/imx8mq_phanbell/imx8mq_phanbell.c |  11 -
 board/technexion/pico-imx8mq/pico-imx8mq.c |  26 +-
 board/toradex/verdin-imx8mm/verdin-imx8mm.c|  11 -
 configs/imx8mp_evk_defconfig   |   1 -
 drivers/clk/imx/clk-imx8mm.c   |  34 --
 drivers/clk/imx/clk-imx8mn.c   |  34 --
 17 files changed, 1089 insertions(+), 196 deletions(-)

-- 
2.16.4

[PATCH 01/11] imx8m: configure arm clk sources from PLL

[peng . fan]

From: Peng Fan 

A53 CCM root max support 1GHz, to support high freq, we need
to switch ARM clk sources from ARM PLL directly.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 130 -
 1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index aafe2ed084..6ab75f0e2c 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 
+static u32 get_root_clk(enum clk_root_index clock_id);
 void enable_ocotp_clk(unsigned char enable)
 {
clock_enable(CCGR_OCOTP, !!enable);
@@ -164,6 +165,109 @@ void dram_disable_bypass(void)
 }
 #endif
 
+int intpll_configure(enum pll_clocks pll, ulong freq)
+{
+   void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
+   u32 pll_div_ctl_val, pll_clke_masks;
+
+   switch (pll) {
+   case ANATOP_SYSTEM_PLL1:
+   pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
+   pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
+   pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+   INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+   INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+   INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+   INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+   break;
+   case ANATOP_SYSTEM_PLL2:
+   pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
+   pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
+   pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+   INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+   INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+   INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+   INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+   break;
+   case ANATOP_SYSTEM_PLL3:
+   pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
+   pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
+   pll_clke_masks = INTPLL_CLKE_MASK;
+   break;
+   case ANATOP_ARM_PLL:
+   pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
+   pll_div_ctl = &ana_pll->arm_pll_div_ctl;
+   pll_clke_masks = INTPLL_CLKE_MASK;
+   break;
+   case ANATOP_GPU_PLL:
+   pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
+   pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
+   pll_clke_masks = INTPLL_CLKE_MASK;
+   break;
+   case ANATOP_VPU_PLL:
+   pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
+   pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
+   pll_clke_masks = INTPLL_CLKE_MASK;
+   break;
+   default:
+   return -EINVAL;
+   };
+
+   switch (freq) {
+   case MHZ(600):
+   /* 24 * 0x12c / 3 / 2 ^ 2 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
+   INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
+   break;
+   case MHZ(750):
+   /* 24 * 0xfa / 2 / 2 ^ 2 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+   INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
+   break;
+   case MHZ(800):
+   /* 24 * 0x190 / 3 / 2 ^ 2 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
+   INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
+   break;
+   case MHZ(1000):
+   /* 24 * 0xfa / 3 / 2 ^ 1 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+   INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+   break;
+   case MHZ(1200):
+   /* 24 * 0xc8 / 2 / 2 ^ 1 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
+   INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
+   break;
+   case MHZ(2000):
+   /* 24 * 0xfa / 3 / 2 ^ 0 */
+   pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+   INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+   break;
+   default:
+   return -EINVAL;
+   };
+   /* Bypass clock and set lock to pll output lock */
+   setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
+   /* Enable reset */
+   clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+   /* Configure */
+   writel(pll_div_ctl_val, pll_div_ctl);
+
+   __udelay(100);
+
+   /* Disable reset */
+   setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+   /* Wait Lock */
+   while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
+   ;
+   /* Clear bypass */
+   clrbits_le32(pll_gnrl_ctl, I

[PATCH 10/11] clk: imx8m: drop clk settings

[peng . fan]

From: Peng Fan 

We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-imx8mm.c | 34 --
 drivers/clk/imx/clk-imx8mn.c | 34 --
 2 files changed, 68 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 85d1757536..d32ff8409a 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -437,40 +437,6 @@ static int imx8mm_clk_probe(struct udevice *dev)
   base + 0x40a0, 0));
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-   struct clk *clkp, *clkp1;
-
-   clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
-   clk_enable(clkp);
-   clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
-   clk_enable(clkp);
-   clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
-   clk_enable(clkp);
-
-   /* Configure SYS_PLL3 to 750MHz */
-   clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
-   clk_set_rate(clkp, 75000UL);
-   clk_enable(clkp);
-
-   /* Configure ARM to sys_pll2_500m */
-   clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
-   clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
-   clk_enable(clkp1);
-   clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
-   clk_set_parent(clkp, clkp1);
-
-   /* Configure ARM PLL to 1.2GHz */
-   clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
-   clk_set_rate(clkp1, 12UL);
-   clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
-   clk_enable(clkp1);
-   clk_set_parent(clkp, clkp1);
-
-   /* Configure DIV to 1.2GHz */
-   clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
-   clk_set_rate(clkp1, 12UL);
-#endif
-
return 0;
 }
 
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 8bf6061a32..e29d902544 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -440,40 +440,6 @@ static int imx8mn_clk_probe(struct udevice *dev)
   base + 0x40a0, 0));
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-   struct clk *clkp, *clkp1;
-
-   clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
-   clk_enable(clkp);
-   clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
-   clk_enable(clkp);
-   clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
-   clk_enable(clkp);
-
-   /* Configure SYS_PLL3 to 600MHz */
-   clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
-   clk_set_rate(clkp, 6UL);
-   clk_enable(clkp);
-
-   /* Configure ARM to sys_pll2_500m */
-   clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
-   clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
-   clk_enable(clkp1);
-   clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
-   clk_set_parent(clkp, clkp1);
-
-   /* Configure ARM PLL to 1.2GHz */
-   clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
-   clk_set_rate(clkp1, 12UL);
-   clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
-   clk_enable(clkp1);
-   clk_set_parent(clkp, clkp1);
-
-   /* Configure DIV to 1.2GHz */
-   clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
-   clk_set_rate(clkp1, 12UL);
-#endif
-
return 0;
 }
 
-- 
2.16.4

[PATCH 06/11] imx8mp: Add fused parts support

[peng . fan]

From: Ye Li 

iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.

The configuration tables for enabled modules:
MIMX8ML8DVNLZAA  Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA  Quad Core, NPU, ISP
MIMX8ML6DVNLZAA  Quad Core, VPU, ISP
MIMX8ML5DVNLZAA  Quad Core, VPU
MIMX8ML4DVNLZAA  Quad Lite
MIMX8ML3DVNLZAA  Dual Core, VPU, NPU, ISP, DSP

Add the support in U-Boot

Reviewed-by: Peng Fan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx/cpu.h   |  5 +
 arch/arm/include/asm/mach-imx/sys_proto.h |  9 +++-
 arch/arm/mach-imx/cpu.c   | 12 ++-
 arch/arm/mach-imx/imx8m/soc.c | 34 ++-
 4 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index e9c0078922..75ff991248 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -41,6 +41,11 @@
 #define MXC_CPU_IMX8MNDL   0x8f /* dummy ID */
 #define MXC_CPU_IMX8MNSL   0x181 /* dummy ID */
 #define MXC_CPU_IMX8MP 0x182/* dummy ID */
+#define MXC_CPU_IMX8MP70x183 /* dummy ID */
+#define MXC_CPU_IMX8MP60x184 /* dummy ID */
+#define MXC_CPU_IMX8MP50x185 /* dummy ID */
+#define MXC_CPU_IMX8MPL0x186 /* dummy ID */
+#define MXC_CPU_IMX8MPD0x187 /* dummy ID */
 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
 #define MXC_CPU_IMX8QXP0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 0bc705df17..ab94024c9b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -66,7 +66,14 @@ struct bd_info;
 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
-#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP))
+#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)  || 
is_cpu_type(MXC_CPU_IMX8MPD) || \
+   is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \
+   is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5))
+#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
+#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
+#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7))
+#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
+#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5))
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index f2070c9714..b89d27ffd2 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -96,7 +96,17 @@ const char *get_imx_type(u32 imxtype)
 {
switch (imxtype) {
case MXC_CPU_IMX8MP:
-   return "8MP";   /* Quad-core version of the imx8mp */
+   return "8MP[8]";/* Quad-core version of the imx8mp */
+   case MXC_CPU_IMX8MPD:
+   return "8MP Dual[3]";   /* Dual-core version of the imx8mp */
+   case MXC_CPU_IMX8MPL:
+   return "8MP Lite[4]";   /* Quad-core Lite version of the imx8mp 
*/
+   case MXC_CPU_IMX8MP7:
+   return "8MP[7]";/* Quad-core version of the imx8mp, VPU 
fused */
+   case MXC_CPU_IMX8MP6:
+   return "8MP[6]";/* Quad-core version of the imx8mp, NPU 
fused */
+   case MXC_CPU_IMX8MP5:
+   return "8MP[5]";/* Quad-core version of the imx8mp, ISP 
fused */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9caf08e86c..c103bc3ad1 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -211,6 +211,38 @@ static u32 get_cpu_variant_type(u32 type)
return MXC_CPU_IMX8MNL;
break;
}
+   } else if (type == MXC_CPU_IMX8MP) {
+   u32 value0 = readl(&fuse->tester3);
+   u32 flag = 0;
+
+   if ((value0 & 0xc) == 0x8)
+   return MXC_CPU_IMX8MPD;
+
+   /* vpu disabled */
+   if ((value0 & 0x4300) == 0x4300)
+   flag = 1;
+
+   /* npu disabled*/
+   if ((value & 0x8) == 0x8)
+   flag |= (1 << 1);
+
+   /* isp disabled */
+   if ((value & 0x3) == 0x3)
+   flag |= (1 << 2);
+
+   switch (flag) {
+   case 7:
+   return MXC_CPU_IMX8MPL;
+   case 6:
+   return MXC_C

[PATCH 08/11] imx8mn/imx8mp: override env_get_offset and env_get_location

[peng . fan]

From: Ye Li 

To use one defconfig for all boot device, we have to runtime set
env offset and return env medium according to the boot device.
This patch overrides the env_get_offset and env_get_location to
implement the feature.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 59 +++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index f74a343ed8..9517a7cfcf 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -616,3 +618,60 @@ void do_error(struct pt_regs *pt_regs, unsigned int esr)
 }
 #endif
 #endif
+
+#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+   enum boot_device dev = get_boot_device();
+   enum env_location env_loc = ENVL_UNKNOWN;
+
+   if (prio)
+   return env_loc;
+
+   switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+   case QSPI_BOOT:
+   env_loc = ENVL_SPI_FLASH;
+   break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_NAND
+   case NAND_BOOT:
+   env_loc = ENVL_NAND;
+   break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+   case SD1_BOOT:
+   case SD2_BOOT:
+   case SD3_BOOT:
+   case MMC1_BOOT:
+   case MMC2_BOOT:
+   case MMC3_BOOT:
+   env_loc =  ENVL_MMC;
+   break;
+#endif
+   default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+   env_loc = ENVL_NOWHERE;
+#endif
+   break;
+   }
+
+   return env_loc;
+}
+
+#ifndef ENV_IS_EMBEDDED
+long long env_get_offset(long long defautl_offset)
+{
+   enum boot_device dev = get_boot_device();
+
+   switch (dev) {
+   case NAND_BOOT:
+   return (60 << 20);  /* 60MB offset for NAND */
+   default:
+   break;
+   }
+
+   return defautl_offset;
+}
+#endif
+#endif
-- 
2.16.4

[PATCH 05/11] imx8m: workaround ROM serror

[peng . fan]

From: Peng Fan 

ROM SError happens on two cases:

1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.

2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause
SError.

Since ROM mask SError until ATF unmask it, so then ATF always meets the
exception. This patch works around the issue in SPL by enabling SPL
Exception vectors table and the SError exception, take the exception
to eret immediately to clear the SError.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 38 ++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index fae69be1c7..9caf08e86c 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -16,8 +16,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -527,3 +529,39 @@ void imx_tmu_arch_init(void *reg_base)
writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
 #endif
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
+bool serror_need_skip = true;
+
+void do_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+   /*
+* If stack is still in ROM reserved OCRAM not switch to SPL,
+* it is the ROM SError
+*/
+   ulong sp;
+
+   asm volatile("mov %0, sp" : "=r"(sp) : );
+
+   if (serror_need_skip && sp < 0x91 && sp >= 0x90) {
+   /* Check for ERR050342, imx8mq HDCP enabled parts */
+   if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 
0x0800)) {
+   serror_need_skip = false;
+   return; /* Do nothing skip the SError in ROM */
+   }
+
+   /* Check for ERR050350, field return mode for imx8mq, mm and mn 
*/
+   if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
+   serror_need_skip = false;
+   return; /* Do nothing skip the SError in ROM */
+   }
+   }
+
+   efi_restore_gd();
+   printf("\"Error\" handler, esr 0x%08x\n", esr);
+   show_regs(pt_regs);
+   panic("Resetting CPU ...\n");
+}
+#endif
+#endif
-- 
2.16.4

[PATCH 07/11] imx8m: power down fused cores

[peng . fan]

From: Peng Fan 

For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.

Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 158 +
 arch/arm/mach-imx/imx8m/soc.c  |  19 
 2 files changed, 177 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3cfa169c97..f1c410ec78 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -331,5 +331,163 @@ struct bootrom_sw_info {
 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
+
+struct gpc_reg {
+   u32 lpcr_bsc;
+   u32 lpcr_ad;
+   u32 lpcr_cpu1;
+   u32 lpcr_cpu2;
+   u32 lpcr_cpu3;
+   u32 slpcr;
+   u32 mst_cpu_mapping;
+   u32 mmdc_cpu_mapping;
+   u32 mlpcr;
+   u32 pgc_ack_sel;
+   u32 pgc_ack_sel_m4;
+   u32 gpc_misc;
+   u32 imr1_core0;
+   u32 imr2_core0;
+   u32 imr3_core0;
+   u32 imr4_core0;
+   u32 imr1_core1;
+   u32 imr2_core1;
+   u32 imr3_core1;
+   u32 imr4_core1;
+   u32 imr1_cpu1;
+   u32 imr2_cpu1;
+   u32 imr3_cpu1;
+   u32 imr4_cpu1;
+   u32 imr1_cpu3;
+   u32 imr2_cpu3;
+   u32 imr3_cpu3;
+   u32 imr4_cpu3;
+   u32 isr1_cpu0;
+   u32 isr2_cpu0;
+   u32 isr3_cpu0;
+   u32 isr4_cpu0;
+   u32 isr1_cpu1;
+   u32 isr2_cpu1;
+   u32 isr3_cpu1;
+   u32 isr4_cpu1;
+   u32 isr1_cpu2;
+   u32 isr2_cpu2;
+   u32 isr3_cpu2;
+   u32 isr4_cpu2;
+   u32 isr1_cpu3;
+   u32 isr2_cpu3;
+   u32 isr3_cpu3;
+   u32 isr4_cpu3;
+   u32 slt0_cfg;
+   u32 slt1_cfg;
+   u32 slt2_cfg;
+   u32 slt3_cfg;
+   u32 slt4_cfg;
+   u32 slt5_cfg;
+   u32 slt6_cfg;
+   u32 slt7_cfg;
+   u32 slt8_cfg;
+   u32 slt9_cfg;
+   u32 slt10_cfg;
+   u32 slt11_cfg;
+   u32 slt12_cfg;
+   u32 slt13_cfg;
+   u32 slt14_cfg;
+   u32 pgc_cpu_0_1_mapping;
+   u32 cpu_pgc_up_trg;
+   u32 mix_pgc_up_trg;
+   u32 pu_pgc_up_trg;
+   u32 cpu_pgc_dn_trg;
+   u32 mix_pgc_dn_trg;
+   u32 pu_pgc_dn_trg;
+   u32 lpcr_bsc2;
+   u32 pgc_cpu_2_3_mapping;
+   u32 lps_cpu0;
+   u32 lps_cpu1;
+   u32 lps_cpu2;
+   u32 lps_cpu3;
+   u32 gpc_gpr;
+   u32 gtor;
+   u32 debug_addr1;
+   u32 debug_addr2;
+   u32 cpu_pgc_up_status1;
+   u32 mix_pgc_up_status0;
+   u32 mix_pgc_up_status1;
+   u32 mix_pgc_up_status2;
+   u32 m4_mix_pgc_up_status0;
+   u32 m4_mix_pgc_up_status1;
+   u32 m4_mix_pgc_up_status2;
+   u32 pu_pgc_up_status0;
+   u32 pu_pgc_up_status1;
+   u32 pu_pgc_up_status2;
+   u32 m4_pu_pgc_up_status0;
+   u32 m4_pu_pgc_up_status1;
+   u32 m4_pu_pgc_up_status2;
+   u32 a53_lp_io_0;
+   u32 a53_lp_io_1;
+   u32 a53_lp_io_2;
+   u32 cpu_pgc_dn_status1;
+   u32 mix_pgc_dn_status0;
+   u32 mix_pgc_dn_status1;
+   u32 mix_pgc_dn_status2;
+   u32 m4_mix_pgc_dn_status0;
+   u32 m4_mix_pgc_dn_status1;
+   u32 m4_mix_pgc_dn_status2;
+   u32 pu_pgc_dn_status0;
+   u32 pu_pgc_dn_status1;
+   u32 pu_pgc_dn_status2;
+   u32 m4_pu_pgc_dn_status0;
+   u32 m4_pu_pgc_dn_status1;
+   u32 m4_pu_pgc_dn_status2;
+   u32 res[3];
+   u32 mix_pdn_flg;
+   u32 pu_pdn_flg;
+   u32 m4_mix_pdn_flg;
+   u32 m4_pu_pdn_flg;
+   u32 imr1_core2;
+   u32 imr2_core2;
+   u32 imr3_core2;
+   u32 imr4_core2;
+   u32 imr1_core3;
+   u32 imr2_core3;
+   u32 imr3_core3;
+   u32 imr4_core3;
+   u32 pgc_ack_sel_pu;
+   u32 pgc_ack_sel_m4_pu;
+   u32 slt15_cfg;
+   u32 slt16_cfg;
+   u32 slt17_cfg;
+   u32 slt18_cfg;
+   u32 slt19_cfg;
+   u32 gpc_pu_pwrhsk;
+   u32 slt0_cfg_pu;
+   u32 slt1_cfg_pu;
+   u32 slt2_cfg_pu;
+   u32 slt3_cfg_pu;
+   u32 slt4_cfg_pu;
+   u32 slt5_cfg_pu;
+   u32 slt6_cfg_pu;
+   u32 slt7_cfg_pu;
+   u32 slt8_cfg_pu;
+   u32 slt9_cfg_pu;
+   u32 slt10_cfg_pu;
+   u32 slt11_cfg_pu;
+   u32 slt12_cfg_pu;
+   u32 slt13_cfg_pu;
+   u32 slt14_cfg_pu;
+   u32 slt15_cfg_pu;
+   u32 slt16_cfg_pu;
+   u32 slt17_cfg_pu;
+   u32 slt18_cfg_pu;
+   u32 slt19_cfg_pu;
+};
+
+struct pgc_reg {
+   u32 pgcr;
+   u32 pgpupscr;
+   u32 pgpdnscr;
+   u32 pgsr;
+   u32 pgauxsw;
+   u32 pgdr;
+};
 #endif
 #endif
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index c103bc3ad1..f74a343ed8 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -342,6 +342,25 @@ int arch_cpu_init(void)
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
clock

[PATCH 09/11] imx8m: disable nodes before kernel/mfgtool boot for fused part

[peng . fan]

From: Peng Fan 

To fused part, we need to disable nodes of dtb to let kernel boot.

To mfgtool, USB issue when using super-speed for mfgtool, temporally
work around the problem to use high-speed only.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 333 ++
 1 file changed, 333 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9517a7cfcf..bb2f112af6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -428,12 +428,298 @@ bool is_usb_boot(void)
 }
 
 #ifdef CONFIG_OF_SYSTEM_SETUP
+bool check_fdt_new_path(void *blob)
+{
+   const char *soc_path = "/soc@0";
+   int nodeoff;
+
+   nodeoff = fdt_path_offset(blob, soc_path);
+   if (nodeoff < 0)
+   return false;
+
+   return true;
+}
+
+static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int 
size_array)
+{
+   int i = 0;
+   int rc;
+   int nodeoff;
+   const char *status = "disabled";
+
+   for (i = 0; i < size_array; i++) {
+   nodeoff = fdt_path_offset(blob, nodes_path[i]);
+   if (nodeoff < 0)
+   continue; /* Not found, skip it */
+
+   printf("Found %s node\n", nodes_path[i]);
+
+add_status:
+   rc = fdt_setprop(blob, nodeoff, "status", status, 
strlen(status) + 1);
+   if (rc) {
+   if (rc == -FDT_ERR_NOSPACE) {
+   rc = fdt_increase_size(blob, 512);
+   if (!rc)
+   goto add_status;
+   }
+   printf("Unable to update property %s:%s, err=%s\n",
+  nodes_path[i], "status", fdt_strerror(rc));
+   } else {
+   printf("Modify %s:%s disabled\n",
+  nodes_path[i], "status");
+   }
+   }
+
+   return 0;
+}
+
+#ifdef CONFIG_IMX8MQ
+bool check_dcss_fused(void)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = &ocotp->bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   u32 value = readl(&fuse->tester4);
+
+   if (value & 0x400)
+   return true;
+
+   return false;
+}
+
+static int disable_mipi_dsi_nodes(void *blob)
+{
+   static const char * const nodes_path[] = {
+   "/mipi_dsi@30A0",
+   "/mipi_dsi_bridge@30A0",
+   "/dsi_phy@30A00300",
+   "/soc@0/bus@3080/mipi_dsi@30a0",
+   "/soc@0/bus@3080/dphy@30a00300"
+   };
+
+   return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
+}
+
+static int disable_dcss_nodes(void *blob)
+{
+   static const char * const nodes_path[] = {
+   "/dcss@0x32e0",
+   "/dcss@32e0",
+   "/hdmi@32c0",
+   "/hdmi_cec@32c33800",
+   "/hdmi_drm@32c0",
+   "/display-subsystem",
+   "/sound-hdmi",
+   "/sound-hdmi-arc",
+   "/soc@0/bus@32c0/display-controller@32e0",
+   "/soc@0/bus@32c0/hdmi@32c0",
+   };
+
+   return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
+}
+
+static int check_mipi_dsi_nodes(void *blob)
+{
+   static const char * const lcdif_path[] = {
+   "/lcdif@3032",
+   "/soc@0/bus@3000/lcdif@3032"
+   };
+   static const char * const mipi_dsi_path[] = {
+   "/mipi_dsi@30A0",
+   "/soc@0/bus@3080/mipi_dsi@30a0"
+   };
+   static const char * const lcdif_ep_path[] = {
+   "/lcdif@3032/port@0/mipi-dsi-endpoint",
+   "/soc@0/bus@3000/lcdif@3032/port@0/endpoint"
+   };
+   static const char * const mipi_dsi_ep_path[] = {
+   "/mipi_dsi@30A0/port@1/endpoint",
+   "/soc@0/bus@3080/mipi_dsi@30a0/ports/port@0/endpoint"
+   };
+
+   int lookup_node;
+   int nodeoff;
+   bool new_path = check_fdt_new_path(blob);
+   int i = new_path ? 1 : 0;
+
+   nodeoff = fdt_path_offset(blob, lcdif_path[i]);
+   if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
+   /*
+* If can't find lcdif node or lcdif node is disabled,
+* then disable all mipi dsi, since they only can input
+* from DCSS
+*/
+   return disable_mipi_dsi_nodes(blob);
+   }
+
+   nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
+   if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
+   return 0;
+
+   nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
+   if (nodeoff < 0) {
+   /*
+  

[PATCH 11/11] imx8m: Refactor the OPTEE memory removal

[peng . fan]

From: Peng Fan 

Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.

When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.

Signed-off-by: Ye Li 
Signed-off-by: Silvano di Ninno 
Tested-by: Silvano di Ninno 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c  | 122 +++--
 board/beacon/imx8mm/imx8mm_beacon.c|  11 ---
 board/freescale/imx8mm_evk/imx8mm_evk.c|  11 ---
 board/freescale/imx8mn_evk/imx8mn_evk.c|   7 --
 board/freescale/imx8mp_evk/imx8mp_evk.c|  40 
 board/freescale/imx8mq_evk/imx8mq_evk.c|  11 ---
 board/google/imx8mq_phanbell/imx8mq_phanbell.c |  11 ---
 board/technexion/pico-imx8mq/pico-imx8mq.c |  26 +++---
 board/toradex/verdin-imx8mm/verdin-imx8mm.c|  11 ---
 configs/imx8mp_evk_defconfig   |   1 -
 10 files changed, 127 insertions(+), 124 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index bb2f112af6..b3c08271e6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -142,6 +142,9 @@ static struct mm_region imx8m_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_OUTER_SHARE
 #endif
+   }, {
+   /* empty entrie to split table entry 5 if needed when TEEs are 
used */
+   0,
}, {
/* List terminator */
0,
@@ -152,18 +155,123 @@ struct mm_region *mem_map = imx8m_mem_map;
 
 void enable_caches(void)
 {
-   /*
-* If OPTEE runs, remove OPTEE memory from MMU table to
-* avoid speculative prefetch. OPTEE runs at the top of
-* the first memory bank
-*/
-   if (rom_pointer[1])
-   imx8m_mem_map[5].size -= rom_pointer[1];
+   /* If OPTEE runs, remove OPTEE memory from MMU table to avoid 
speculative prefetch */
+   if (rom_pointer[1]) {
+   /*
+* TEE are loaded, So the ddr bank structures
+* have been modified update mmu table accordingly
+*/
+   int i = 0;
+   /*
+* please make sure that entry initial value matches
+* imx8m_mem_map for DRAM1
+*/
+   int entry = 5;
+   u64 attrs = imx8m_mem_map[entry].attrs;
+
+   while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
+   if (gd->bd->bi_dram[i].start == 0)
+   break;
+   imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+   imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+   imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+   imx8m_mem_map[entry].attrs = attrs;
+   debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx8m_mem_map[entry].phys, 
imx8m_mem_map[entry].size);
+   i++; entry++;
+   }
+   }
 
icache_enable();
dcache_enable();
 }
 
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+   if (!size)
+   return -EINVAL;
+
+   *size = PHYS_SDRAM_SIZE;
+   return 0;
+}
+
+int dram_init(void)
+{
+   phys_size_t sdram_size;
+   int ret;
+
+   ret = board_phys_sdram_size(&sdram_size);
+   if (ret)
+   return ret;
+
+   /* rom_pointer[1] contains the size of TEE occupies */
+   if (rom_pointer[1])
+   gd->ram_size = sdram_size - rom_pointer[1];
+   else
+   gd->ram_size = sdram_size;
+
+#ifdef PHYS_SDRAM_2_SIZE
+   gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+
+   return 0;
+}
+
+int dram_init_banksize(void)
+{
+   int bank = 0;
+   int ret;
+   phys_size_t sdram_size;
+
+   ret = board_phys_sdram_size(&sdram_size);
+   if (ret)
+   return ret;
+
+   gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+   if (rom_pointer[1]) {
+   phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+   phys_size_t optee_size = (size_t)rom_pointer[1];
+
+   gd->bd->bi_dram[bank].size = optee_start - 
gd->bd->bi_dram[bank].start;
+   if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+   if (++bank >= CONFIG_NR_DRAM_BANKS) {
+   puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+   return -1;
+   }
+
+   gd->bd->bi_dram[bank].start = optee_start + optee_size;
+   gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+ 

Re: [PATCH] Clean up the Spansion/Cypress/Infineon device ID table

[Jagan Teki]

On Fri, May 22, 2020 at 10:41 PM  wrote:
>
> From: Bacem Daassi 
>
> Signed-off-by: Bacem Daassi 
>
> Clean up the Spansion/Cypress/Infineon device ID table.
>Remove s25fl512s_256k since it's a duplicate of s25fl512s.
>Remove s25fl512s_64k and s25fl512s_512k since these devices do not exist.

Why these removed, what if legacy board usage still exists?

>Rename s25fl128s to s25fl128s1.
>Add the new device s25fl128s0.
>Add device s25fl256l to the device ID table.
> All devices were tested on real silicon and confirmed to be working.
> ---

Please work with a proper commit message.

mtd: spi: Clean up Spansion/Cypress/Infineon ID table

< body >

Signed-off-by: Bacem Daassi 

Re: [PATCH 2/2] spi: add support for all spi modes with soft spi

[Jagan Teki]

On Mon, May 11, 2020 at 6:53 PM Johannes Holland
 wrote:
>
> The spi bitbanging driver did not implement all spi modes properly. Add
> code to support all spi modes, honoring soft_spi_set_mode() and
> defaulting to spi mode 0. Previously, CPHA was implemented inversely
> (defaulting to CPHA=1) and CPOL=1 was hardcoded.
>
> Signed-off-by: Johannes Holland 
> ---

Applied to u-boot-spi/master

Re: [PATCH] mtd: spi-nor: Enable QE bit for ISSI flash in case of SFDP

[Jagan Teki]

On Sun, Jun 21, 2020 at 5:22 PM Pragnesh Patel
 wrote:
>
> Enable QE bit for ISSI flash chips.
>
> QE enablement logic is similar to what Macronix
> has, so reuse the existing code itself.
>
> Signed-off-by: Pragnesh Patel 
> ---

Applied to u-boot-spi/master

Re: [PATCH v2 1/2] pwm: Add DT documentation for SiFive PWM Controller

[Heiko Schocher]

Hello Yash,

Am 23.04.2020 um 13:27 schrieb Yash Shah:

DT documentation for PWM controller added from Linux v5.6

commit: daa78cc3408e
("pwm: sifive: Add DT documentation for SiFive PWM Controller")

Signed-off-by: Yash Shah 
---
  doc/device-tree-bindings/pwm/pwm-sifive.txt | 31 +
  1 file changed, 31 insertions(+)
  create mode 100644 doc/device-tree-bindings/pwm/pwm-sifive.txt


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v2 2/2] pwm: Add PWM driver for SiFive SoC

[Heiko Schocher]

Hello Yash,

Am 23.04.2020 um 13:27 schrieb Yash Shah:

Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC
This driver is simple port of Linux pwm sifive driver from Linux v5.6

commit: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM")

Signed-off-by: Yash Shah 
---
  drivers/pwm/Kconfig  |   6 ++
  drivers/pwm/Makefile |   1 +
  drivers/pwm/pwm-sifive.c | 172 +++
  3 files changed, 179 insertions(+)
  create mode 100644 drivers/pwm/pwm-sifive.c


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v2] i2c: octeon_i2c: Add I2C controller driver for Octeon

[Heiko Schocher]

Hello Stefan,

Am 26.05.2020 um 14:13 schrieb Stefan Roese:

From: Suneel Garapati 

Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.

Signed-off-by: Aaron Williams 
Signed-off-by: Suneel Garapati 
Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Simon Glass 
Cc: Daniel Schwierzeck 
Cc: Aaron Williams 
Cc: Chandrakala Chavva 
---
v2 (Stefan):
- Added clk framework support and dropped ad-hoc clock code
- Removed #ifdef's for Octeon vs OcteonTX/TX2 completely
   The differentiation is now made via driver data / compatible
   string
- Added device-tree bindings documentation
- Removed unused macro

RFC -> v1 (Stefan):
- Separated this patch from the OcteonTX/TX2 RFC patch series into a
   single patch. This is useful, as the upcoming MIPS Octeon support will
   use this I2C driver.
- Added MIPS Octeon II/III support (big endian). Rename driver and its
   function names from "octeontx" to "octeon" to better match all Octeon
   platforms.
- Moved from union to defines / bitmasks as suggested by Simon. This makes
   the driver usage on little- and big-endian platforms much easier.
- Enhanced Kconfig text
- Removed all clock macros (use values from DT)
- Removed long driver debug strings. This is only available when a debug
   version of this driver is built. The user / developer can lookup the
   descriptive error messages in the driver in this case anyway.
- Removed static "last_id"
- Dropped misc blank lines. Misc reformatting.
- Dropped "!= 0"
- Added missing function comments
- Added missing strut comments
- Changed comment style
- Renames "result" to "ret"
- Hex numbers uppercase
- Minor other changes
- Reword commit text and subject

  doc/device-tree-bindings/i2c/octeon-i2c.txt |  24 +
  drivers/i2c/Kconfig |  10 +
  drivers/i2c/Makefile|   1 +
  drivers/i2c/octeon_i2c.c| 847 
  4 files changed, 882 insertions(+)
  create mode 100644 doc/device-tree-bindings/i2c/octeon-i2c.txt
  create mode 100644 drivers/i2c/octeon_i2c.c


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v9 1/2] i2c: i2c-cortina: added CAxxxx I2C support

[Heiko Schocher]

Hello Alex,

Am 01.06.2020 um 21:56 schrieb Alex Nemirovsky:

From: Arthur Li 

Add I2C controller support for Cortina Access CA SoCs

Signed-off-by: Arthur Li 
Signed-off-by: Alex Nemirovsky 
CC: Heiko Schocher 
Reviewed-by: Heiko Schocher 

---

Changes in v9:
- specially include bitops.h and delay.h which
were removed from common.h

Changes in v8:
- No code change
- Split out individual driver from Cortina Package 2 patch series
to help streamline acceptence into master

Changes in v7:
- Added additional description info in I2C KConfig

Changes in v6:
- Add I2C DT binding document

Changes in v4:
- Utilize standard I2C macros from 
- Return ETIMEDOUT in funcs that can timeout
- Return i2c_xfer_init() result to caller of i2c_read() if it
fails within i2c_read() execution
- Fix misc. style guide conformance issues
- Use printf() to report i2c_xfer() runtime errors
instead of debug()

  MAINTAINERS  |   4 +
  doc/device-tree-bindings/i2c/i2c-cortina.txt |  18 ++
  drivers/i2c/Kconfig  |   8 +
  drivers/i2c/Makefile |   1 +
  drivers/i2c/i2c-cortina.c| 346 +++
  drivers/i2c/i2c-cortina.h|  87 +++
  6 files changed, 464 insertions(+)
  create mode 100644 doc/device-tree-bindings/i2c/i2c-cortina.txt
  create mode 100644 drivers/i2c/i2c-cortina.c
  create mode 100644 drivers/i2c/i2c-cortina.h


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v9 2/2] board: presidio-asic: Add I2C support

[Heiko Schocher]

Hello Alex,

Am 01.06.2020 um 21:56 schrieb Alex Nemirovsky:

Add I2C board support for Cortina Access Presidio Engineering Board

Signed-off-by: Alex Nemirovsky 
CC: Heiko Schocher 
Reviewed-by: Heiko Schocher 
---

Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v4: None

  configs/cortina_presidio-asic-emmc_defconfig | 3 +++
  1 file changed, 3 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
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Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH] i2c: imx_lpi2c: Improve the codes to use private data

[Heiko Schocher]

Hello Ye Li,

Am 10.06.2020 um 05:29 schrieb Ye Li:

Current driver calls the devfdt_get_addr to get the base address
of lpi2c controller in each sub-functions. Since the devfdt_get_addr
accesses the DTB and translate the address, it introduces much
overhead.
Improve the codes to use private variable which has recorded the
base address from probe.

Signed-off-by: Ye Li 
Reviewed-by: Peng Fan 
---
  drivers/i2c/imx_lpi2c.c | 22 +++---
  1 file changed, 11 insertions(+), 11 deletions(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko

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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [PATCH 1/1] mvpp2: fix second cp110 initialization

[Stefan Roese]

On 01.07.20 17:43, Sven Auhagen wrote:

Since the mdio code got upstreamed it is not possible
to activate network ports on CP110 Master and Slave.

The problem is in mvpp2_base_probe which is called for each
CP110 and it initializes the buffer area for descs and rx_buffers.

This should only happen once though and the bd space is actually
set to 0 after the first run of the function.

This leads to an error when the second CP110 tries the initialization
again and disables all network ports on this CP110.

This patch adds a static variable to check if the buffer area is
initialized only once globally.

Signed-off-by: Sven Auhagen 


Reviewed-by: Stefan Roese 

Thanks,
Stefan


---
  drivers/net/mvpp2.c | 63 -
  1 file changed, 34 insertions(+), 29 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 19b9375ee2..1296ff9430 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -1263,6 +1263,7 @@ struct buffer_location {
   * can be enabled at once
   */
  static struct buffer_location buffer_loc;
+static int buffer_loc_init;
  
  /*

   * Page table entries are set to 1MB, or multiples of 1MB
@@ -5247,40 +5248,44 @@ static int mvpp2_base_probe(struct udevice *dev)
 * be active. Make this area DMA-safe by disabling the D-cache
 */
  
-	/* Align buffer area for descs and rx_buffers to 1MiB */

-   bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-   mmu_set_region_dcache_behaviour((unsigned long)bd_space,
-   BD_SPACE, DCACHE_OFF);
-
-   buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
-   size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
-
-   buffer_loc.tx_descs =
-   (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
-   size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
+   if (!buffer_loc_init) {
+   /* Align buffer area for descs and rx_buffers to 1MiB */
+   bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+   mmu_set_region_dcache_behaviour((unsigned long)bd_space,
+   BD_SPACE, DCACHE_OFF);
+
+   buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
+   size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
+
+   buffer_loc.tx_descs =
+   (struct mvpp2_tx_desc *)((unsigned long)bd_space + 
size);
+   size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
+
+   buffer_loc.rx_descs =
+   (struct mvpp2_rx_desc *)((unsigned long)bd_space + 
size);
+   size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
+
+   for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
+   buffer_loc.bm_pool[i] =
+   (unsigned long *)((unsigned long)bd_space + 
size);
+   if (priv->hw_version == MVPP21)
+   size += MVPP2_BM_POOL_SIZE_MAX * 2 * 
sizeof(u32);
+   else
+   size += MVPP2_BM_POOL_SIZE_MAX * 2 * 
sizeof(u64);
+   }
  
-	buffer_loc.rx_descs =

-   (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
-   size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
+   for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
+   buffer_loc.rx_buffer[i] =
+   (unsigned long *)((unsigned long)bd_space + 
size);
+   size += RX_BUFFER_SIZE;
+   }
  
-	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {

-   buffer_loc.bm_pool[i] =
-   (unsigned long *)((unsigned long)bd_space + size);
-   if (priv->hw_version == MVPP21)
-   size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
-   else
-   size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
-   }
+   /* Clear the complete area so that all descriptors are cleared 
*/
+   memset(bd_space, 0, size);
  
-	for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {

-   buffer_loc.rx_buffer[i] =
-   (unsigned long *)((unsigned long)bd_space + size);
-   size += RX_BUFFER_SIZE;
+   buffer_loc_init = 1;
}
  
-	/* Clear the complete area so that all descriptors are cleared */

-   memset(bd_space, 0, size);
-
/* Save base addresses for later use */
priv->base = (void *)devfdt_get_addr_index(dev, 0);
if (IS_ERR(priv->base))




Viele Grüße,
Stefan

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Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH 2/3] i2c: stm32f7: add stm32mp15 compatible

[Heiko Schocher]

Hello Patrick,

Am 06.07.2020 um 13:26 schrieb Patrick Delaunay:

Add a new compatible "st,stm32mp15-i2c" introduced in Linux kernel v5.8

Signed-off-by: Patrick Delaunay 
---

  drivers/i2c/stm32f7_i2c.c | 1 +
  1 file changed, 1 insertion(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH] i2c: stm32f7: SYSCFG Fast Mode Plus support for I2C STM32F7

[Heiko Schocher]

Hello Patrick,

Am 06.07.2020 um 13:31 schrieb Patrick Delaunay:

Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus
speed is selected.

Handle the stm32mp15 specific compatible to handle FastMode+
registers handling which is different on the stm32mp15 compared
to the stm32f7 or stm32h7.
Indeed, on the stm32mp15, the FastMode+ set and clear registers
are separated while on the other platforms (F7 or H7) the control
is done in a unique register.

Signed-off-by: Patrick Delaunay 
---

  drivers/i2c/stm32f7_i2c.c | 74 ++-
  1 file changed, 73 insertions(+), 1 deletion(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 01/11] rtc: add dm_rtc_read helper and ->read method

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Some users may want to read multiple consecutive 8-bit
registers. Instead of each caller having to implement the loop,
provide a dm_rtc_read() helper. Also, allow a driver to provide a
->read method, which can be more efficient than reading one register
at a time.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/rtc-uclass.c | 19 +++
  include/rtc.h| 23 +++
  2 files changed, 42 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 02/11] rtc: add dm_rtc_write() helper

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Similar to dm_rtc_read(), introduce a helper that allows the caller to
write multiple consecutive 8-bit registers with one call. If the
driver provides the ->write method, use that, otherwise loop using
->write8.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/rtc-uclass.c | 19 +++
  include/rtc.h| 24 
  2 files changed, 43 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
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Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 03/11] rtc: fall back to ->{read,write} if ->{read,write}8 are not provided

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Similar to how the dm_rtc_{read,write} functions fall back to using
the {read,write}8 methods, do the opposite in the rtc_{read,write}8
functions.

This way, each driver only needs to provide either ->read8 or ->read
to make both rtc_read8() and dm_rtc_read() work - without this, a
driver that provides ->read() would most likely just duplicate the
logic here for implementing a ->read8() method in term of its ->read()
method. The same remarks of course apply to the write case.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/rtc-uclass.c | 25 +++--
  1 file changed, 19 insertions(+), 6 deletions(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 04/11] rtc: pcf2127: provide ->read method

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

This simply consists of renaming the existing pcf2127_read_reg()
helper to follow the naming of the other
methods (i.e. pcf2127_rtc_) and changing the type of its
"len" parameter.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/pcf2127.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 05/11] rtc: pcf2127: provide ->write method

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/pcf2127.c | 7 +++
  1 file changed, 7 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 07/11] rtc: sandbox-rtc: fix set method

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

The current set method is broken; a simple test case is to first set
the date to something in April, then change the date to 31st May:

=> date 040412122020.34
Date: 2020-04-04 (Saturday)Time: 12:12:34
=> date 053112122020.34
Date: 2020-05-01 (Friday)Time: 12:12:34

or via the amending of the existing rtc_set_get test case similarly:

$ ./u-boot -T -v
=> ut dm rtc_set_get
Test: dm_test_rtc_set_get: rtc.c
expected: 31/08/2004 18:18:00
actual: 01/08/2004 18:18:00

The problem is that after each register write,
sandbox_i2c_rtc_complete_write() gets called and sets the internal
time from the current set of registers. However, when we get to
writing 31 to mday, the registers are in an inconsistent state (mon is
still 4), so the mktime machinery ends up translating April 31st to
May 1st. Upon the next register write, the registers are populated by
sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets
overwritten by a 1.

Fix it by writing all registers at once, and for consistency, update
the get method to retrieve them all with one "i2c transfer".

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/sandbox_rtc.c | 65 +++
  test/dm/rtc.c | 15 -
  2 files changed, 38 insertions(+), 42 deletions(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
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Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 06/11] rtc: add rtc command

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Mostly as an aid for debugging RTC drivers, provide a command that can
be used to read/write arbitrary registers (assuming the driver
provides the read/write methods or their single-register-at-a-time
variants).

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  cmd/Kconfig  |   6 ++
  cmd/Makefile |   1 +
  cmd/rtc.c| 167 +++
  3 files changed, 174 insertions(+)
  create mode 100644 cmd/rtc.c


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 10/11] sandbox: add rtc command to defconfigs

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

In order to allow adding unit tests of the rtc command, add it to the
various sandbox defconfigs.

Signed-off-by: Rasmus Villemoes 
---
  configs/sandbox64_defconfig| 1 +
  configs/sandbox_defconfig  | 1 +
  configs/sandbox_flattree_defconfig | 1 +
  3 files changed, 3 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
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Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 09/11] test: dm: rtc: add test of dm_rtc_read, dm_rtc_write

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Define a few aux registers and check that they can be read/written
individually. Also check that one can access the time-keeping
registers directly and get the expected results.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  arch/sandbox/include/asm/rtc.h |  5 
  test/dm/rtc.c  | 45 ++
  2 files changed, 50 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 08/11] rtc: i2c_rtc_emul: catch any write to the "reset" register

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

It's more natural that any write that happens to touch the reset
register should cause a reset, rather than just a write that starts at
that offset.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  drivers/rtc/i2c_rtc_emul.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH v4 11/11] test: dm: rtc: add tests of rtc shell command

[Heiko Schocher]

Hello Rasmus,

Am 06.07.2020 um 22:01 schrieb Rasmus Villemoes:

Add tests of the "list", "read" and "write" subcommands of the rtc
shell command.

Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Signed-off-by: Rasmus Villemoes 
---
  test/dm/rtc.c | 58 +++
  1 file changed, 58 insertions(+)


Applied to u-boot-i2c.git master

Thanks!

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

[U-Boot] Please pull from u-boot-i2c

[Heiko Schocher]

Hello Tom,

please pull from u-boot-i2c master

The following changes since commit 61608f395e7dcb2be6060407a72a1149b046430a:

  Merge branch '2020-07-08-misc-features-and-fixes' (2020-07-08 20:20:24 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git tags/for-v2020.10

for you to fetch changes up to 7239a610b796b0bb8f85c5c21798596c2768cb50:

  pwm: Add PWM driver for SiFive SoC (2020-07-09 06:03:12 +0200)


i2c changes for v2020.10
- Add support for I2C controllers found on Octeon II/III and Octeon TX
  TX2 SoC platforms.
- Add I2C controller support for Cortina Access CA SoCs
- new rtc methods, rtc command, and tests
- imx_lpi2c: Improve the codes to use private data
- stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c"
- stm32f7_i2c.c: Add Fast Mode Plus support
- pwm: Add PWM driver for SiFive SoC


Alex Nemirovsky (1):
  board: presidio-asic: Add I2C support

Arthur Li (1):
  i2c: i2c-cortina: added CA I2C support

Patrick Delaunay (2):
  i2c: stm32f7: add stm32mp15 compatible
  i2c: stm32f7: SYSCFG Fast Mode Plus support for I2C STM32F7

Rasmus Villemoes (11):
  rtc: add dm_rtc_read helper and ->read method
  rtc: add dm_rtc_write() helper
  rtc: fall back to ->{read, write} if ->{read, write}8 are not provided
  rtc: pcf2127: provide ->read method
  rtc: pcf2127: provide ->write method
  rtc: add rtc command
  rtc: sandbox-rtc: fix set method
  rtc: i2c_rtc_emul: catch any write to the "reset" register
  test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
  sandbox: add rtc command to defconfigs
  test: dm: rtc: add tests of rtc shell command

Suneel Garapati (1):
  i2c: octeon_i2c: Add I2C controller driver for Octeon

Yash Shah (2):
  pwm: Add DT documentation for SiFive PWM Controller
  pwm: Add PWM driver for SiFive SoC

Ye Li (1):
  i2c: imx_lpi2c: Improve the codes to use private data

 MAINTAINERS  |   4 +
 arch/sandbox/include/asm/rtc.h   |   5 +
 cmd/Kconfig  |   6 +
 cmd/Makefile |   1 +
 cmd/rtc.c| 167 +++
 configs/cortina_presidio-asic-emmc_defconfig |   3 +
 configs/sandbox64_defconfig  |   1 +
 configs/sandbox_defconfig|   1 +
 configs/sandbox_flattree_defconfig   |   1 +
 doc/device-tree-bindings/i2c/i2c-cortina.txt |  18 +++
 doc/device-tree-bindings/i2c/octeon-i2c.txt  |  24 
 doc/device-tree-bindings/pwm/pwm-sifive.txt  |  31 +
 drivers/i2c/Kconfig  |  18 +++
 drivers/i2c/Makefile |   2 +
 drivers/i2c/i2c-cortina.c| 347 

 drivers/i2c/i2c-cortina.h|  87 
 drivers/i2c/imx_lpi2c.c  |  22 ++--
 drivers/i2c/octeon_i2c.c | 847 
+

 drivers/i2c/stm32f7_i2c.c|  73 ++
 drivers/pwm/Kconfig  |   6 +
 drivers/pwm/Makefile |   1 +
 drivers/pwm/pwm-sifive.c | 172 
 drivers/rtc/i2c_rtc_emul.c   |   3 +-
 drivers/rtc/pcf2127.c|  13 +-
 drivers/rtc/rtc-uclass.c |  59 -
 drivers/rtc/sandbox_rtc.c|  65 -
 include/rtc.h|  47 +++
 test/dm/rtc.c| 118 -
 28 files changed, 2081 insertions(+), 61 deletions(-)
 create mode 100644 cmd/rtc.c
 create mode 100644 doc/device-tree-bindings/i2c/i2c-cortina.txt
 create mode 100644 doc/device-tree-bindings/i2c/octeon-i2c.txt
 create mode 100644 doc/device-tree-bindings/pwm/pwm-sifive.txt
 create mode 100644 drivers/i2c/i2c-cortina.c
 create mode 100644 drivers/i2c/i2c-cortina.h
 create mode 100644 drivers/i2c/octeon_i2c.c
 create mode 100644 drivers/pwm/pwm-sifive.c

travis build:

https://travis-ci.org/github/hsdenx/u-boot-i2c/builds/706396477

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Please pull u-boot-marvell/master

[Stefan Roese]

Hi Tom,

please pull these MVEBU related patches:


- Armada 38x DDR3 fixes, enhancements (Chris)
- Armada 38x UTMI PHY SerDes fix (Chris)
- Helios4 update - sync with clearfog (Dennis)
- LaCie Kirkwood board rework - enable DM (Simon)
- net/mvpp2 memory init fix (Sven)


Here the Azure build, without any issues:

https://dev.azure.com/sr0718/u-boot/_build/results?buildId=10&view=results

Thanks,
Stefan

The following changes since commit 61608f395e7dcb2be6060407a72a1149b046430a:

  Merge branch '2020-07-08-misc-features-and-fixes' (2020-07-08 
20:20:24 -0400)


are available in the Git repository at:

  g...@gitlab.denx.de:u-boot/custodians/u-boot-marvell.git

for you to fetch changes up to 3078e03516934c016ef3ea15f8bce19df3948dfe:

  net: mvpp2: fix second cp110 initialization (2020-07-09 06:52:20 +0200)


Chris Packham (4):
  mv_ddr: ddr3: Use correct bitmask for read sample delay
  mv_ddr: ddr3: Update {min,max}_read_sample calculation
  arm: mvebu: a38x: Fix typo
  arm: mvebu: a38x: Adjust UTMI PHY parameters

Dennis Gilmore (1):
  arm: mvebu: helios4: sync helios4 config to clearfog and dts to 
kernel


Simon Guinot (5):
  arm: kirkwood: add DT spi0 alias to LaCie boards
  arm: kirkwood: convert LaCie boards to DM_SPI_FLASH
  arm: kirkwood: switch LaCie boards to sata_mv driver
  arm: kirkwood: enable DM_USB for LaCie board
  arm: kirkwood: enable DM_ETH for LaCie board

Sven Auhagen (1):
  net: mvpp2: fix second cp110 initialization

 arch/arm/dts/armada-388-helios4-u-boot.dtsi| 15 
 arch/arm/dts/armada-388-helios4.dts| 16 ++--
 arch/arm/dts/kirkwood-d2net-u-boot.dtsi|  7 ++
 arch/arm/dts/kirkwood-is2-u-boot.dtsi  |  7 ++
 arch/arm/dts/kirkwood-net2big-u-boot.dtsi  |  7 ++
 arch/arm/dts/kirkwood-ns2-u-boot.dtsi  |  7 ++
 arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi  |  7 ++
 arch/arm/dts/kirkwood-ns2max-u-boot.dtsi   |  7 ++
 arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi  |  7 ++
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.c   | 27 --
 board/LaCie/net2big_v2/MAINTAINERS |  6 ++
 board/LaCie/net2big_v2/net2big_v2.c|  2 +-
 board/LaCie/netspace_v2/MAINTAINERS| 21 +++--
 board/LaCie/netspace_v2/netspace_v2.c  |  4 +-
 configs/d2net_v2_defconfig | 13 ++-
 configs/helios4_defconfig  | 20 +++--
 configs/inetspace_v2_defconfig | 13 ++-
 configs/net2big_v2_defconfig   | 13 ++-
 configs/netspace_lite_v2_defconfig | 14 +++-
 configs/netspace_max_v2_defconfig  | 14 +++-
 configs/netspace_mini_v2_defconfig | 12 ++-
 configs/netspace_v2_defconfig  | 13 ++-
 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c   |  6 +-
 drivers/net/mvpp2.c| 63 +++---
 include/configs/helios4.h  | 95 
+-

 include/configs/lacie_kw.h | 19 ++---
 26 files changed, 297 insertions(+), 138 deletions(-)
 create mode 100644 arch/arm/dts/kirkwood-d2net-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-is2-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-net2big-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-ns2-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-ns2max-u-boot.dtsi
 create mode 100644 arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi

Re: [PATCH v8 1/2] spi: ca_sflash: Add CAxxxx SPI Flash Controller

[Jagan Teki]

On Tue, Jun 2, 2020 at 1:45 AM Alex Nemirovsky
 wrote:
>
>
>
> > On Jun 1, 2020, at 9:45 AM, Jagan Teki  wrote:
> >
> > On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky
> >  wrote:
> >>
> >> From: Pengpeng Chen 
> >>
> >> Add SPI Flash controller driver for Cortina Access
> >> CA SoCs
> >>
> >> Signed-off-by: Pengpeng Chen 
> >> Signed-off-by: Alex Nemirovsky 
> >> CC: Jagan Teki 
> >> CC: Vignesh R 
> >> CC: Tom Rini 
> >>
> >> ---
> >>
> >> Changes in v8:
> >> - No code change
> >> - Split out individual driver from Cortina Package 2 patch series
> >> to help streamline acceptence into master
> >>
> >> Changes in v7:
> >> - Replace substring "OPCODE" with "OP" in MACROs to help
> >> reduce code line lengths
> >> - Replace substring "_MASK" with "_MSK" in MACROs to help
> >> reduce code line lengths
> >>
> >> Changes in v5: None
> >> Changes in v3:
> >> - Fixup syntax issues related to checkpatch.pl cleanup
> >>
> >> MAINTAINERS |   8 +
> >> drivers/spi/Kconfig |   8 +
> >> drivers/spi/Makefile|   1 +
> >> drivers/spi/ca_sflash.c | 576 
> >> 
> >> 4 files changed, 593 insertions(+)
> >> create mode 100644 drivers/spi/ca_sflash.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 8add9d4..57ce45e 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -181,6 +181,10 @@ F: drivers/gpio/cortina_gpio.c
> >> F: drivers/watchdog/cortina_wdt.c
> >> F: drivers/serial/serial_cortina.c
> >> F: drivers/mmc/ca_dw_mmc.c
> >> +F: drivers/i2c/i2c-cortina.c
> >> +F: drivers/i2c/i2c-cortina.h
> >> +F: drivers/led/led_cortina.c
> >> +F: drivers/spi/ca_sflash.c
> >>
> >> ARM/CZ.NIC TURRIS MOX SUPPORT
> >> M: Marek Behun 
> >> @@ -732,6 +736,10 @@ F: drivers/gpio/cortina_gpio.c
> >> F: drivers/watchdog/cortina_wdt.c
> >> F: drivers/serial/serial_cortina.c
> >> F: drivers/mmc/ca_dw_mmc.c
> >> +F: drivers/i2c/i2c-cortina.c
> >> +F: drivers/i2c/i2c-cortina.h
> >> +F: drivers/led/led_cortina.c
> >
> > These changes are unrelated to SPI, keep out of this patch.
>
> will be corrected in v9
> >
> >> +F: drivers/spi/ca_sflash.c
> >>
> >> MIPS MSCC
> >> M: Gregory CLEMENT 
> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> index dccd5ea..09f2a2a 100644
> >> --- a/drivers/spi/Kconfig
> >> +++ b/drivers/spi/Kconfig
> >> @@ -106,6 +106,14 @@ config BCMSTB_SPI
> >>  be used to access the SPI flash on platforms embedding this
> >>  Broadcom SPI core.
> >>
> >> +config CORTINA_SFLASH
> >> +   bool "Cortina-Access Serial Flash controller driver"
> >> +   depends on DM_SPI && SPI_MEM
> >> +   help
> >> + Enable the Cortina-Access Serial Flash controller driver. This 
> >> driver
> >> + can be used to access the SPI NOR/NAND flash on platforms 
> >> embedding this
> >> + Cortina-Access IP core.
> >> +
> >> config CADENCE_QSPI
> >>bool "Cadence QSPI driver"
> >>help
> >> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> >> index 6441694..5e53f11 100644
> >> --- a/drivers/spi/Makefile
> >> +++ b/drivers/spi/Makefile
> >> @@ -25,6 +25,7 @@ obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
> >> obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
> >> obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
> >> obj-$(CONFIG_CF_SPI) += cf_spi.o
> >> +obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
> >> obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> >> obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
> >> obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
> >> diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c
> >> new file mode 100644
> >> index 000..00af6bf
> >> --- /dev/null
> >> +++ b/drivers/spi/ca_sflash.c
> >> @@ -0,0 +1,576 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Driver for Cortina SPI-FLASH Controller
> >> + *
> >> + * Copyright (C) 2020 Cortina Access Inc. All Rights Reserved.
> >> + *
> >> + * Author: PengPeng Chen 
> >> + */
> >> +
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +struct ca_sflash_regs {
> >> +   u32 idr;/* 0x00:Flash word ID Register */
> >> +   u32 tc; /* 0x04:Flash Timeout Counter Register */
> >> +   u32 sr; /* 0x08:Flash Status Register */
> >> +   u32 tr; /* 0x0C:Flash Type Register */
> >> +   u32 asr;/* 0x10:Flash ACCESS START/BUSY Register */
> >> +   u32 isr;/* 0x14:Flash Interrupt Status Register */
> >> +   u32 imr;/* 0x18:Flash Interrupt Mask Register */
> >> +   u32 fcr;/* 0x1C:NAND Flash FIFO Control Register */
> >> +   u32 ffsr;   /* 0x20:Flash FIFO Status Regis

[PATCH] arm: dts: lx2160a: Increase configuration window size

[Wasim Khan]

lx2160a rev2 requires 4KB space for type0 and 4KB
space for type1 iATU window. Increase configuration
size to 8KB to have sufficient space for type0
and type1 window.

Signed-off-by: Wasim Khan 
---
 arch/arm/dts/fsl-lx2160a.dtsi | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 1789da8..c62960e 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -284,7 +284,7 @@
reg = <0x00 0x0340 0x0 0x8   /* PAB registers */
   0x00 0x0348 0x0 0x4   /* LUT registers */
   0x00 0x034c 0x0 0x4   /* PF control registers */
-  0x80 0x 0x0 0x1000>; /* configuration space */
+  0x80 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@@ -298,7 +298,7 @@
reg = <0x00 0x0350 0x0 0x8   /* PAB registers */
   0x00 0x0358 0x0 0x4   /* LUT registers */
   0x00 0x035c 0x0 0x4   /* PF control registers */
-  0x88 0x 0x0 0x1000>; /* configuration space */
+  0x88 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@@ -313,7 +313,7 @@
reg = <0x00 0x0360 0x0 0x8   /* PAB registers */
   0x00 0x0368 0x0 0x4   /* LUT registers */
   0x00 0x036c 0x0 0x4   /* PF control registers */
-  0x90 0x 0x0 0x1000>; /* configuration space */
+  0x90 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@@ -327,7 +327,7 @@
reg = <0x00 0x0370 0x0 0x8   /* PAB registers */
   0x00 0x0378 0x0 0x4   /* LUT registers */
   0x00 0x037c 0x0 0x4   /* PF control registers */
-  0x98 0x 0x0 0x1000>; /* configuration space */
+  0x98 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@@ -341,7 +341,7 @@
reg = <0x00 0x0380 0x0 0x8   /* PAB registers */
   0x00 0x0388 0x0 0x4   /* LUT registers */
   0x00 0x038c 0x0 0x4   /* PF control registers */
-  0xa0 0x 0x0 0x1000>; /* configuration space */
+  0xa0 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@@ -355,7 +355,7 @@
reg = <0x00 0x0390 0x0 0x8   /* PAB registers */
   0x00 0x0398 0x0 0x4   /* LUT registers */
   0x00 0x039c 0x0 0x4   /* PF control registers */
-  0xa8 0x 0x0 0x1000>; /* configuration space */
+  0xa8 0x 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
-- 
2.7.4

Re: [PATCH 05/10] board_f: mips: Factor out mips-specific bdinfo setup

[Heinrich Schuchardt]

On 09.07.20 10:04, Ovidiu Panait wrote:
> Factor out mips-specific bdinfo setup from generic init sequence to
> arch_setup_bdinfo in arch/mips/lib/boot.c.
>
> Signed-off-by: Ovidiu Panait 
> ---
>
>  arch/mips/lib/boot.c | 18 ++
>  common/board_f.c | 25 +
>  2 files changed, 19 insertions(+), 24 deletions(-)
>
> diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
> index db862f6379..b3a48ce10f 100644
> --- a/arch/mips/lib/boot.c
> +++ b/arch/mips/lib/boot.c
> @@ -9,6 +9,24 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +int arch_setup_bdinfo(void)
> +{
> + bd_t *bd = gd->bd;
> +
> + /*
> +  * Save local variables to board info struct
> +  */
> + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
> + bd->bi_memsize = gd->ram_size;  /* size in bytes */
> +
> +#ifdef CONFIG_SYS_SRAM_BASE

We want to get rid of #ifdef where possible. So it is preferable to write:

if IS_ENABLED(CONFIG_SYS_SRAM_BASE) {

One benefit is that static code analysis will consider the code.

Best regards

Heinrich

> + bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
> + bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
> +#endif
> +
> + return 0;
> +}
> +
>  unsigned long do_go_exec(ulong (*entry)(int, char * const []),
>int argc, char * const argv[])
>  {
> diff --git a/common/board_f.c b/common/board_f.c
> index 9bfcd6b236..fd7e6a17ad 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -602,26 +602,6 @@ __weak int arch_setup_bdinfo(void)
>   return 0;
>  }
>
> -#if defined(CONFIG_MIPS)
> -static int setup_board_part1(void)
> -{
> - bd_t *bd = gd->bd;
> -
> - /*
> -  * Save local variables to board info struct
> -  */
> - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
> - bd->bi_memsize = gd->ram_size;  /* size in bytes */
> -
> -#ifdef CONFIG_SYS_SRAM_BASE
> - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
> - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
>  #ifdef CONFIG_POST
>  static int init_post(void)
>  {
> @@ -942,11 +922,8 @@ static const init_fnc_t init_sequence_f[] = {
>   reserve_stacks,
>   dram_init_banksize,
>   show_dram_config,
> - arch_setup_bdinfo,
> -#if defined(CONFIG_MIPS)
> - setup_board_part1,
>   INIT_FUNC_WATCHDOG_RESET
> -#endif
> + arch_setup_bdinfo,
>   display_new_sp,
>  #ifdef CONFIG_OF_BOARD_FIXUP
>   fix_fdt,
>

Please pull u-boot-x86

[Bin Meng]

Hi Tom,

This PR includes the following changes for U-Boot v2020.10:

- Add two- and three-argument versions of CONFIG_IS_ENABLED in linux/kconfig.h
- Adds a new feature which supports copying modified parts of
the frame buffer to the uncached hardware buffer
- Enable the copy framebuffer on various x86 targets

Azure pipeline results: PASS
https://dev.azure.com/bmeng/GitHub/_build/results?buildId=253&view=results

The following changes since commit 61608f395e7dcb2be6060407a72a1149b046430a:

  Merge branch '2020-07-08-misc-features-and-fixes' (2020-07-08 20:20:24 -0400)

are available in the git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-x86

for you to fetch changes up to db17e40ccab6526a9db6ffdd071182a37dd888eb:

  x86: apl: Re-enable loading of SPL (2020-07-09 12:33:24 +0800)


Bin Meng (1):
  arm: cmd_stm32prog: Fix the CONFIG_IS_ENABLED() usage

Rasmus Villemoes (3):
  linux/kconfig.h: simplify logic for choosing CONFIG_{SPL_, TPL_, }*
  linux/kconfig.h: remove unused helper macros
  linux/kconfig.h: create two- and three-argument versions of
CONFIG_IS_ENABLED

Simon Glass (29):
  x86: fsp: Reinit the FPU after FSP meminit
  console: Add a way to output to serial only
  video: Show an error when a vidconsole function fails
  sandbox: video: Allow selection of rotated console
  video: Split out expression parts into variables
  video: Adjust rotated console to start at right edge
  video: Drop unnecessary #ifdef around vid_console_color()
  video: Add a comment for struct video_uc_platdata
  video: Add support for copying to a hardware framebuffer
  video: Set up the copy framebuffer when enabled
  video: Clear the copy framebuffer when clearing the screen
  video: Add helpers for vidconsole for the copy framebuffer
  video: Update normal console to support copy buffer
  video: Update truetype console to support copy buffer
  video: Update rotated console to support copy buffer
  video: Update the copy framebuffer when writing bitmaps
  video: Add comments to struct sandbox_sdl_plat
  video: sandbox: Add support for the copy framebuffer
  video: pci: Set up the copy framebuffer
  x86: fsp: video: Allocate a frame buffer when needed
  video: Correctly handle multiple framebuffers
  x86: video: Support copy framebuffer with probed devices
  chromebook_samus: Enable the copy framebuffer
  chromebook_link: Enable the copy framebuffer
  minnowmax: Enable the copy framebuffer
  x86: minnowmax: Drop screen resolution to 1024x768
  bootstage: Fix 'stacked' typo
  spi: Remove unnecessary #ifdefs in header file
  x86: apl: Re-enable loading of SPL

 arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c |   2 +-
 arch/x86/cpu/apollolake/Makefile|   2 +-
 arch/x86/cpu/i386/cpu.c |   5 +
 arch/x86/include/asm/u-boot-x86.h   |   8 
 arch/x86/lib/fsp/fsp_graphics.c |  12 
 arch/x86/lib/fsp2/fsp_meminit.c |   1 +
 common/console.c|  28
++--
 configs/chromebook_link_defconfig   |   2 +-
 configs/chromebook_samus_defconfig  |   2 +-
 configs/minnowmax_defconfig |   4 ++--
 configs/sandbox_defconfig   |   1 +
 drivers/pci/pci_rom.c   |  22
+-
 drivers/video/Kconfig   |  31
+++
 drivers/video/broadwell_igd.c   |  16 +++-
 drivers/video/console_normal.c  |  26
+++---
 drivers/video/console_rotate.c  | 103
++-
 drivers/video/console_truetype.c|  43
+++
 drivers/video/ivybridge_igd.c   |  26
--
 drivers/video/sandbox_sdl.c |  10 +-
 drivers/video/vesa.c|  30
+-
 drivers/video/vidconsole-uclass.c   |  38
+++---
 drivers/video/video-uclass.c|  93
+++--
 drivers/video/video_bmp.c   |  16 +---
 include/bootstage.h |   2 +-
 include/console.h   |  13 +
 include/dm/test.h   |  14 +-
 include/linux/kconfig.h | 103
++

Re: [PATCH 05/10] board_f: mips: Factor out mips-specific bdinfo setup

[Ovidiu Panait]

Hi,

On 09.07.2020 12:15, Heinrich Schuchardt wrote:

On 09.07.20 10:04, Ovidiu Panait wrote:

Factor out mips-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/mips/lib/boot.c.

Signed-off-by: Ovidiu Panait 
---

  arch/mips/lib/boot.c | 18 ++
  common/board_f.c | 25 +
  2 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6379..b3a48ce10f 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -9,6 +9,24 @@

  DECLARE_GLOBAL_DATA_PTR;

+int arch_setup_bdinfo(void)
+{
+   bd_t *bd = gd->bd;
+
+   /*
+* Save local variables to board info struct
+*/
+   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
+   bd->bi_memsize = gd->ram_size;/* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE

We want to get rid of #ifdef where possible. So it is preferable to write:

if IS_ENABLED(CONFIG_SYS_SRAM_BASE) {

One benefit is that static code analysis will consider the code.

Best regards

Heinrich


My understanding is that IS_ENABLED() only works with with boolean and 
tristate options.


In this case, CONFIG_SYS_SRAM_BASE is a hex value:

include/configs/pic32mzdask.h:22:#define CONFIG_SYS_SRAM_BASE     0x8000


Switching to IS_ENABLED() produces the following build errors for qemu mips:

$ git diff
diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index b3a48ce10f..aa047335ec 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -19,10 +19,10 @@ int arch_setup_bdinfo(void)
    bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;    /* start of 
memory */

    bd->bi_memsize = gd->ram_size;  /* size in bytes */

-#ifdef CONFIG_SYS_SRAM_BASE
-   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;    /* start of SRAM */
-   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
-#endif
+   if (IS_ENABLED(CONFIG_SYS_SRAM_BASE)) {
+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
+   }

    return 0;
 }

$ make

...

arch/mips/lib/boot.c: In function 'arch_setup_bdinfo':
  CC  common/init/board_init.o
arch/mips/lib/boot.c:23:22: error: 'CONFIG_SYS_SRAM_BASE' undeclared 
(first use in this function); did you mean 'CONFIG_SYS_SDRAM_BASE'?

   23 |   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  |  ^~~~
  |  CONFIG_SYS_SDRAM_BASE
arch/mips/lib/boot.c:23:22: note: each undeclared identifier is reported 
only once for each function it appears in
arch/mips/lib/boot.c:24:21: error: 'CONFIG_SYS_SRAM_SIZE' undeclared 
(first use in this function); did you mean 'CONFIG_SYS_SDRAM_BASE'?

   24 |   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
  | ^~~~
  | CONFIG_SYS_SDRAM_BASE

Thanks,

Ovidiu


+   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
+#endif
+
+   return 0;
+}
+
  unsigned long do_go_exec(ulong (*entry)(int, char * const []),
 int argc, char * const argv[])
  {
diff --git a/common/board_f.c b/common/board_f.c
index 9bfcd6b236..fd7e6a17ad 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -602,26 +602,6 @@ __weak int arch_setup_bdinfo(void)
return 0;
  }

-#if defined(CONFIG_MIPS)
-static int setup_board_part1(void)
-{
-   bd_t *bd = gd->bd;
-
-   /*
-* Save local variables to board info struct
-*/
-   bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
-   bd->bi_memsize = gd->ram_size;/* size in bytes */
-
-#ifdef CONFIG_SYS_SRAM_BASE
-   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
-   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
-#endif
-
-   return 0;
-}
-#endif
-
  #ifdef CONFIG_POST
  static int init_post(void)
  {
@@ -942,11 +922,8 @@ static const init_fnc_t init_sequence_f[] = {
reserve_stacks,
dram_init_banksize,
show_dram_config,
-   arch_setup_bdinfo,
-#if defined(CONFIG_MIPS)
-   setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
-#endif
+   arch_setup_bdinfo,
display_new_sp,
  #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,

[PATCH] rtc: pcf2127: fix uninitialized variable msg

[Biwen Li]

From: Biwen Li 

Fix uninitialized variable msg

Signed-off-by: Biwen Li 
---
 drivers/rtc/pcf2127.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index f695350..58c4ee9 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2016 by NXP Semiconductors Inc.
  * Date & Time support for PCF2127 RTC
+ * Copyright 2020 NXP
  */
 
 /* #define DEBUG   */
@@ -26,7 +27,7 @@ static int pcf2127_read_reg(struct udevice *dev, uint offset,
u8 *buffer, int len)
 {
struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
-   struct i2c_msg msg;
+   struct i2c_msg msg = {0};
int ret;
 
/* Set the address of the start register to be read */
-- 
2.7.4

[PATCH] bcmgenet: fix DMA buffer management

[etienne . duble]

From: Etienne Dublé 

This commit fixes a serious issue occuring when several network
commands are run on a raspberry pi 4 board: for instance a "dhcp"
command and then one or several "tftp" commands. In this case,
packet recv callbacks were called several times on the same packets,
and send function was failing most of the time.

note: if the boot procedure is made of a single network
command, the issue is not visible.

The issue is related to management of the packet ring buffers
(producer / consumer) and DMA.
Each time a packet is received, the ethernet device stores it
in the buffer and increments an index called RDMA_PROD_INDEX.
Each time the driver outputs a received packet, it increments
another index called RDMA_CONS_INDEX.

Between each pair of network commands, as part of the driver
'start' function, previous code tried to reset both RDMA_CONS_INDEX
and RDMA_PROD_INDEX to 0. But RDMA_PROD_INDEX cannot be written from
driver side, thus its value was actually not updated, and only
RDMA_CONS_INDEX was reset to 0. This was resulting in a major
synchronization issue between the driver and the device. Most
visible bahavior was that the driver seemed to receive again the
packets from the previous commands (e.g. DHCP response packets
"received" again when performing the first TFTP command).

This fix consists in setting RDMA_CONS_INDEX to the same
value as RDMA_PROD_INDEX, when resetting the driver.

The same kind of fix was needed on the TX side, and a few variables
had to be reset accordingly (c_index, tx_index, rx_index).
---
 drivers/net/bcmgenet.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
index 11b6148ab6..a4facfd63f 100644
--- a/drivers/net/bcmgenet.c
+++ b/drivers/net/bcmgenet.c
@@ -378,8 +378,6 @@ static void rx_descs_init(struct bcmgenet_eth_priv *priv)
u32 len_stat, i;
void *desc_base = priv->rx_desc_base;
 
-   priv->c_index = 0;
-
len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
 
for (i = 0; i < RX_DESCS; i++) {
@@ -403,8 +401,10 @@ static void rx_ring_init(struct bcmgenet_eth_priv *priv)
writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
   priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
 
-   writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
-   writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
+   /* cannot init RDMA_PROD_INDEX to 0, so align RDMA_CONS_INDEX on it 
instead */
+   priv->c_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
+   writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
+   priv->rx_index = priv->c_index;
writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
   priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
@@ -421,8 +421,9 @@ static void tx_ring_init(struct bcmgenet_eth_priv *priv)
writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
   priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
-   writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
-   writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
+   /* cannot init TDMA_CONS_INDEX to 0, so align TDMA_PROD_INDEX on it 
instead */
+   priv->tx_index = readl(priv->mac_reg + TDMA_CONS_INDEX);
+   writel(priv->tx_index, priv->mac_reg + TDMA_PROD_INDEX);
writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
@@ -469,8 +470,6 @@ static int bcmgenet_gmac_eth_start(struct udevice *dev)
 
priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
-   priv->tx_index = 0x0;
-   priv->rx_index = 0x0;
 
bcmgenet_umac_reset(priv);
 
-- 
2.17.1

fs:fat: Fix small file read error

[zzp blizzard]

get_cluster()  disk_read idx eque zero while size < mydata->sect_size.


fix_fs_fat_read_small_file_fail.patch
Description: Binary data

[PATCH 0/5] mtd: Implement MTD UCLASS (use SPINOR)

[Jagan Teki]

This was few years backlog work of mine, and it's been 
blocked to various reasons of having a priority to sync 
Linux MTD spinor code and most of the community developers 
are interested in feature-based Linux MTD sync/copy than 
full functional MTD driver model.

As years passing on to the driver model support the actual 
migration still seems a myth. So, let us not wait for too 
long to implement the basic driver model structure to MTD.

So, this series implement the MTD driver model in a fully
functional way with all possible dm_mtd ops and necessary 
API to use SPINOR.

absolute spinor flow:
sf.c => sf uclass => sf driver => spi-nor-core
- flash operations via dm_spi_flash_ops

updated spinor flow:
sf.c => mtd uclass => mtd driver => spi-nor-core
- flash operations via mtd_ops (dm variant)

Future work:
- cleanup of spi_flash with spinor
- renaming of CONFIG option changes
- implement common mtd probe
- implement mtd flash interface types so that the respective
  commands like sf, mtd can make use of dm-mtd in the proper way.

Tested on real target with SPINOR test, and Boot.

Repo available at:
https://gitlab.denx.de/u-boot/custodians/u-boot-spi/-/tree/mtd

Any inputs?
Jagan.

Jagan Teki (5):
  mtd: spi: Drop redundent SPI flash driver
  mtd: Add dm-mtd core ops
  mtd: Add SPL_DM_MTD option
  mtd: Build mtd-uclass as obj
  mtd: spi: Switch to MTD uclass (absolute UCLASS_SPI_FLASH)

 arch/arm/mach-rockchip/spl-boot-order.c |   4 +-
 arch/x86/cpu/apollolake/spl.c   |  68 +---
 arch/x86/lib/fsp2/fsp_init.c|   2 +-
 arch/x86/lib/fsp2/fsp_support.c |   7 +-
 arch/x86/lib/mrccache.c |   8 +-
 board/atmel/common/mac-spi-nor.c|   4 +-
 drivers/mtd/Kconfig |   8 ++
 drivers/mtd/Makefile|   4 +-
 drivers/mtd/mtd-uclass.c|  38 +++
 drivers/mtd/spi/Kconfig |   2 +
 drivers/mtd/spi/sandbox.c   |   2 +-
 drivers/mtd/spi/sf-uclass.c | 135 ++--
 drivers/mtd/spi/sf_dataflash.c  |  25 +++--
 include/dm/uclass-id.h  |   1 -
 include/mtd.h   |  41 +++
 include/spi_flash.h |  65 +---
 test/dm/sf.c|  12 +--
 17 files changed, 189 insertions(+), 237 deletions(-)

-- 
2.25.1

[PATCH 1/5] mtd: spi: Drop redundent SPI flash driver

[Jagan Teki]

UCLASS_SPI_FLASH driver at driver/mtd/spi is a generic
spi flash driver to probe jedec,spi-nor flash chips.

Technically a probe call in U_BOOT_DRIVER is local to that
driver and not applicable to use it another driver or in
another code.

The apollolake SPL code using the generic probe by adding
extra SPI flash driver, which make more confusion in terms
of code readability and driver model structure.

The fact that apollolake SPL requires a separate SPI flash
driver to handle of-platdata via bind call, so move the
bind call in the generic flash driver and drop the driver
from apollolake code.

I hope this wouldn't break generic code usage flash chips
otherwise, we can handle this via driver data or a separate
spi driver in drivers/mtd/spi.

Cc: Bin Meng 
Cc: Simon Glass 
Cc: Vignesh R 
Signed-off-by: Jagan Teki 
---
 arch/x86/cpu/apollolake/spl.c | 60 ---
 drivers/mtd/spi/sf-uclass.c   | 29 -
 include/spi_flash.h   | 12 ---
 3 files changed, 28 insertions(+), 73 deletions(-)

diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index 5a53831dc6..e1ee1e0624 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -68,66 +68,6 @@ SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, 
rom_load_image);
 
 #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
 
-static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
- void *buf)
-{
-   struct spi_flash *flash = dev_get_uclass_priv(dev);
-   struct mtd_info *mtd = &flash->mtd;
-   size_t retlen;
-
-   return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
-}
-
-static int apl_flash_probe(struct udevice *dev)
-{
-   return spi_flash_std_probe(dev);
-}
-
-/*
- * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
- * need to allocate the parent_platdata since by the time this function is
- * called device_bind() has already gone past that step.
- */
-static int apl_flash_bind(struct udevice *dev)
-{
-   if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
-   struct dm_spi_slave_platdata *plat;
-   struct udevice *spi;
-   int ret;
-
-   ret = uclass_first_device_err(UCLASS_SPI, &spi);
-   if (ret)
-   return ret;
-   dev->parent = spi;
-
-   plat = calloc(sizeof(*plat), 1);
-   if (!plat)
-   return -ENOMEM;
-   dev->parent_platdata = plat;
-   }
-
-   return 0;
-}
-
-static const struct dm_spi_flash_ops apl_flash_ops = {
-   .read   = apl_flash_std_read,
-};
-
-static const struct udevice_id apl_flash_ids[] = {
-   { .compatible = "jedec,spi-nor" },
-   { }
-};
-
-U_BOOT_DRIVER(winbond_w25q128fw) = {
-   .name   = "winbond_w25q128fw",
-   .id = UCLASS_SPI_FLASH,
-   .of_match   = apl_flash_ids,
-   .bind   = apl_flash_bind,
-   .probe  = apl_flash_probe,
-   .priv_auto_alloc_size = sizeof(struct spi_flash),
-   .ops= &apl_flash_ops,
-};
-
 /* This uses a SPI flash device to read the next phase */
 static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
   struct spl_boot_device *bootdev)
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index b09046fec3..44cdb3151d 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -122,7 +122,7 @@ static int spi_flash_std_erase(struct udevice *dev, u32 
offset, size_t len)
return mtd->_erase(mtd, &instr);
 }
 
-int spi_flash_std_probe(struct udevice *dev)
+static int spi_flash_std_probe(struct udevice *dev)
 {
struct spi_slave *slave = dev_get_parent_priv(dev);
struct spi_flash *flash;
@@ -164,6 +164,32 @@ static int spi_flash_std_remove(struct udevice *dev)
return 0;
 }
 
+/*
+ * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
+ * need to allocate the parent_platdata since by the time this function is
+ * called device_bind() has already gone past that step.
+ */
+static int spi_flash_std_bind(struct udevice *dev)
+{
+   if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+   struct dm_spi_slave_platdata *plat;
+   struct udevice *spi;
+   int ret;
+
+   ret = uclass_first_device_err(UCLASS_SPI, &spi);
+   if (ret)
+   return ret;
+   dev->parent = spi;
+
+   plat = calloc(sizeof(*plat), 1);
+   if (!plat)
+   return -ENOMEM;
+   dev->parent_platdata = plat;
+   }
+
+   return 0;
+}
+
 static const struct dm_spi_flash_ops spi_flash_std_ops = {
.read = spi_flash_std_read,
.write = spi_flash_std_write,
@@ -180,6 +206,7 @@ U_BOOT_DRIVER(spi_flash_std) = {
.id = UC

[PATCH 2/5] mtd: Add dm-mtd core ops

[Jagan Teki]

- Add generic mtd operations for UCLASS_MTD
- Add mtd_dread|derase|dwrite

The respetive MTD_UCLASS drivers must install the hooks to these
mtd_ops and other core ops are act as a interface b/w drivers
vs command code.

Cc: Simon Glass 
Cc: Vignesh R 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/mtd-uclass.c | 38 +
 include/mtd.h| 41 
 2 files changed, 79 insertions(+)

diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index 5418217431..bb00336a60 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Copyright (c) 2020 Jagan Teki 
  * Copyright (C) 2015 Thomas Chou 
  */
 
@@ -8,6 +10,42 @@
 #include 
 #include 
 #include 
+#include 
+
+int mtd_dread(struct udevice *dev, loff_t from, size_t len, u_char *buf)
+{
+   const struct mtd_ops *ops = mtd_get_ops(dev);
+
+   if (!ops->read)
+   return -EOPNOTSUPP;
+
+   return ops->read(dev, from, len, buf);
+}
+
+int mtd_derase(struct udevice *dev, loff_t off, size_t len)
+{
+   const struct mtd_ops *ops = mtd_get_ops(dev);
+   struct erase_info instr;
+
+   if (!ops->erase)
+   return -EOPNOTSUPP;
+
+   memset(&instr, 0, sizeof(instr));
+   instr.addr = off;
+   instr.len = len;
+
+   return ops->erase(dev, &instr);
+}
+
+int mtd_dwrite(struct udevice *dev, loff_t to, size_t len, const u_char *buf)
+{
+   const struct mtd_ops *ops = mtd_get_ops(dev);
+
+   if (!ops->write)
+   return -EOPNOTSUPP;
+
+   return ops->write(dev, to, len, buf);
+}
 
 /**
  * mtd_probe - Probe the device @dev if not already done
diff --git a/include/mtd.h b/include/mtd.h
index b0f8693386..b94afe8945 100644
--- a/include/mtd.h
+++ b/include/mtd.h
@@ -8,6 +8,47 @@
 
 #include 
 
+struct mtd_ops {
+   int (*erase)(struct udevice *dev, struct erase_info *instr);
+   int (*read)(struct udevice *dev, loff_t from, size_t len,
+   u_char *buf);
+   int (*write)(struct udevice *dev, loff_t to, size_t len,
+const u_char *buf);
+};
+
+#define mtd_get_ops(dev) ((struct mtd_ops *)(dev)->driver->ops)
+
+/**
+ * mtd_dread() - Read data from mtd device
+ *
+ * @dev:   mtd udevice
+ * @from:  Offset into device in bytes to read from
+ * @len:   Length of bytes to read
+ * @buf:   Buffer to put the data that is read
+ * @return 0 if OK, -ve on error
+ */
+int mtd_dread(struct udevice *dev, loff_t from, size_t len, u_char *buf);
+
+/**
+ * mtd_dwrite() - Write data to mtd device
+ *
+ * @dev:   mtd udevice
+ * @to:Offset into device in bytes to write to
+ * @len:   Length of bytes to write
+ * @buf:   Buffer containing bytes to write
+ * @return 0 if OK, -ve on error
+ */
+int mtd_dwrite(struct udevice *dev, loff_t to, size_t len, const u_char *buf);
+
+/**
+ * mtd_derase() - Erase blocks of the mtd device
+ *
+ * @dev:   mtd udevice
+ * @instr: Erase info details of mtd device
+ * @return 0 if OK, -ve on error
+ */
+int mtd_derase(struct udevice *dev, loff_t off, size_t len);
+
 int mtd_probe(struct udevice *dev);
 int mtd_probe_devices(void);
 
-- 
2.25.1

[PATCH 5/5] mtd: spi: Switch to MTD uclass (absolute UCLASS_SPI_FLASH)

[Jagan Teki]

Why MTD UCLASS switch?

>From a nutshell, all the memory-related flash devices like
Parallel NOR, Raw NAND, SPI NOR/NAND stacks should be part
of the MTD layer.

The same theory applies to incase of MTD UCLASS in U-Boot.

Unfortunately, no flash drivers are using the MTD UCLASS in the
fully functional driver model. There are several reasons behind
it like
- MTD code always copies/sync from Linux to support the latest
  flash features.
- So no special interest to touch since flash code is much bigger
  than usual and a lot of features are tested with existing code.
- No real taker to implement it.

So, this patch is trying to move further to use a common flash
interface layer called MTD in the driver model way.

As initial support it supporting spinor flash device drivers would
be written as UCLASS_MTD.

What happened to UCLASS_SPI_FLASH, why it is absolute now?

Due to the effect of Linux MTD/SPI_NOR sync the existing spi_flash
the structure has been affected such a way that it was dead and
typedefs to spi_nor.

What happened with this patch then?

With this patch, the UCLASS_SPI_FLASH will be replaced with
UCLASS_MTD by using dm-driven mtd_ops.

absolute link:
sf.c => sf uclass => sf driver => spi-nor-core
- flash operations via dm_spi_flash_ops

updated link:
sf.c => mtd uclass => mtd driver => spi-nor-core
- flash operations via mtd_ops (dm variant)

Future work?

- cleanup of spi_flash with spinor
- renaming of CONFIG option changes
- implement common mtd probe
- implement mtd flash interface types so that the respective
  commands like sf, mtd can make use of dm-mtd in the proper way.

Signed-off-by: Jagan Teki 
---
 arch/arm/mach-rockchip/spl-boot-order.c |   4 +-
 arch/x86/cpu/apollolake/spl.c   |   8 +-
 arch/x86/lib/fsp2/fsp_init.c|   2 +-
 arch/x86/lib/fsp2/fsp_support.c |   7 +-
 arch/x86/lib/mrccache.c |   8 +-
 board/atmel/common/mac-spi-nor.c|   4 +-
 drivers/mtd/spi/Kconfig |   2 +
 drivers/mtd/spi/sandbox.c   |   2 +-
 drivers/mtd/spi/sf-uclass.c | 106 ++--
 drivers/mtd/spi/sf_dataflash.c  |  25 +++---
 include/dm/uclass-id.h  |   1 -
 include/spi_flash.h |  53 +---
 test/dm/sf.c|  12 +--
 13 files changed, 71 insertions(+), 163 deletions(-)

diff --git a/arch/arm/mach-rockchip/spl-boot-order.c 
b/arch/arm/mach-rockchip/spl-boot-order.c
index 94673f34c9..64a745d189 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -62,7 +62,7 @@ static int spl_node_to_boot_device(int node)
default:
return -ENOSYS;
}
-   } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
+   } else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node,
&parent)) {
return BOOT_DEVICE_SPI;
}
@@ -73,7 +73,7 @@ static int spl_node_to_boot_device(int node)
 * extended with awareness of the BLK layer (and matching OF_CONTROL)
 * soon.
 */
-   if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+   if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent))
return BOOT_DEVICE_SPI;
 
return -1;
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index e1ee1e0624..9c80440bbb 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -41,7 +42,7 @@ static int rom_load_image(struct spl_image_info *spl_image,
debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
 
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
-   ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+   ret = uclass_find_first_device(UCLASS_MTD, &dev);
if (ret)
return log_msg_ret("spi_flash", ret);
if (!dev)
@@ -77,7 +78,7 @@ static int spl_fast_spi_load_image(struct spl_image_info 
*spl_image,
struct udevice *dev;
int ret;
 
-   ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
+   ret = uclass_first_device_err(UCLASS_MTD, &dev);
if (ret)
return ret;
 
@@ -89,8 +90,7 @@ static int spl_fast_spi_load_image(struct spl_image_info 
*spl_image,
spl_image->name = "U-Boot";
spl_pos &= ~0xff00;
debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
-   ret = spi_flash_read_dm(dev, spl_pos, spl_size,
-   (void *)spl_image->load_addr);
+   ret = mtd_dread(dev, spl_pos, spl_size, (void *)spl_image->load_addr);
cpu_flush_l1d_to_l2();
if (ret)
return ret;
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index 85cae54a0c..61af4

[PATCH 4/5] mtd: Build mtd-uclass as obj

[Jagan Teki]

Technically dm and nodm codebases have to build separately
since the SPL and U-Boot proper will enable based on the
requirements and foot-print sizes.

Till now there is no usage of SPL DM_MTD, but if we enable
it can't build since the mtd-uclass is linked with nodm
MTD code.

So move the build link from mtd to obj so-that it can make
compatible with all build types.

Cc: Simon Glass 
Cc: Vignesh R 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/Makefile | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index f6b0719746..baab7b8657 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -4,7 +4,6 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
 mtd-$(CONFIG_MTD) += mtdcore.o mtd_uboot.o
-mtd-$(CONFIG_$(SPL_)DM_MTD) += mtd-uclass.o
 mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
 mtd-$(CONFIG_MTD_CONCAT) += mtdconcat.o
 mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
@@ -18,6 +17,9 @@ mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o
 mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
 mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
 
+# dm-mtd
+obj-$(CONFIG_$(SPL_)DM_MTD) += mtd-uclass.o
+
 # U-Boot build
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 
-- 
2.25.1

[PATCH 3/5] mtd: Add SPL_DM_MTD option

[Jagan Teki]

Add SPL option for DM_MTD.

Cc: Simon Glass 
Cc: Vignesh R 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/Kconfig  | 8 
 drivers/mtd/Makefile | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 348b43e653..3feedf311f 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -17,6 +17,14 @@ config DM_MTD
  flash, RAM and similar chips, often used for solid state file
  systems on embedded devices.
 
+config SPL_DM_MTD
+   bool "Enable Driver Model for MTD drivers in SPL"
+   depends on SPL_DM
+   help
+ Enable driver model for Memory Technology Devices (MTD), such as
+ flash, RAM and similar chips, often used for solid state file
+ systems on embedded devices.
+
 config MTD_NOR_FLASH
bool "Enable parallel NOR flash support"
help
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 318788c5e2..f6b0719746 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -4,7 +4,7 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
 mtd-$(CONFIG_MTD) += mtdcore.o mtd_uboot.o
-mtd-$(CONFIG_DM_MTD) += mtd-uclass.o
+mtd-$(CONFIG_$(SPL_)DM_MTD) += mtd-uclass.o
 mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
 mtd-$(CONFIG_MTD_CONCAT) += mtdconcat.o
 mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
-- 
2.25.1

Re: [PATCH] rtc: pcf2127: fix uninitialized variable msg

[Rasmus Villemoes]

On 09/07/2020 12.58, Biwen Li wrote:
> From: Biwen Li 
> 
> Fix uninitialized variable msg
> 
>   struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
> - struct i2c_msg msg;
> + struct i2c_msg msg = {0};
>   int ret;
>  
>   /* Set the address of the start register to be read */
> 

I assume it's the

msg.flags |= I2C_M_RD;

line that is warned about (please include such info)? Isn't the right
fix to replace that by

msg.flags = I2C_M_RD;

?

Rasmus

RE: [EXT] Re: [PATCH] rtc: pcf2127: fix uninitialized variable msg

[Biwen Li]

> 
> On 09/07/2020 12.58, Biwen Li wrote:
> > From: Biwen Li 
> >
> > Fix uninitialized variable msg
> >
> >   struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
> > - struct i2c_msg msg;
> > + struct i2c_msg msg = {0};
> >   int ret;
> >
> >   /* Set the address of the start register to be read */
> >
> 
> I assume it's the
> 
> msg.flags |= I2C_M_RD;
> 
> line that is warned about (please include such info)? Isn't the right fix to
> replace that by
> 
> msg.flags = I2C_M_RD;
> 
> ?
Two lines("struct i2c msg;" and "msg.flags |= I2C_M_RD") are warned by build 
system. Initializing msg variable will be better.
> 
> Rasmus

Re: [EXT] Re: [PATCH] rtc: pcf2127: fix uninitialized variable msg

[Rasmus Villemoes]

On 09/07/2020 13.38, Biwen Li wrote:
>>
>> On 09/07/2020 12.58, Biwen Li wrote:
>>> From: Biwen Li 
>>>
>>> Fix uninitialized variable msg
>>>
>>>   struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
>>> - struct i2c_msg msg;
>>> + struct i2c_msg msg = {0};
>>>   int ret;
>>>
>>>   /* Set the address of the start register to be read */
>>>
>>
>> I assume it's the
>>
>> msg.flags |= I2C_M_RD;
>>
>> line that is warned about (please include such info)? Isn't the right fix to
>> replace that by
>>
>> msg.flags = I2C_M_RD;
>>
>> ?
> Two lines("struct i2c msg;" and "msg.flags |= I2C_M_RD") are warned by build 
> system. 

What? That doesn't make sense. Perhaps your compiler is just friendly
enough to show you the declaration of the struct i2c_msg, but clearly
declaring an automatic variable without initializing it is not, by
itself, wrong. Otherwise "int ret;" in that very same function should be
warned about, and 10 other instances in any code base written in C.

Please show the exact output from the compiler and the compiler version.

> Initializing msg variable will be better.

No, understanding the cause of the warning and fixing that is clearly
better.

Rasmus

[PATCH] efi_loader: display RO attribute with TEE-backed variables

[Ilias Apalodimas]

A previous commit adds support for displaying variables RO flag.
Let's add it on the TEE backed variable storage as well.

Signed-off-by: Ilias Apalodimas 
---
- Depends on https://lists.denx.de/pipermail/u-boot/2020-July/419269.html

 include/mm_communication.h|  39 
 lib/efi_loader/efi_variable_tee.c | 144 --
 2 files changed, 178 insertions(+), 5 deletions(-)

diff --git a/include/mm_communication.h b/include/mm_communication.h
index 193c4d157874..8c0087ba1611 100644
--- a/include/mm_communication.h
+++ b/include/mm_communication.h
@@ -205,4 +205,43 @@ struct smm_variable_query_info {
u32 attr;
 };
 
+#define VAR_CHECK_VARIABLE_PROPERTY_REVISION 0x0001
+#define VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY BIT(0)
+/**
+ * struct var_check_property - Used to store variable properties in StMM
+ *
+ * @revision:   properties version
+ * @property:   properties mask
+ * @attributes: variable attributes
+ * @minsize:minimum allowed size
+ * @maxsize:maximum allowed size
+ *
+ * Defined in EDK2 as VAR_CHECK_VARIABLE_PROPERTY.
+ */
+struct var_check_property {
+   u16 revision;
+   u16 property;
+   u32 attributes;
+   efi_uintn_t minsize;
+   efi_uintn_t maxsize;
+};
+
+/**
+ * struct smm_variable_var_check_property - Used to communicate variable
+ *  properties with StMM
+ *
+ * @guid:   vendor GUID
+ * @name_size:  size of EFI name
+ * @property:   variable properties struct
+ * @name:   variable name
+ *
+ * Defined in EDK2 as SMM_VARIABLE_COMMUNICATE_VAR_CHECK_VARIABLE_PROPERTY.
+ */
+struct smm_variable_var_check_property {
+   efi_guid_tguid;
+   efi_uintn_t   name_size;
+   struct var_check_property property;
+   u16   name[];
+};
+
 #endif /* _MM_COMMUNICATION_H_ */
diff --git a/lib/efi_loader/efi_variable_tee.c 
b/lib/efi_loader/efi_variable_tee.c
index ff90aa8e81c6..4bcac5f67e23 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -244,10 +244,99 @@ out:
return ret;
 }
 
+/*
+ * StMM can store internal attributes and properties for variables, i.e 
enabling
+ * R/O variables
+ */
+static efi_status_t set_property_int(u16 *variable_name, efi_uintn_t name_size,
+const efi_guid_t *vendor, u32 attributes,
+u32 property)
+{
+   struct smm_variable_var_check_property *smm_property;
+   struct var_check_property var_property;
+   efi_uintn_t payload_size;
+   u8 *comm_buf = NULL;
+   efi_status_t ret;
+
+   payload_size = sizeof(*smm_property) + name_size;
+   if (payload_size > max_payload_size) {
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   comm_buf = setup_mm_hdr((void **)&smm_property, payload_size,
+   
SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_SET,
+   &ret);
+   if (!comm_buf)
+   goto out;
+
+   var_property.revision = VAR_CHECK_VARIABLE_PROPERTY_REVISION;
+   var_property.property = property;
+   var_property.attributes = attributes;
+   var_property.minsize = 1;
+   var_property.maxsize = max_payload_size;
+
+   guidcpy(&smm_property->guid, vendor);
+   smm_property->name_size = name_size;
+   memcpy(&smm_property->property, &var_property,
+  sizeof(smm_property->property));
+   memcpy(smm_property->name, variable_name, name_size);
+
+   ret = mm_communicate(comm_buf, payload_size);
+
+out:
+   free(comm_buf);
+   return ret;
+}
+
+static efi_status_t get_property_int(u16 *variable_name, efi_uintn_t name_size,
+const efi_guid_t *vendor,
+struct var_check_property *var_property)
+{
+   struct smm_variable_var_check_property *smm_property;
+   efi_uintn_t payload_size;
+   u8 *comm_buf = NULL;
+   efi_status_t ret;
+
+   memset(var_property, 0, sizeof(*var_property));
+   payload_size = sizeof(*smm_property) + name_size;
+   if (payload_size > max_payload_size) {
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   comm_buf = setup_mm_hdr((void **)&smm_property, payload_size,
+   
SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET,
+   &ret);
+   if (!comm_buf)
+   goto out;
+
+   guidcpy(&smm_property->guid, vendor);
+   smm_property->name_size = name_size;
+   memcpy(smm_property->name, variable_name, name_size);
+
+   ret = mm_communicate(comm_buf, payload_size);
+   /*
+* Currently only R/O property is supported in StMM.
+* Variables that are not set to R/O will not set the property in StMM
+* and the call will return 

Re: [PATCH 05/10] board_f: mips: Factor out mips-specific bdinfo setup

[Heinrich Schuchardt]

On 09.07.20 12:27, Ovidiu Panait wrote:
> Hi,
>
> On 09.07.2020 12:15, Heinrich Schuchardt wrote:
>> On 09.07.20 10:04, Ovidiu Panait wrote:
>>> Factor out mips-specific bdinfo setup from generic init sequence to
>>> arch_setup_bdinfo in arch/mips/lib/boot.c.
>>>
>>> Signed-off-by: Ovidiu Panait 
>>> ---
>>>
>>>   arch/mips/lib/boot.c | 18 ++
>>>   common/board_f.c | 25 +
>>>   2 files changed, 19 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
>>> index db862f6379..b3a48ce10f 100644
>>> --- a/arch/mips/lib/boot.c
>>> +++ b/arch/mips/lib/boot.c
>>> @@ -9,6 +9,24 @@
>>>
>>>   DECLARE_GLOBAL_DATA_PTR;
>>>
>>> +int arch_setup_bdinfo(void)
>>> +{
>>> +    bd_t *bd = gd->bd;
>>> +
>>> +    /*
>>> + * Save local variables to board info struct
>>> + */
>>> +    bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;    /* start of memory */
>>> +    bd->bi_memsize = gd->ram_size;    /* size in bytes */
>>> +
>>> +#ifdef CONFIG_SYS_SRAM_BASE
>> We want to get rid of #ifdef where possible. So it is preferable to
>> write:
>>
>> if IS_ENABLED(CONFIG_SYS_SRAM_BASE) {
>>
>> One benefit is that static code analysis will consider the code.
>>
>> Best regards
>>
>> Heinrich
>
> My understanding is that IS_ENABLED() only works with with boolean and
> tristate options.
>
> In this case, CONFIG_SYS_SRAM_BASE is a hex value:
>
> include/configs/pic32mzdask.h:22:#define CONFIG_SYS_SRAM_BASE    
> 0x8000
>
>
> Switching to IS_ENABLED() produces the following build errors for qemu
> mips:

You could add the following helper macro to include/linux/kconfig.h

#define config_defined(cfg) _config_defined(cfg, #cfg)
#define _config_defined(a1, a2) !!__builtin_strcmp(#a1, a2)

config_defined(cfg) evaluates to true if:
* cfg is defined and
* cfg is not defined as cfg.

As long as optimization is switch on __builtin_strcmp() is evaluated at
compile time.

Best regards

Heinrich

>
> $ git diff
> diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
> index b3a48ce10f..aa047335ec 100644
> --- a/arch/mips/lib/boot.c
> +++ b/arch/mips/lib/boot.c
> @@ -19,10 +19,10 @@ int arch_setup_bdinfo(void)
>     bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;    /* start of
> memory */
>     bd->bi_memsize = gd->ram_size;  /* size in bytes */
>
> -#ifdef CONFIG_SYS_SRAM_BASE
> -   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;    /* start of SRAM */
> -   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
> -#endif
> +   if (IS_ENABLED(CONFIG_SYS_SRAM_BASE)) {
> +   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of
> SRAM */
> +   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size  of SRAM */
> +   }
>
>     return 0;
>  }
>
> $ make
>
> ...
>
> arch/mips/lib/boot.c: In function 'arch_setup_bdinfo':
>   CC  common/init/board_init.o
> arch/mips/lib/boot.c:23:22: error: 'CONFIG_SYS_SRAM_BASE' undeclared
> (first use in this function); did you mean 'CONFIG_SYS_SDRAM_BASE'?
>    23 |   bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
>   |  ^~~~
>   |  CONFIG_SYS_SDRAM_BASE
> arch/mips/lib/boot.c:23:22: note: each undeclared identifier is reported
> only once for each function it appears in
> arch/mips/lib/boot.c:24:21: error: 'CONFIG_SYS_SRAM_SIZE' undeclared
> (first use in this function); did you mean 'CONFIG_SYS_SDRAM_BASE'?
>    24 |   bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */
>   | ^~~~
>   | CONFIG_SYS_SDRAM_BASE
>
> Thanks,
>
> Ovidiu
>
>>> +    bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;    /* start of SRAM */
>>> +    bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;    /* size  of SRAM */
>>> +#endif
>>> +
>>> +    return 0;
>>> +}
>>> +
>>>   unsigned long do_go_exec(ulong (*entry)(int, char * const []),
>>>    int argc, char * const argv[])
>>>   {
>>> diff --git a/common/board_f.c b/common/board_f.c
>>> index 9bfcd6b236..fd7e6a17ad 100644
>>> --- a/common/board_f.c
>>> +++ b/common/board_f.c
>>> @@ -602,26 +602,6 @@ __weak int arch_setup_bdinfo(void)
>>>   return 0;
>>>   }
>>>
>>> -#if defined(CONFIG_MIPS)
>>> -static int setup_board_part1(void)
>>> -{
>>> -    bd_t *bd = gd->bd;
>>> -
>>> -    /*
>>> - * Save local variables to board info struct
>>> - */
>>> -    bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;    /* start of memory */
>>> -    bd->bi_memsize = gd->ram_size;    /* size in bytes */
>>> -
>>> -#ifdef CONFIG_SYS_SRAM_BASE
>>> -    bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;    /* start of SRAM */
>>> -    bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;    /* size  of SRAM */
>>> -#endif
>>> -
>>> -    return 0;
>>> -}
>>> -#endif
>>> -
>>>   #ifdef CONFIG_POST
>>>   static int init_post(void)
>>>   {
>>> @@ -942,11 +922,8 @@ static const init_fnc_t init_sequence_f[] = {
>>>   

Re: using sudo?, Re: [PATCH v2 8/8] test/py: efi_secboot: add test for intermediate certificates

[Tom Rini]

On Thu, Jul 09, 2020 at 02:33:49PM +0900, AKASHI Takahiro wrote:
> Tom,
> 
> On Wed, Jul 08, 2020 at 11:15:26PM -0400, Tom Rini wrote:
> > On Thu, Jul 09, 2020 at 09:58:03AM +0900, AKASHI Takahiro wrote:
> > 
> > > Hi Tom,
> > > 
> > > I'd like to make sure of your policy about usage of "sudo" on CI.
> > > Do you think that we should always avoid using "sudo" in testing?
> > > 
> > > I remember that you had allowed us to run sudo in (python)
> > > test scripts on Travis CI when I requested this (for FAT filesystem?).
> > 
> > So, the best practices at this time are to have the code try and use
> > guestmount (or similar tools) when possible and fall back to sudo, as
> > Ubuntu breaks guestmount (and similar tools) by default.
> 
> See the commands log (on my ubuntu 19.10) below:
> 
> ===8<===
> << try 1 >>
> tmp$ mkdir tmpdir
> tmp$ virt-make-fs -t vfat -s +1M --partition=gpt ./tmpdir tmp.img
> libguestfs: error: /usr/bin/supermin exited with error status 1.
> To see full error messages you may need to enable debugging.
> Do:
>   export LIBGUESTFS_DEBUG=1 LIBGUESTFS_TRACE=1
> and run the command again.  For further information, read:
>   http://libguestfs.org/guestfs-faq.1.html#debugging-libguestfs
> You can also run 'libguestfs-test-tool' and post the *complete* output
> into a bug report or message to the libguestfs mailing list.
> 
> << try 2 >>
> tmp$ LIBGUESTFS_DEBUG=1 virt-make-fs -t vfat -s +1M --partition=gpt ./tmpdir 
> tmp.img
> ...
> supermin: kernel: kernel_version 5.3.0-62-generic
> supermin: kernel: modpath /lib/modules/5.3.0-62-generic
> cp: cannot open '/boot/vmlinuz-5.3.0-62-generic' for reading: Permission 
> denied
> supermin: cp -p '/boot/vmlinuz-5.3.0-62-generic' 
> '/var/tmp/.guestfs-1000/appliance.d.op62psoy/kernel': command failed, see 
> earlier errors
> libguestfs: error: /usr/bin/supermin exited with error status 1, see debug 
> messages above
> ...
> 
> << try 3 >>
> tmp$ sudo chmod a+rw /boot/vmlinuz-5.3.0-62-generic 
> tmp$ LIBGUESTFS_DEBUG=1 virt-make-fs -t vfat -s +1M --partition=gpt ./tmpdir 
> tmp.img
> ...
> tmp$ ls -l tmp.img
> -rw-r--r-- 1 akashi akashi 1341440 Jul  9 13:50 tmp.img
> ===>8===
> 
> As you can see, virt-make-fs will fail on *standard* ubuntu.
> You have to change the permission of the current kernel's binary.

Yes, exactly.  This is an intentional behavior in Ubuntu (and not
Debian) and why we cannot rely on the various virt tools working.

I fixed the current tests over in
http://patchwork.ozlabs.org/project/uboot/patch/20200707155309.24770-1-tr...@konsulko.com/
but need to follow up and try what Stephen was saying to clean it up
more still.

> While I can't make sure, we will have the same issue with guestmount
> as it will also create a minimum virtual machine before execution.
> 
> What does it mean?
> You must change the permission every time when you re-install the OS
> or re-bump the kernel version. Obviously, I can't do that from my own
> test script (without sudo).
> So if you don't have any way (or workaround) to deal with it,
> libguestfs-tools or guestmount cannot be a solution here.

Well, just like the test_fs tests, we try guestmount, if it doesn't work
we fall back to just sudo'ing what we need to run directly.  I think
Ubuntu did something very stupid here.  I just don't know if moving CI
to be Debian based (and I guess Travis is just working-around the issue
by default for us, given the fs tests run there today) is good enough as
it will leave everyone else's Ubuntu-based setups broken.

-- 
Tom


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[PATCH] lib: fdt: Introduce fdtdec_setup_mem_size_base_lowest()

[Michal Simek]

New function should be called from board dram_init() because it initialized
gd->ram_base/ram_size. It finds the lowest available memory.

On systems with multiple memory nodes finding out the first memory node by
fdtdec_setup_mem_size_base() is not enough because this memory can be above
actual U-Boot VA mapping. Currently only mapping till 39bit is supported
(Full 44bit mapping was removed by commit 7985cdf74b28 ("arm64: Remove
non-full-va map code")).
If DT starts with the first memory node above 39bit address then system can
be unpredictable.

The function is available only when multiple memory bank support is
enabled.

Calling fdtdec_setup_memory_banksize() from dram_init() is not possible
because fdtdec_setup_memory_banksize() is saving dram information to bd
structure which is placed on stack but not initialized at this time. Also
stack is placed at location setup in dram_init().

Signed-off-by: Michal Simek 
---

 board/xilinx/versal/board.c |  2 +-
 include/fdtdec.h| 17 ++
 lib/fdtdec.c| 44 +
 3 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 45cf1d2d0cad..3dc7044b213e 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -229,7 +229,7 @@ int dram_init_banksize(void)
 
 int dram_init(void)
 {
-   if (fdtdec_setup_mem_size_base() != 0)
+   if (fdtdec_setup_mem_size_base_lowest() != 0)
return -EINVAL;
 
return 0;
diff --git a/include/fdtdec.h b/include/fdtdec.h
index abd6d4267194..6e378028e975 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -946,6 +946,23 @@ int fdtdec_setup_mem_size_base_fdt(const void *blob);
  */
 int fdtdec_setup_mem_size_base(void);
 
+/**
+ * fdtdec_setup_mem_size_base_lowest() - decode and setup gd->ram_size and
+ * gd->ram_start by lowest available memory base
+ *
+ * Decode the /memory 'reg' property to determine the lowest start of the 
memory
+ * bank bank and populate the global data with it.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size and start
+ * address instead of hard coding the value in the case where the memory size
+ * and start address cannot be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_mem_size_base_lowest(void);
+
 /**
  * fdtdec_setup_memory_banksize_fdt() - decode and populate gd->bd->bi_dram
  *
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0dd7ff1ac3f7..04b32f675876 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1115,7 +1115,51 @@ int fdtdec_setup_memory_banksize_fdt(const void *blob)
 int fdtdec_setup_memory_banksize(void)
 {
return fdtdec_setup_memory_banksize_fdt(gd->fdt_blob);
+}
+
+int fdtdec_setup_mem_size_base_lowest(void)
+{
+   int bank, ret, mem, reg = 0;
+   struct fdt_resource res;
+   unsigned long base;
+   phys_size_t size;
+   const void *blob = gd->fdt_blob;
+
+   gd->ram_base = (unsigned long)~0;
+
+   mem = get_next_memory_node(blob, -1);
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
 
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
+   if (ret == -FDT_ERR_NOTFOUND) {
+   reg = 0;
+   mem = get_next_memory_node(blob, mem);
+   if (mem == -FDT_ERR_NOTFOUND)
+   break;
+
+   ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
+   if (ret == -FDT_ERR_NOTFOUND)
+   break;
+   }
+   if (ret != 0)
+   return -EINVAL;
+
+   base = (unsigned long)res.start;
+   size = (phys_size_t)(res.end - res.start + 1);
+
+   if (gd->ram_base > base && size) {
+   gd->ram_base = base;
+   gd->ram_size = size;
+   debug("%s: Initial DRAM base %lx size %lx\n",
+ __func__, base, (unsigned long)size);
+   }
+   }
+
+   return 0;
 }
 #endif
 
-- 
2.27.0

[v2] test: Have test_fs work with non-functional guestmount tools

[Tom Rini]

Since 2011 Ubuntu has intentionally broken support for guestmount[1] by
default and requires sysadmin intervention to re-enable support.  This
in turn exposed that in our tests if guestmount is available but fails
we do not fall back to trying to use sudo.  Restructure our code to try
sudo if guestmount fails rather than only when it is not in our path.
Further, only note that we are using fuse on success of the call.

[1]: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/759725

Cc: Heinrich Schuchardt 
Cc: Simon Glass 
Cc: Stephen Warren 
Signed-off-by: Tom Rini 
---
Changes in v2:
- Rework to not have another try/except nesting as Stephen suggested.
  Tested this out and we still skip the tests and now note that sudo
  doesn't work.  Since the README for tests says sudo or guestmount, I
  think this is OK.

This, I suspect, will also fix the cases where in CI we attempt to run
the FS tests but do not as guestmount fails.  I'm not going to remove
guestmount from the Docker containers as it's a useful reference for
"what is required for a minimal environment for U-Boot builds" and
perhaps we will switch to Debian instead at some point.
---
 test/py/tests/test_fs/conftest.py | 20 +---
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/test/py/tests/test_fs/conftest.py 
b/test/py/tests/test_fs/conftest.py
index ee82169c2a37..188b9b1ddef8 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -206,21 +206,19 @@ def mount_fs(fs_type, device, mount_point):
 fuse_mounted = False
 try:
 if tool_is_in_path('guestmount'):
-fuse_mounted = True
 check_call('guestmount -a %s -m /dev/sda %s'
 % (device, mount_point), shell=True)
-else:
-mount_opt = 'loop,rw'
-if re.match('fat', fs_type):
-mount_opt += ',umask='
+fuse_mounted = True
+except CalledProcessError:
+mount_opt = 'loop,rw'
+if re.match('fat', fs_type):
+mount_opt += ',umask='
 
-check_call('sudo mount -o %s %s %s'
-% (mount_opt, device, mount_point), shell=True)
+check_call('sudo mount -o %s %s %s'
+% (mount_opt, device, mount_point), shell=True)
 
-# may not be effective for some file systems
-check_call('sudo chmod a+rw %s' % mount_point, shell=True)
-except CalledProcessError:
-raise
+# may not be effective for some file systems
+check_call('sudo chmod a+rw %s' % mount_point, shell=True)
 
 def umount_fs(mount_point):
 """Unmount a volume.
-- 
2.17.1

Re: Please pull u-boot-marvell/master

[Tom Rini]

On Thu, Jul 09, 2020 at 10:42:09AM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull these MVEBU related patches:
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] Please pull from u-boot-i2c

[Tom Rini]

On Thu, Jul 09, 2020 at 10:41:00AM +0200, Heiko Schocher wrote:

> Hello Tom,
> 
> please pull from u-boot-i2c master
> 
> The following changes since commit 61608f395e7dcb2be6060407a72a1149b046430a:
> 
>   Merge branch '2020-07-08-misc-features-and-fixes' (2020-07-08 20:20:24 
> -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git tags/for-v2020.10
> 
> for you to fetch changes up to 7239a610b796b0bb8f85c5c21798596c2768cb50:
> 
>   pwm: Add PWM driver for SiFive SoC (2020-07-09 06:03:12 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[PATCH] serial: Fix SIFIVE debug serial dependency

[Michal Simek]

The commit 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for
debug consoles") has added incorrect dependency for SIFIVE debug uart which
should depend on SIFIVE driver instead of PL01x.

Signed-off-by: Michal Simek 
---

 drivers/serial/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 17d0e7362379..006cb5a50140 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -359,7 +359,7 @@ config DEBUG_UART_SANDBOX
 
 config DEBUG_UART_SIFIVE
bool "SiFive UART"
-   depends on PL01X_SERIAL
+   depends on SIFIVE_SERIAL
help
  Select this to enable a debug UART using the serial_sifive driver. You
  will need to provide parameters to make this work. The driver will
-- 
2.27.0

Re: [PATCH v3 15/17] efi_loader: use memory based variable storage

[ilias . apalodimas]

Hi Heinrich

On Wed, Jul 08, 2020 at 06:29:34PM +0200, Heinrich Schuchardt wrote:
> Saving UEFI variable as encoded U-Boot environment variables does not allow
> implement run-time support.
> 
> Use a memory buffer for storing UEFI variables.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  lib/efi_loader/efi_variable.c | 556 ++
>  1 file changed, 93 insertions(+), 463 deletions(-)
> 
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index f2f787fc8d..13123e7e41 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -30,145 +30,6 @@ static bool efi_secure_boot;
>  static enum efi_secure_mode efi_secure_mode;
> -}

[...]

> -
>  /**
>  }
>  #endif /* CONFIG_EFI_SECURE_BOOT */
> 
> -efi_status_t efi_get_variable_int(u16 *variable_name, const efi_guid_t 
> *vendor,
> -   u32 *attributes, efi_uintn_t *data_size,
> -   void *data, u64 *timep)
> +efi_status_t __efi_runtime
> +efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor,
> +  u32 *attributes, efi_uintn_t *data_size, void *data,
> +  u64 *timep)
>  {
> - char *native_name;
> - efi_status_t ret;
> - unsigned long in_size;
> - const char *val = NULL, *s;
> - u64 time = 0;
> - u32 attr;
> + efi_uintn_t old_size;
> + struct efi_var_entry *var;
> + u16 *pdata;
> 
>   if (!variable_name || !vendor || !data_size)
>   return EFI_INVALID_PARAMETER;
> -
> - ret = efi_to_native(&native_name, variable_name, vendor);
> - if (ret)
> - return ret;
> -
> - EFI_PRINT("get '%s'\n", native_name);
> -
> - val = env_get(native_name);
> - free(native_name);
> - if (!val)
> + var = efi_var_mem_find(vendor, variable_name, NULL);
> + if (!var)
>   return EFI_NOT_FOUND;
> 
> - val = parse_attr(val, &attr, &time);
> -
> - if (timep)
> - *timep = time;
> -
> - in_size = *data_size;
> -
> - if ((s = prefix(val, "(blob)"))) {
> - size_t len = strlen(s);
> -
> - /* number of hexadecimal digits must be even */
> - if (len & 1)
> - return EFI_DEVICE_ERROR;
> -
> - /* two characters per byte: */
> - len /= 2;
> - *data_size = len;
> -
> - if (in_size < len) {
> - ret = EFI_BUFFER_TOO_SMALL;
> - goto out;
> - }
> -
> - if (!data) {
> - EFI_PRINT("Variable with no data shouldn't exist.\n");
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - if (hex2bin(data, s, len))
> - return EFI_DEVICE_ERROR;
> -
> - EFI_PRINT("got value: \"%s\"\n", s);
> - } else if ((s = prefix(val, "(utf8)"))) {
> - unsigned len = strlen(s) + 1;
> -
> - *data_size = len;
> -
> - if (in_size < len) {
> - ret = EFI_BUFFER_TOO_SMALL;
> - goto out;
> - }
> -
> - if (!data) {
> - EFI_PRINT("Variable with no data shouldn't exist.\n");
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - memcpy(data, s, len);
> - ((char *)data)[len] = '\0';
> -
> - EFI_PRINT("got value: \"%s\"\n", (char *)data);
> - } else {
> - EFI_PRINT("invalid value: '%s'\n", val);
> - return EFI_DEVICE_ERROR;
> - }
> -
> -out:
>   if (attributes)
> - *attributes = attr;
> -
> - return ret;
> -}
> -
> -static char *efi_variables_list;
> -static char *efi_cur_variable;
> -
> -/**
> - * parse_uboot_variable() - parse a u-boot variable and get uefi-related
> - *   information
> - * @variable:whole data of u-boot variable (ie. name=value)
> - * @variable_name_size: size of variable_name buffer in byte
> - * @variable_name:   name of uefi variable in u16, null-terminated
> - * @vendor:  vendor's guid
> - * @attributes:  attributes
> - *
> - * A uefi variable is encoded into a u-boot variable as described above.
> - * This function parses such a u-boot variable and retrieve uefi-related
> - * information into respective parameters. In return, variable_name_size
> - * is the size of variable name including NULL.
> - *
> - * Return:   EFI_SUCCESS if parsing is OK, EFI_NOT_FOUND when
> - *   the entire variable list has been returned,
> - *   otherwise non-zero status code
> - */

[...]

>  }
> 
> -efi_status_t efi_get_next_variable_name_int(efi_uintn_t *variable_name_size,
> - u16 *variable_name,
> - efi_guid_t *vendor)
> +efi_status_t __efi_runtime
> +efi_get_next_variable

Re: [PATCH v4 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Matthias Brugger]

On 25/05/2020 13:39, Sylwester Nawrocki wrote:

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
  e7d4a95da86e0 "bitfield: fix *_encode_bits()",
  37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 


This seems to break compilation of
arch/arm/mach-uniphier/clk/pll-base-ld20.c

https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi/-/jobs/121248

Nicolas, Sylwester, can you please have a look.

Regards,
Matthias


---
Changes since v3:
  - none.
Changes since v2:
  - added some more missing whitespaces as pointed out by checkpatch.pl.
Changes since v1:
  - added empty lines between functions and macros.
Changes since RFC:
  - new patch.
---
  include/linux/bitfield.h | 52 
  1 file changed, 52 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7ad8b08 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,56 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));   \
})
  
+extern void __compiletime_error("value doesn't fit into mask")

+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type, base, to, from)  \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type * p, \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field) / field_multiplier(field); \
+}
+
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
+   MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
+   MAKE_OP(u##size, u##size, ,)
+
+MAKE_OP(u8, u8, ,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
  #endif

Re: [PATCH v4 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Matthias Brugger]

On 09/07/2020 17:35, Matthias Brugger wrote:



On 25/05/2020 13:39, Sylwester Nawrocki wrote:

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
  e7d4a95da86e0 "bitfield: fix *_encode_bits()",
  37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 


This seems to break compilation of
arch/arm/mach-uniphier/clk/pll-base-ld20.c

https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi/-/jobs/121248

Nicolas, Sylwester, can you please have a look.



Just in case you can't access the URL:
https://pastebin.com/KhDHf8e1


Regards,
Matthias


---
Changes since v3:
  - none.
Changes since v2:
  - added some more missing whitespaces as pointed out by checkpatch.pl.
Changes since v1:
  - added empty lines between functions and macros.
Changes since RFC:
  - new patch.
---
  include/linux/bitfield.h | 52 
  1 file changed, 52 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7ad8b08 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,56 @@
  (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));    \
  })
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+
+static __always_inline u64 field_multiplier(u64 field)
+{
+    if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+    __bad_mask();
+    return field & -field;
+}
+
+static __always_inline u64 field_mask(u64 field)
+{
+    return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type, base, to, from)    \
+static __always_inline __##type type##_encode_bits(base v, base field)    \
+{    \
+    if (__builtin_constant_p(v) && (v & ~field_mask(field)))    \
+    __field_overflow();    \
+    return to((v & field_mask(field)) * field_multiplier(field));    \
+}    \
+static __always_inline __##type type##_replace_bits(__##type old,    \
+    base val, base field)    \
+{    \
+    return (old & ~to(field)) | type##_encode_bits(val, field);    \
+}    \
+static __always_inline void type##p_replace_bits(__##type * p,    \
+    base val, base field)    \
+{    \
+    *p = (*p & ~to(field)) | type##_encode_bits(val, field);    \
+}    \
+static __always_inline base type##_get_bits(__##type v, base field)    \
+{    \
+    return (from(v) & field) / field_multiplier(field);    \
+}
+
+#define __MAKE_OP(size)    \
+    MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
+    MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
+    MAKE_OP(u##size, u##size, ,)
+
+MAKE_OP(u8, u8, ,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
  #endif

[PATCHv2 00/10] pci: layerscape: Split EP mode code into a

[Zhiqiang Hou]

From: Hou Zhiqiang 

Hou Zhiqiang (1):
  pci: layerscape: Add specific config entry for RC and EP mode driver

Xiaowei Bao (9):
  pci: layerscape: Split the EP and RC driver
  pci_ep: Add the init function
  armv8: dts: ls1046a: Add the PCIe EP node
  PCI_EP: layerscape: Add the multiple function support
  pci_ep: layerscape: Add the workaround for errata A-009460
  pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
  pci_ep: layerscape: Add the SRIOV VFs of PF support
  pci: layerscaple: Modify the ls_pcie_dump_atu function
  pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2

 arch/arm/dts/fsl-ls1046a.dtsi |  33 ++
 common/board_r.c  |  12 +
 configs/ls1012afrdm_qspi_defconfig|   2 +-
 configs/ls1012afrdm_tfa_defconfig |   2 +-
 .../ls1012afrwy_qspi_SECURE_BOOT_defconfig|   2 +-
 configs/ls1012afrwy_qspi_defconfig|   2 +-
 configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig |   2 +-
 configs/ls1012afrwy_tfa_defconfig |   2 +-
 configs/ls1012aqds_qspi_defconfig |   2 +-
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1012aqds_tfa_defconfig  |   2 +-
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |   2 +-
 configs/ls1012ardb_qspi_defconfig |   2 +-
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1012ardb_tfa_defconfig  |   2 +-
 configs/ls1021aiot_qspi_defconfig |   2 +-
 configs/ls1021aiot_sdcard_defconfig   |   2 +-
 configs/ls1021aqds_ddr4_nor_defconfig |   2 +-
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig  |   2 +-
 configs/ls1021aqds_nand_defconfig |   2 +-
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1021aqds_nor_defconfig  |   2 +-
 configs/ls1021aqds_nor_lpuart_defconfig   |   2 +-
 configs/ls1021aqds_qspi_defconfig |   2 +-
 configs/ls1021aqds_sdcard_ifc_defconfig   |   2 +-
 configs/ls1021aqds_sdcard_qspi_defconfig  |   2 +-
 configs/ls1021atsn_qspi_defconfig |   2 +-
 configs/ls1021atsn_sdcard_defconfig   |   2 +-
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1021atwr_nor_defconfig  |   2 +-
 configs/ls1021atwr_nor_lpuart_defconfig   |   2 +-
 configs/ls1021atwr_qspi_defconfig |   2 +-
 ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |   2 +-
 configs/ls1021atwr_sdcard_ifc_defconfig   |   2 +-
 configs/ls1021atwr_sdcard_qspi_defconfig  |   2 +-
 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1028aqds_tfa_defconfig  |   2 +-
 configs/ls1028aqds_tfa_lpuart_defconfig   |   2 +-
 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1028ardb_tfa_defconfig  |   2 +-
 configs/ls1043aqds_defconfig  |   2 +-
 configs/ls1043aqds_lpuart_defconfig   |   2 +-
 configs/ls1043aqds_nand_defconfig |   2 +-
 configs/ls1043aqds_nor_ddr3_defconfig |   2 +-
 configs/ls1043aqds_qspi_defconfig |   2 +-
 configs/ls1043aqds_sdcard_ifc_defconfig   |   2 +-
 configs/ls1043aqds_sdcard_qspi_defconfig  |   2 +-
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1043aqds_tfa_defconfig  |   2 +-
 configs/ls1043ardb_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1043ardb_defconfig  |   2 +-
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig |   2 +-
 configs/ls1043ardb_nand_defconfig |   2 +-
 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig   |   2 +-
 configs/ls1043ardb_sdcard_defconfig   |   2 +-
 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig  |   2 +-
 configs/ls1043ardb_tfa_defconfig  |   2 +-
 configs/ls1046afrwy_tfa_defconfig |   3 +-
 configs/ls1046aqds_SECURE_BOOT_defconfig  |   3 +-
 configs/ls1046aqds_defconfig  |   3 +-
 configs/ls1046aqds_lpuart_defconfig   |   3 +-
 configs/ls1046aqds_nand_defconfig |   3 +-
 configs/ls1046aqds_qspi_defconfig |   3 +-
 configs/ls1046aqds_sdcard_ifc_defconfig   |   3 +-
 configs/ls1046aqds_sdcard_qspi_defconfig  |   3 +-
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig  |   3 +-
 configs/ls1046aqds_tfa_defconfig  |   3 +-
 configs/ls1046ardb_emmc_defconfig |   3 +-
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |   3 +-
 configs/ls1046ardb_qspi_defconfig |   3 +-
 configs/ls1046ardb_qspi_spl_defconfig |   3 +-
 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig   |   3 +-
 configs/ls1046ardb_sdcard_defconfig   |   3 +-
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig  |   3 +-
 configs/ls1046ardb_tfa_defconfig  |   3 +-
 configs/ls1088aqds_defconfig  |   2 +-
 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig |   2 +-
 configs/ls1088aqds_qspi_defconfig |   2 +-
 configs/ls1088aqds_s

[PATCHv2 02/10] pci_ep: Add the init function

[Zhiqiang Hou]

From: Xiaowei Bao 

Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 common/board_r.c | 12 
 drivers/pci_endpoint/pci_ep-uclass.c | 11 +++
 include/init.h   |  1 +
 3 files changed, 24 insertions(+)

diff --git a/common/board_r.c b/common/board_r.c
index fa57fa9b69..d4db44fc59 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -233,6 +233,15 @@ static int initr_unlock_ram_in_cache(void)
 }
 #endif
 
+#ifdef CONFIG_PCI_ENDPOINT
+static int initr_pci_ep(void)
+{
+   pci_ep_init();
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_PCI
 static int initr_pci(void)
 {
@@ -830,6 +839,9 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_BITBANGMII
initr_bbmii,
 #endif
+#ifdef CONFIG_PCI_ENDPOINT
+   initr_pci_ep,
+#endif
 #ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
initr_net,
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c 
b/drivers/pci_endpoint/pci_ep-uclass.c
index 9f53a9a9b9..38a5f08376 100644
--- a/drivers/pci_endpoint/pci_ep-uclass.c
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -209,3 +209,14 @@ UCLASS_DRIVER(pci_ep) = {
.name   = "pci_ep",
.flags  = DM_UC_FLAG_SEQ_ALIAS,
 };
+
+void pci_ep_init(void)
+{
+   struct udevice *dev;
+
+   for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
+dev;
+uclass_next_device_check(&dev)) {
+   ;
+   }
+}
diff --git a/include/init.h b/include/init.h
index b5a167b6ed..2d79afc381 100644
--- a/include/init.h
+++ b/include/init.h
@@ -213,6 +213,7 @@ int set_cpu_clk_info(void);
 int update_flash_size(int flash_size);
 int arch_early_init_r(void);
 void pci_init(void);
+void pci_ep_init(void);
 int misc_init_r(void);
 #if defined(CONFIG_VID)
 int init_func_vid(void);
-- 
2.17.1

[PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node

[Zhiqiang Hou]

From: Xiaowei Bao 

Add the PCIe EP node for ls1046a.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 arch/arm/dts/fsl-ls1046a.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5db2a..3f11d6cd18 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -257,6 +257,17 @@
  0x8200 0x0 0x4000 0x40 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
+   pcie_ep@340 {
+   compatible = "fsl,ls-pcie-ep";
+   reg = <0x00 0x0340 0x0 0x8
+  0x00 0x034c 0x0 0x4
+  0x40 0x 0x8 0x>;
+   reg-names = "regs", "ctrl", "addr_space";
+   num-ib-windows = <6>;
+   num-ob-windows = <8>;
+   big-endian;
+   };
+
pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8   /* dbi registers */
@@ -274,6 +285,17 @@
  0x8200 0x0 0x4000 0x48 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
+   pcie_ep@350 {
+   compatible = "fsl,ls-pcie-ep";
+   reg = <0x00 0x0350 0x0 0x8
+  0x00 0x035c 0x0 0x4
+  0x48 0x 0x8 0x>;
+   reg-names = "regs", "ctrl", "addr_space";
+   num-ib-windows = <6>;
+   num-ob-windows = <8>;
+   big-endian;
+   };
+
pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8   /* dbi registers */
@@ -290,6 +312,17 @@
  0x8200 0x0 0x4000 0x50 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
+   pcie_ep@360 {
+   compatible = "fsl,ls-pcie-ep";
+   reg = <0x00 0x0360 0x0 0x8
+  0x00 0x036c 0x0 0x4
+  0x50 0x 0x8 0x>;
+   reg-names = "regs", "ctrl", "addr_space";
+   num-ib-windows = <6>;
+   num-ob-windows = <8>;
+   big-endian;
+   };
+
sata: sata@320 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x320 0x0 0x1 /* ccsr sata base */
-- 
2.17.1

[PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support

[Zhiqiang Hou]

From: Xiaowei Bao 

Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape.c|   6 +-
 drivers/pci/pcie_layerscape.h|  21 --
 drivers/pci/pcie_layerscape_ep.c | 119 +--
 3 files changed, 98 insertions(+), 48 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 93018feb7c..ea0fc43441 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -108,13 +108,13 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int 
idx, int type,
 }
 
 /* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
-int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+int idx, int bar, u64 phys)
 {
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
-   dbi_writel(pcie, type, PCIE_ATU_CR1);
+   dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 217dcda6d1..dabfff32db 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -9,6 +9,7 @@
 #define _PCIE_LAYERSCAPE_H_
 #include 
 #include 
+#include 
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -44,6 +45,7 @@
 #define PCIE_ATU_TYPE_IO   (0x2 << 0)
 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_FUNC_NUM(pf)  ((pf) << 20)
 #define PCIE_ATU_CR2   0x908
 #define PCIE_ATU_ENABLE(0x1 << 31)
 #define PCIE_ATU_BAR_MODE_ENABLE   (0x1 << 30)
@@ -86,11 +88,16 @@
 #define FSL_PCIE_EP_MIN_APERTURE4096 /* 4 Kbytes */
 #define PCIE_PF_NUM2
 #define PCIE_VF_NUM64
+#define BAR_NUM4
 
-#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#define PCIE_BAR0_SIZE SZ_4K
+#define PCIE_BAR1_SIZE SZ_8K
+#define PCIE_BAR2_SIZE SZ_4K
+#define PCIE_BAR4_SIZE SZ_1M
+
+#define PCIE_SRIOV_VFBAR0  0x19C
+
+#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x2 * (pf)))
 
 /* LUT registers */
 #define PCIE_LUT_UDR(n)(0x800 + (n) * 8)
@@ -158,6 +165,8 @@ struct ls_pcie_ep {
struct ls_pcie *pcie;
struct udevice *bus;
void __iomem *addr;
+   u32 cfg2_flag;
+   u32 sriov_flag;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
@@ -171,8 +180,8 @@ unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int 
offset);
 void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int 
offset);
 void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
  u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
-int bar, u64 phys);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+int idx, int bar, u64 phys);
 void ls_pcie_dump_atu(struct ls_pcie *pcie);
 int ls_pcie_link_up(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index b463a7734a..e609607c3a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct 
pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
 
-   ls_pcie_atu_inbound_set(pcie, idx, bar, bar_phys, type);
+   ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
 
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -64,51 +64,61 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
.set_bar = ls_ep_set_bar,
 };
 
-static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep)
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
 {
struct ls_pcie *pcie = pcie_ep->pcie;
-   u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+   u64 phys = 0;
 
+   phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+
+   phys = ALIGN(phy

[PATCHv2 01/10] pci: layerscape: Split the EP and RC driver

[Zhiqiang Hou]

From: Xiaowei Bao 

Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/Makefile|   2 +-
 drivers/pci/pcie_layerscape.c   | 487 ++--
 drivers/pci/pcie_layerscape.h   |  44 ++-
 drivers/pci/pcie_layerscape_ep.c| 241 ++
 drivers/pci/pcie_layerscape_fixup.c |  79 +++--
 drivers/pci/pcie_layerscape_rc.c| 379 ++
 6 files changed, 735 insertions(+), 497 deletions(-)
 create mode 100644 drivers/pci/pcie_layerscape_ep.c
 create mode 100644 drivers/pci/pcie_layerscape_rc.c

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc9f3..440b5af588 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,7 +33,7 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o pcie_layerscape_rc.o 
pcie_layerscape_ep.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o 
pcie_layerscape_fixup_common.o
 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o \
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 39b6d40802..93018feb7c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,18 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
-#include 
 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
defined(CONFIG_ARM)
 #include 
@@ -23,18 +20,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 LIST_HEAD(ls_pcie_list);
 
-static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
 {
return in_le32(pcie->dbi + offset);
 }
 
-static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
-  unsigned int offset)
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
 {
out_le32(pcie->dbi + offset, value);
 }
 
-static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
 {
if (pcie->big_endian)
return in_be32(pcie->ctrl + offset);
@@ -42,8 +38,8 @@ static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned 
int offset)
return in_le32(pcie->ctrl + offset);
 }
 
-static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
-   unsigned int offset)
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+unsigned int offset)
 {
if (pcie->big_endian)
out_be32(pcie->ctrl + offset, value);
@@ -51,6 +47,26 @@ static void ctrl_writel(struct ls_pcie *pcie, unsigned int 
value,
out_le32(pcie->ctrl + offset, value);
 }
 
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
+{
+   u32 reg, val;
+
+   reg = PCIE_MISC_CONTROL_1_OFF;
+   val = dbi_readl(pcie, reg);
+   val |= PCIE_DBI_RO_WR_EN;
+   dbi_writel(pcie, val, reg);
+}
+
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
+{
+   u32 reg, val;
+
+   reg = PCIE_MISC_CONTROL_1_OFF;
+   val = dbi_readl(pcie, reg);
+   val &= ~PCIE_DBI_RO_WR_EN;
+   dbi_writel(pcie, val, reg);
+}
+
 static int ls_pcie_ltssm(struct ls_pcie *pcie)
 {
u32 state;
@@ -67,7 +83,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
return state;
 }
 
-static int ls_pcie_link_up(struct ls_pcie *pcie)
+int ls_pcie_link_up(struct ls_pcie *pcie)
 {
int ltssm;
 
@@ -78,22 +94,8 @@ static int ls_pcie_link_up(struct ls_pcie *pcie)
return 1;
 }
 
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-   dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-  PCIE_ATU_VIEWPORT);
-   dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-   dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-  PCIE_ATU_VIEWPORT);
-   dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size)
 {
dbi_writel(pcie, PC

[PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460

[Zhiqiang Hou]

From: Xiaowei Bao 

The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape_ep.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index e609607c3a..3f22c5ef7a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -164,6 +164,15 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
pcie_ep->sriov_flag = 1;
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+   /*
+* The VF_BARn_REG register's Prefetchable and Type bit
+* fields are overwritten by a write to VF's BAR Mask
+* register. Before writing to the VF_BARn_MASK_REG
+* register, write 0b to the PCIE_MISC_CONTROL_1_OFF
+* register.
+*/
+   writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+
if (pcie_ep->cfg2_flag) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
-- 
2.17.1

[PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode

[Zhiqiang Hou]

From: Xiaowei Bao 

Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape_ep.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 3f22c5ef7a..20de056b8a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -173,17 +173,25 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
 */
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
 
+   bar_base = pcie->dbi +
+  PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+
if (pcie_ep->cfg2_flag) {
-   for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+   ctrl_writel(pcie,
+   PCIE_LCTRL0_VAL(pf, 0),
+   PCIE_PF_VF_CTRL);
+   ls_pcie_ep_setup_bars(bar_base);
+
+   for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
PCIE_LCTRL0_VAL(pf, vf),
PCIE_PF_VF_CTRL);
+   ls_pcie_ep_setup_vf_bars(bar_base);
}
+   } else {
+   ls_pcie_ep_setup_bars(bar_base);
+   ls_pcie_ep_setup_vf_bars(bar_base);
}
-   bar_base = pcie->dbi +
-  PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
-   ls_pcie_ep_setup_bars(bar_base);
-   ls_pcie_ep_setup_vf_bars(bar_base);
 
ls_pcie_ep_setup_atu(pcie_ep, pf);
}
-- 
2.17.1

[PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function

[Zhiqiang Hou]

From: Xiaowei Bao 

Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape.c| 25 +
 drivers/pci/pcie_layerscape.h|  2 +-
 drivers/pci/pcie_layerscape_ep.c |  3 +++
 drivers/pci/pcie_layerscape_rc.c |  2 +-
 4 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0116af8aa5..25b5272d4e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -121,24 +121,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 
pf, u32 vf_flag,
   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
 
-void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
 {
-   int i;
+   int win_idx;
 
-   for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
-   dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
-  PCIE_ATU_VIEWPORT);
-   debug("iATU%d:\n", i);
+   for (win_idx = 0; win_idx < win_num; win_idx++) {
+   dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+   debug("iATU%d:\n", win_idx);
debug("\tLOWER PHYS 0x%08x\n",
  dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
  dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
-   debug("\tLOWER BUS  0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
-   debug("\tUPPER BUS  0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
-   debug("\tLIMIT  0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LIMIT));
+   if (type == PCIE_ATU_REGION_OUTBOUND) {
+   debug("\tLOWER BUS  0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+   debug("\tUPPER BUS  0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+   debug("\tLIMIT  0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LIMIT));
+   }
debug("\tCR10x%08x\n",
  dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR20x%08x\n",
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 26d0177ca2..5f5c51d3d6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -185,7 +185,7 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int 
idx, int type,
  u64 phys, u64 bus_addr, u64 size);
 void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
 int type, int idx, int bar, u64 phys);
-void ls_pcie_dump_atu(struct ls_pcie *pcie);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
 int ls_pcie_link_up(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index cbf73e72c1..52d6397064 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -227,6 +227,9 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
ls_pcie_ep_setup_atu(pcie_ep, 0);
}
 
+   ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+PCIE_ATU_REGION_INBOUND);
+
ls_pcie_ep_enable_cfg(pcie_ep);
 }
 
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index e922e5dbcd..25c6ddebce 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -115,7 +115,7 @@ static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
 pref->bus_start,
 pref->size);
 
-   ls_pcie_dump_atu(pcie);
+   ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
 }
 
 /* Return 0 if the address is valid, -errno if not valid */
-- 
2.17.1

[PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support

[Zhiqiang Hou]

From: Xiaowei Bao 

Add the INBOUND configuration for VFs of PF.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape.c|  8 +---
 drivers/pci/pcie_layerscape.h| 13 +++-
 drivers/pci/pcie_layerscape_ep.c | 34 +++-
 3 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index ea0fc43441..0116af8aa5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -95,7 +95,7 @@ int ls_pcie_link_up(struct ls_pcie *pcie)
 }
 
 void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+ u64 phys, u64 bus_addr, u64 size)
 {
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
@@ -108,14 +108,16 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int 
idx, int type,
 }
 
 /* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
-int idx, int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+int type, int idx, int bar, u64 phys)
 {
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+  (vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
+  (vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
 
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index dabfff32db..26d0177ca2 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -20,7 +20,7 @@
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
 #endif
 
 #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
@@ -40,6 +40,7 @@
 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
 #define PCIE_ATU_REGION_NUM6
+#define PCIE_ATU_REGION_NUM_SRIOV  24
 #define PCIE_ATU_CR1   0x904
 #define PCIE_ATU_TYPE_MEM  (0x0 << 0)
 #define PCIE_ATU_TYPE_IO   (0x2 << 0)
@@ -49,6 +50,8 @@
 #define PCIE_ATU_CR2   0x908
 #define PCIE_ATU_ENABLE(0x1 << 31)
 #define PCIE_ATU_BAR_MODE_ENABLE   (0x1 << 30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_EN   BIT(26)
 #define PCIE_ATU_BAR_NUM(bar)  ((bar) << 8)
 #define PCIE_ATU_LOWER_BASE0x90C
 #define PCIE_ATU_UPPER_BASE0x910
@@ -88,7 +91,7 @@
 #define FSL_PCIE_EP_MIN_APERTURE4096 /* 4 Kbytes */
 #define PCIE_PF_NUM2
 #define PCIE_VF_NUM64
-#define BAR_NUM4
+#define BAR_NUM8
 
 #define PCIE_BAR0_SIZE SZ_4K
 #define PCIE_BAR1_SIZE SZ_8K
@@ -179,9 +182,9 @@ void dbi_writel(struct ls_pcie *pcie, unsigned int value, 
unsigned int offset);
 unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
 void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int 
offset);
 void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
-int idx, int bar, u64 phys);
+ u64 phys, u64 bus_addr, u64 size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+int type, int idx, int bar, u64 phys);
 void ls_pcie_dump_atu(struct ls_pcie *pcie);
 int ls_pcie_link_up(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 20de056b8a..cbf73e72c1 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct 
pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
 
-   ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
+   ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
 
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -67,27 +67,51 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
 static void ls_pc

[PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2

[Zhiqiang Hou]

From: Xiaowei Bao 

Add the PCIe EP mode support for lx2160a-v2 platform.

Signed-off-by: Xiaowei Bao 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape.h| 9 -
 drivers/pci/pcie_layerscape_ep.c | 8 +++-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 5f5c51d3d6..593798e3e3 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -100,7 +100,7 @@
 
 #define PCIE_SRIOV_VFBAR0  0x19C
 
-#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x2 * (pf)))
+#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
 
 /* LUT registers */
 #define PCIE_LUT_UDR(n)(0x800 + (n) * 8)
@@ -139,6 +139,12 @@
 #define LS1021_PEXMSCPORTSR(pex_idx)   (0x94 + (pex_idx) * 4)
 #define LS1021_LTSSM_STATE_SHIFT   20
 
+/* LX2160a PF1 offset */
+#define LX2160_PCIE_PF1_OFFSET 0x8000
+
+/* layerscape PF1 offset */
+#define LS_PCIE_PF1_OFFSET 0x2
+
 struct ls_pcie {
void __iomem *dbi;
void __iomem *lut;
@@ -170,6 +176,7 @@ struct ls_pcie_ep {
void __iomem *addr;
u32 cfg2_flag;
u32 sriov_flag;
+   u32 pf1_offset;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 52d6397064..eba230e3a5 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -198,7 +198,8 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
 
bar_base = pcie->dbi +
-  PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+  PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
+   pcie_ep->pf1_offset);
 
if (pcie_ep->cfg2_flag) {
ctrl_writel(pcie,
@@ -271,6 +272,11 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 
svr = SVR_SOC_VER(get_svr());
 
+   if (svr == SVR_LX2160A)
+   pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
+   else
+   pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
+
if (svr == SVR_LS2080A || svr == SVR_LS2085A)
pcie_ep->cfg2_flag = 1;
else
-- 
2.17.1

Re: [PATCH v6 4/4] usb: xhci: Add reset controller support

[Matthias Brugger]

On 29/06/2020 18:37, Nicolas Saenz Julienne wrote:

Some atypical users of xhci might need to manually reset their xHCI
controller before starting the HCD setup. Check if a reset controller
device is available to the PCI bus and trigger a reset.

Signed-off-by: Nicolas Saenz Julienne 

---
Changes since v5:
  - Take !CONFIG_IS_ENABLED(DM_RESET) into account

  drivers/usb/host/xhci-mem.c |  2 ++
  drivers/usb/host/xhci.c | 33 +
  include/usb/xhci.h  |  2 ++
  3 files changed, 37 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index f446520528..108f4bd8cf 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl)
xhci_free_virt_devices(ctrl);
free(ctrl->erst.entries);
free(ctrl->dcbaa);
+   if (reset_valid(&ctrl->reset))
+   reset_free(&ctrl->reset);
memset(ctrl, '\0', sizeof(struct xhci_ctrl));
  }
  
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c

index ebd2954571..e252964d0d 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -190,6 +190,35 @@ static int xhci_start(struct xhci_hcor *hcor)
return ret;
  }
  
+/**

+ * Resets XHCI Hardware
+ *
+ * @param ctrl pointer to host controller
+ * @return 0 if OK, or a negative error code.
+ */
+static int xhci_reset_hw(struct xhci_ctrl *ctrl)
+{
+   int ret;
+
+   ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);


That seems to break arm32 builds:
https://pastebin.com/eHBf7Xp0
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi/-/jobs/121247

Nicolas, can you have a look?

Thanks
Matthias


+   if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
+   dev_err(ctrl->dev, "failed to get reset\n");
+   return ret;
+   }
+
+   if (reset_valid(&ctrl->reset)) {
+   ret = reset_assert(&ctrl->reset);
+   if (ret)
+   return ret;
+
+   ret = reset_deassert(&ctrl->reset);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
  /**
   * Resets the XHCI Controller
   *
@@ -1508,6 +1537,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr 
*hccr,
  
  	ctrl->dev = dev;
  
+	ret = xhci_reset_hw(ctrl);

+   if (ret)
+   goto err;
+
/*
 * XHCI needs to issue a Address device command to setup
 * proper device context structures, before it can interact
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 1170c0ac69..7d34103fd5 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -16,6 +16,7 @@
  #ifndef HOST_XHCI_H_
  #define HOST_XHCI_H_
  
+#include 

  #include 
  #include 
  #include 
@@ -1209,6 +1210,7 @@ struct xhci_ctrl {
  #if CONFIG_IS_ENABLED(DM_USB)
struct udevice *dev;
  #endif
+   struct reset_ctl reset;
struct xhci_hccr *hccr; /* R/O registers, not need for volatile */
struct xhci_hcor *hcor;
struct xhci_doorbell_array *dba;

[PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver

[Zhiqiang Hou]

From: Hou Zhiqiang 

Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.

Signed-off-by: Hou Zhiqiang 
---
V2:
 - New patch.

 configs/ls1012afrdm_qspi_defconfig|  2 +-
 configs/ls1012afrdm_tfa_defconfig |  2 +-
 .../ls1012afrwy_qspi_SECURE_BOOT_defconfig|  2 +-
 configs/ls1012afrwy_qspi_defconfig|  2 +-
 configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig |  2 +-
 configs/ls1012afrwy_tfa_defconfig |  2 +-
 configs/ls1012aqds_qspi_defconfig |  2 +-
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1012aqds_tfa_defconfig  |  2 +-
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |  2 +-
 configs/ls1012ardb_qspi_defconfig |  2 +-
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1012ardb_tfa_defconfig  |  2 +-
 configs/ls1021aiot_qspi_defconfig |  2 +-
 configs/ls1021aiot_sdcard_defconfig   |  2 +-
 configs/ls1021aqds_ddr4_nor_defconfig |  2 +-
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig  |  2 +-
 configs/ls1021aqds_nand_defconfig |  2 +-
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1021aqds_nor_defconfig  |  2 +-
 configs/ls1021aqds_nor_lpuart_defconfig   |  2 +-
 configs/ls1021aqds_qspi_defconfig |  2 +-
 configs/ls1021aqds_sdcard_ifc_defconfig   |  2 +-
 configs/ls1021aqds_sdcard_qspi_defconfig  |  2 +-
 configs/ls1021atsn_qspi_defconfig |  2 +-
 configs/ls1021atsn_sdcard_defconfig   |  2 +-
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1021atwr_nor_defconfig  |  2 +-
 configs/ls1021atwr_nor_lpuart_defconfig   |  2 +-
 configs/ls1021atwr_qspi_defconfig |  2 +-
 ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |  2 +-
 configs/ls1021atwr_sdcard_ifc_defconfig   |  2 +-
 configs/ls1021atwr_sdcard_qspi_defconfig  |  2 +-
 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1028aqds_tfa_defconfig  |  2 +-
 configs/ls1028aqds_tfa_lpuart_defconfig   |  2 +-
 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1028ardb_tfa_defconfig  |  2 +-
 configs/ls1043aqds_defconfig  |  2 +-
 configs/ls1043aqds_lpuart_defconfig   |  2 +-
 configs/ls1043aqds_nand_defconfig |  2 +-
 configs/ls1043aqds_nor_ddr3_defconfig |  2 +-
 configs/ls1043aqds_qspi_defconfig |  2 +-
 configs/ls1043aqds_sdcard_ifc_defconfig   |  2 +-
 configs/ls1043aqds_sdcard_qspi_defconfig  |  2 +-
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1043aqds_tfa_defconfig  |  2 +-
 configs/ls1043ardb_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1043ardb_defconfig  |  2 +-
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig |  2 +-
 configs/ls1043ardb_nand_defconfig |  2 +-
 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig   |  2 +-
 configs/ls1043ardb_sdcard_defconfig   |  2 +-
 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1043ardb_tfa_defconfig  |  2 +-
 configs/ls1046afrwy_tfa_defconfig |  3 +-
 configs/ls1046aqds_SECURE_BOOT_defconfig  |  3 +-
 configs/ls1046aqds_defconfig  |  3 +-
 configs/ls1046aqds_lpuart_defconfig   |  3 +-
 configs/ls1046aqds_nand_defconfig |  3 +-
 configs/ls1046aqds_qspi_defconfig |  3 +-
 configs/ls1046aqds_sdcard_ifc_defconfig   |  3 +-
 configs/ls1046aqds_sdcard_qspi_defconfig  |  3 +-
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig  |  3 +-
 configs/ls1046aqds_tfa_defconfig  |  3 +-
 configs/ls1046ardb_emmc_defconfig |  3 +-
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |  3 +-
 configs/ls1046ardb_qspi_defconfig |  3 +-
 configs/ls1046ardb_qspi_spl_defconfig |  3 +-
 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig   |  3 +-
 configs/ls1046ardb_sdcard_defconfig   |  3 +-
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig  |  3 +-
 configs/ls1046ardb_tfa_defconfig  |  3 +-
 configs/ls1088aqds_defconfig  |  2 +-
 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig |  2 +-
 configs/ls1088aqds_qspi_defconfig |  2 +-
 configs/ls1088aqds_sdcard_ifc_defconfig   |  2 +-
 configs/ls1088aqds_sdcard_qspi_defconfig  |  2 +-
 configs/ls1088aqds_tfa_defconfig  |  2 +-
 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig |  2 +-
 configs/ls1088ardb_qspi_defconfig |  2 +-
 ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig |  2 +-
 configs/ls1088ardb_sdcard_qspi_defconfig  |  2 +-
 configs/ls1088ardb_tfa_SECURE_BOOT_defconfig  |  2 +-
 configs/ls1088ardb_tfa_defconfig  |  2 +-
 configs/ls2080aqds_SECURE_BOOT_defconfig  |  2 +-
 configs/ls2080aqds_defconfig  |  2 +-
 conf

[PATCH 3/3] serial: uniphier: enable FIFO

[Masahiro Yamada]

This UART controller is integrated with a FIFO. Enable it.

You can put the next character into the FIFO while the transmitter
is sending out the current character. This works slightly faster.

Signed-off-by: Masahiro Yamada 
---

 drivers/serial/serial_uniphier.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index aaf8657ee1..ad691b66da 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -23,6 +23,7 @@
 #define UNIPHIER_UART_TX   UNIPHIER_UART_RX
 /* bit[15:8] = CHAR, bit[7:0] = FCR */
 #define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
+#define   UNIPHIER_UART_FCR_MASK   GENMASK(7, 0)
 /* bit[15:8] = LCR, bit[7:0] = MCR */
 #define UNIPHIER_UART_LCR_MCR  (4 << (UNIPHIER_UART_REGSHIFT))
 #define   UNIPHIER_UART_LCR_MASK   GENMASK(15, 8)
@@ -140,6 +141,12 @@ static int uniphier_serial_probe(struct udevice *dev)
while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
;
 
+   /* enable FIFO */
+   tmp = readl(priv->membase + UNIPHIER_UART_CHAR_FCR);
+   tmp &= ~UNIPHIER_UART_FCR_MASK;
+   tmp |= FIELD_PREP(UNIPHIER_UART_FCR_MASK, UART_FCR_ENABLE_FIFO);
+   writel(tmp, priv->membase + UNIPHIER_UART_CHAR_FCR);
+
tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR);
tmp &= ~UNIPHIER_UART_LCR_MASK;
tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8);
-- 
2.25.1

[PATCH 2/3] serial: uniphier: flush transmitter before changing hardware settings

[Masahiro Yamada]

Ensure the transmitter is empty when chaining the baudrate or any
hardware settings. If a character is remaining in the transmitter,
the console will be garbled.

Signed-off-by: Masahiro Yamada 
---

 drivers/serial/serial_uniphier.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 2ffab004bd..aaf8657ee1 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -43,6 +43,10 @@ static int uniphier_serial_setbrg(struct udevice *dev, int 
baudrate)
 
divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
 
+   /* flush the trasmitter before changing hw setting */
+   while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
+   ;
+
writel(divisor, priv->membase + UNIPHIER_UART_DLR);
 
return 0;
@@ -132,6 +136,10 @@ static int uniphier_serial_probe(struct udevice *dev)
 
priv->uartclk = clk_data->clk_rate;
 
+   /* flush the trasmitter empty before changing hw setting */
+   while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
+   ;
+
tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR);
tmp &= ~UNIPHIER_UART_LCR_MASK;
tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8);
-- 
2.25.1

Pull request for UEFI sub-system for efi-2020-10-rc1 (2)

[Heinrich Schuchardt]

The following changes since commit 61608f395e7dcb2be6060407a72a1149b046430a:

  Merge branch '2020-07-08-misc-features-and-fixes' (2020-07-08 20:20:24
-0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git efi-2020-10-rc1-2

for you to fetch changes up to f4cef8e7585c268f05a8c39e368ca115c25e40d5:

  efi_selftest: adjust runtime test for variables (2020-07-09 12:08:41
+0200)


Pull request for UEFI sub-system for efi-2020-10-rc1 (2)

Up to now UEFI variables where stored in U-Boot environment variables.
Saving UEFI variables was not possible without saving the U-Boot
environment variables. With this patch series file ubootefi.var in the
EFI system partition is used for saving UEFI variables. Furthermore the
UEFI variables are exposed for reading at runtime.

Code corrections for UEFI secure boot are provided.

A buffer overrun in the RSA library is fixed.


AKASHI Takahiro (13):
  efi_loader: image_loader: add a check against certificate type of
authenticode
  efi_loader: image_loader: retrieve authenticode only if it exists
  efi_loader: signature: fix a size check against revocation list
  efi_loader: signature: make efi_hash_regions more generic
  efi_loader: image_loader: verification for all signatures should pass
  efi_loader: image_loader: add digest-based verification for signed
image
  test/py: efi_secboot: apply autopep8
  test/py: efi_secboot: more fixes against pylint
  test/py: efi_secboot: split "signed image" test case-1 into two cases
  test/py: efi_secboot: add a test against certificate revocation
  test/py: efi_secboot: add a test for multiple signatures
  test/py: efi_secboot: add a test for verifying with digest of
signed image
  lib: rsa: export rsa_verify_with_pkey()

Heinrich Schuchardt (22):
  lib/crypto: use qualified path for x509_parser.h
  efi_loader: wrong printf format in efi_image_parse
  efi_loader: fix efi_get_child_controllers()
  efi_loader: NULL dereference in efi_convert_pointer
  fs/fat: reduce data size for FAT_WRITE
  efi_loader: prepare for read only OP-TEE variables
  efi_loader: display RO attribute in printenv -e
  efi_loader: separate UEFI variable API from implemementation
  efi_loader: OsIndicationsSupported, PlatformLangCodes
  efi_loader: simplify boot manager
  efi_loader: keep attributes in efi_set_variable_int
  efi_loader: value of VendorKeys
  efi_loader: read-only AuditMode and DeployedMode
  efi_loader: secure boot flag
  efi_loader: UEFI variable persistence
  efi_loader: export efi_convert_pointer()
  efi_loader: optional pointer for ConvertPointer
  efi_loader: new function efi_memcpy_runtime()
  efi_loader: memory buffer for variables
  efi_loader: use memory based variable storage
  efi_loader: enable UEFI variables at runtime
  efi_selftest: adjust runtime test for variables

Ilias Apalodimas (1):
  efi_loader: cleanup for tee backed variables

 cmd/nvedit_efi.c  |  24 +-
 doc/api/efi.rst   |   2 +
 fs/fat/fat_write.c|   9 +-
 include/crypto/pkcs7_parser.h |   2 +-
 include/efi_api.h |   2 +
 include/efi_loader.h  |  21 +-
 include/efi_variable.h| 198 ++
 include/u-boot/rsa.h  |   3 +
 lib/efi_loader/Kconfig|   8 +
 lib/efi_loader/Makefile   |   3 +
 lib/efi_loader/efi_bootmgr.c  |  28 +-
 lib/efi_loader/efi_boottime.c |  12 +-
 lib/efi_loader/efi_image_loader.c | 164 +++--
 lib/efi_loader/efi_runtime.c  |  38 +-
 lib/efi_loader/efi_setup.c|  59 +-
 lib/efi_loader/efi_signature.c| 435 ++--
 lib/efi_loader/efi_var_common.c   | 140 
 lib/efi_loader/efi_var_file.c | 239 +++
 lib/efi_loader/efi_var_mem.c  | 266 +++
 lib/efi_loader/efi_variable.c | 830
+-
 lib/efi_loader/efi_variable_tee.c | 138 +---
 lib/efi_selftest/efi_selftest_variables_runtime.c |  13 +-
 lib/rsa/rsa-verify.c  |   8 +-
 test/py/tests/test_efi_secboot/conftest.py| 104 +--
 test/py/tests/test_efi_secboot/defs.py|  14 +-
 test/py/tests/test_efi_secboot/test_authvar.py|  92 +--
 test/py/tests/test_efi_secboot/test_signed.py | 206 +-
 test/py/tests/test_efi_secboot/test_unsigned.py   |  66 +-
 28 files changed, 1867 insertions(+), 1257 deletions(-)
 create mode 100644 include/e

[PATCH 1/3] serial: uniphier: use register macros instead of structure

[Masahiro Yamada]

After all, I am not a big fan of using a structure to represent the
hardware register map.

You do not need to know the entire register map.

Add only necessary register macros.

Use FIELD_PREP() instead of maintaining a pair of shift and mask.

Signed-off-by: Masahiro Yamada 
---

 drivers/serial/serial_uniphier.c | 75 ++--
 1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index c7f46e5598..2ffab004bd 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -7,6 +7,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -15,77 +17,67 @@
 #include 
 #include 
 
-/*
- * Note: Register map is slightly different from that of 16550.
- */
-struct uniphier_serial {
-   u32 rx; /* In:  Receive buffer */
-#define tx rx  /* Out: Transmit buffer */
-   u32 ier;/* Interrupt Enable Register */
-   u32 iir;/* In: Interrupt ID Register */
-   u32 char_fcr;   /* Charactor / FIFO Control Register */
-   u32 lcr_mcr;/* Line/Modem Control Register */
-#define LCR_SHIFT  8
-#define LCR_MASK   (0xff << (LCR_SHIFT))
-   u32 lsr;/* In: Line Status Register */
-   u32 msr;/* In: Modem Status Register */
-   u32 __rsv0;
-   u32 __rsv1;
-   u32 dlr;/* Divisor Latch Register */
-};
+#define UNIPHIER_UART_REGSHIFT 2
+
+#define UNIPHIER_UART_RX   (0 << (UNIPHIER_UART_REGSHIFT))
+#define UNIPHIER_UART_TX   UNIPHIER_UART_RX
+/* bit[15:8] = CHAR, bit[7:0] = FCR */
+#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
+/* bit[15:8] = LCR, bit[7:0] = MCR */
+#define UNIPHIER_UART_LCR_MCR  (4 << (UNIPHIER_UART_REGSHIFT))
+#define   UNIPHIER_UART_LCR_MASK   GENMASK(15, 8)
+#define UNIPHIER_UART_LSR  (5 << (UNIPHIER_UART_REGSHIFT))
+/* Divisor Latch Register */
+#define UNIPHIER_UART_DLR  (9 << (UNIPHIER_UART_REGSHIFT))
 
 struct uniphier_serial_priv {
-   struct uniphier_serial __iomem *membase;
+   void __iomem *membase;
unsigned int uartclk;
 };
 
-#define uniphier_serial_port(dev)  \
-   ((struct uniphier_serial_priv *)dev_get_priv(dev))->membase
-
 static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
 {
struct uniphier_serial_priv *priv = dev_get_priv(dev);
-   struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
-   const unsigned int mode_x_div = 16;
+   static const unsigned int mode_x_div = 16;
unsigned int divisor;
 
divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
 
-   writel(divisor, &port->dlr);
+   writel(divisor, priv->membase + UNIPHIER_UART_DLR);
 
return 0;
 }
 
 static int uniphier_serial_getc(struct udevice *dev)
 {
-   struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+   struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
-   if (!(readl(&port->lsr) & UART_LSR_DR))
+   if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR))
return -EAGAIN;
 
-   return readl(&port->rx);
+   return readl(priv->membase + UNIPHIER_UART_RX);
 }
 
 static int uniphier_serial_putc(struct udevice *dev, const char c)
 {
-   struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+   struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
-   if (!(readl(&port->lsr) & UART_LSR_THRE))
+   if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE))
return -EAGAIN;
 
-   writel(c, &port->tx);
+   writel(c, priv->membase + UNIPHIER_UART_TX);
 
return 0;
 }
 
 static int uniphier_serial_pending(struct udevice *dev, bool input)
 {
-   struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+   struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
if (input)
-   return readl(&port->lsr) & UART_LSR_DR;
+   return readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR;
else
-   return !(readl(&port->lsr) & UART_LSR_THRE);
+   return !(readl(priv->membase + UNIPHIER_UART_LSR) & 
UART_LSR_THRE);
 }
 
 /*
@@ -113,7 +105,6 @@ static const struct uniphier_serial_clk_data 
uniphier_serial_clk_data[] = {
 static int uniphier_serial_probe(struct udevice *dev)
 {
struct uniphier_serial_priv *priv = dev_get_priv(dev);
-   struct uniphier_serial __iomem *port;
const struct uniphier_serial_clk_data *clk_data;
ofnode root_node;
fdt_addr_t base;
@@ -123,12 +114,10 @@ static int uniphier_serial_probe(struct udevice *dev)
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
 
-   port = devm_ioremap(dev, base, SZ_64);
-   if (!port)
+

Re: [PATCH 2/2] mtd: nand: raw: denali: Wait for reset completion status

[Masahiro Yamada]

On Mon, Jun 29, 2020 at 7:12 PM Ley Foon Tan  wrote:
>
> Fixed delay 200us is not working in certain platforms. Change to
> poll for reset completion status to have more reliable reset process.
>
> Controller will set the rst_comp bit in intr_status register after
> controller has completed its reset and initialization process.
>
> Signed-off-by: Radu Bacrau 
> Signed-off-by: Ley Foon Tan 
> ---
>  drivers/mtd/nand/raw/denali.c| 11 +++
>  drivers/mtd/nand/raw/denali.h|  1 +
>  drivers/mtd/nand/raw/denali_dt.c | 10 +++---
>  3 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
> index 15e90291de09..ab91db85467d 100644
> --- a/drivers/mtd/nand/raw/denali.c
> +++ b/drivers/mtd/nand/raw/denali.c
> @@ -1220,6 +1220,17 @@ static int denali_multidev_fixup(struct 
> denali_nand_info *denali)
> return 0;
>  }
>
> +int denali_wait_reset_complete(struct denali_nand_info *denali)
> +{
> +   u32 irq_status;
> +
> +   irq_status = denali_wait_for_irq(denali, INTR__RST_COMP);
> +   if (!(irq_status & INTR__RST_COMP))
> +   return -EIO;
> +
> +   return 0;
> +}
> +
>  int denali_init(struct denali_nand_info *denali)
>  {
> struct nand_chip *chip = &denali->nand;
> diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
> index 019deda094e5..6cd02b2e26ee 100644
> --- a/drivers/mtd/nand/raw/denali.h
> +++ b/drivers/mtd/nand/raw/denali.h
> @@ -321,6 +321,7 @@ struct denali_nand_info {
>  #define DENALI_CAP_DMA_64BIT   BIT(1)
>
>  int denali_calc_ecc_bytes(int step_size, int strength);
> +int denali_wait_reset_complete(struct denali_nand_info *denali);
>  int denali_init(struct denali_nand_info *denali);
>
>  #endif /* __DENALI_H__ */
> diff --git a/drivers/mtd/nand/raw/denali_dt.c 
> b/drivers/mtd/nand/raw/denali_dt.c
> index 75ad15b0758c..8a6950f8a39f 100644
> --- a/drivers/mtd/nand/raw/denali_dt.c
> +++ b/drivers/mtd/nand/raw/denali_dt.c
> @@ -154,10 +154,14 @@ static int denali_dt_probe(struct udevice *dev)
>
> /*
>  * When the reset is deasserted, the initialization sequence 
> is
> -* kicked (bootstrap process). The driver must wait until it 
> is
> -* finished. Otherwise, it will result in unpredictable 
> behavior.
> +* kicked. The driver must wait until it is finished. 
> Otherwise,
> +* it will result in unpredictable behavior.


What is your motivation for this hunk of change?
(removal of "bootstrap process")

What was wrong with the current comment block?

The term "bootstrap" appears in the
Cadence (Denali) Flash Controller User Guide.




>  */
> -   udelay(200);
> +   ret = denali_wait_reset_complete(denali);
> +   if (ret) {
> +   dev_err(denali->dev, "reset not completed.\n");
> +   return ret;
> +   }
> }
>
> return denali_init(denali);
> --
> 2.19.0
>


I tested this patch on some of my socionext SoC boards,
and I did not see regression.

Tested-by: Masahiro Yamada 


But, please note this code will diverge from the Linux code.


-- 
Best Regards
Masahiro Yamada

Re: [PATCH 1/2] mtd: nand: raw: denali: Assert reset before deassert

[Masahiro Yamada]

On Mon, Jun 29, 2020 at 7:11 PM Ley Foon Tan  wrote:
>
> Always put the controller in reset, then take it out of reset.
> This is to make sure controller always in reset state in both SPL and
> proper Uboot.
>
> This is preparation for the next patch to poll for reset completion
> (rst_comp) bit after reset.
>
> Signed-off-by: Radu Bacrau 
> Signed-off-by: Ley Foon Tan 
> ---
>  drivers/mtd/nand/raw/denali_dt.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/denali_dt.c 
> b/drivers/mtd/nand/raw/denali_dt.c
> index 2728e8098faa..75ad15b0758c 100644
> --- a/drivers/mtd/nand/raw/denali_dt.c
> +++ b/drivers/mtd/nand/raw/denali_dt.c
> @@ -148,6 +148,8 @@ static int denali_dt_probe(struct udevice *dev)
> if (ret) {
> dev_warn(dev, "Can't get reset: %d\n", ret);
> } else {
> +   reset_assert_bulk(&resets);
> +   udelay(2);
> reset_deassert_bulk(&resets);
>
> /*


Tested-by: Masahiro Yamada 


-- 
Best Regards
Masahiro Yamada

Re: [v2] test: Have test_fs work with non-functional guestmount tools

[Stephen Warren]

On 7/9/20 7:42 AM, Tom Rini wrote:
> Since 2011 Ubuntu has intentionally broken support for guestmount[1] by
> default and requires sysadmin intervention to re-enable support.  This
> in turn exposed that in our tests if guestmount is available but fails
> we do not fall back to trying to use sudo.  Restructure our code to try
> sudo if guestmount fails rather than only when it is not in our path.
> Further, only note that we are using fuse on success of the call.
> 
> [1]: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/759725

Reviewed-by: Stephen Warren