[PATCH 0/2] mkimage/rockchip: support packing optional second level boot-loader

2019-12-05 Thread Jeffy Chen


When enabling back-to-bootrom, the bootrom would continue to load the
second level boot-loader. And currently we are packing it by appending
the generated image manually (with a predefined max size):

./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
   firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
   cat firefly-rk3288/u-boot-dtb.bin >> out

This series add support of packing optional second level loader with
mkimage tool:
./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out



Jeffy Chen (2):
  rockchip: mkimage: support packing optional second level boot-loader
  doc: rockchip: document packing second level loader with mkimage

 doc/README.rockchip |  11 +++
 tools/imagetool.h   |   1 +
 tools/mkimage.c |   8 ++
 tools/rkcommon.c| 236 +++-
 tools/rkcommon.h|  18 ++--
 tools/rksd.c|  35 +---
 tools/rkspi.c   |  42 --
 7 files changed, 237 insertions(+), 114 deletions(-)

-- 
2.11.0





RE: [v3 5/8] dm: ls1012a: add i2c DM support

2019-12-05 Thread Priyanka Jain



>-Original Message-
>From: Biwen Li 
>Sent: Thursday, December 5, 2019 11:41 AM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>bhaskar.upadh...@nxp.com; feng.l...@nxp.com; jh80.ch...@samsung.com;
>Pramod Kumar ; Rajesh Bhagat
>; Ruchika Gupta ;
>olte...@gmail.com
>Cc: Xiaobo Xie ; Jiafei Pan ; u-
>b...@lists.denx.de; Biwen Li 
>Subject: [v3 5/8] dm: ls1012a: add i2c DM support
>
>This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A
>
>Signed-off-by: Biwen Li 
>---
>Changes in v3:
>   - none
>
>Changes in v2:
>   - merge some patches to one patch
>
> arch/arm/include/asm/gpio.h   |   1 +
> board/freescale/ls1012aqds/ls1012aqds.c   |  20 ++-
> board/freescale/ls1012ardb/eth.c  |  35 +
> board/freescale/ls1012ardb/ls1012ardb.c   | 147 +++---
> configs/ls1012a2g5rdb_qspi_defconfig  |   3 +
> configs/ls1012a2g5rdb_tfa_defconfig   |   3 +
> configs/ls1012afrdm_qspi_defconfig|   3 +
> configs/ls1012afrdm_tfa_defconfig |   3 +
> .../ls1012afrwy_qspi_SECURE_BOOT_defconfig|   3 +
> configs/ls1012afrwy_qspi_defconfig|   3 +
> configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig |   3 +
> configs/ls1012afrwy_tfa_defconfig |   3 +
> configs/ls1012aqds_qspi_defconfig |   3 +
> configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |   3 +
> configs/ls1012aqds_tfa_defconfig  |   3 +
> configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |   3 +
> configs/ls1012ardb_qspi_defconfig |   3 +
> configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  |   3 +
> configs/ls1012ardb_tfa_defconfig  |   3 +
> include/configs/ls1012a_common.h  |   5 +
> 20 files changed, 227 insertions(+), 26 deletions(-)
>
>diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
>index 6ff5f42424..9f8c9da564 100644
>--- a/arch/arm/include/asm/gpio.h
>+++ b/arch/arm/include/asm/gpio.h
>@@ -3,6 +3,7 @@
>   !defined(CONFIG_ARCH_BCM63158) &&
>!defined(CONFIG_ARCH_ROCKCHIP) && \
>   !defined(CONFIG_ARCH_LX2160A) &&
>!defined(CONFIG_ARCH_LS1028A) && \
>   !defined(CONFIG_ARCH_LS2080A) &&
>!defined(CONFIG_ARCH_LS1088A) && \
>+  !defined(CONFIG_ARCH_LS1012A) && \
>   !defined(CONFIG_ARCH_ASPEED)
> #include 
> #endif
>diff --git a/board/freescale/ls1012aqds/ls1012aqds.c
>b/board/freescale/ls1012aqds/ls1012aqds.c
>index 86c72ee357..30bf1047d5 100644
>--- a/board/freescale/ls1012aqds/ls1012aqds.c
>+++ b/board/freescale/ls1012aqds/ls1012aqds.c
>@@ -107,10 +107,26 @@ int board_early_init_f(void)  int misc_init_r(void)  {
>   u8 mux_sdhc_cd = 0x80;
>-
>-  i2c_set_bus_num(0);
>+  int bus_num = 0;
>+
>+#ifdef CONFIG_DM_I2C
>+  struct udevice *dev;
>+  int ret;
>+
>+  ret = i2c_get_chip_for_busnum(bus_num,
>CONFIG_SYS_I2C_FPGA_ADDR,
>+1, &dev);
>+  if (ret) {
>+  printf("%s: Cannot find udev for a bus %d\n", __func__,
>+ bus_num);
>+  return ret;
>+  }
>+  dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); #else
>+  i2c_set_bus_num(bus_num);
>
>   i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
>+#endif
>+
>   return 0;
> }
> #endif
>diff --git a/board/freescale/ls1012ardb/eth.c
>b/board/freescale/ls1012ardb/eth.c
>index b35d5343e4..0f33128996 100644
>--- a/board/freescale/ls1012ardb/eth.c
>+++ b/board/freescale/ls1012ardb/eth.c
>@@ -27,12 +27,47 @@ static inline void ls1012ardb_reset_phy(void)  {  #ifdef
>CONFIG_TARGET_LS1012ARDB
>   /* Through reset IO expander reset both RGMII and SGMII PHYs */
>+#ifdef CONFIG_DM_I2C
>+  struct udevice *dev;
>+  int ret;
>+
>+  /*
>+   * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number
>is 0).
>+   */
>+  ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
>+1, &dev);
>+  if (ret) {
>+  printf("%s: Cannot find udev for a bus %d\n", __func__,
>+ 0);
>+  return;
>+  }
>+  /* Config port 0
>+   * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
>+   *   are enabled as an output.
>+   */
>+  dm_i2c_reg_write(dev, 6, __PHY_MASK);
>+
>+  /*
>+   * Set port 0 output a value to reset ETH2 interface
>+   * - pin IOXP_RST_ETH2_B output 0b0
>+   */
>+  dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
>+  mdelay(10);
>+  dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
>+  /*
>+   * Set port 0 output a value to reset ETH1 interface
>+   * - pin IOXP_RST_ETH1_B output 0b0
>+   */
>+  mdelay(10);
>+  dm_i2c_reg_write(dev, 2, 0xFF);
>+#else
>   i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
>   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
>   mdelay(10);
>   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
>   mdelay(10

[PATCH] usb: cdns3: ep0: Fix build warnings related to cache ops

2019-12-05 Thread Vignesh Raghavendra
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own 
header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.

Signed-off-by: Vignesh Raghavendra 
---
 drivers/usb/cdns3/ep0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
index 1903f6110388..0b6d9cf7274e 100644
--- a/drivers/usb/cdns3/ep0.c
+++ b/drivers/usb/cdns3/ep0.c
@@ -10,6 +10,7 @@
  *  Peter Chen 
  */
 
+#include 
 #include 
 #include 
 
-- 
2.24.0



[PATCH 1/2] rockchip: mkimage: support packing optional second level boot-loader

2019-12-05 Thread Jeffy Chen
Support packing optional second level boot-loader:

$ ./tools/mkimage -n rk3399 -T rksd -d \
  rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image Type:   Rockchip RK33 (SD/MMC) boot image
Init Data Size: 116736 bytes
Boot Data Size: 88064 bytes

Mainly parse init file and boot file from datafile option, copy them to
the image, and padding each one to 2KB boundary.

Signed-off-by: Jeffy Chen 
---

 tools/imagetool.h |   1 +
 tools/mkimage.c   |   8 ++
 tools/rkcommon.c  | 236 +-
 tools/rkcommon.h  |  18 ++---
 tools/rksd.c  |  35 +---
 tools/rkspi.c |  42 --
 6 files changed, 226 insertions(+), 114 deletions(-)

diff --git a/tools/imagetool.h b/tools/imagetool.h
index 2689a4004a..e1c778b0df 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -253,6 +253,7 @@ void pbl_load_uboot(int fd, struct image_tool_params 
*mparams);
 int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
 int imx8image_copy_image(int fd, struct image_tool_params *mparams);
 int imx8mimage_copy_image(int fd, struct image_tool_params *mparams);
+int rockchip_copy_image(int fd, struct image_tool_params *mparams);
 
 #define ___cat(a, b) a ## b
 #define __cat(a, b) ___cat(a, b)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 4217188310..5f51d2cc89 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -544,6 +544,14 @@ int main(int argc, char **argv)
ret = imx8mimage_copy_image(ifd, ¶ms);
if (ret)
return ret;
+   } else if ((params.type == IH_TYPE_RKSD) ||
+   (params.type == IH_TYPE_RKSPI)) {
+   /* Rockchip has special Image format */
+   int ret;
+
+   ret = rockchip_copy_image(ifd, ¶ms);
+   if (ret)
+   return ret;
} else {
copy_file(ifd, params.datafile, pad_len);
}
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0d908daee8..1095aa3426 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -80,6 +80,24 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false },
 };
 
+/**
+ * struct spl_params - spl params parsed in check_params()
+ *
+ * @init_file: Init data file path
+ * @init_size: Aligned size of init data in bytes
+ * @boot_file: Boot data file path
+ * @boot_size: Aligned size of boot data in bytes
+ */
+
+struct spl_params {
+   char *init_file;
+   uint32_t init_size;
+   char *boot_file;
+   uint32_t boot_size;
+};
+
+static struct spl_params spl_params = { 0 };
+
 static unsigned char rc4_key[16] = {
124, 78, 3, 4, 85, 5, 9, 7,
45, 44, 123, 56, 23, 13, 23, 17
@@ -99,12 +117,25 @@ static struct spl_info *rkcommon_get_spl_info(char 
*imagename)
return NULL;
 }
 
-int rkcommon_check_params(struct image_tool_params *params)
+static int rkcommon_get_aligned_size(struct image_tool_params *params,
+const char *fname)
 {
-   int i;
+   int size;
 
-   if (rkcommon_get_spl_info(params->imagename) != NULL)
-   return EXIT_SUCCESS;
+   size = imagetool_get_filesize(params, fname);
+   if (size < 0)
+   return -1;
+
+   /*
+* Pad to a 2KB alignment, as required for init/boot size by the ROM
+* (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html)
+*/
+   return ROUND(size, RK_SIZE_ALIGN);
+}
+
+int rkcommon_check_params(struct image_tool_params *params)
+{
+   int i, spl_size;
 
/*
 * If this is a operation (list or extract), the don't require
@@ -113,6 +144,41 @@ int rkcommon_check_params(struct image_tool_params *params)
if (params->lflag || params->iflag)
return EXIT_SUCCESS;
 
+   if (!rkcommon_get_spl_info(params->imagename))
+   goto err_spl_info;
+
+   spl_params.init_file = params->datafile;
+
+   spl_params.boot_file = strchr(spl_params.init_file, ':');
+   if (spl_params.boot_file) {
+   *spl_params.boot_file = '\0';
+   spl_params.boot_file += 1;
+   }
+
+   spl_params.init_size =
+   rkcommon_get_aligned_size(params, spl_params.init_file);
+   if (spl_params.init_size < 0)
+   return EXIT_FAILURE;
+
+   /* Boot file is optional, and only for back-to-bootrom functionality. */
+   if (spl_params.boot_file) {
+   spl_params.boot_size =
+   rkcommon_get_aligned_size(params, spl_params.boot_file);
+   if (spl_params.boot_size < 0)
+   return EXIT_FAILURE;
+   }
+
+   spl

Re: [U-Boot] [PATCH v5 10/26] mtd: ensure UBI is compiled when ENV_IS_IN_UBI is selected

2019-12-05 Thread Tom Rini
On Thu, Oct 03, 2019 at 07:50:12PM +0200, Miquel Raynal wrote:

> UBI must be enabled when the environment is in UBI.
> 
> Signed-off-by: Miquel Raynal 
> Reviewed-by: Boris Brezillon 

Applied to u-boot/master, thanks!

-- 
Tom


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[PATCH v2 2/7] clk: stm32mp1: Add a clock entry for RNG1 device

2019-12-05 Thread Sughosh Ganu
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---
 drivers/clk/clk_stm32mp1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 3718970..da66bde 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -563,6 +563,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = 
{
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+   STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
-- 
2.7.4



[PATCH v2 5/7] sandbox: rng: Add a random number generator(rng) driver

2019-12-05 Thread Sughosh Ganu
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---
 arch/sandbox/dts/test.dts |  4 
 drivers/rng/Kconfig   |  7 +++
 drivers/rng/Makefile  |  1 +
 drivers/rng/sandbox_rng.c | 36 
 4 files changed, 48 insertions(+)
 create mode 100644 drivers/rng/sandbox_rng.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fdb08f2..2c85540 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -599,6 +599,10 @@
reset-names = "other", "test";
};
 
+   rng@0 {
+   compatible = "sandbox,sandbox-rng";
+   };
+
rproc_1: rproc@1 {
compatible = "sandbox,test-processor";
remoteproc-name = "remoteproc-test-dev1";
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 5fc11db..3a1d3f0 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -6,6 +6,13 @@ config DM_RNG
  This interface is used to initialise the rng device and to
  read the random seed from the device.
 
+config RNG_SANDBOX
+   bool "Sandbox random number generator"
+   depends on SANDBOX && DM_RNG
+   help
+ Enable random number generator for sandbox. This is an
+emulation of a rng device.
+
 config RNG_STM32MP1
bool "Enable random number generator for STM32MP1"
depends on ARCH_STM32MP && DM_RNG
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 699beb3..3517005 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -4,4 +4,5 @@
 #
 
 obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
 obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
diff --git a/drivers/rng/sandbox_rng.c b/drivers/rng/sandbox_rng.c
new file mode 100644
index 000..c5be552
--- /dev/null
+++ b/drivers/rng/sandbox_rng.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+
+static unsigned long random = 0xdeadbeef;
+
+static int sandbox_rng_read(struct udevice *dev, void *data, size_t len)
+{
+   random ^= ~0UL;
+   *(unsigned long *)data = random;
+
+   return sizeof(random);
+}
+
+static const struct dm_rng_ops sandbox_rng_ops = {
+   .read = sandbox_rng_read,
+};
+
+static const struct udevice_id sandbox_rng_match[] = {
+   {
+   .compatible = "sandbox,sandbox-rng",
+   },
+   {},
+};
+
+U_BOOT_DRIVER(sandbox_rng) = {
+   .name = "sandbox-rng",
+   .id = UCLASS_RNG,
+   .of_match = sandbox_rng_match,
+   .ops = &sandbox_rng_ops,
+};
-- 
2.7.4



[PATCH v2 6/7] configs: sandbox: Enable random number generator(rng) device

2019-12-05 Thread Sughosh Ganu
Enable support for random number generator on sandbox configs. This is
aimed primarily at adding unit test support for rng uclass.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---
 configs/sandbox64_defconfig | 2 ++
 configs/sandbox_defconfig   | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index d467841..2ef1097 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -158,6 +158,8 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_DM_REGULATOR_SANDBOX=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_SANDBOX=y
 CONFIG_RAM=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ed7ff78..417d775 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -179,6 +179,8 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_DM_REGULATOR_SANDBOX=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_SANDBOX=y
 CONFIG_RAM=y
-- 
2.7.4



[PATCH v2 7/7] test: rng: Add basic test for random number generator(rng) uclass

2019-12-05 Thread Sughosh Ganu
Add a unit test for testing the rng uclass functionality using the
sandbox rng driver.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---
 test/dm/Makefile |  1 +
 test/dm/rng.c| 26 ++
 2 files changed, 27 insertions(+)
 create mode 100644 test/dm/rng.c

diff --git a/test/dm/Makefile b/test/dm/Makefile
index 0c2fd5c..f61bf65 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -65,4 +65,5 @@ obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
 obj-$(CONFIG_DMA) += dma.o
 obj-$(CONFIG_DM_MDIO) += mdio.o
 obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
+obj-$(CONFIG_DM_RNG) += rng.o
 endif
diff --git a/test/dm/rng.c b/test/dm/rng.c
new file mode 100644
index 000..879e80a
--- /dev/null
+++ b/test/dm/rng.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Basic test of the rng uclass */
+static int dm_test_rng_read(struct unit_test_state *uts)
+{
+   unsigned long val1 = 0, val2 = 0;
+   struct udevice *dev;
+
+   ut_assertok(uclass_get_device(UCLASS_RNG, 0, &dev));
+   ut_assertnonnull(dev);
+   dm_rng_read(dev, &val1, sizeof(val1));
+   dm_rng_read(dev, &val2, sizeof(val2));
+   ut_assert(val1 != val2);
+
+   return 0;
+}
+DM_TEST(dm_test_rng_read, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-- 
2.7.4



Re: [U-Boot] [PATCH v5 18/26] configs: ls104x/ls108x/ls208x: Build the raw NAND core with TFABOOT

2019-12-05 Thread Tom Rini
On Thu, Oct 03, 2019 at 07:50:20PM +0200, Miquel Raynal wrote:

> Enabling TFABOOT configuration will compile-in a call to nand_read in
> the boot sequence. Handle the situation by also selecting officially
> the raw NAND core in this case.
> 
> Signed-off-by: Miquel Raynal 

Applied to u-boot/master, thanks!

-- 
Tom


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[PATCH v2 4/7] configs: stm32mp15: Enable random number generator(rng) device

2019-12-05 Thread Sughosh Ganu
Enable support for the rng device on the stm32mp15 configs.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---
 configs/stm32mp15_basic_defconfig   | 2 ++
 configs/stm32mp15_optee_defconfig   | 2 ++
 configs/stm32mp15_trusted_defconfig | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index 14e1127..725381d 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -140,3 +140,5 @@ CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
 CONFIG_FDT_FIXUP_PARTITIONS=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32MP1=y
diff --git a/configs/stm32mp15_optee_defconfig 
b/configs/stm32mp15_optee_defconfig
index 791c1a9..5e3c826 100644
--- a/configs/stm32mp15_optee_defconfig
+++ b/configs/stm32mp15_optee_defconfig
@@ -124,3 +124,5 @@ CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
 CONFIG_FDT_FIXUP_PARTITIONS=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32MP1=y
diff --git a/configs/stm32mp15_trusted_defconfig 
b/configs/stm32mp15_trusted_defconfig
index 5556b18..cbdb903 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -123,3 +123,5 @@ CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
 CONFIG_FDT_FIXUP_PARTITIONS=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32MP1=y
-- 
2.7.4



[PATCH v2 1/7] dm: rng: Add random number generator(rng) uclass

2019-12-05 Thread Sughosh Ganu
Add a uclass for reading a random number seed from a random number
generator device.

Signed-off-by: Sughosh Ganu 
Reviewed-by: Patrice Chotard 
---

Changes since V1:
* Add a SPDX header in rng.h
* Change the UCLASS_DRIVER name from hwrng to rng, to be consistent
  with the rest of the naming convention

 drivers/Kconfig  |  2 ++
 drivers/Makefile |  1 +
 drivers/rng/Kconfig  |  7 +++
 drivers/rng/Makefile |  6 ++
 drivers/rng/rng-uclass.c | 23 +++
 include/dm/uclass-id.h   |  1 +
 include/rng.h| 30 ++
 7 files changed, 70 insertions(+)
 create mode 100644 drivers/rng/Kconfig
 create mode 100644 drivers/rng/Makefile
 create mode 100644 drivers/rng/rng-uclass.c
 create mode 100644 include/rng.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9d99ce0..e34a227 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -90,6 +90,8 @@ source "drivers/remoteproc/Kconfig"
 
 source "drivers/reset/Kconfig"
 
+source "drivers/rng/Kconfig"
+
 source "drivers/rtc/Kconfig"
 
 source "drivers/scsi/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 0d1d6bd..50e5c70 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -114,4 +114,5 @@ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
 
 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
 obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
+obj-$(CONFIG_DM_RNG) += rng/
 endif
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
new file mode 100644
index 000..dd44cc0
--- /dev/null
+++ b/drivers/rng/Kconfig
@@ -0,0 +1,7 @@
+config DM_RNG
+   bool "Driver support for Random Number Generator devices"
+   depends on DM
+   help
+ Enable driver model for random number generator(rng) devices.
+ This interface is used to initialise the rng device and to
+ read the random seed from the device.
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
new file mode 100644
index 000..311705b
--- /dev/null
+++ b/drivers/rng/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019, Linaro Limited
+#
+
+obj-$(CONFIG_DM_RNG) += rng-uclass.o
diff --git a/drivers/rng/rng-uclass.c b/drivers/rng/rng-uclass.c
new file mode 100644
index 000..b6af3b8
--- /dev/null
+++ b/drivers/rng/rng-uclass.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+
+int dm_rng_read(struct udevice *dev, void *buffer, size_t size)
+{
+   const struct dm_rng_ops *ops = device_get_ops(dev);
+
+   if (!ops->read)
+   return -ENOSYS;
+
+   return ops->read(dev, buffer, size);
+}
+
+UCLASS_DRIVER(rng) = {
+   .name = "rng",
+   .id = UCLASS_RNG,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0c563d8..192202d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -86,6 +86,7 @@ enum uclass_id {
UCLASS_REGULATOR,   /* Regulator device */
UCLASS_REMOTEPROC,  /* Remote Processor device */
UCLASS_RESET,   /* Reset controller device */
+   UCLASS_RNG, /* Random Number Generator */
UCLASS_RTC, /* Real time clock device */
UCLASS_SCSI,/* SCSI device */
UCLASS_SERIAL,  /* Serial UART */
diff --git a/include/rng.h b/include/rng.h
new file mode 100644
index 000..61d5da9
--- /dev/null
+++ b/include/rng.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#if !defined _RNG_H_
+#define _RNG_H_
+
+#include 
+
+/**
+ * dm_rng_read() - read a random number seed from the rng device
+ * @buffer:input buffer to put the read random seed into
+ * @size:  number of bytes of random seed read
+ *
+ */
+int dm_rng_read(struct udevice *dev, void *buffer, size_t size);
+
+/* struct dm_rng_ops - Operations for the hwrng uclass */
+struct dm_rng_ops {
+   /**
+* @read() - read a random number seed
+*
+* @data:   input buffer to read the random seed
+* @max:total number of bytes to read
+*/
+   int (*read)(struct udevice *dev, void *data, size_t max);
+};
+
+#endif /* _RNG_H_ */
-- 
2.7.4



[PATCH v2] arm64: zynqmp: Add support for u-boot.itb generation with ATF

2019-12-05 Thread Michal Simek
Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
quite a long time but with using out of tree solution. The patch is filling
this gap.

Tested on zcu102, zcu104 and zcu100/Ultra96.

zcu100/Ultra96 v2.2 ATF build by:
make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31

Signed-off-by: Michal Simek 
---

Changes in v2:
- Exchange u-boot/atf in config section
- Use default ATF baseaddr from mainline
- Update commit message

 Kconfig |  3 +-
 arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 99 +
 include/configs/xilinx_zynqmp.h |  6 +-
 3 files changed, 106 insertions(+), 2 deletions(-)
 create mode 100755 arch/arm/mach-zynqmp/mkimage_fit_atf.sh

diff --git a/Kconfig b/Kconfig
index e22417ec4471..7efafffec0a4 100644
--- a/Kconfig
+++ b/Kconfig
@@ -253,7 +253,7 @@ config BUILD_TARGET
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-   ARCH_SUNXI || RISCV)
+   ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@@ -481,6 +481,7 @@ config SPL_FIT_GENERATOR
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && 
ARCH_ROCKCHIP
+   default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && 
ARCH_ZYNQMP
default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
  Specifies a (platform specific) script file to generate the FIT
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh 
b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
new file mode 100755
index ..c50aba45ca5c
--- /dev/null
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@@ -0,0 +1,99 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Xilinx ZynqMP boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0  [ [&2
+else
+   echo "$BL31 size: " >&2
+   ls -lct $BL31 | awk '{print $5}' >&2
+fi
+
+
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+   description = "Configuration to load ATF before U-Boot";
+
+   images {
+   uboot {
+   description = "U-Boot (64-bit)";
+   data = /incbin/("$BL33");
+   type = "firmware";
+   os = "u-boot";
+   arch = "arm64";
+   compression = "none";
+   load = <$BL33_LOAD_ADDR>;
+   hash {
+   algo = "md5";
+   };
+   };
+   atf {
+   description = "ARM Trusted Firmware";
+   data = /incbin/("$BL31");
+   type = "firmware";
+   os = "arm-trusted-firmware";
+   arch = "arm64";
+   compression = "none";
+   load = <$ATF_LOAD_ADDR>;
+   entry = <$ATF_LOAD_ADDR>;
+   hash {
+   algo = "md5";
+   };
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt_$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   arch = "arm64";
+   compression = "none";
+   hash {
+   algo = "md5";
+   };
+   };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config_1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION1_EOF
+   config_$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "atf";
+   loadables = "uboot";
+   fdt = "fdt_$cnt";
+   };
+__CONF_SECTION1_EOF
+cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ee1ceebf1291..e7eb8dbfcb45 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -243,7 +243,11 @@
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW

[PATCH 2/2] doc: rockchip: document packing second level loader with mkimage

2019-12-05 Thread Jeffy Chen
Add documentation about packing optional second level boot-loader with
mkimage tool.

Signed-off-by: Jeffy Chen 
---

 doc/README.rockchip | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 67c14006a3..39dc9c5e9f 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -341,6 +341,12 @@ You can create the image via the following operations:
cat firefly-rk3288/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
 
+Or:
+   ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
+   firefly-rk3288/spl/u-boot-spl-dtb.bin:firefly-rk3288/u-boot-dtb.bin \
+   out && \
+   sudo dd if=out of=/dev/sdc seek=64
+
 If you have an HDMI cable attached you should see a video console.
 
 For evb_rk3036 board:
@@ -348,6 +354,11 @@ For evb_rk3036 board:
cat evb-rk3036/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
 
+Or:
+   ./evb-rk3036/tools/mkimage -n rk3036 -T rksd -d \
+   evb-rk3036/spl/u-boot-spl.bin:evb-rk3036/u-boot-dtb.bin out && \
+   sudo dd if=out of=/dev/sdc seek=64
+
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, 
the
   debug uart must be disabled
 
-- 
2.11.0





[PATCH v2 3/7] stm32mp1: rng: Add a driver for random number generator(rng) device

2019-12-05 Thread Sughosh Ganu
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.

Signed-off-by: Sughosh Ganu 
---

Changes since V1:
* Handle review comment from Patrice Chotard to remove the 'inited'
  member

 drivers/rng/Kconfig|   7 ++
 drivers/rng/Makefile   |   1 +
 drivers/rng/stm32mp1_rng.c | 158 +
 3 files changed, 166 insertions(+)
 create mode 100644 drivers/rng/stm32mp1_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index dd44cc0..5fc11db 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -5,3 +5,10 @@ config DM_RNG
  Enable driver model for random number generator(rng) devices.
  This interface is used to initialise the rng device and to
  read the random seed from the device.
+
+config RNG_STM32MP1
+   bool "Enable random number generator for STM32MP1"
+   depends on ARCH_STM32MP && DM_RNG
+   default n
+   help
+ Enable STM32MP1 rng driver.
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 311705b..699beb3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
new file mode 100644
index 000..5cd736d
--- /dev/null
+++ b/drivers/rng/stm32mp1_rng.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define RNG_CR 0x00
+#define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
+
+#define RNG_SR 0x04
+#define RNG_SR_SEIS BIT(6)
+#define RNG_SR_CEIS BIT(5)
+#define RNG_SR_SECS BIT(2)
+#define RNG_SR_DRDY BIT(0)
+
+#define RNG_DR 0x08
+
+struct stm32_rng_platdata {
+   fdt_addr_t base;
+   struct clk clk;
+   struct reset_ctl rst;
+};
+
+static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
+{
+   int retval = 0, i;
+   u32 sr, count, reg;
+   size_t increment;
+   struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+
+   while (len > 0) {
+   retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
+   sr & RNG_SR_DRDY, 1);
+   if (retval)
+   return retval;
+
+   if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
+   /* As per SoC TRM */
+   clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
+   for (i = 0; i < 12; i++)
+   readl(pdata->base + RNG_DR);
+   if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
+   printf("RNG Noise");
+   return -EIO;
+   }
+   /* start again */
+   continue;
+   }
+
+   count = 4;
+   while (len && count) {
+   reg = readl(pdata->base + RNG_DR);
+   memcpy(data, ®, min(len, sizeof(u32)));
+   increment = min(len, sizeof(u32));
+   data += increment;
+   retval += increment;
+   len -= increment;
+   count--;
+   }
+   }
+
+   return retval;
+}
+
+static int stm32_rng_init(struct stm32_rng_platdata *pdata)
+{
+   int err;
+
+   err = clk_enable(&pdata->clk);
+   if (err)
+   return err;
+
+   /* Disable CED */
+   writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR);
+
+   /* clear error indicators */
+   writel(0, pdata->base + RNG_SR);
+
+   return 0;
+}
+
+static int stm32_rng_cleanup(struct stm32_rng_platdata *pdata)
+{
+
+   writel(0, pdata->base + RNG_CR);
+
+   return clk_disable(&pdata->clk);
+}
+
+static int stm32_rng_probe(struct udevice *dev)
+{
+   struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+
+   reset_assert(&pdata->rst);
+   udelay(20);
+   reset_deassert(&pdata->rst);
+
+   return stm32_rng_init(pdata);
+}
+
+static int stm32_rng_remove(struct udevice *dev)
+{
+   struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+
+   return stm32_rng_cleanup(pdata);
+}
+
+static int stm32_rng_ofdata_to_platdata(struct udevice *dev)
+{
+   struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+   int err;
+
+   pdata->base = dev_read_addr(dev);
+   if (!pdata->base)
+   return -ENOMEM;
+
+   err = clk_get_by_index(dev, 0, &pdata->clk);
+   if (err)
+   return err;
+
+   err = reset_get_by_index(dev, 0, &pdata->rst);
+   if (err)
+   return err;
+
+   return 0;
+}
+
+static const struct dm_rng_ops stm32

RE: [v3 1/8] rtc: pcf8563: support driver model

2019-12-05 Thread Priyanka Jain



>-Original Message-
>From: Biwen Li 
>Sent: Thursday, December 5, 2019 11:40 AM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>bhaskar.upadh...@nxp.com; feng.l...@nxp.com; jh80.ch...@samsung.com;
>Pramod Kumar ; Rajesh Bhagat
>; Ruchika Gupta ;
>olte...@gmail.com
>Cc: Xiaobo Xie ; Jiafei Pan ; u-
>b...@lists.denx.de; Biwen Li 
>Subject: [v3 1/8] rtc: pcf8563: support driver model
Please update subject to something like : rtc: pcf8563: Add driver model support
>
>This supports driver model for pcf8563
Please update description to something like : "Add support of driver model of 
pcf8563"
>
>Signed-off-by: Biwen Li 
>---
>Changes in v3:
>   - update commit messages
>
>Changes in v2:
>   - none
>
> drivers/rtc/pcf8563.c | 107 ++
> 1 file changed, 107 insertions(+)
>
>diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index
>a839d6cc98..44204e133e 100644
>--- a/drivers/rtc/pcf8563.c
>+++ b/drivers/rtc/pcf8563.c
>@@ -12,9 +12,11 @@
>
As significant code changes are done, this might need change in copyright. 
Please check
> #include 
> #include 
>+#include 
> #include 
> #include 
>
>+#if !CONFIG_IS_ENABLED(DM_RTC)
> static uchar rtc_read  (uchar reg);
> static void  rtc_write (uchar reg, uchar val);
>
>@@ -115,3 +117,108 @@ static void rtc_write (uchar reg, uchar val)  {
>   i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);  }
>+#else
>+static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) {
>+  int rel = 0;
>+  uchar sec, min, hour, mday, wday, mon_cent, year;
>+
>+  sec = dm_i2c_reg_read(dev, 0x02);
>+  min = dm_i2c_reg_read(dev, 0x03);
>+  hour= dm_i2c_reg_read(dev, 0x04);
>+  mday= dm_i2c_reg_read(dev, 0x05);
>+  wday= dm_i2c_reg_read(dev, 0x06);
>+  mon_cent = dm_i2c_reg_read(dev, 0x07);
>+  year= dm_i2c_reg_read(dev, 0x08);
>+
>+  debug ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x
>"
>+ "hr: %02x min: %02x sec: %02x\n",
>+ year, mon_cent, mday, wday,
>+ hour, min, sec);
>+  debug ("Alarms: wday: %02x day: %02x hour: %02x min: %02x\n",
>+ dm_i2c_reg_read(dev, 0x0C),
>+ dm_i2c_reg_read(dev, 0x0B),
>+ dm_i2c_reg_read(dev, 0x0A),
>+ dm_i2c_reg_read(dev, 0x09));
>+
>+  if (sec & 0x80) {
>+  puts ("### Warning: RTC Low Voltage - date/time not
>reliable\n");
>+  rel = -1;
>+  }
>+
>+  tmp->tm_sec = bcd2bin (sec & 0x7F);
>+  tmp->tm_min = bcd2bin (min & 0x7F);
>+  tmp->tm_hour = bcd2bin (hour & 0x3F);
>+  tmp->tm_mday = bcd2bin (mday & 0x3F);
>+  tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
>+  tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 1900 : 2000);
>+  tmp->tm_wday = bcd2bin (wday & 0x07);
>+  tmp->tm_yday = 0;
>+  tmp->tm_isdst = 0;
>+
>+  debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
>+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+  return rel;
>+}
>+
>+static int pcf8563_rtc_set(struct udevice *dev, const struct rtc_time
>+*tmp) {
>+  uchar century;
>+
>+  debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
>+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+  dm_i2c_reg_write(dev, 0x08, bin2bcd(tmp->tm_year % 100));
>+
>+  century = (tmp->tm_year >= 2000) ? 0 : 0x80;
>+  dm_i2c_reg_write(dev, 0x07, bin2bcd(tmp->tm_mon) | century);
>+
>+  dm_i2c_reg_write(dev, 0x06, bin2bcd(tmp->tm_wday));
>+  dm_i2c_reg_write(dev, 0x05, bin2bcd(tmp->tm_mday));
>+  dm_i2c_reg_write(dev, 0x04, bin2bcd(tmp->tm_hour));
>+  dm_i2c_reg_write(dev, 0x03, bin2bcd(tmp->tm_min));
>+  dm_i2c_reg_write(dev, 0x02, bin2bcd(tmp->tm_sec));
>+
>+  return 0;
>+}
>+
>+static int pcf8563_rtc_reset(struct udevice *dev) {
>+  /* clear all control & status registers */
>+  dm_i2c_reg_write(dev, 0x00, 0x00);
>+  dm_i2c_reg_write(dev, 0x01, 0x00);
>+  dm_i2c_reg_write(dev, 0x0D, 0x00);
>+
>+  /* clear Voltage Low bit */
>+  dm_i2c_reg_write(dev, 0x02, dm_i2c_reg_read (dev, 0x02) & 0x7F);
>+
>+  /* reset all alarms */
>+  dm_i2c_reg_write(dev, 0x09, 0x00);
>+  dm_i2c_reg_write(dev, 0x0A, 0x00);
>+  dm_i2c_reg_write(dev, 0x0B, 0x00);
>+  dm_i2c_reg_write(dev, 0x0C, 0x00);
>+
>+  return 0;
>+}
>+
>+static const struct rtc_ops pcf8563_rtc_ops = {
>+  .get = pcf8563_rtc_get,
>+  .set = pcf8563_rtc_set,
>+  .reset = pcf8563_rtc_reset,
>+};
>+
>+static const struct udevice_id pcf8563_rtc_ids[] = {
>+  { .compatible = "nxp,pcf8563" },
>+  { }
>+};
>+
>+U_BOOT_DRIVER(rtc_pcf8563) = {
>+  .name   = "rtc-pcf8563",
>+  .id = UCLASS_RTC,
>+  .

[PATCH 2/4] rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399

2019-12-05 Thread Kever Yang
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for
STACK and the size may not enough when loding FIT image in SPL.

If the size is not enough, you can see log like this when loding FIT:

U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53)
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800)
Trying to boot from MMC2

And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc
sending CMD16 for 'uboot' loadables binary because this step need a
large stack cost(about 0x2d00).

External data: dst=840, offset=72638, size=b3580
Image OS is Trusted Execution Environment
board_fit_config_name_match: rk3288-evb
Selecting config 'rk3288-evb'loadables: 'uboot'
blk_find_device: if_type=6, devnum=1: dw...@ff0c.blk, 6, 0
blk_find_device: if_type=6, devnum=1: dw...@ff0f.blk, 6, 1
Sending CMD16

Signed-off-by: Kever Yang 
---

 configs/evb-rk3288_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 36f6d4a18e..685120cd78 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x0100
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_EVB_RK3288=y
 CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK_R_ADDR=0x0400
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL_SIZE_LIMIT=0x4b000
 CONFIG_DEBUG_UART_BASE=0xff69
@@ -17,7 +17,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
-- 
2.17.1



[PATCH 3/4] rockchip: rk3288-evb: update CONFIG_NR_DRAM_BANKS to 2

2019-12-05 Thread Kever Yang
The OPTEE will use the ram start at 0x840 which make the DRAM be two
banks.

Signed-off-by: Kever Yang 
---

 configs/evb-rk3288_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 685120cd78..9391328bce 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -5,7 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_EVB_RK3288=y
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_SPL_STACK_R_ADDR=0x0400
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL_SIZE_LIMIT=0x4b000
 CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
-- 
2.17.1



[PATCH 1/3] mtd: spi-nor-core: Add octal mode support

2019-12-05 Thread Vignesh Raghavendra
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra 
---
 drivers/mtd/spi/sf_internal.h  |  3 ++-
 drivers/mtd/spi/spi-nor-core.c | 20 +++-
 drivers/spi/spi-mem.c  |  6 ++
 drivers/spi/spi-uclass.c   |  6 ++
 include/linux/mtd/spi-nor.h|  8 
 include/spi.h  |  2 ++
 6 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5c643034c691..940b2e4c9e00 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -37,7 +37,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
 
-   u16 flags;
+   u32 flags;
 #define SECT_4KBIT(0)  /* SPINOR_OP_BE_4K works 
uniformly */
 #define SPI_NOR_NO_ERASE   BIT(1)  /* No erase command needed */
 #define SST_WRITE  BIT(2)  /* use SST byte programming */
@@ -66,6 +66,7 @@ struct flash_info {
 #define SPI_NOR_SKIP_SFDP  BIT(13) /* Skip parsing of SFDP tables */
 #define USE_CLSR   BIT(14) /* use CLSR command */
 #define SPI_NOR_HAS_SST26LOCK  BIT(15) /* Flash supports lock/unlock via BPR */
+#define SPI_NOR_OCTAL_READ  BIT(16) /* Flash supports Octal Read */
 };
 
 extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5a8c08425566..9b726be5d22d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -251,6 +251,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+   { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+   { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
 
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -267,6 +269,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4,   SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4,   SPINOR_OP_PP_1_4_4_4B },
+   { SPINOR_OP_PP_1_1_8,   SPINOR_OP_PP_1_1_8_4B },
+   { SPINOR_OP_PP_1_8_8,   SPINOR_OP_PP_1_8_8_4B },
};
 
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -2121,6 +2125,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
  SNOR_PROTO_1_1_4);
}
 
+   if (info->flags & SPI_NOR_OCTAL_READ) {
+   params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+   spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+   }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
@@ -2428,7 +2439,14 @@ int spi_nor_scan(struct spi_nor *nor)
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
 
-   if (spi->mode & SPI_RX_QUAD) {
+   if (spi->mode & SPI_RX_OCTAL) {
+   hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+   if (spi->mode & SPI_TX_OCTAL)
+   hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+   SNOR_HWCAPS_PP_1_1_8 |
+   SNOR_HWCAPS_PP_1_8_8);
+   } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
if (spi->mode & SPI_TX_QUAD)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 7788ab995344..cc358bd4f7ce 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -123,6 +123,12 @@ static int spi_check_buswidth_req(struct spi_slave *slave, 
u8 buswidth, bool tx)
return 0;
 
break;
+   case 8:
+   if ((tx && (mode & SPI_TX_OCTAL)) ||
+   (!tx && (mode & SPI_RX_OCTAL)))
+   return 0;
+
+   break;
 
default:
break;
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 665611f7e23a..e16e9b4a4e98 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -445,6 +445,9 @@ int spi_slave_ofdata_to_platdata(struct udevice *dev,
case 4:
mode |= SPI_TX_QUAD;
break;
+   case 8:
+   mode |= SPI_TX_OCTAL;
+   break;
default:
warn_non_spl("spi-tx-bus-width %d no

[PATCH 0/3] spi-nor: Add octal mode support

2019-12-05 Thread Vignesh Raghavendra
This series adds Octal mode support for Micron's mt35x flash.
Also adds Octal mode support for Cadance OSPI/QSPI controller.
Currently only 1-1-8 mode is supported.

Vignesh Raghavendra (3):
  mtd: spi-nor-core: Add octal mode support
  spi: cadence-qspi: Add support for Cadence Octal SPI controller
  spi: cadence-qspi: Add compatible for TI AM654

 drivers/mtd/spi/sf_internal.h  |  3 ++-
 drivers/mtd/spi/spi-nor-core.c | 20 +++-
 drivers/spi/cadence_qspi.c |  2 ++
 drivers/spi/cadence_qspi_apb.c |  8 ++--
 drivers/spi/spi-mem.c  |  6 ++
 drivers/spi/spi-uclass.c   |  6 ++
 include/linux/mtd/spi-nor.h|  8 
 include/spi.h  |  2 ++
 8 files changed, 51 insertions(+), 4 deletions(-)

-- 
2.24.0



[PATCH 2/3] spi: cadence-qspi: Add support for Cadence Octal SPI controller

2019-12-05 Thread Vignesh Raghavendra
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible

Signed-off-by: Vignesh Raghavendra 
---
 drivers/spi/cadence_qspi.c | 1 +
 drivers/spi/cadence_qspi_apb.c | 8 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 619fff70de2f..6374d3976a4a 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a0e14f93e020..0a5af0561430 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -43,6 +43,7 @@
 #define CQSPI_INST_TYPE_SINGLE 0
 #define CQSPI_INST_TYPE_DUAL   1
 #define CQSPI_INST_TYPE_QUAD   2
+#define CQSPI_INST_TYPE_OCTAL  3
 
 #define CQSPI_STIG_DATA_LEN_MAX8
 
@@ -537,7 +538,10 @@ int cadence_qspi_apb_read_setup(struct 
cadence_spi_platdata *plat,
/* Configure the opcode */
rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
-   if (op->data.buswidth == 4)
+   if (op->data.buswidth == 8)
+   /* Instruction and address at DQ0, data at DQ0-7. */
+   rd_reg |= CQSPI_INST_TYPE_OCTAL << 
CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+   else if (op->data.buswidth == 4)
/* Instruction and address at DQ0, data at DQ0-3. */
rd_reg |= CQSPI_INST_TYPE_QUAD << 
CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 
@@ -653,7 +657,7 @@ failrd:
 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
  const struct spi_mem_op *op)
 {
-   u32 from = op->addr.val;
+   u64 from = op->addr.val;
void *buf = op->data.buf.in;
size_t len = op->data.nbytes;
 
-- 
2.24.0



[PATCH 3/3] spi: cadence-qspi: Add compatible for TI AM654

2019-12-05 Thread Vignesh Raghavendra
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.

Signed-off-by: Vignesh Raghavendra 
---
 drivers/spi/cadence_qspi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 6374d3976a4a..f8b69406d4b9 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -340,6 +340,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
 
 static const struct udevice_id cadence_spi_ids[] = {
{ .compatible = "cdns,qspi-nor" },
+   { .compatible = "ti,am654-ospi" },
{ }
 };
 
-- 
2.24.0



Re: Load Debian/Fedora via EFI

2019-12-05 Thread Michal Simek
út 3. 12. 2019 v 20:56 odesílatel Heinrich Schuchardt
 napsal:
>
> On 12/2/19 3:21 PM, Michal Simek wrote:
> > On 29. 11. 19 19:23, Heinrich Schuchardt wrote:
> >> On 11/29/19 11:16 AM, Michal Simek wrote:
> >>> Hi,
> >>>
> >>> I tried to boot latest debian and fedora rootfs via distro boot and
> >>> getting errors.
> >>> I have tried to run just one command and it is failing.
> >>>
> >>> ZynqMP> bootefi bootmgr ${fdtcontroladdr}
> >>> BootOrder not defined
> >>> EFI boot manager: Cannot load any image
> >>>
> >>> How to define BootOrder?
> >>>
> >>> Thanks,
> >>> Michal
> >>
> >> # Booting via boot manager
> >>
> >> U-Boot currently has no runtime support for variables. But Linaro is
> >> working on it. So update-grub cannot set the variables for you.
> >
> > Who from Linaro is working on it? Akashi?
>
> I was in contact with Ilias Apalodimas but do not know who is doing the
> actual work.
>
> See https://youtu.be/SEMJGOzjrHY @ 14:00
>
> >
> >>
> >> You can use the efidebug command to prepare for booting via the boot
> >> manager:
> >>
> >> => efidebug boot add 0001 Debian mmc 0:1 \
> >>efi/debian/grubarm.efi console=${console}
> >>
> >> There seems to be a bug with communication lines in U-Boot. So you
> >> actually have to put this into a single line.
> >>
> >> => efidebug boot order 0001
> >>
> >> Use saveenv if you want to save the settings.
> >>
> >> If you do not want to use the internal device tree load the proper
> >> device tree, e.g.
> >>
> >> => load mmc 0:2 $fdt_addr_r dtb
> >>
> >> Now you are ready to boot via the boot manager:
> >>
> >> => bootefi bootmgr $fdt_addr_r
> >>
> >> # Booting via distro defaults
> >>
> >> DISTRO_DEFAULTS tries to load the devicetree from ${fdtfile} and the
> >> UEFI binary from efi/boot/bootaa64.efi on ARM64. See
> >> ./include/config_distro_bootcmd.h.
> >>
> >> OpenBSD and FreeBSD follow the distro boot convention, Debian GRUB does
> >> not.
> >
> > Fedora is the same case.
> > I got it working based on your guidance but would be IMHO better to
> > extend distroboot to cover one of the major distribution even through
> > workaround till variable support is done.
>
> I don't like the idea of distribution specific stuff getting into U-Boot.
>
> We would end up with a plethora of possible UEFI binaries to search for:
> shim, GRUB, iPXE, any Linux kernel. All of these are binaries could be
> used for booting Fedora, Debian, or any other Linux distribution via
> bootefi. And which one should we take if there is more than one of these?
>
> I especially dislike any claim that one distribution is "major" and
> another is not. Should we kick out CentOS and Fedora because they are
> less popular than Ubuntu and Android?
>
> So let's leave it to the distribution to create boot.scr or provide a
> binary following the naming convention given in the UEFI specification
> (chapter 3.5.1.1 Removable Media Boot Behavior).

ok understand.

>
> >
> >>
> >> # Booting via boot script.
> >>
> >> On Debian I use package flash-kernel to keep /boot/dtb in sync with the
> >> kernel and have a u-boot.scr.uimg script with something like the
> >> following lines:
> >>
> >> setenv bootargs console=${console}
> >> load mmc 2:1 ${kernel_addr_r} EFI/debian/grubarm.efi
> >> load mmc 2:2 ${fdt_addr_r} dtb
> >> bootefi ${kernel_addr_r} ${fdt_addr_r}
> >
> >
> > flash-kernel is interesting. It generates u-boot script but if extX
> > partition has no bootable flag u-boot distroboot ignores it completely.
> > What's your default partition setup?
>
> I have separate partitions:
>
> /boot of type 83 (Linux, ext2) and marked as bootable and with boot.scr
> on it.
> /boot/efi of type ef (EFI, vfat) and not marked as bootable
>
> The sequence on the block device does not matter.
>
> When booting via iSCSI with iPXE I put boot.scr and snp.efi on an EFI
> partition marked as bootable.

That means that you had done that changes by hand.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs


[PATCH 1/4] rockchip: fit_spl_optee: get text and optee base from build

2019-12-05 Thread Kever Yang
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x6000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/fit_spl_optee.sh | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh 
b/arch/arm/mach-rockchip/fit_spl_optee.sh
index 89ef04312c..4118472d9f 100755
--- a/arch/arm/mach-rockchip/fit_spl_optee.sh
+++ b/arch/arm/mach-rockchip/fit_spl_optee.sh
@@ -17,6 +17,12 @@ if [ ! -f $TEE ]; then
 fi
 
 dtname=$1
+text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \
+  |tr -d '\r'`
+dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \
+  include/autoconf.mk|tr -d '\r'`
+tee_base=`echo "obase=16;$(($dram_base+0x840))"|bc`
+tee_base='0x'$tee_base
 
 cat << __HEADER_EOF
 /*
@@ -39,7 +45,7 @@ cat << __HEADER_EOF
os = "U-Boot";
arch = "arm";
compression = "none";
-   load = <0x6100>;
+   load = <$text_base>;
};
optee {
description = "OP-TEE";
@@ -48,8 +54,8 @@ cat << __HEADER_EOF
arch = "arm";
os = "tee";
compression = "none";
-   load = <0x6840>;
-   entry = <0x6840>;
+   load = <$tee_base>;
+   entry = <$tee_base>;
};
fdt {
description = "$(basename $dtname .dtb)";
-- 
2.17.1



[PATCH 4/4] rockchip: rk3288-evb: update config to support OPTEE

2019-12-05 Thread Kever Yang
Upstream kernel and rockchip kernel has default enable PSCI which needs
OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT
option to pack OPTEE with U-Boot proper.

Signed-off-by: Kever Yang 
---

 configs/evb-rk3288_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 9391328bce..ffa90127c7 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -11,6 +11,10 @@ CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/fit_spl_optee.sh"
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
@@ -18,6 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
+CONFIG_SPL_OPTEE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
-- 
2.17.1



Re: [PATCH v2 3/7] stm32mp1: rng: Add a driver for random number generator(rng) device

2019-12-05 Thread Patrice CHOTARD
On 12/5/19 9:42 AM, Sughosh Ganu wrote:
> Add a driver for the rng device found on stm32mp1 platforms. The
> driver provides a routine for reading the random number seed from the
> hardware device.
>
> Signed-off-by: Sughosh Ganu 
> ---
>
> Changes since V1:
> * Handle review comment from Patrice Chotard to remove the 'inited'
>   member
>
>  drivers/rng/Kconfig|   7 ++
>  drivers/rng/Makefile   |   1 +
>  drivers/rng/stm32mp1_rng.c | 158 
> +
>  3 files changed, 166 insertions(+)
>  create mode 100644 drivers/rng/stm32mp1_rng.c
>
> diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> index dd44cc0..5fc11db 100644
> --- a/drivers/rng/Kconfig
> +++ b/drivers/rng/Kconfig
> @@ -5,3 +5,10 @@ config DM_RNG
> Enable driver model for random number generator(rng) devices.
> This interface is used to initialise the rng device and to
> read the random seed from the device.
> +
> +config RNG_STM32MP1
> +   bool "Enable random number generator for STM32MP1"
> +   depends on ARCH_STM32MP && DM_RNG
> +   default n
> +   help
> + Enable STM32MP1 rng driver.
> diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> index 311705b..699beb3 100644
> --- a/drivers/rng/Makefile
> +++ b/drivers/rng/Makefile
> @@ -4,3 +4,4 @@
>  #
>  
>  obj-$(CONFIG_DM_RNG) += rng-uclass.o
> +obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
> diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
> new file mode 100644
> index 000..5cd736d
> --- /dev/null
> +++ b/drivers/rng/stm32mp1_rng.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (c) 2019, Linaro Limited
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +#define RNG_CR 0x00
> +#define RNG_CR_RNGEN BIT(2)
> +#define RNG_CR_CED BIT(5)
> +
> +#define RNG_SR 0x04
> +#define RNG_SR_SEIS BIT(6)
> +#define RNG_SR_CEIS BIT(5)
> +#define RNG_SR_SECS BIT(2)
> +#define RNG_SR_DRDY BIT(0)
> +
> +#define RNG_DR 0x08
> +
> +struct stm32_rng_platdata {
> + fdt_addr_t base;
> + struct clk clk;
> + struct reset_ctl rst;
> +};
> +
> +static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
> +{
> + int retval = 0, i;
> + u32 sr, count, reg;
> + size_t increment;
> + struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
> +
> + while (len > 0) {
> + retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
> + sr & RNG_SR_DRDY, 1);
> + if (retval)
> + return retval;
> +
> + if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
> + /* As per SoC TRM */
> + clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
> + for (i = 0; i < 12; i++)
> + readl(pdata->base + RNG_DR);
> + if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
> + printf("RNG Noise");
> + return -EIO;
> + }
> + /* start again */
> + continue;
> + }
> +
> + count = 4;
> + while (len && count) {
> + reg = readl(pdata->base + RNG_DR);
> + memcpy(data, ®, min(len, sizeof(u32)));
> + increment = min(len, sizeof(u32));
> + data += increment;
> + retval += increment;
> + len -= increment;
> + count--;
> + }
> + }
> +
> + return retval;
> +}
> +
> +static int stm32_rng_init(struct stm32_rng_platdata *pdata)
> +{
> + int err;
> +
> + err = clk_enable(&pdata->clk);
> + if (err)
> + return err;
> +
> + /* Disable CED */
> + writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR);
> +
> + /* clear error indicators */
> + writel(0, pdata->base + RNG_SR);
> +
> + return 0;
> +}
> +
> +static int stm32_rng_cleanup(struct stm32_rng_platdata *pdata)
> +{
> +
> + writel(0, pdata->base + RNG_CR);
> +
> + return clk_disable(&pdata->clk);
> +}
> +
> +static int stm32_rng_probe(struct udevice *dev)
> +{
> + struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
> +
> + reset_assert(&pdata->rst);
> + udelay(20);
> + reset_deassert(&pdata->rst);
> +
> + return stm32_rng_init(pdata);
> +}
> +
> +static int stm32_rng_remove(struct udevice *dev)
> +{
> + struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
> +
> + return stm32_rng_cleanup(pdata);
> +}
> +
> +static int stm32_rng_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
> + int err;
> +
> + pdata->base = dev_read_addr(dev);
> + if (!pdata->base)
> + return -ENOMEM;
> +
>

Re: [U-Boot] [PATCH v2 3/8] cmd: bootimg: Add bootimg command

2019-12-05 Thread Eugeniu Rosca
On Thu, Dec 05, 2019 at 04:17:38AM +0200, Aleksandr Bulyshchenko wrote:
>Hello Sam,
>I'd like to add my 5 cents regarding separating dtimg start|size into 3
>subcommands
> 
>  dtimg start index   [varname]
>  dtimg start id   [varname]
>  dtimg start rev   [varname]
> 
>While I don't see real usecases for combining index with id or rev (if
>someone applies metainformation to dtb entries for meaningful lookup,
>identical entries most probably mean copy-paste error),
>but at the same time I see space for at least two-factor identification
>(e.g. model and revision).
>Thus API should allow (but not require) combining id and rev.
>The same remains relevant for abootimg as well.

[shameless plug] Agreed with Aleksandr. Users will want to provide 
and  (and possibly cust[0-4] in future) in one go/command launch.

-- 
Best Regards,
Eugeniu


[PATCH v2 2/3] doc: rockchip: document packing second level loader with mkimage

2019-12-05 Thread Jeffy Chen
Add documentation about packing optional second level boot-loader with
mkimage tool.

Signed-off-by: Jeffy Chen 
---

Changes in v2: None

 doc/README.rockchip | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 67c14006a3..39dc9c5e9f 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -341,6 +341,12 @@ You can create the image via the following operations:
cat firefly-rk3288/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
 
+Or:
+   ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
+   firefly-rk3288/spl/u-boot-spl-dtb.bin:firefly-rk3288/u-boot-dtb.bin \
+   out && \
+   sudo dd if=out of=/dev/sdc seek=64
+
 If you have an HDMI cable attached you should see a video console.
 
 For evb_rk3036 board:
@@ -348,6 +354,11 @@ For evb_rk3036 board:
cat evb-rk3036/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
 
+Or:
+   ./evb-rk3036/tools/mkimage -n rk3036 -T rksd -d \
+   evb-rk3036/spl/u-boot-spl.bin:evb-rk3036/u-boot-dtb.bin out && \
+   sudo dd if=out of=/dev/sdc seek=64
+
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, 
the
   debug uart must be disabled
 
-- 
2.11.0





[PATCH v2 0/3] mkimage/rockchip: support packing optional second level boot-loader

2019-12-05 Thread Jeffy Chen


When enabling back-to-bootrom, the bootrom would continue to load the
second level boot-loader. And currently we are packing it by appending
the generated image manually (with a predefined max size):

./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
   firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
   cat firefly-rk3288/u-boot-dtb.bin >> out

This series add support of packing optional second level loader with
mkimage tool:
./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out


Changes in v2:
Do rc4 encode for boot data when needed as well.

Jeffy Chen (3):
  rockchip: mkimage: support packing optional second level boot-loader
  doc: rockchip: document packing second level loader with mkimage
  rockchip: mkimage: fix wrong range of rc4 encoding for boot image

 doc/README.rockchip |  11 +++
 tools/imagetool.h   |   1 +
 tools/mkimage.c |   8 ++
 tools/rkcommon.c| 245 +++-
 tools/rkcommon.h|  18 ++--
 tools/rkimage.c |   2 +-
 tools/rksd.c|  35 +---
 tools/rkspi.c   |  42 +++--
 8 files changed, 245 insertions(+), 117 deletions(-)

-- 
2.11.0





[PATCH v2 1/3] rockchip: mkimage: support packing optional second level boot-loader

2019-12-05 Thread Jeffy Chen
Support packing optional second level boot-loader:

$ ./tools/mkimage -n rk3399 -T rksd -d \
  rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image Type:   Rockchip RK33 (SD/MMC) boot image
Init Data Size: 116736 bytes
Boot Data Size: 88064 bytes

Mainly parse init file and boot file from datafile option, copy them to
the image with 2KB alignment.

Signed-off-by: Jeffy Chen 
---

Changes in v2:
Do rc4 encode for boot data when needed as well.

 tools/imagetool.h |   1 +
 tools/mkimage.c   |   8 ++
 tools/rkcommon.c  | 245 --
 tools/rkcommon.h  |  18 ++--
 tools/rksd.c  |  35 +---
 tools/rkspi.c |  42 --
 6 files changed, 233 insertions(+), 116 deletions(-)

diff --git a/tools/imagetool.h b/tools/imagetool.h
index 2689a4004a..e1c778b0df 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -253,6 +253,7 @@ void pbl_load_uboot(int fd, struct image_tool_params 
*mparams);
 int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
 int imx8image_copy_image(int fd, struct image_tool_params *mparams);
 int imx8mimage_copy_image(int fd, struct image_tool_params *mparams);
+int rockchip_copy_image(int fd, struct image_tool_params *mparams);
 
 #define ___cat(a, b) a ## b
 #define __cat(a, b) ___cat(a, b)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 4217188310..5f51d2cc89 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -544,6 +544,14 @@ int main(int argc, char **argv)
ret = imx8mimage_copy_image(ifd, ¶ms);
if (ret)
return ret;
+   } else if ((params.type == IH_TYPE_RKSD) ||
+   (params.type == IH_TYPE_RKSPI)) {
+   /* Rockchip has special Image format */
+   int ret;
+
+   ret = rockchip_copy_image(ifd, ¶ms);
+   if (ret)
+   return ret;
} else {
copy_file(ifd, params.datafile, pad_len);
}
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0d908daee8..5fcd2a55d5 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -14,8 +14,6 @@
 #include "mkimage.h"
 #include "rkcommon.h"
 
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
 enum {
RK_SIGNATURE= 0x0ff0aa55,
 };
@@ -80,6 +78,24 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false },
 };
 
+/**
+ * struct spl_params - spl params parsed in check_params()
+ *
+ * @init_file: Init data file path
+ * @init_size: Aligned size of init data in bytes
+ * @boot_file: Boot data file path
+ * @boot_size: Aligned size of boot data in bytes
+ */
+
+struct spl_params {
+   char *init_file;
+   uint32_t init_size;
+   char *boot_file;
+   uint32_t boot_size;
+};
+
+static struct spl_params spl_params = { 0 };
+
 static unsigned char rc4_key[16] = {
124, 78, 3, 4, 85, 5, 9, 7,
45, 44, 123, 56, 23, 13, 23, 17
@@ -99,12 +115,25 @@ static struct spl_info *rkcommon_get_spl_info(char 
*imagename)
return NULL;
 }
 
-int rkcommon_check_params(struct image_tool_params *params)
+static int rkcommon_get_aligned_size(struct image_tool_params *params,
+const char *fname)
 {
-   int i;
+   int size;
 
-   if (rkcommon_get_spl_info(params->imagename) != NULL)
-   return EXIT_SUCCESS;
+   size = imagetool_get_filesize(params, fname);
+   if (size < 0)
+   return -1;
+
+   /*
+* Pad to a 2KB alignment, as required for init/boot size by the ROM
+* (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html)
+*/
+   return ROUND(size, RK_SIZE_ALIGN);
+}
+
+int rkcommon_check_params(struct image_tool_params *params)
+{
+   int i, spl_size;
 
/*
 * If this is a operation (list or extract), the don't require
@@ -113,6 +142,41 @@ int rkcommon_check_params(struct image_tool_params *params)
if (params->lflag || params->iflag)
return EXIT_SUCCESS;
 
+   if (!rkcommon_get_spl_info(params->imagename))
+   goto err_spl_info;
+
+   spl_params.init_file = params->datafile;
+
+   spl_params.boot_file = strchr(spl_params.init_file, ':');
+   if (spl_params.boot_file) {
+   *spl_params.boot_file = '\0';
+   spl_params.boot_file += 1;
+   }
+
+   spl_params.init_size =
+   rkcommon_get_aligned_size(params, spl_params.init_file);
+   if (spl_params.init_size < 0)
+   return EXIT_FAILURE;
+
+   /* Boot file is optional, and only for back-to-bootrom functionality. */
+   if (spl_params.boot_file) {
+   

Re: [PATCH v1 3/5] colibri_imx6: add update_uboot wrapper

2019-12-05 Thread Igor Opaniuk
Hi Lukasz,

On Thu, Dec 5, 2019 at 12:46 AM Lukasz Majewski  wrote:
>
> Hi Igor,
>
> > From: Igor Opaniuk 
> >
> > Add universal update_uboot wrapper that helps to update
> > U-Boot image on internal storage.
> >
> > > tftpboot ${loadaddr} ${board_name}/u-boot.img
> > > run update_uboot
> > > tftpboot ${loadaddr} ${board_name}/SPL
> > > run update_spl
> >
> > Signed-off-by: Igor Opaniuk 
> > ---
> >
> >  include/configs/colibri_imx6.h | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/include/configs/colibri_imx6.h
> > b/include/configs/colibri_imx6.h index 95b5a14b59..750463ef47 100644
> > --- a/include/configs/colibri_imx6.h
> > +++ b/include/configs/colibri_imx6.h
> > @@ -110,6 +110,17 @@
> >   "imx6dl-colibri-eval-v3.dtb fat 0 1;" \
> >   "imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
> >
> > +#define UBOOT_UPDATE \
> > + "uboot_hwpart=1\0" \
> > + "uboot_blk=8a\0" \
> > + "uboot_spl_blk=2\0" \
> > + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
> > + "setexpr blkcnt ${blkcnt} / 0x200\0" \
> > + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
> > " \
> > + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
> > + "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && "
> > \
> > + "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0"
> > +
>
> Do you see any chance to make this code common and being re-usable by
> other imx6 devices?

Not sure, because:
1. Some platforms use "user" hw partition instead of boot0 for
storing SPL/U-boot proper (AFAIK this is actual for i.MX6Q Sabre)
IMHO, for this case it's much more convenient to use DFU/UMS/Fastboot
(which is not possible for boot0/boot1) for flashing instead of some
wrapper like this.
2. I don't have any mx6-based boards other than from Toradex, so at
least I won't be
able to test it.

If you insist, I can add "update_uboot" to the common include, but to be honest
I really doubt that someone will use it :)

>
> >  #define EMMC_BOOTCMD \
> >   "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
> >   "rw,noatime rootfstype=ext4 " \
> > @@ -163,6 +174,7 @@
> >   "fdt_fixup=;\0" \
> >   MEM_LAYOUT_ENV_SETTINGS \
> >   NFS_BOOTCMD \
> > + UBOOT_UPDATE \
> >   "setethupdate=if env exists ethaddr; then; else setenv
> > ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
> >   "flash_eth.img && source ${loadaddr}\0" \
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de

Thanks
--
Best regards - Freundliche Grüsse - Meilleures salutations

Igor Opaniuk

mailto: igor.opan...@gmail.com
skype: igor.opanyuk
+380 (93) 836 40 67
http://ua.linkedin.com/in/iopaniuk


rk3328-firefly ddr4 tpl init

2019-12-05 Thread Peter Geis
Good Evening,

I am trying to get TPL/SPL working on the rk3328-firefly ddr4 4gb board.
I've pulled the ddr4 dtsi from the rockchip u-boot repository [0].

Unfortunately I cannot get the ddr4 to detect correctly.

With the u-boot tpl, I get the following:
U-Boot TPL 2020.01-rc3-00072-g1a1bea82b2-dirty (Dec 04 2019 - 08:33:54)
data training error
row errordata training error
DDR4, 333MHz
BW=16 Col=10 Bk=4 BG=2 CS0 Row=17 CS=1 Die BW=16 Size=2048MB

With the rk3328_ddr_333MHz_v1.16.bin, I get the following:
DDR version 1.16 20190528
ID:0x805 N
In
DDR4
333MHz
Bus Width=32 Col=10 Bank=4 Bank Group=2 Row=16/16 CS=2 Die
Bus-Width=16 Size=4096MB
ddrconfig:19
OUT

[0] 
https://github.com/rockchip-linux/u-boot/blob/next-dev/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi


[PATCH v2 3/3] rockchip: mkimage: fix wrong range of rc4 encoding for boot image

2019-12-05 Thread Jeffy Chen
The rc4 encoding should cover spl header as well, and the file_size
contains spl header too.

Signed-off-by: Jeffy Chen 
---

Changes in v2: None

 tools/rkimage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/rkimage.c b/tools/rkimage.c
index ae50de55c9..1c5540b1c3 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -18,7 +18,7 @@ static void rkimage_set_header(void *buf, struct stat *sbuf, 
int ifd,
memcpy(buf, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
 
if (rkcommon_need_rc4_spl(params))
-   rkcommon_rc4_encode_spl(buf, 4, params->file_size);
+   rkcommon_rc4_encode_spl(buf, 0, params->file_size);
 }
 
 static int rkimage_check_image_type(uint8_t type)
-- 
2.11.0





Re: [U-Boot] [PATCH v2 3/8] cmd: bootimg: Add bootimg command

2019-12-05 Thread Aleksandr Bulyshchenko
Hello Sam,

I'd like to add my 5 cents regarding separating dtimg start|size into 3
subcommands

> dtimg start index   [varname]
> dtimg start id   [varname]
> dtimg start rev   [varname]
>
> While I don't see real usecases for combining index with id or rev (if
someone applies metainformation to dtb entries for meaningful lookup,
identical entries most probably mean copy-paste error),
but at the same time I see space for at least two-factor identification
(e.g. model and revision).
Thus API should allow (but not require) combining id and rev.

The same remains relevant for abootimg as well.

Thanks,
Aleksandr Bulyshchenko

On Wed, Dec 4, 2019 at 9:12 PM Sam Protsenko 
wrote:

> Hi,
>
> On Wed, Dec 4, 2019 at 7:33 PM Eugeniu Rosca 
> wrote:
> >
> > Hello Sam,
> > Please, see one more suggestion below.
> >
> > On Tue, Dec 03, 2019 at 08:29:10PM +0100, Eugeniu Rosca wrote:
> > > Hi Sam,
> > > Cc: Aleksandr, Roman
> > >
> > > As expressed in the attached e-mail, to minimize the headaches
> extending
> > > the argument list of "bootimg" in future, can we please agree on below?
> > >
> > > On Wed, Oct 23, 2019 at 05:34:22PM +0300, Sam Protsenko wrote:
> > > > +U_BOOT_CMD(
> > > > +   bootimg, CONFIG_SYS_MAXARGS, 0, do_bootimg,
> > > > +   "manipulate Android Boot Image",
> > > > +   "set_addr \n"
> > > > +   "- set the address in RAM where boot image is located\n"
> > > > +   "  ($loadaddr is used by default)\n"
> > > > +   "bootimg ver \n"
> > >
> > > Can we make  optional, with the background provided in [1]?
> > >
> > > > +   "- get header version\n"
> > > > +   "bootimg get_dtbo  [size_var]\n"
> > >
> > > How about converting  to an optional argument too?
> > >
> > > > +   "- get address and size (hex) of recovery DTBO area in the
> image\n"
> > > > +   "  : variable name to contain DTBO area address\n"
> > > > +   "  [size_var]: variable name to contain DTBO area size\n"
> > > > +   "bootimg dtb_dump\n"
> > > > +   "- print info for all files in DTB area\n"
> > > > +   "bootimg dtb_load_addr \n"
> > >
> > > Same as above w.r.t. .
> > >
> > > > +   "- get load address (hex) of DTB\n"
> > > > +   "bootimg get_dtb_file   [size_var]\n"
> >
> > How about "get_dte" or "get_dtbe" instead of "get_dtb_file" ?
> > It's shorter and should be easier to remember (dt{b}e = DT{B} Entry).
> >
>
> Sorry, I like get_dtb more. It's .dtb file in the end, and it's called
> exactly "dtb" in boot.img struct. So this is a keeper :)
>
> > --
> > Best Regards,
> > Eugeniu
>


Re: Load Debian/Fedora via EFI

2019-12-05 Thread Heinrich Schuchardt

On 12/5/19 11:21 AM, Michal Simek wrote:

I have separate partitions:

/boot of type 83 (Linux, ext2) and marked as bootable and with boot.scr
on it.
/boot/efi of type ef (EFI, vfat) and not marked as bootable

The sequence on the block device does not matter.

When booting via iSCSI with iPXE I put boot.scr and snp.efi on an EFI
partition marked as bootable.

That means that you had done that changes by hand.

Thanks,
Michal


If you boot the kernel of the Debian installer via UEFI, it installs
GRUB EFI but you may have to install flash-kernel manually.

If you you want to use iPXE on ARM, you are on your own. There isn't
even a package with snp.efi provided by Debian. But at least the
installer allows you to set up your partitions and do the installation
on an iSCSI drive.

Best regards

Heinrich


[PATCH 1/1] drivers: net: add Broadcom bnxt driver for supported platforms

2019-12-05 Thread Vladimir Olovyannikov
From: Suresh Channappa 

Add bnxt L2 driver support.
This driver is used by several Broadcom iProc platforms.

Signed-off-by: Suresh Channappa 
Signed-off-by: Vladimir Olovyannikov 
---
 drivers/net/Kconfig |1 +
 drivers/net/Makefile|1 +
 drivers/net/bnxt/Kconfig|8 +
 drivers/net/bnxt/Makefile   |5 +
 drivers/net/bnxt/bnxt.c | 2202 +++
 drivers/net/bnxt/bnxt.h |  403 +++
 drivers/net/bnxt/bnxt_dbg.h |  538 +
 drivers/net/bnxt/bnxt_hsi.h |  889 ++
 drivers/net/bnxt/bnxt_ver.h |   22 +
 drivers/net/bnxt/pci_ids.h  |   17 +
 10 files changed, 4086 insertions(+)
 create mode 100644 drivers/net/bnxt/Kconfig
 create mode 100644 drivers/net/bnxt/Makefile
 create mode 100644 drivers/net/bnxt/bnxt.c
 create mode 100644 drivers/net/bnxt/bnxt.h
 create mode 100644 drivers/net/bnxt/bnxt_dbg.h
 create mode 100644 drivers/net/bnxt/bnxt_hsi.h
 create mode 100644 drivers/net/bnxt/bnxt_ver.h
 create mode 100644 drivers/net/bnxt/pci_ids.h

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4182897d89..3c136eeaa7 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,6 +1,7 @@
 source "drivers/net/phy/Kconfig"
 source "drivers/net/pfe_eth/Kconfig"
 source "drivers/net/fsl-mc/Kconfig"
+source "drivers/net/bnxt/Kconfig"

 config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 30991834ec..7b26cf9f2c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -3,6 +3,7 @@
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.

+obj-$(CONFIG_BNXT_ETH) += bnxt/
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
 obj-$(CONFIG_AG7XXX) += ag7xxx.o
 obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig
new file mode 100644
index 00..0805f6e53d
--- /dev/null
+++ b/drivers/net/bnxt/Kconfig
@@ -0,0 +1,8 @@
+config BNXT_ETH
+   bool "BNXT PCI support"
+   depends on DM_ETH && DM_PCI
+   help
+ This driver implements support for
+ Broadcom pcie BCM57320 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb
+ RDMA Ethernet Controller (bnxt pci controller).
+ The controller is used on Broadcom iProc platforms.
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
new file mode 100644
index 00..6ba101b44c
--- /dev/null
+++ b/drivers/net/bnxt/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Broadcom.
+
+# Broadcom nxe Ethernet driver
+obj-y += bnxt.o
\ No newline at end of file
diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c
new file mode 100644
index 00..45199083b1
--- /dev/null
+++ b/drivers/net/bnxt/bnxt.c
@@ -0,0 +1,2202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "bnxt.h"
+#include "bnxt_dbg.h"
+#include "pci_ids.h"
+
+static void print_mac(u8 *mac, u8 flag);
+static const char banner[]  = DRV_MODULE_DESC " v" UBOOT_MODULE_VER ",";
+static const char fw_ver[]  = " FW v";
+
+static void display_banner(struct bnxt *bp)
+{
+   int i;
+
+   printf(banner);
+   printf(fw_ver);
+   printf("%d.%d.", bp->fw_maj, bp->fw_min);
+   printf("%d.%d\n", bp->fw_bld, bp->fw_rsvd);
+   printf("ETH MAC: ");
+   for (i = 0; i < ETH_ALEN; i++) {
+   printf("%02x", bp->mac_set[i]);
+   if (i != (ETH_ALEN - 1))
+   printf(":");
+   }
+
+   printf(", Port(%d), PF(%d)\n", bp->port_idx, bp->ordinal_value);
+}
+
+/* Broadcom ethernet driver PCI APIs. */
+static void bnxt_bring_pci(struct bnxt *bp)
+{
+   u16 cmd_reg = 0;
+
+   pci_read_word16(bp->pdev, PCI_VENDOR_ID, &bp->vendor_id);
+   pci_read_word16(bp->pdev, PCI_DEVICE_ID, &bp->device_id);
+   pci_read_word16(bp->pdev,
+   PCI_SUBSYSTEM_VENDOR_ID,
+   &bp->subsystem_vendor);
+   pci_read_word16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device);
+   pci_read_word16(bp->pdev, PCI_COMMAND, &bp->cmd_reg);
+   pci_read_byte(bp->pdev, PCICFG_ME_REGISTER, &bp->pf_num);
+   pci_read_byte(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq);
+   bp->bar0 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+   bp->bar1 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+   bp->bar2 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
+   cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+   cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */
+   pci_write_word(bp->pdev, PCI_COMMAND, cmd_reg);
+   pci_read_word16(bp->pdev, PCI_COMMAND, &cmd_reg);
+   dbg_pci(bp, __func__, cmd_reg);
+}
+
+int bnxt_free_rx_iob(struct bnxt *bp)
+{
+   unsigned int i;

[PATCH v2 0/7] Add a random number generator uclass

2019-12-05 Thread Sughosh Ganu
Add a random number generator(rng) uclass to facilitate adding drivers
for rng devices. I plan to add an implementation of the
EFI_RNG_PROTOCOL, which would get the random number from the rng
uclass -- the protocol would be used by the efi stub for getting a
random number for the kaslr feature.

The patch series also adds a driver for the rng device found on the
stm32mp1 platforms. A dummy rng driver for sandbox has also been
added, along with the unit test for the rng uclass.

Changes since V1:
* Add a SPDX header in rng.h
* Change the UCLASS_DRIVER name from hwrng to rng, consistent with the
  rest of the naming convention
* Handle review comment from Patrice Chotard

Sughosh Ganu (7):
  dm: rng: Add random number generator(rng) uclass
  clk: stm32mp1: Add a clock entry for RNG1 device
  stm32mp1: rng: Add a driver for random number generator(rng) device
  configs: stm32mp15: Enable random number generator(rng) device
  sandbox: rng: Add a random number generator(rng) driver
  configs: sandbox: Enable random number generator(rng) device
  test: rng: Add basic test for random number generator(rng) uclass

 arch/sandbox/dts/test.dts   |   4 +
 configs/sandbox64_defconfig |   2 +
 configs/sandbox_defconfig   |   2 +
 configs/stm32mp15_basic_defconfig   |   2 +
 configs/stm32mp15_optee_defconfig   |   2 +
 configs/stm32mp15_trusted_defconfig |   2 +
 drivers/Kconfig |   2 +
 drivers/Makefile|   1 +
 drivers/clk/clk_stm32mp1.c  |   1 +
 drivers/rng/Kconfig |  21 +
 drivers/rng/Makefile|   8 ++
 drivers/rng/rng-uclass.c|  23 ++
 drivers/rng/sandbox_rng.c   |  36 
 drivers/rng/stm32mp1_rng.c  | 158 
 include/dm/uclass-id.h  |   1 +
 include/rng.h   |  30 +++
 test/dm/Makefile|   1 +
 test/dm/rng.c   |  26 ++
 18 files changed, 322 insertions(+)
 create mode 100644 drivers/rng/Kconfig
 create mode 100644 drivers/rng/Makefile
 create mode 100644 drivers/rng/rng-uclass.c
 create mode 100644 drivers/rng/sandbox_rng.c
 create mode 100644 drivers/rng/stm32mp1_rng.c
 create mode 100644 include/rng.h
 create mode 100644 test/dm/rng.c

-- 
2.7.4



Re: [PATCH] usb: cdns3: ep0: Fix build warnings related to cache ops

2019-12-05 Thread Marek Vasut
On 12/5/19 8:59 AM, Vignesh Raghavendra wrote:
> Since, commit 62f9b6544728 ("common: Move older CPU functions to their own 
> header")
> cache ops functions are declared in a separate header. Include the same
> to avoid build warnings.

Applied, thanks.


Re: [U-Boot] [PATCH v2 3/8] cmd: bootimg: Add bootimg command

2019-12-05 Thread Sam Protsenko
Hi Aleksandr,

On Thu, Dec 5, 2019 at 4:17 AM Aleksandr Bulyshchenko
 wrote:
>
> Hello Sam,
>
> I'd like to add my 5 cents regarding separating dtimg start|size into 3 
> subcommands
>>
>> dtimg start index   [varname]
>> dtimg start id   [varname]
>> dtimg start rev   [varname]
>
> While I don't see real usecases for combining index with id or rev (if 
> someone applies metainformation to dtb entries for meaningful lookup, 
> identical entries most probably mean copy-paste error),
> but at the same time I see space for at least two-factor identification (e.g. 
> model and revision).
> Thus API should allow (but not require) combining id and rev.
>

Agreed on id+rev usage. Can we still try and keep the interface as
simple as possible, e.g. like this:

dtimg start index   [varname]
dtimg start id [varname]

In case when user wants to use only "id" or only  "rev", other bit
should be specified as "-":

dtimg start id 10 - -  [varname]
dtimg start id - 10 -  [varname]

It's similar to what is done in 'bootm' command:

To boot that kernel without an initrd image,use a '-' for the
second argument.

This way we can keep away the 'index' usage, making two things possible:
  1. Code will be easier (we can provide one function for 'index' case
and one function for 'id/rev/custom' case)
  2. Easier for us to split the work and avoid dependencies between
our patch series

If everyone agrees on usage I suggested above, we can go ahead and
change it correspondingly for 'dtimg' and 'abootimg' patch series.

> The same remains relevant for abootimg as well.
>
> Thanks,
> Aleksandr Bulyshchenko
>
> On Wed, Dec 4, 2019 at 9:12 PM Sam Protsenko  
> wrote:
>>
>> Hi,
>>
>> On Wed, Dec 4, 2019 at 7:33 PM Eugeniu Rosca  wrote:
>> >
>> > Hello Sam,
>> > Please, see one more suggestion below.
>> >
>> > On Tue, Dec 03, 2019 at 08:29:10PM +0100, Eugeniu Rosca wrote:
>> > > Hi Sam,
>> > > Cc: Aleksandr, Roman
>> > >
>> > > As expressed in the attached e-mail, to minimize the headaches extending
>> > > the argument list of "bootimg" in future, can we please agree on below?
>> > >
>> > > On Wed, Oct 23, 2019 at 05:34:22PM +0300, Sam Protsenko wrote:
>> > > > +U_BOOT_CMD(
>> > > > +   bootimg, CONFIG_SYS_MAXARGS, 0, do_bootimg,
>> > > > +   "manipulate Android Boot Image",
>> > > > +   "set_addr \n"
>> > > > +   "- set the address in RAM where boot image is located\n"
>> > > > +   "  ($loadaddr is used by default)\n"
>> > > > +   "bootimg ver \n"
>> > >
>> > > Can we make  optional, with the background provided in [1]?
>> > >
>> > > > +   "- get header version\n"
>> > > > +   "bootimg get_dtbo  [size_var]\n"
>> > >
>> > > How about converting  to an optional argument too?
>> > >
>> > > > +   "- get address and size (hex) of recovery DTBO area in the 
>> > > > image\n"
>> > > > +   "  : variable name to contain DTBO area address\n"
>> > > > +   "  [size_var]: variable name to contain DTBO area size\n"
>> > > > +   "bootimg dtb_dump\n"
>> > > > +   "- print info for all files in DTB area\n"
>> > > > +   "bootimg dtb_load_addr \n"
>> > >
>> > > Same as above w.r.t. .
>> > >
>> > > > +   "- get load address (hex) of DTB\n"
>> > > > +   "bootimg get_dtb_file   [size_var]\n"
>> >
>> > How about "get_dte" or "get_dtbe" instead of "get_dtb_file" ?
>> > It's shorter and should be easier to remember (dt{b}e = DT{B} Entry).
>> >
>>
>> Sorry, I like get_dtb more. It's .dtb file in the end, and it's called
>> exactly "dtb" in boot.img struct. So this is a keeper :)
>>
>> > --
>> > Best Regards,
>> > Eugeniu


Re: [PATCH v2] arm64: zynqmp: Add support for u-boot.itb generation with ATF

2019-12-05 Thread Tom Rini
On Thu, Dec 05, 2019 at 09:46:57AM +0100, Michal Simek wrote:
> Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
> includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
> quite a long time but with using out of tree solution. The patch is filling
> this gap.
> 
> Tested on zcu102, zcu104 and zcu100/Ultra96.
> 
> zcu100/Ultra96 v2.2 ATF build by:
> make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31
> 
> Signed-off-by: Michal Simek 
> ---
> 
> Changes in v2:
> - Exchange u-boot/atf in config section
> - Use default ATF baseaddr from mainline
> - Update commit message
> 
>  Kconfig |  3 +-
>  arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 99 +

My only complaint here is adding and N'th version of mkimage_fit_atf.sh
that varies seemingly only in addresses.  Can we not abstract this
enough to make it for everyone to use and pass in the needed values?

-- 
Tom


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Re: Load Debian/Fedora via EFI

2019-12-05 Thread Tom Rini
On Tue, Dec 03, 2019 at 08:51:09PM +0100, Heinrich Schuchardt wrote:
> On 12/2/19 3:21 PM, Michal Simek wrote:
> > On 29. 11. 19 19:23, Heinrich Schuchardt wrote:
> >> On 11/29/19 11:16 AM, Michal Simek wrote:
> >>> Hi,
> >>>
> >>> I tried to boot latest debian and fedora rootfs via distro boot and
> >>> getting errors.
> >>> I have tried to run just one command and it is failing.
> >>>
> >>> ZynqMP> bootefi bootmgr ${fdtcontroladdr}
> >>> BootOrder not defined
> >>> EFI boot manager: Cannot load any image
> >>>
> >>> How to define BootOrder?
> >>>
> >>> Thanks,
> >>> Michal
> >>
> >> # Booting via boot manager
> >>
> >> U-Boot currently has no runtime support for variables. But Linaro is
> >> working on it. So update-grub cannot set the variables for you.
> >
> > Who from Linaro is working on it? Akashi?
> 
> I was in contact with Ilias Apalodimas but do not know who is doing the
> actual work.
> 
> See https://youtu.be/SEMJGOzjrHY @ 14:00
> 
> >
> >>
> >> You can use the efidebug command to prepare for booting via the boot
> >> manager:
> >>
> >> => efidebug boot add 0001 Debian mmc 0:1 \
> >>    efi/debian/grubarm.efi console=${console}
> >>
> >> There seems to be a bug with communication lines in U-Boot. So you
> >> actually have to put this into a single line.
> >>
> >> => efidebug boot order 0001
> >>
> >> Use saveenv if you want to save the settings.
> >>
> >> If you do not want to use the internal device tree load the proper
> >> device tree, e.g.
> >>
> >> => load mmc 0:2 $fdt_addr_r dtb
> >>
> >> Now you are ready to boot via the boot manager:
> >>
> >> => bootefi bootmgr $fdt_addr_r
> >>
> >> # Booting via distro defaults
> >>
> >> DISTRO_DEFAULTS tries to load the devicetree from ${fdtfile} and the
> >> UEFI binary from efi/boot/bootaa64.efi on ARM64. See
> >> ./include/config_distro_bootcmd.h.
> >>
> >> OpenBSD and FreeBSD follow the distro boot convention, Debian GRUB does
> >> not.
> >
> > Fedora is the same case.
> > I got it working based on your guidance but would be IMHO better to
> > extend distroboot to cover one of the major distribution even through
> > workaround till variable support is done.
> 
> I don't like the idea of distribution specific stuff getting into U-Boot.
> 
> We would end up with a plethora of possible UEFI binaries to search for:
> shim, GRUB, iPXE, any Linux kernel. All of these are binaries could be
> used for booting Fedora, Debian, or any other Linux distribution via
> bootefi. And which one should we take if there is more than one of these?
> 
> I especially dislike any claim that one distribution is "major" and
> another is not. Should we kick out CentOS and Fedora because they are
> less popular than Ubuntu and Android?
> 
> So let's leave it to the distribution to create boot.scr or provide a
> binary following the naming convention given in the UEFI specification
> (chapter 3.5.1.1 Removable Media Boot Behavior).
> 
> >
> >>
> >> # Booting via boot script.
> >>
> >> On Debian I use package flash-kernel to keep /boot/dtb in sync with the
> >> kernel and have a u-boot.scr.uimg script with something like the
> >> following lines:
> >>
> >> setenv bootargs console=${console}
> >> load mmc 2:1 ${kernel_addr_r} EFI/debian/grubarm.efi
> >> load mmc 2:2 ${fdt_addr_r} dtb
> >> bootefi ${kernel_addr_r} ${fdt_addr_r}
> >
> >
> > flash-kernel is interesting. It generates u-boot script but if extX
> > partition has no bootable flag u-boot distroboot ignores it completely.
> > What's your default partition setup?
> 
> I have separate partitions:
> 
> /boot of type 83 (Linux, ext2) and marked as bootable and with boot.scr
> on it.
> /boot/efi of type ef (EFI, vfat) and not marked as bootable
> 
> The sequence on the block device does not matter.
> 
> When booting via iSCSI with iPXE I put boot.scr and snp.efi on an EFI
> partition marked as bootable.

I'm concerned that we're talking about what Linux distros should /
shouldn't be doing right now, but haven't been CC'ing a lot of the folks
involved on that side of things.  Adding some folks.

-- 
Tom


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Re: [U-Boot] [PATCH v2] Prevented possible null dereference.

2019-12-05 Thread Tom Rini
On Mon, Aug 26, 2019 at 05:54:59AM -0700, Niv Shetrit wrote:

> Signed-off-by: Niv Shetrit 

Sorry for taking so long to get back to this.  A few problems.  And
re-ordering the diff to make explanation clearer:

> ---
>  common/cli_hush.c | 73 ---
>  1 file changed, 38 insertions(+), 35 deletions(-)
> 
> diff --git a/common/cli_hush.c b/common/cli_hush.c
> index 8f86e4aa4a..c14302c3ad 100644
> --- a/common/cli_hush.c
> +++ b/common/cli_hush.c
> @@ -3539,41 +3539,44 @@ static char *insert_var_value_sub(char *inp, int 
> tag_subst)
>   }
>   inp = ++p;
>   /* find the ending marker */
> - p = strchr(inp, SPECIAL_VAR_SYMBOL);
> + p = strchr(inp, SPECIAL_VAR_SYMBOL)

You forgot the trailing ';' so this can't compile and wasn't tested.

> - *p = '\0';
> - /* look up the value to substitute */
> - if ((p1 = lookup_param(inp))) {
> + p1 = lookup_param(inp)
> + if (p1 != NULL) {

Again you forgot a trailing ';' and you've expanded equivalent
statements.  If we had a single set of parenthesis, in other words:
if (p1 = lookup_param(inp)) {
   ...

it would still check if we got NULL/non-NULL, but gcc would complain:
warning: suggest parentheses around assignment used as truth value 
[-Wparenthese]

and with the parenthesis we have, it does what we want here.

But we have the extra set of parenthesis to say we care about the result
of that assignment and are doing this on purpose.

Which brings us to the other functional change (which is more visible
with git show -w or similar, to ignore whitespace changes):

> + p = strchr(inp, SPECIAL_VAR_SYMBOL)
> + if (p != NULL) {
> + *p = '\0';
> + /* look up the value to substitute */
> + p1 = lookup_param(inp)

[I've re-included the code above back here for more context]
You're making sure that if strchr gives us NULL back, we don't call
lookup_param.  But lookup_param handles being passed NULL correctly.

So in sum, there's no problem here.  Thanks for looking around.

-- 
Tom


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Re: [PATCH 1/2] rockchip: mkimage: support packing optional second level boot-loader

2019-12-05 Thread Kever Yang



On 2019/12/5 下午3:48, Jeffy Chen wrote:

Support packing optional second level boot-loader:

$ ./tools/mkimage -n rk3399 -T rksd -d \
   rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image Type:   Rockchip RK33 (SD/MMC) boot image
Init Data Size: 116736 bytes
Boot Data Size: 88064 bytes

Mainly parse init file and boot file from datafile option, copy them to
the image, and padding each one to 2KB boundary.

Signed-off-by: Jeffy Chen 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---

  tools/imagetool.h |   1 +
  tools/mkimage.c   |   8 ++
  tools/rkcommon.c  | 236 +-
  tools/rkcommon.h  |  18 ++---
  tools/rksd.c  |  35 +---
  tools/rkspi.c |  42 --
  6 files changed, 226 insertions(+), 114 deletions(-)

diff --git a/tools/imagetool.h b/tools/imagetool.h
index 2689a4004a..e1c778b0df 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -253,6 +253,7 @@ void pbl_load_uboot(int fd, struct image_tool_params 
*mparams);
  int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
  int imx8image_copy_image(int fd, struct image_tool_params *mparams);
  int imx8mimage_copy_image(int fd, struct image_tool_params *mparams);
+int rockchip_copy_image(int fd, struct image_tool_params *mparams);
  
  #define ___cat(a, b) a ## b

  #define __cat(a, b) ___cat(a, b)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 4217188310..5f51d2cc89 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -544,6 +544,14 @@ int main(int argc, char **argv)
ret = imx8mimage_copy_image(ifd, ¶ms);
if (ret)
return ret;
+   } else if ((params.type == IH_TYPE_RKSD) ||
+   (params.type == IH_TYPE_RKSPI)) {
+   /* Rockchip has special Image format */
+   int ret;
+
+   ret = rockchip_copy_image(ifd, ¶ms);
+   if (ret)
+   return ret;
} else {
copy_file(ifd, params.datafile, pad_len);
}
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0d908daee8..1095aa3426 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -80,6 +80,24 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false },
  };
  
+/**

+ * struct spl_params - spl params parsed in check_params()
+ *
+ * @init_file: Init data file path
+ * @init_size: Aligned size of init data in bytes
+ * @boot_file: Boot data file path
+ * @boot_size: Aligned size of boot data in bytes
+ */
+
+struct spl_params {
+   char *init_file;
+   uint32_t init_size;
+   char *boot_file;
+   uint32_t boot_size;
+};
+
+static struct spl_params spl_params = { 0 };
+
  static unsigned char rc4_key[16] = {
124, 78, 3, 4, 85, 5, 9, 7,
45, 44, 123, 56, 23, 13, 23, 17
@@ -99,12 +117,25 @@ static struct spl_info *rkcommon_get_spl_info(char 
*imagename)
return NULL;
  }
  
-int rkcommon_check_params(struct image_tool_params *params)

+static int rkcommon_get_aligned_size(struct image_tool_params *params,
+const char *fname)
  {
-   int i;
+   int size;
  
-	if (rkcommon_get_spl_info(params->imagename) != NULL)

-   return EXIT_SUCCESS;
+   size = imagetool_get_filesize(params, fname);
+   if (size < 0)
+   return -1;
+
+   /*
+* Pad to a 2KB alignment, as required for init/boot size by the ROM
+* (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html)
+*/
+   return ROUND(size, RK_SIZE_ALIGN);
+}
+
+int rkcommon_check_params(struct image_tool_params *params)
+{
+   int i, spl_size;
  
  	/*

 * If this is a operation (list or extract), the don't require
@@ -113,6 +144,41 @@ int rkcommon_check_params(struct image_tool_params *params)
if (params->lflag || params->iflag)
return EXIT_SUCCESS;
  
+	if (!rkcommon_get_spl_info(params->imagename))

+   goto err_spl_info;
+
+   spl_params.init_file = params->datafile;
+
+   spl_params.boot_file = strchr(spl_params.init_file, ':');
+   if (spl_params.boot_file) {
+   *spl_params.boot_file = '\0';
+   spl_params.boot_file += 1;
+   }
+
+   spl_params.init_size =
+   rkcommon_get_aligned_size(params, spl_params.init_file);
+   if (spl_params.init_size < 0)
+   return EXIT_FAILURE;
+
+   /* Boot file is optional, and only for back-to-bootrom functionality. */
+   if (spl_params.boot_file) {
+   spl_params.boot_size =
+   rkcommon_get_aligned_size(params, spl_params.boot_file);
+ 

Re: [PATCH] rockchip: rk3328: rock64: enable CONFIG_MISC_INIT_R

2019-12-05 Thread Kever Yang



On 2019/12/3 下午1:24, Ben Wolsieffer wrote:

This enables reading of the cpuid and a static MAC address.

Signed-off-by: Ben Wolsieffer 


Reviewed-by: Kever Yang 

Thanks,
- Kever


---

  configs/rock64-rk3328_defconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 14c77b0a4e..720b5e0424 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -19,6 +19,7 @@ CONFIG_FIT=y
  CONFIG_FIT_VERBOSE=y
  CONFIG_SPL_LOAD_FIT=y
  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
+CONFIG_MISC_INIT_R=y
  # CONFIG_DISPLAY_CPUINFO is not set
  CONFIG_DISPLAY_BOARDINFO_LATE=y
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set





Re: [PATCH] rockchip: allow loading larger kernels

2019-12-05 Thread Kever Yang



On 2019/12/3 下午1:40, Ben Wolsieffer wrote:

Recent versions of the Linux kernel with many options enabled have
grown large enough to overwrite the beginning of the initrd. For
example, the kernel I use on my Rock64 and RockPro64 is 34.1 MiB,
while only 31.5 MiB are available between kernel_addr_r and
ramdisk_addr_r.

This patch moves ramdisk_addr_r up by 32 MiB on the RK3328 and RK3399,
allowing for much larger kernels.

Signed-off-by: Ben Wolsieffer 


Reviewed-by: Kever Yang 

Thanks,
- Kever


---

  include/configs/rk3328_common.h | 2 +-
  include/configs/rk3399_common.h | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index e51e1b0e0e..b14da3a626 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -36,7 +36,7 @@
"pxefile_addr_r=0x0060\0" \
"fdt_addr_r=0x01f0\0" \
"kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0400\0"
+   "ramdisk_addr_r=0x0600\0"
  
  #include 

  #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 7331c6dc02..127ca1f09c 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -51,7 +51,7 @@
"pxefile_addr_r=0x0060\0" \
"fdt_addr_r=0x01f0\0" \
"kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0400\0"
+   "ramdisk_addr_r=0x0600\0"
  
  #ifndef ROCKCHIP_DEVICE_SETTINGS

  #define ROCKCHIP_DEVICE_SETTINGS





Re: [PATCH v2] pwm: rk_pwm: Make PWM driver to support all Rockchip Socs

2019-12-05 Thread Kever Yang



On 2019/12/3 下午5:49, David Wu wrote:

This PWM driver can be used to support pwm functions
for on all Rockchip Socs.

The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.

The RK3288 keep the current functions.

RK3308 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.

Signed-off-by: David Wu 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---
Change in v2: None
  - Remove RK3399 compatible

  arch/arm/include/asm/arch-rockchip/pwm.h |  17 ++-
  drivers/pwm/rk_pwm.c | 138 +++
  2 files changed, 130 insertions(+), 25 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h 
b/arch/arm/include/asm/arch-rockchip/pwm.h
index b5178db394..e8594055cd 100644
--- a/arch/arm/include/asm/arch-rockchip/pwm.h
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -7,13 +7,15 @@
  #ifndef _ASM_ARCH_PWM_H
  #define _ASM_ARCH_PWM_H
  
-struct rk3288_pwm {

-   u32 cnt;
-   u32 period_hpr;
-   u32 duty_lpr;
-   u32 ctrl;
+struct rockchip_pwm_regs {
+   unsigned long duty;
+   unsigned long period;
+   unsigned long cntr;
+   unsigned long ctrl;
  };
-check_member(rk3288_pwm, ctrl, 0xc);
+
+#define PWM_CTRL_TIMER_EN  (1 << 0)
+#define PWM_CTRL_OUTPUT_EN (1 << 3)
  
  #define RK_PWM_DISABLE  (0 << 0)

  #define RK_PWM_ENABLE   (1 << 0)
@@ -33,6 +35,9 @@ check_member(rk3288_pwm, ctrl, 0xc);
  #define PWM_OUTPUT_LEFT (0 << 5)
  #define PWM_OUTPUT_CENTER   (1 << 5)
  
+#define PWM_LOCK			(1 << 6)

+#define PWM_UNLOCK (0 << 6)
+
  #define PWM_LP_ENABLE   (1 << 8)
  #define PWM_LP_DISABLE  (0 << 8)
  
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c

index 88db294cf1..46888e9077 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -15,22 +15,38 @@
  #include 
  #include 
  
+DECLARE_GLOBAL_DATA_PTR;

+
+struct rockchip_pwm_data {
+   struct rockchip_pwm_regs regs;
+   unsigned int prescaler;
+   bool supports_polarity;
+   bool supports_lock;
+   u32 enable_conf;
+   u32 enable_conf_mask;
+};
+
  struct rk_pwm_priv {
-   struct rk3288_pwm *regs;
+   fdt_addr_t base;
ulong freq;
-   uint enable_conf;
+   u32 conf_polarity;
+   const struct rockchip_pwm_data *data;
  };
  
  static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)

  {
struct rk_pwm_priv *priv = dev_get_priv(dev);
  
+	if (!priv->data->supports_polarity) {

+   debug("%s: Do not support polarity\n", __func__);
+   return 0;
+   }
+
debug("%s: polarity=%u\n", __func__, polarity);
-   priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
if (polarity)
-   priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
+   priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
else
-   priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
+   priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  
  	return 0;

  }
@@ -39,20 +55,44 @@ static int rk_pwm_set_config(struct udevice *dev, uint 
channel, uint period_ns,
 uint duty_ns)
  {
struct rk_pwm_priv *priv = dev_get_priv(dev);
-   struct rk3288_pwm *regs = priv->regs;
+   const struct rockchip_pwm_regs *regs = &priv->data->regs;
unsigned long period, duty;
+   u32 ctrl;
  
  	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);

-   writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
-   PWM_CONTINUOUS | priv->enable_conf |
-   RK_PWM_DISABLE,
-   ®s->ctrl);
  
-	period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 100);

-   duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 100);
+   ctrl = readl(priv->base + regs->ctrl);
+   /*
+* Lock the period and duty of previous configuration, then
+* change the duty and period, that would not be effective.
+*/
+   if (priv->data->supports_lock) {
+   ctrl |= PWM_LOCK;
+   writel(ctrl, priv->base + regs->ctrl);
+   }
+
+   period = lldiv((uint64_t)priv->freq * period_ns,
+  priv->data->prescaler * 10);
+   duty = lldiv((uint64_t)priv->freq * duty_ns,
+priv->data->prescaler * 10);
+
+   writel(period, priv->base + regs->period);
+   writel(duty, priv->base + regs->duty);
+
+   if (priv->data->supports_polarity) {
+   ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
+   ctrl |= priv->conf_polarity;
+   }
+
+   /*
+* Unlock and set polarity at the same time

Re: [PATCH v2] arm: rockchip: rk3308: Initialize the iomux configuration

2019-12-05 Thread Kever Yang



On 2019/12/3 下午7:02, David Wu wrote:

When we want to use plus pinctrl feature, we need to enable
them at spl.

Signed-off-by: David Wu 
---
Change in v2:
  - Fix GPIO3B2_SEL_SRC_CTRL_SEL_PLUS

  arch/arm/mach-rockchip/rk3308/rk3308.c | 37 ++


Reviewed-by: Kever Yang 

Thanks,
- Kever

  1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c 
b/arch/arm/mach-rockchip/rk3308/rk3308.c
index f27f9e8c0b..b6815ddc55 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -72,6 +72,11 @@ enum {
UART2_IO_SEL_M1,
UART2_IO_SEL_USB,
  
+	GPIO2C0_SEL_SRC_CTRL_SHIFT	= 11,

+   GPIO2C0_SEL_SRC_CTRL_MASK   = BIT(11),
+   GPIO2C0_SEL_SRC_CTRL_IOMUX  = 0,
+   GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
+
GPIO3B3_SEL_SRC_CTRL_SHIFT  = 7,
GPIO3B3_SEL_SRC_CTRL_MASK   = BIT(7),
GPIO3B3_SEL_SRC_CTRL_IOMUX  = 0,
@@ -97,6 +102,18 @@ enum {
GPIO3B2_SEL_PLUS_EMMC_RSTN,
GPIO3B2_SEL_PLUS_SPI1_MISO,
GPIO3B2_SEL_PLUS_LCDC_D22_M1,
+
+   I2C3_IOFUNC_SRC_CTRL_SHIFT  = 10,
+   I2C3_IOFUNC_SRC_CTRL_MASK   = BIT(10),
+   I2C3_IOFUNC_SRC_CTRL_SEL_PLUS   = 1,
+
+   GPIO2A3_SEL_SRC_CTRL_SHIFT  = 7,
+   GPIO2A3_SEL_SRC_CTRL_MASK   = BIT(7),
+   GPIO2A3_SEL_SRC_CTRL_SEL_PLUS   = 1,
+
+   GPIO2A2_SEL_SRC_CTRL_SHIFT  = 3,
+   GPIO2A2_SEL_SRC_CTRL_MASK   = BIT(3),
+   GPIO2A2_SEL_SRC_CTRL_SEL_PLUS   = 1,
  };
  
  enum {

@@ -166,10 +183,30 @@ __weak void board_debug_uart_init(void)
  int arch_cpu_init(void)
  {
static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
+   static struct rk3308_grf * const grf = (void *)GRF_BASE;
  
  	/* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */

rk_clrreg(&sgrf->con_secure0, 0x2b83);
  
+	/*

+* Enable plus options to use more pinctrl functions, including
+* GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
+*/
+   rk_clrsetreg(&grf->soc_con13,
+I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
+GPIO2A2_SEL_SRC_CTRL_MASK,
+I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << 
I2C3_IOFUNC_SRC_CTRL_SHIFT |
+GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << 
GPIO2A3_SEL_SRC_CTRL_SHIFT |
+GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << 
GPIO2A2_SEL_SRC_CTRL_SHIFT);
+
+   /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
+   rk_clrsetreg(&grf->soc_con15,
+GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
+GPIO3B2_SEL_SRC_CTRL_MASK,
+GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << 
GPIO2C0_SEL_SRC_CTRL_SHIFT |
+GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << 
GPIO3B3_SEL_SRC_CTRL_SHIFT |
+GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << 
GPIO3B2_SEL_SRC_CTRL_SHIFT);
+
return 0;
  }
  #endif





Re: [PATCH v2] pinctrl: rockchip: Add pinctrl support for rk3308

2019-12-05 Thread Kever Yang



On 2019/12/3 下午7:26, David Wu wrote:

An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.

For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.

So add a type IOMUX_8WIDTH_2BIT to calculate offset.

Signed-off-by: David Wu 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---
Change in v2:
  - None

  drivers/pinctrl/rockchip/Makefile |   1 +
  drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 ++
  .../pinctrl/rockchip/pinctrl-rockchip-core.c  |   3 +-
  drivers/pinctrl/rockchip/pinctrl-rockchip.h   |   1 +
  4 files changed, 468 insertions(+), 1 deletion(-)
  create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3308.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 83913f668f..fcf19f877a 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
  obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
  obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
  obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
  obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
  obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
  obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
new file mode 100644
index 00..abd57e54a5
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   

Re: [PATCH v2 1/3] rockchip: mkimage: support packing optional second level boot-loader

2019-12-05 Thread Kever Yang



On 2019/12/5 下午6:58, Jeffy Chen wrote:

Support packing optional second level boot-loader:

$ ./tools/mkimage -n rk3399 -T rksd -d \
   rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image Type:   Rockchip RK33 (SD/MMC) boot image
Init Data Size: 116736 bytes
Boot Data Size: 88064 bytes

Mainly parse init file and boot file from datafile option, copy them to
the image with 2KB alignment.

Signed-off-by: Jeffy Chen 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---

Changes in v2:
Do rc4 encode for boot data when needed as well.

  tools/imagetool.h |   1 +
  tools/mkimage.c   |   8 ++
  tools/rkcommon.c  | 245 --
  tools/rkcommon.h  |  18 ++--
  tools/rksd.c  |  35 +---
  tools/rkspi.c |  42 --
  6 files changed, 233 insertions(+), 116 deletions(-)

diff --git a/tools/imagetool.h b/tools/imagetool.h
index 2689a4004a..e1c778b0df 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -253,6 +253,7 @@ void pbl_load_uboot(int fd, struct image_tool_params 
*mparams);
  int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
  int imx8image_copy_image(int fd, struct image_tool_params *mparams);
  int imx8mimage_copy_image(int fd, struct image_tool_params *mparams);
+int rockchip_copy_image(int fd, struct image_tool_params *mparams);
  
  #define ___cat(a, b) a ## b

  #define __cat(a, b) ___cat(a, b)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 4217188310..5f51d2cc89 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -544,6 +544,14 @@ int main(int argc, char **argv)
ret = imx8mimage_copy_image(ifd, ¶ms);
if (ret)
return ret;
+   } else if ((params.type == IH_TYPE_RKSD) ||
+   (params.type == IH_TYPE_RKSPI)) {
+   /* Rockchip has special Image format */
+   int ret;
+
+   ret = rockchip_copy_image(ifd, ¶ms);
+   if (ret)
+   return ret;
} else {
copy_file(ifd, params.datafile, pad_len);
}
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0d908daee8..5fcd2a55d5 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -14,8 +14,6 @@
  #include "mkimage.h"
  #include "rkcommon.h"
  
-#define DIV_ROUND_UP(n, d)	(((n) + (d) - 1) / (d))

-
  enum {
RK_SIGNATURE= 0x0ff0aa55,
  };
@@ -80,6 +78,24 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false },
  };
  
+/**

+ * struct spl_params - spl params parsed in check_params()
+ *
+ * @init_file: Init data file path
+ * @init_size: Aligned size of init data in bytes
+ * @boot_file: Boot data file path
+ * @boot_size: Aligned size of boot data in bytes
+ */
+
+struct spl_params {
+   char *init_file;
+   uint32_t init_size;
+   char *boot_file;
+   uint32_t boot_size;
+};
+
+static struct spl_params spl_params = { 0 };
+
  static unsigned char rc4_key[16] = {
124, 78, 3, 4, 85, 5, 9, 7,
45, 44, 123, 56, 23, 13, 23, 17
@@ -99,12 +115,25 @@ static struct spl_info *rkcommon_get_spl_info(char 
*imagename)
return NULL;
  }
  
-int rkcommon_check_params(struct image_tool_params *params)

+static int rkcommon_get_aligned_size(struct image_tool_params *params,
+const char *fname)
  {
-   int i;
+   int size;
  
-	if (rkcommon_get_spl_info(params->imagename) != NULL)

-   return EXIT_SUCCESS;
+   size = imagetool_get_filesize(params, fname);
+   if (size < 0)
+   return -1;
+
+   /*
+* Pad to a 2KB alignment, as required for init/boot size by the ROM
+* (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html)
+*/
+   return ROUND(size, RK_SIZE_ALIGN);
+}
+
+int rkcommon_check_params(struct image_tool_params *params)
+{
+   int i, spl_size;
  
  	/*

 * If this is a operation (list or extract), the don't require
@@ -113,6 +142,41 @@ int rkcommon_check_params(struct image_tool_params *params)
if (params->lflag || params->iflag)
return EXIT_SUCCESS;
  
+	if (!rkcommon_get_spl_info(params->imagename))

+   goto err_spl_info;
+
+   spl_params.init_file = params->datafile;
+
+   spl_params.boot_file = strchr(spl_params.init_file, ':');
+   if (spl_params.boot_file) {
+   *spl_params.boot_file = '\0';
+   spl_params.boot_file += 1;
+   }
+
+   spl_params.init_size =
+   rkcommon_get_aligned_size(params, spl_params.init_file);
+   if (spl_params.init_size < 0)
+   return EXIT_FAILURE;
+
+   /* Boot file is

Re: [PATCH 3/3] dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC

2019-12-05 Thread Kever Yang



On 2019/11/26 上午9:39, David Wu wrote:

The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.

Signed-off-by: David Wu 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  arch/arm/dts/rk3308-roc-cc.dts | 9 +
  1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
index e10aa638a3..b4a54a852c 100644
--- a/arch/arm/dts/rk3308-roc-cc.dts
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -143,6 +143,15 @@
};
  };
  
+&mac {

+   assigned-clocks = <&cru SCLK_MAC>;
+   assigned-clock-parents = <&mac_clkin>;
+   clock_in_out = "input";
+   pinctrl-names = "default";
+   pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
+   status = "okay";
+};
+
  &pwm5 {
status = "okay";
pinctrl-names = "active";





Re: [PATCH 2/3] arm: dts: Add mac node for rk3308 at dtsi level

2019-12-05 Thread Kever Yang



On 2019/11/26 上午9:39, David Wu wrote:

The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.

Signed-off-by: David Wu 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  arch/arm/dts/rk3308.dtsi | 22 ++
  1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
index 0eeec165d4..a5c0b72ae0 100644
--- a/arch/arm/dts/rk3308.dtsi
+++ b/arch/arm/dts/rk3308.dtsi
@@ -627,6 +627,28 @@
status = "disabled";
};
  
+	mac: ethernet@ff4e {

+   compatible = "rockchip,rk3308-mac";
+   reg = <0x0 0xff4e 0x0 0x1>;
+   rockchip,grf = <&grf>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
+<&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
+<&cru SCLK_MAC>, <&cru ACLK_MAC>,
+<&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
+   clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac", "clk_mac_speed";
+   phy-mode = "rmii";
+   pinctrl-names = "default";
+   pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+   resets = <&cru SRST_MAC_A>;
+   reset-names = "stmmaceth";
+   status = "disabled";
+   };
+
cru: clock-controller@ff50 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff50 0x0 0x1000>;





Re: [U-Boot] [PATCH v2 16/16] travis: add packages for UEFI secure boot test

2019-12-05 Thread Tom Rini
On Tue, Nov 26, 2019 at 09:51:20AM +0900, AKASHI Takahiro wrote:

> Pytest for UEFI secure boot will use several host commands.
> In paricular, Test setup relies on efitools, whose version must be v1.5.2
> or later. So fetch a new version of deb package directly.
> Please note it has a dependency on mtools, which must also be installed
> along wih efitools.
> 
> In addition, the path, '/sbin', is added to PATH for use of sgdisk and
> mkfs.
> 
> Signed-off-by: AKASHI Takahiro 

Ah, so that's on the list of stuff that's not installed and why we don't
run these tests in Travis today but only GitLab/Azure.  Thanks for
fixing that.  The rest looks good and I'll post something to update the
Docker container GitLab/Azure use.

-- 
Tom


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Description: PGP signature


Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions

2019-12-05 Thread Joe Hershberger
Hi Michael,

On Fri, Oct 25, 2019 at 7:28 PM Michael Walle  wrote:
>
> Provide functions to read and write the Atheros debug registers.
>
> Signed-off-by: Michael Walle 

This series is adding too much size to several of the boards' SPL it seems.

https://travis-ci.org/jhershbe/u-boot/builds/620804934

Please address this and resend.

Thanks,
-Joe


Re: [PATCH v2] sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2

2019-12-05 Thread Diego Rondini
On Tue, Nov 19, 2019 at 2:47 PM Diego Rondini
 wrote:
>
> Orangepi Zero Plus 2 is an open-source single-board computer, available
> in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
> here, as the H5 is already supported.
>
> H3 Orangepi Zero Plus 2 has:
> - Quad-core Cortex-A7
> - 512MB DDR3
> - microSD slot and 8GB eMMC
> - Debug TTL UART
> - HDMI
> - Wifi + BT
> - OTG + power supply
>
> Sync dts from linux v5.2 commit:
> "ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry"
> (sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b)
> Commit:
> "ARM: dts: sun8i: h3: Refactor the pinctrl node names"
> (sha1: a4dc791974e568a15f7f37131729b1a6912f4811)
> has been avoided as it breaks U-Boot build.
>
> Signed-off-by: Diego Rondini 
> ---
> Changes in v2:
> - clarify where the dts comes from
> ---

Hi,

is the commit message ok now?

Diego Rondini


Re: [PATCH v4 1/6] fat: write: fix broken write to fragmented files

2019-12-05 Thread Lukasz Majewski
Hi Tom, Matthias,

> The code for handing file overwrite incorrectly assumed that the file
> on disk is always contiguous. This resulted in corrupting disk
> structure every time when write to existing fragmented file happened.
> Fix this by adding proper check for cluster discontinuity and adjust
> chunk size on each partial write.
> 
> Signed-off-by: Marek Szyprowski 
> ---
> 
> This patch partially fixes the issue revealed by the following test
> script:
> 

Tom could you pic this patch and the following one (2/6):
https://patchwork.ozlabs.org/patch/1203101/

to -master as a fix?

This seems like a _real_ fix for FAT.

The dfu part of this series IMHO shall be grabbed by Matthias or me into
the -next branch of u-boot-dfu/rpi4 tree.

I do guess that Matthias shall fetch this series as he is assigned to
it in the patchwork?
I'm fine for this as I've already acked / reviewed DFU part of this
series.

> --->8-fat_test1.sh---  
> #!/bin/bash
> make sandbox_defconfig
> make
> dd if=/dev/zero of=/tmp/10M.img bs=1024 count=10k
> mkfs.vfat -v /tmp/10M.img
> cat >/tmp/cmds < x
> host bind 0 /tmp/10M.img
> fatls host 0
> mw 0x100 0x0a434241 0x1000 # "ABC\n"
> mw 0x110 0x0a464544 0x8000 # "DEF\n"
> fatwrite host 0 0x100 file0001.raw 0x1000
> fatwrite host 0 0x100 file0002.raw 0x1000
> fatwrite host 0 0x100 file0003.raw 0x1000
> fatwrite host 0 0x100 file0004.raw 0x1000
> fatwrite host 0 0x100 file0005.raw 0x1000
> fatrm host 0 file0002.raw
> fatrm host 0 file0004.raw
> fatls host 0
> fatwrite host 0 0x110 file0007.raw 0x4000
> fatwrite host 0 0x110 file0007.raw 0x4000
> reset
> EOF
> ./u-boot  #verify
> rm -r /tmp/result /tmp/model
> mkdir /tmp/result
> mkdir /tmp/model
> yes ABC | head -c 4096 >/tmp/model/file0001.raw
> yes ABC | head -c 4096 >/tmp/model/file0003.raw
> yes ABC | head -c 4096 >/tmp/model/file0005.raw
> yes DEF | head -c 16384 >/tmp/model/file0007.raw
> mcopy -n -i /tmp/10M.img ::file0001.raw /tmp/result
> mcopy -n -i /tmp/10M.img ::file0003.raw /tmp/result
> mcopy -n -i /tmp/10M.img ::file0005.raw /tmp/result
> mcopy -n -i /tmp/10M.img ::file0007.raw /tmp/result
> hd /tmp/10M.img
> if diff -urq /tmp/model /tmp/result
> then
>   echo Test okay
> else
>   echo Test fail
> fi
> --->8---  
> 
> Overwritting a discontiguous test file (file0007.raw) no longer causes
> corruption to file0003.raw, which's data lies between the chunks of
> the test file. The amount of data written to disk is still incorrect,
> what causes damage to the file (file0005.raw), which's data lies next
> to the test file. This will be fixed by the next patch.
> 
> Feel free to prepare a proper sandbox/py_test based tests based on the
> provided test scripts.
> ---
>  fs/fat/fat_write.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
> index 729cf39630..f946030f7d 100644
> --- a/fs/fat/fat_write.c
> +++ b/fs/fat/fat_write.c
> @@ -794,6 +794,8 @@ set_contents(fsdata *mydata, dir_entry *dentptr,
> loff_t pos, __u8 *buffer, 
>   newclust = get_fatent(mydata, endclust);
>  
> + if (newclust != endclust + 1)
> + break;
>   if (IS_LAST_CLUST(newclust, mydata->fatsize))
>   break;
>   if (CHECK_CLUST(newclust, mydata->fatsize)) {
> @@ -824,8 +826,6 @@ set_contents(fsdata *mydata, dir_entry *dentptr,
> loff_t pos, __u8 *buffer, if (filesize <= cur_pos)
>   break;
>  
> - /* CHECK: newclust = get_fatent(mydata, endclust); */
> -
>   if (IS_LAST_CLUST(newclust, mydata->fatsize))
>   /* no more clusters */
>   break;




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


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Re: [PATCH 2/2] rpi: Enable DRAM bank initialization on arm64

2019-12-05 Thread Matthias Brugger



On 04/12/2019 22:28, Heinrich Schuchardt wrote:
> On 12/4/19 5:52 PM, matthias@kernel.org wrote:
>> From: Matthias Brugger 
>>
>> Up to now we only update the DRAM banks when we are define
>> CONFIG_BCM2711. But our one binary approach uses a config that supports
>> BCM2837 and BCM2711. As a result we only see one gigabyte of RAM on
> 
> %s/gigabyte/gibibyte/
> 
> There are RPi 4 with 1GiB, 2GiB, 4GiB. All have more than 1 GB but only
> some have more than 1GiB.
> 
>> Raspberry Pi 4, although it has more RAM.
> 
> I guess this should be changed to "even if it has more RAM" as you can
> also buy a RPi 4 with 1 GiB of RAM.
> 
>> Fix this by calling dram_init_banksize when we are booting a U-Boot build
>> for arm64.
>>
>> Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4")
>>
>> Signed-off-by: Matthias Brugger 
>>
>> ---
>>
>>   board/raspberrypi/rpi/rpi.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
>> index 76f1c55b65..35fcef2b56 100644
>> --- a/board/raspberrypi/rpi/rpi.c
>> +++ b/board/raspberrypi/rpi/rpi.c
>> @@ -271,7 +271,7 @@ int dram_init(void)
>>   }
>>
>>   #ifdef CONFIG_OF_BOARD
>> -#ifdef CONFIG_BCM2711
>> +#ifdef CONFIG_ARM64
> 
> The change does not relate to your commit message.
> 
> Please, explain why you enable fdtdec_decode_ram_size() on the RPi 3 in
> 64bit configuration and disables it on the RPi 4 in 32bit configuration.
> 

Right, I'll test with 32 bit, but I think it does no harm. Will delete the ARM64
ifdef.

> What happens here if we have a RPi 4 with more than 1 GiB of memory and
> use a 32bit U-Boot?
> 

Just tested that. It will always show you 1 GiB of memory because the
rpi_4_32b_defconfig states only one DRAM banks. I'll fix this as well.

Regards,
Matthias

> Best regards
> 
> Heinrich
> 
>>   int dram_init_banksize(void)
>>   {
>>   int ret;
>>
> 


Sourcing a signed boot script

2019-12-05 Thread Diego Rondini
Hi,

I would like to ask if it is possible to source a script after
verifying its signature.

Currently I've been able to source a script from a signed FIT image,
before doing "bootm", with:
source :
But this way the signature is not checked yet, so the script cannot be trusted.

According to the docs[1] it seems that it's not possible yet to verify
a FIT image signature without also booting the corresponding image. Is
that right?


[1] 
https://gitlab.denx.de/u-boot/u-boot/blob/v2019.10/doc/uImage.FIT/signature.txt#L580

Thank you,
Diego Rondini


[PATCH 1/2] video: add guards around 16bpp/32bbp code

2019-12-05 Thread Anatolij Gustschin
Many boards use only single depth configuration, for such boards
there is some unused code in video and console uclass routines.
Add guards to avoid dead code.

Signed-off-by: Anatolij Gustschin 
---
 drivers/video/vidconsole-uclass.c | 6 ++
 drivers/video/video-uclass.c  | 4 
 2 files changed, 10 insertions(+)

diff --git a/drivers/video/vidconsole-uclass.c 
b/drivers/video/vidconsole-uclass.c
index af88588904..c690eceeaa 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -116,6 +116,7 @@ static void vidconsole_newline(struct udevice *dev)
video_sync(dev->parent, false);
 }
 
+#if CONFIG_IS_ENABLED(VIDEO_BPP16) || CONFIG_IS_ENABLED(VIDEO_BPP32)
 static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0x00, 0x00 },  /* black */
{ 0xc0, 0x00, 0x00 },  /* red */
@@ -134,18 +135,23 @@ static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0xff, 0xff },  /* bright cyan */
{ 0xff, 0xff, 0xff },  /* white */
 };
+#endif
 
 u32 vid_console_color(struct video_priv *priv, unsigned int idx)
 {
switch (priv->bpix) {
+#if CONFIG_IS_ENABLED(VIDEO_BPP16)
case VIDEO_BPP16:
return ((colors[idx].r >> 3) << 11) |
   ((colors[idx].g >> 2) <<  5) |
   ((colors[idx].b >> 3) <<  0);
+#endif
+#if CONFIG_IS_ENABLED(VIDEO_BPP32)
case VIDEO_BPP32:
return (colors[idx].r << 16) |
   (colors[idx].g <<  8) |
   (colors[idx].b <<  0);
+#endif
default:
/*
 * For unknown bit arrangements just support
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index f660c5205e..5ea7568fa4 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -92,6 +92,7 @@ int video_clear(struct udevice *dev)
struct video_priv *priv = dev_get_uclass_priv(dev);
 
switch (priv->bpix) {
+#ifdef CONFIG_VIDEO_BPP16
case VIDEO_BPP16: {
u16 *ppix = priv->fb;
u16 *end = priv->fb + priv->fb_size;
@@ -100,6 +101,8 @@ int video_clear(struct udevice *dev)
*ppix++ = priv->colour_bg;
break;
}
+#endif
+#ifdef CONFIG_VIDEO_BPP32
case VIDEO_BPP32: {
u32 *ppix = priv->fb;
u32 *end = priv->fb + priv->fb_size;
@@ -108,6 +111,7 @@ int video_clear(struct udevice *dev)
*ppix++ = priv->colour_bg;
break;
}
+#endif
default:
memset(priv->fb, priv->colour_bg, priv->fb_size);
break;
-- 
2.17.1



[PATCH 2/2] video: make BPP and ANSI configs optional

2019-12-05 Thread Anatolij Gustschin
Many boards do not use all selected framebuffer depth
configurations, for such boards there is some unused
code in video and console uclass routines. Make depth
specific code optional to avoid dead code and slightly
reduce binary size. Also make ANSI code optional for
the same reason. When i.e. using only VIDEO_BPP16 the
code size shrinks (below values when using gcc-7.3.0):

  $ ./tools/buildman/buildman -b video-wip -sS wandboard
  ...
  01: Merge git://git.denx.de/u-boot-sh
  02: video: add guards around 16bpp/32bbp code
  03: video: make BPP and ANSI configs optional
 arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0

Also adjust defconfigs of DM_VIDEO enabled boards to select
actually used BPP values.

Signed-off-by: Anatolij Gustschin 
---
 configs/apalis_imx6_defconfig  |  1 +
 configs/at91sam9x5ek_dataflash_defconfig   |  1 +
 configs/at91sam9x5ek_mmc_defconfig |  1 +
 configs/at91sam9x5ek_nandflash_defconfig   |  1 +
 configs/at91sam9x5ek_spiflash_defconfig|  1 +
 configs/chromebit_mickey_defconfig |  2 ++
 configs/chromebook_jerry_defconfig |  2 ++
 configs/chromebook_minnie_defconfig|  2 ++
 configs/chromebook_speedy_defconfig|  2 ++
 configs/colibri-imx6ull_defconfig  |  3 +++
 configs/colibri_imx6_defconfig |  1 +
 configs/colibri_imx7_defconfig |  3 +++
 configs/colibri_imx7_emmc_defconfig|  3 +++
 configs/colibri_t20_defconfig  |  2 ++
 configs/colibri_vf_defconfig   |  1 +
 configs/evb-px30_defconfig |  3 +++
 configs/evb-rk3288_defconfig   |  2 ++
 configs/evb-rk3399_defconfig   |  2 ++
 configs/firefly-rk3288_defconfig   |  2 ++
 configs/gazerbeam_defconfig|  3 +++
 configs/ge_bx50v3_defconfig|  1 +
 configs/gurnard_defconfig  |  2 ++
 configs/harmony_defconfig  |  2 ++
 configs/imx6dl_icore_nand_defconfig|  1 +
 configs/imx6q_icore_nand_defconfig |  1 +
 configs/imx6qdl_icore_mmc_defconfig|  1 +
 configs/imx6qdl_icore_nand_defconfig   |  1 +
 configs/libretech-ac_defconfig |  1 +
 configs/libretech-cc_defconfig |  1 +
 configs/m53menlo_defconfig |  1 +
 configs/medcom-wide_defconfig  |  2 ++
 configs/miqi-rk3288_defconfig  |  2 ++
 configs/mx53cx9020_defconfig   |  1 +
 configs/mx6sabreauto_defconfig |  1 +
 configs/mx6sabresd_defconfig   |  1 +
 configs/mx6ul_14x14_evk_defconfig  |  3 +++
 configs/mx6ul_9x9_evk_defconfig|  3 +++
 configs/novena_defconfig   |  1 +
 configs/nyan-big_defconfig |  1 +
 configs/opos6uldev_defconfig   |  1 +
 configs/paz00_defconfig|  2 ++
 configs/peach-pi_defconfig |  2 ++
 configs/peach-pit_defconfig|  2 ++
 configs/pico-dwarf-imx7d_defconfig |  3 +++
 configs/pico-hobbit-imx7d_defconfig|  3 +++
 configs/pico-imx7d_bl33_defconfig  |  3 +++
 configs/pico-imx7d_defconfig   |  3 +++
 configs/pico-nymph-imx7d_defconfig |  3 +++
 configs/pico-pi-imx7d_defconfig|  3 +++
 configs/pm9261_defconfig   |  2 ++
 configs/pm9263_defconfig   |  2 ++
 configs/puma-rk3399_defconfig  |  2 ++
 configs/rock2_defconfig|  2 ++
 configs/rpi_0_w_defconfig  |  1 +
 configs/rpi_2_defconfig|  1 +
 configs/rpi_3_32b_defconfig|  1 +
 configs/rpi_3_b_plus_defconfig |  1 +
 configs/rpi_3_defconfig|  1 +
 configs/rpi_4_32b_defconfig|  1 +
 configs/rpi_4_defconfig|  1 +
 configs/rpi_arm64_defconfig|  1 +
 configs/rpi_defconfig  |  1 +
 configs/sama5d27_som1_ek_mmc1_defconfig|  1 +
 configs/sama5d27_som1_ek_mmc_defconfig |  1 +
 configs/sama5d27_som1_ek_qspiflash_defconfig   |  1 +
 configs/sama5d27_wlsom1_ek_mmc_defconfig   |  1 +
 configs/sama5d27_wlsom1_ek_qspiflash_defconfig |  1 +
 configs/sama5d2_xplained_emmc_defconfig|  1 +
 configs/sama5d2_xplained_mmc_defconfig |  1 +
 configs/sama5d2_xplained_qspiflash_defconfig   |  1 +
 configs/sama5d2_xplained_spiflash_defconfig|  1 +
 configs/sama5d36ek_cmp_mmc_defconfig   |  1 +
 configs/sama5d36ek_cmp_nandflash_defconfig |  1 +
 configs/sama5d36ek_cmp_spiflash_defconfig  |  1 +
 configs/sama5d3xek_mmc_defconfig   |  3 +++
 configs/sama5d3xek_nandflash_defconfig |  3 +++
 c

Re: [PATCH 0/2] travis-ci: provide 'addr' in file2env()

2019-12-05 Thread Stephen Warren

On 12/4/19 11:42 PM, Heinrich Schuchardt wrote:

Function fetch_tftp_file() in test/py/tests/test_efi_loader.py expects that
the dictionary describing a file contains an entry 'addr' specifying the
loading address. Otherwise it defaults to the start of RAM. On
qemu_arm64_defconfig and qemu_arm_defconfig this collides with the hardware
supplied device tree.

Add an optional parameter in function file2env() to set the 'addr' entry.

Set the load address for files to the value of $kernel_addr_r for the
qemu_arm64_defconfig and qemu_arm_defconfig boards to avoid collisions with
the device tree.


The series looks fine to me; I hope to apply it tomorrow just in case 
there are other comments.


P.S. It might have been useful to mention the target repo in the patch 
subject or at least at the top of the cover letter, since it took me a 
few extra seconds to realize this was a patch to my hooks repo not 
U-Boot's test/py directory, which was confusing! "[hooks PATCH] ..." 
might have helped there.


[PATCH v2 3/3] ARM: defconfig: Fix 32bit config for RPi4

2019-12-05 Thread matthias . bgg
From: Matthias Brugger 

The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.

Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)")

Signed-off-by: Matthias Brugger 

---

Changes in v2:
- fix rpi_4_32b_defconfig

 configs/rpi_4_32b_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 7ff390cd24..ce729df2a0 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x8000
 CONFIG_TARGET_RPI_4_32B=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-- 
2.24.0



[PATCH v2 2/3] rpi: Enable DRAM bank initialization on arm64

2019-12-05 Thread matthias . bgg
From: Matthias Brugger 

Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_banksize.

Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4")

Signed-off-by: Matthias Brugger 

---

Changes in v2:
- fix commit message
- call dram_init_banksize independent of ARM64

 board/raspberrypi/rpi/rpi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index e19610f40f..e367ba3092 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -272,7 +272,6 @@ int dram_init(void)
 }
 
 #ifdef CONFIG_OF_BOARD
-#ifdef CONFIG_BCM2711
 int dram_init_banksize(void)
 {
int ret;
@@ -284,7 +283,6 @@ int dram_init_banksize(void)
return fdtdec_setup_mem_size_base();
 }
 #endif
-#endif
 
 static void set_fdtfile(void)
 {
-- 
2.24.0



[PATCH v2 1/3] rpi: fix dram bank initialization

2019-12-05 Thread matthias . bgg
From: Matthias Brugger 

To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the default values defined in the spec, we can end up with wrong RAM
bank information.

Switch to the "standard" way to update the RAM bank information to
avoid this.

Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization")

Signed-off-by: Matthias Brugger 
---

Changes in v2: None

 board/raspberrypi/rpi/rpi.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 5f120ea9c2..e19610f40f 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -275,8 +275,13 @@ int dram_init(void)
 #ifdef CONFIG_BCM2711
 int dram_init_banksize(void)
 {
-   return fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
-(phys_size_t *)&gd->ram_size, gd->bd);
+   int ret;
+
+   ret = fdtdec_setup_memory_banksize();
+   if (ret)
+   return ret;
+
+   return fdtdec_setup_mem_size_base();
 }
 #endif
 #endif
-- 
2.24.0



Re: [U-Boot] [PATCH v2 1/1] net: avoid address-of-packed-member error

2019-12-05 Thread Joe Hershberger
On Thu, Dec 5, 2019 at 1:19 AM Heinrich Schuchardt  wrote:
>
> On 11/6/19 12:07 AM, Joe Hershberger wrote:
> > On Tue, Nov 5, 2019 at 5:49 AM Heinrich Schuchardt  
> > wrote:
> >>
> >> sandbox_defconfig does not compile using GCC 9.2.1:
> >>
> >> net/net.c: In function ‘net_process_received_packet’:
> >> net/net.c:1288:23: error: taking address of packed member of ‘struct
> >> ip_udp_hdr’ may result in an unaligned pointer value
> >> [-Werror=address-of-packed-member]
> >>   1288 |sumptr = (ushort *)&(ip->udp_src);
> >>|   ^~
> >>
> >> Avoid the error by using a u8 pointer instead of an u16 pointer and
> >> in-lining ntohs().
> >
> > Seems reasonable.
> >
> >> Simplify the checksumming of the last message byte.
> >>
> >> Signed-off-by: Heinrich Schuchardt 
> >
> > Acked-by: Joe Hershberger 
> >
>
> Hello Joe,
>
> this patch did not yet make it into
> https://gitlab.denx.de/u-boot/custodians/u-boot-net/commits/master
>
> Is there something that needs to be changed?

No, it is among the patches I'm currently testing [1].

[1] - https://github.com/jhershbe/u-boot/commits/travis_ci/test_1184510

Cheers,
-Joe


Re: [PATCH v4 1/6] fat: write: fix broken write to fragmented files

2019-12-05 Thread Matthias Brugger


On 05/12/2019 17:52, Lukasz Majewski wrote:
> Hi Tom, Matthias,
> 
>> The code for handing file overwrite incorrectly assumed that the file
>> on disk is always contiguous. This resulted in corrupting disk
>> structure every time when write to existing fragmented file happened.
>> Fix this by adding proper check for cluster discontinuity and adjust
>> chunk size on each partial write.
>>
>> Signed-off-by: Marek Szyprowski 
>> ---
>>
>> This patch partially fixes the issue revealed by the following test
>> script:
>>
> 
> Tom could you pic this patch and the following one (2/6):
> https://patchwork.ozlabs.org/patch/1203101/
> 
> to -master as a fix?
> 
> This seems like a _real_ fix for FAT.

Right, I think the first patches should go in for v2020.01. I can send them
together with some fixes for RPi I'm working on.

Tom what do you think?

Regards,
Matthias

> 
> The dfu part of this series IMHO shall be grabbed by Matthias or me into
> the -next branch of u-boot-dfu/rpi4 tree.
> 
> I do guess that Matthias shall fetch this series as he is assigned to
> it in the patchwork?
> I'm fine for this as I've already acked / reviewed DFU part of this
> series.
> 
>> --->8-fat_test1.sh---  
>> #!/bin/bash
>> make sandbox_defconfig
>> make
>> dd if=/dev/zero of=/tmp/10M.img bs=1024 count=10k
>> mkfs.vfat -v /tmp/10M.img
>> cat >/tmp/cmds <> x
>> host bind 0 /tmp/10M.img
>> fatls host 0
>> mw 0x100 0x0a434241 0x1000 # "ABC\n"
>> mw 0x110 0x0a464544 0x8000 # "DEF\n"
>> fatwrite host 0 0x100 file0001.raw 0x1000
>> fatwrite host 0 0x100 file0002.raw 0x1000
>> fatwrite host 0 0x100 file0003.raw 0x1000
>> fatwrite host 0 0x100 file0004.raw 0x1000
>> fatwrite host 0 0x100 file0005.raw 0x1000
>> fatrm host 0 file0002.raw
>> fatrm host 0 file0004.raw
>> fatls host 0
>> fatwrite host 0 0x110 file0007.raw 0x4000
>> fatwrite host 0 0x110 file0007.raw 0x4000
>> reset
>> EOF
>> ./u-boot > #verify
>> rm -r /tmp/result /tmp/model
>> mkdir /tmp/result
>> mkdir /tmp/model
>> yes ABC | head -c 4096 >/tmp/model/file0001.raw
>> yes ABC | head -c 4096 >/tmp/model/file0003.raw
>> yes ABC | head -c 4096 >/tmp/model/file0005.raw
>> yes DEF | head -c 16384 >/tmp/model/file0007.raw
>> mcopy -n -i /tmp/10M.img ::file0001.raw /tmp/result
>> mcopy -n -i /tmp/10M.img ::file0003.raw /tmp/result
>> mcopy -n -i /tmp/10M.img ::file0005.raw /tmp/result
>> mcopy -n -i /tmp/10M.img ::file0007.raw /tmp/result
>> hd /tmp/10M.img
>> if diff -urq /tmp/model /tmp/result
>> then
>>  echo Test okay
>> else
>>  echo Test fail
>> fi
>> --->8---  
>>
>> Overwritting a discontiguous test file (file0007.raw) no longer causes
>> corruption to file0003.raw, which's data lies between the chunks of
>> the test file. The amount of data written to disk is still incorrect,
>> what causes damage to the file (file0005.raw), which's data lies next
>> to the test file. This will be fixed by the next patch.
>>
>> Feel free to prepare a proper sandbox/py_test based tests based on the
>> provided test scripts.
>> ---
>>  fs/fat/fat_write.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
>> index 729cf39630..f946030f7d 100644
>> --- a/fs/fat/fat_write.c
>> +++ b/fs/fat/fat_write.c
>> @@ -794,6 +794,8 @@ set_contents(fsdata *mydata, dir_entry *dentptr,
>> loff_t pos, __u8 *buffer, 
>>  newclust = get_fatent(mydata, endclust);
>>  
>> +if (newclust != endclust + 1)
>> +break;
>>  if (IS_LAST_CLUST(newclust, mydata->fatsize))
>>  break;
>>  if (CHECK_CLUST(newclust, mydata->fatsize)) {
>> @@ -824,8 +826,6 @@ set_contents(fsdata *mydata, dir_entry *dentptr,
>> loff_t pos, __u8 *buffer, if (filesize <= cur_pos)
>>  break;
>>  
>> -/* CHECK: newclust = get_fatent(mydata, endclust); */
>> -
>>  if (IS_LAST_CLUST(newclust, mydata->fatsize))
>>  /* no more clusters */
>>  break;
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
> 



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Re: [PATCH 2/2] video: make BPP and ANSI configs optional

2019-12-05 Thread Anatolij Gustschin
On Thu,  5 Dec 2019 18:15:49 +0100
Anatolij Gustschin ag...@denx.de wrote:

> Many boards do not use all selected framebuffer depth
> configurations, for such boards there is some unused
> code in video and console uclass routines. Make depth
> specific code optional to avoid dead code and slightly
> reduce binary size. Also make ANSI code optional for
> the same reason. When i.e. using only VIDEO_BPP16 the
> code size shrinks (below values when using gcc-7.3.0):
> 
>   $ ./tools/buildman/buildman -b video-wip -sS wandboard
>   ...
>   01: Merge git://git.denx.de/u-boot-sh
>   02: video: add guards around 16bpp/32bbp code
>   03: video: make BPP and ANSI configs optional
>  arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0
> 
> Also adjust defconfigs of DM_VIDEO enabled boards to select
> actually used BPP values.

Forgot to CC board maintainers. Maybe you could review or test these
two patches [1],[2] on your board to confirm that these don't break
frame buffer support.

[1] http://patchwork.ozlabs.org/patch/1204707
[2] http://patchwork.ozlabs.org/patch/1204704

Thanks,
Anatolij


Re: [PATCH v4 1/6] fat: write: fix broken write to fragmented files

2019-12-05 Thread Tom Rini
On Thu, Dec 05, 2019 at 06:58:15PM +0100, Matthias Brugger wrote:
> 
> 
> On 05/12/2019 17:52, Lukasz Majewski wrote:
> > Hi Tom, Matthias,
> > 
> >> The code for handing file overwrite incorrectly assumed that the file
> >> on disk is always contiguous. This resulted in corrupting disk
> >> structure every time when write to existing fragmented file happened.
> >> Fix this by adding proper check for cluster discontinuity and adjust
> >> chunk size on each partial write.
> >>
> >> Signed-off-by: Marek Szyprowski 
> >> ---
> >>
> >> This patch partially fixes the issue revealed by the following test
> >> script:
> >>
> > 
> > Tom could you pic this patch and the following one (2/6):
> > https://patchwork.ozlabs.org/patch/1203101/
> > 
> > to -master as a fix?
> > 
> > This seems like a _real_ fix for FAT.
> 
> Right, I think the first patches should go in for v2020.01. I can send them
> together with some fixes for RPi I'm working on.
> 
> Tom what do you think?

I'd _really_ like to see the test that's in the commit message turned in
to a test we can run from CI as Travis will be doing those Soon(TM) and
GitLab/Azure do.  Then I'll pick them up (I'm testing some other fat
fixes right now).  Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] cmd: pxe: Increase maximum path length

2019-12-05 Thread Joe Hershberger
On Tue, Dec 3, 2019 at 6:35 AM Ben Wolsieffer  wrote:
>
> On NixOS, cross compiled kernels have long suffixes that cause them to
> exceed the current maximum path length. The PXE/TFTP max path length is
> used for extlinux.conf support as well, which is where this problem
> usually manifest's itself.
>
> Signed-off-by: Ben Wolsieffer 

We'll try it and see if it blows any memory limits.

Acked-by: Joe Hershberger 

>
> ---
>
>  cmd/pxe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/cmd/pxe.c b/cmd/pxe.c
> index 2059975446..744cd82730 100644
> --- a/cmd/pxe.c
> +++ b/cmd/pxe.c
> @@ -21,7 +21,7 @@
>  #include "menu.h"
>  #include "cli.h"
>
> -#define MAX_TFTP_PATH_LEN 127
> +#define MAX_TFTP_PATH_LEN 512
>
>  const char *pxe_default_paths[] = {
>  #ifdef CONFIG_SYS_SOC
> --
> 2.24.0
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot


Re: [U-Boot] [PATCH 2/2] Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"

2019-12-05 Thread Tom Rini
On Sun, Nov 10, 2019 at 08:23:15AM -0800, Thomas Hebb wrote:

> Signed-off-by: Thomas Hebb 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] ARM: omapl138_lcdk: Shrink code size by building with Thumb

2019-12-05 Thread Tom Rini
On Sun, Nov 10, 2019 at 06:33:40AM -0600, Adam Ford wrote:

> SPL has limited available resources, and the performance between
> ARM and Thumb isn't that significant.
> 
> This patch builds using Thumb instruction set to reduce the code
> size by nearly 6K.
> 
> Original:
>text  data bss dec hex filename
>   26526  40041376   319067ca2 spl/u-boot-spl
> 
> Thumb:
> 
>text  data bss dec hex filename
>   20232  40041376   25612640c spl/u-boot-spl
> 
> Signed-off-by: Adam Ford 
> Tested-by: Bartosz Golaszewski 
> Reviewed-by: Bartosz Golaszewski 
> 
> diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
> index 9821df9884..16287a4ac2 100644

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] ARM: da850-evm: Disable SYS_MMCSD_RAW_MODE_USE_SECTOR

2019-12-05 Thread Tom Rini
On Wed, Nov 13, 2019 at 07:42:00AM -0600, Adam Ford wrote:

> The da850-evm doesn't have the boot pins configured in a way
> to make MMC/SD booting an option, and MMC/SD support is not
> enabled in SPL.  Therefore, there is no need to support raw mode
> mmc/sd support in SPL.
> 
> This patch disables CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
> index 4ff08e7d44..ed4a8609af 100644

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] spl: fix entry_point equal to load_addr

2019-12-05 Thread Tom Rini
On Mon, Nov 25, 2019 at 05:18:20PM +0100, Giulio Benetti wrote:

> At the moment entry_point is set to image_get_load(header) that sets it
> to "load address" instead of "entry point", assuming entry_point is
> equal to load_addr, but it's not true. Then load_addr is set to
> "entry_point - header_size", but this is wrong too since load_addr is
> not an entry point.
> 
> So use image_get_ep() for entry_point assignment and image_get_load()
> for load_addr assignment.
> 
> Signed-off-by: Giulio Benetti 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] fs: fat: handle deleted directory entries correctly

2019-12-05 Thread Tom Rini
On Tue, Nov 26, 2019 at 05:29:31PM +0900, AKASHI Takahiro wrote:

> Unlink test for FAT file system seems to fail at test_unlink2.
> (When I added this test, I haven't seen any errors though.)
> for example,
> ===8<===
> fs_obj_unlink = ['fat', '/home/akashi/tmp/uboot_sandbox_test/128MB.fat32.img']
> 
> def test_unlink2(self, u_boot_console, fs_obj_unlink):
> """
> Test Case 2 - delete many files
> """
> fs_type,fs_img = fs_obj_unlink
> with u_boot_console.log.section('Test Case 2 - unlink (many)'):
> output = u_boot_console.run_command('host bind 0 %s' % fs_img)
> 
> for i in range(0, 20):
> output = u_boot_console.run_command_list([
> '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
> '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
> assert('' == ''.join(output))
> 
> output = u_boot_console.run_command(
> '%sls host 0:0 dir2' % fs_type)
> >   assert('0 file(s), 2 dir(s)' in output)
> E   AssertionError: assert '0 file(s), 2 dir(s)' in '
> ./\r\r\n../\r\r\n0   0123456789abcdef11\r\r\n\r\r\n1 
> file(s), 2 dir(s)'
> 
> test/py/tests/test_fs/test_unlink.py:52: AssertionError
> ===>8===
> 
> This can happen when fat_itr_next() wrongly detects an already-
> deleted directory entry.
> 
> File deletion, which was added in the commit f8240ce95d64 ("fs: fat:
> support unlink"), is implemented by marking its entry for a short name
> with DELETED_FLAG, but related entry slots for a long file name are kept
> unmodified. (So entries will never be actually deleted from media.)
> 
> To handle this case correctly, an additional check for a directory slot
> will be needed in fat_itr_next().
> 
> In addition, I added extra comments about long file name and short file
> name format in FAT file system. Although they are not directly related
> to the issue, I hope it will be helpful for better understandings
> in general.
> 
> Signed-off-by: AKASHI Takahiro 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] test/py: test_fs: add tests for creating/deleting many files

2019-12-05 Thread Tom Rini
On Tue, Nov 26, 2019 at 05:28:49PM +0900, AKASHI Takahiro wrote:

> # This is actually a resent patch of
> # [1] https://lists.denx.de/pipermail/u-boot/2019-May/369170.html
> 
> Two test cases are added under test_fs_ext:
> test case 10: for root directory
> test case 11: for non-root directory
> 
> Those will verify a behavior fixed by the commits related to
> root directory
> ("fs: fat: allocate a new cluster for root directory of fat32" and
> "fs: fat: flush a directory cluster properly"), and focus on
> handling long-file-name directory entries under a directory.
> 
> Signed-off-by: AKASHI Takahiro 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] drivers: optee: rpmb: fix returning CID to TEE

2019-12-05 Thread Tom Rini
On Tue, Nov 26, 2019 at 05:19:34PM +0100, Jorge Ramirez-Ortiz wrote:

> The mmc CID value is one of the input parameters used to provision the
> RPMB key. The trusted execution environment expects this value to be
> specified in big endian format.
> 
> Before this fix, on little endian systems, the value returned by the
> linux kernel mmc driver differed from the one returned by u-boot.
> This meant that if linux provisioned the RPMB key, u-boot would not
> have access to the partition (and the other way around).
> 
> Signed-off-by: Jorge Ramirez-Ortiz 
> Reviewed-by: Jens Wiklander 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] drivers: pci: ignore disabled devices

2019-12-05 Thread Tom Rini
On Sun, Dec 01, 2019 at 05:45:18PM +0100, Michael Walle wrote:

> PCI devices may be disabled in the device tree. Devices which are probed
> by the device tree handle the "status" property and are skipped if
> disabled. Devices which are probed by the PCI enumeration don't check
> that property. Fix it.
> 
> Signed-off-by: Michael Walle 
> Reviewed-by: Alex Marginean 
> Tested-by: Alex Marginean 
> Reviewed-by: Bin Meng 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [RESEND PATCH v2] spl: Introduce SPL_DM_GPIO Kconfig define

2019-12-05 Thread Tom Rini
On Mon, Dec 02, 2019 at 10:24:16AM +0100, Lukasz Majewski wrote:

> This define indicates if DM_GPIO shall be supported in SPL. This allows
> proper operation of DM converted GPIO drivers in SPL, which use
> boards.
> 
> Signed-off-by: Lukasz Majewski 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] cmd: cp: add missing map_sysmem

2019-12-05 Thread Tom Rini
On Mon, Dec 02, 2019 at 05:33:22PM +0100, Philippe Reynes wrote:

> The command cp fails on sandbox because the address is used
> directly. To fix this issue, we call the function map_sysmem
> to translate the address.
> 
> Signed-off-by: Philippe Reynes 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] iminfo: add missing map_sysmem

2019-12-05 Thread Tom Rini
On Mon, Dec 02, 2019 at 03:45:50PM +0100, Philippe Reynes wrote:

> The command iminfo fails on sandbox because the address
> is used directly. To fix this issue, we call the function
> map_sysmem to translate the address.
> 
> Signed-off-by: Philippe Reynes 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: Sourcing a signed boot script

2019-12-05 Thread Lukasz Majewski
Hi Diego,

> Hi,
> 
> I would like to ask if it is possible to source a script after
> verifying its signature.
> 
> Currently I've been able to source a script from a signed FIT image,
> before doing "bootm", with:
> source :
> But this way the signature is not checked yet, so the script cannot
> be trusted.
> 
> According to the docs[1] it seems that it's not possible yet to verify
> a FIT image signature without also booting the corresponding image. Is
> that right?

You can look into the "spl" command, which does the FIT parsing (to
prepare data for falcon mode booting).

You may want to re-use such "dry-run" feature to verify the signature,
extract the script and use it.

(And yes, I don't think that checking the signature for script works
out of the box).

> 
> 
> [1]
> https://gitlab.denx.de/u-boot/u-boot/blob/v2019.10/doc/uImage.FIT/signature.txt#L580
> 
> Thank you,
> Diego Rondini




Best regards,

Lukasz Majewski

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[PATCH v2 04/12] phy: atheros: Explicitly disable RGMII delays

2019-12-05 Thread Michael Walle
From: Vladimir Oltean 

To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.

If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.

Signed-off-by: Vladimir Oltean 
Acked-by: Joe Hershberger 
---
 drivers/net/phy/atheros.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 1da18eb5d4..3e59c3f391 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -70,10 +70,14 @@ static int ar8031_config(struct phy_device *phydev)
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
ar803x_enable_tx_delay(phydev, true);
+   else
+   ar803x_enable_tx_delay(phydev, false);
 
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
ar803x_enable_rx_delay(phydev, true);
+   else
+   ar803x_enable_rx_delay(phydev, false);
 
phydev->supported = phydev->drv->features;
 
@@ -96,10 +100,14 @@ static int ar8035_config(struct phy_device *phydev)
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
ar803x_enable_tx_delay(phydev, true);
+   else
+   ar803x_enable_tx_delay(phydev, false);
 
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
ar803x_enable_rx_delay(phydev, true);
+   else
+   ar803x_enable_rx_delay(phydev, false);
 
phydev->supported = phydev->drv->features;
 
-- 
2.20.1



[PATCH v2 02/12] phy: atheros: Use common functions for RGMII internal delays

2019-12-05 Thread Michael Walle
From: Vladimir Oltean 

Signed-off-by: Vladimir Oltean 
Acked-by: Joe Hershberger 
---
 drivers/net/phy/atheros.c | 69 +++
 1 file changed, 41 insertions(+), 28 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 537c1a9125..c0c2b4db39 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -12,16 +12,45 @@
 #define AR803x_PHY_DEBUG_DATA_REG  0x1e
 
 #define AR803x_DEBUG_REG_5 0x5
-#define AR803x_RGMII_TX_CLK_DLY0x100
+#define AR803x_RGMII_TX_CLK_DLYBIT(8)
 
 #define AR803x_DEBUG_REG_0 0x0
-#define AR803x_RGMII_RX_CLK_DLY0x8000
+#define AR803x_RGMII_RX_CLK_DLYBIT(15)
+
+static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+{
+   int regval;
+
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_0);
+   regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+   if (on)
+   regval |= AR803x_RGMII_RX_CLK_DLY;
+   else
+   regval &= ~AR803x_RGMII_RX_CLK_DLY;
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
+
+static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
+{
+   int regval;
+
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+   regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+   if (on)
+   regval |= AR803x_RGMII_TX_CLK_DLY;
+   else
+   regval &= ~AR803x_RGMII_TX_CLK_DLY;
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
 
 static int ar8021_config(struct phy_device *phydev)
 {
phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
 
phydev->supported = phydev->drv->features;
return 0;
@@ -30,20 +59,12 @@ static int ar8021_config(struct phy_device *phydev)
 static int ar8031_config(struct phy_device *phydev)
 {
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
-   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_5);
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_TX_CLK_DLY);
-   }
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+   ar803x_enable_tx_delay(phydev, true);
 
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_0);
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_RX_CLK_DLY);
-   }
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+   ar803x_enable_rx_delay(phydev, true);
 
phydev->supported = phydev->drv->features;
 
@@ -64,20 +85,12 @@ static int ar8035_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
 
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-   (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
-   /* select debug reg 5 */
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
-   /* enable tx delay */
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
-   }
+   (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
+   ar803x_enable_tx_delay(phydev, true);
 
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-   (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
-   /* select debug reg 0 */
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
-   /* enable rx delay */
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
-   }
+   (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
+   ar803x_enable_rx_delay(phydev, true);
 
phydev->supported = phydev->drv->features;
 
-- 
2.20.1



[PATCH v2 01/12] phy: atheros: Make RGMII Tx delays actually configurable for AR8035

2019-12-05 Thread Michael Walle
From: Vladimir Oltean 

Delete the extraneous write to debug reg 5 that enables Tx delay

When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.

Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and RGMII_RXID", the author did not notice that code for enabling Tx
delay code was already. Therefore, the if condition for Tx delay has
always been useless for this PHY since this commit introduced it.

Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
After this patch, only those who define the interface as RGMII_TXID or
RGMII_ID will. This is to be expected, but will nonetheless break the
setups of those who didn't know they rely on Tx delay implicitly.

Signed-off-by: Vladimir Oltean 
Acked-by: Joe Hershberger 
---
 drivers/net/phy/atheros.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3783d155e7..537c1a9125 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -63,10 +63,6 @@ static int ar8035_config(struct phy_device *phydev)
regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
 
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-   regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
-
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
/* select debug reg 5 */
-- 
2.20.1



[PATCH v2 08/12] phy: atheros: introduce debug read and write functions

2019-12-05 Thread Michael Walle
Provide functions to read and write the Atheros debug registers.

Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 57 ---
 1 file changed, 41 insertions(+), 16 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 5ff5875d3d..660dcd9491 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -30,32 +30,57 @@
 #define AR8031_PHY_ID 0x004dd074
 #define AR8035_PHY_ID 0x004dd072
 
-static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 {
-   int regval;
+   int ret;
+
+   ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+   reg);
+   if (ret < 0)
+   return ret;
+
+   return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+}
+
+static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+u16 clear, u16 set)
+{
+   int val;
+
+   val = ar803x_debug_reg_read(phydev, reg);
+   if (val < 0)
+   return val;
+
+   val &= 0x;
+   val &= ~clear;
+   val |= set;
+
+   return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+val);
+}
+
+static int ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+{
+   u16 clear = 0, set = 0;
 
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_0);
-   regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
if (on)
-   regval |= AR803x_RGMII_RX_CLK_DLY;
+   set = AR803x_RGMII_RX_CLK_DLY;
else
-   regval &= ~AR803x_RGMII_RX_CLK_DLY;
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+   clear = AR803x_RGMII_RX_CLK_DLY;
+
+   return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, clear, set);
 }
 
-static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
+static int ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
 {
-   int regval;
+   u16 clear = 0, set = 0;
 
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_5);
-   regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
if (on)
-   regval |= AR803x_RGMII_TX_CLK_DLY;
+   set = AR803x_RGMII_TX_CLK_DLY;
else
-   regval &= ~AR803x_RGMII_TX_CLK_DLY;
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+   clear = AR803x_RGMII_TX_CLK_DLY;
+
+   return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, clear, set);
 }
 
 static int ar8021_config(struct phy_device *phydev)
-- 
2.20.1



[PATCH v2 07/12] phy: atheros: use defines for PHY IDs

2019-12-05 Thread Michael Walle
Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 01953a1390..5ff5875d3d 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -26,6 +26,10 @@
 #define AR8035_CLK_25M_FREQ_125M   (BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASKGENMASK(4, 3)
 
+#define AR8021_PHY_ID 0x004dd040
+#define AR8031_PHY_ID 0x004dd074
+#define AR8035_PHY_ID 0x004dd072
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
int regval;
@@ -119,7 +123,7 @@ static int ar8035_config(struct phy_device *phydev)
 
 static struct phy_driver AR8021_driver =  {
.name = "AR8021",
-   .uid = 0x4dd040,
+   .uid = AR8021_PHY_ID,
.mask = 0xfff0,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
@@ -129,7 +133,7 @@ static struct phy_driver AR8021_driver =  {
 
 static struct phy_driver AR8031_driver =  {
.name = "AR8031/AR8033",
-   .uid = 0x4dd074,
+   .uid = AR8031_PHY_ID,
.mask = 0xffef,
.features = PHY_GBIT_FEATURES,
.config = ar8031_config,
@@ -139,7 +143,7 @@ static struct phy_driver AR8031_driver =  {
 
 static struct phy_driver AR8035_driver =  {
.name = "AR8035",
-   .uid = 0x4dd072,
+   .uid = AR8035_PHY_ID,
.mask = 0xffef,
.features = PHY_GBIT_FEATURES,
.config = ar8035_config,
-- 
2.20.1



[PATCH v2 03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin

2019-12-05 Thread Michael Walle
From: Vladimir Oltean 

Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.

Signed-off-by: Vladimir Oltean 
Acked-by: Joe Hershberger 
---
 drivers/net/phy/atheros.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index c0c2b4db39..1da18eb5d4 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -17,6 +17,15 @@
 #define AR803x_DEBUG_REG_0 0x0
 #define AR803x_RGMII_RX_CLK_DLYBIT(15)
 
+/* CLK_25M register is at MMD 7, address 0x8016 */
+#define AR803x_CLK_25M_SEL_REG 0x8016
+/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
+#define AR8035_CLK_25M_FREQ_25M(0 | 0)
+#define AR8035_CLK_25M_FREQ_50M(0 | BIT(3))
+#define AR8035_CLK_25M_FREQ_62M(BIT(4) | 0)
+#define AR8035_CLK_25M_FREQ_125M   (BIT(4) | BIT(3))
+#define AR8035_CLK_25M_MASKGENMASK(4, 3)
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
int regval;
@@ -78,11 +87,11 @@ static int ar8035_config(struct phy_device *phydev)
 {
int regval;
 
-   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-   regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-   phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
+   /* Configure CLK_25M output clock at 125 MHz */
+   regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
+   regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
+   regval |= AR8035_CLK_25M_FREQ_125M;
+   phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
-- 
2.20.1



[PATCH v2 00/12] phy: atheros: dt bindings and cleanup

2019-12-05 Thread Michael Walle
[RESEND because I've forgot to add the mailinglist. Sorry!]

This patch series superseeds the following two:
>From Vladimir Oltean
  https://patchwork.ozlabs.org/cover/1031360/
>From me:
  https://patchwork.ozlabs.org/cover/1184507/

Although the first is marked as accepted into u-boot-net I guess it was
removed due to broken boards ("DT as ABI", RGMII delay was fixed and thus
breaks the board).

After disussing with Vladimir, I've integrated his patches with this
series. Also the first one
  Address packet drops at low traffic rate due to SmartEEE feature
was dropped because it will likely be fixed by making u-boot support the
eee-broken-X device tree properties. Apart from that, only the subject was
changed and a note about possible board breakage was added the patch which
changes the delay behaviour.

For all of those, who will test this patchset, the device tree binding
needs the phydev->node property, which needs to be set in every network
driver. If the device tree binding is not working for you have a look at
the
  ar803x_of_init: found PHY node: phy@0
output. In the case above "phy@0" is the phy node in the device tree. If
instead the node of your network device is displayed, you have to set
the phydev->node property in your network device driver.

For the fsl_enetc driver this patchset will add it:
  https://patchwork.ozlabs.org/cover/1188043/

changes since v1:
 - pull all Vladimirs Oltan's patches and rebase mine onto them
 - fix the CLK_25M settings for the AR8035
 - add two new patches "fix AR8021 PHY ID mask" and "use defines for PHY
   IDs"
 - use the new kernel device tree binding for the AR803x PHYs:
   https://patchwork.ozlabs.org/patch/1188293/
 - add debugging output

Michael Walle (7):
  phy: atheros: fix AR8021 PHY ID mask
  phy: atheros: use defines for PHY IDs
  phy: atheros: introduce debug read and write functions
  phy: atheros: move delay config to common function
  phy: atheros: add device tree bindings and config
  phy: atheros: ar8035: remove static clock config
  phy: atheros: consolidate {ar8031|ar8035}_config()

Vladimir Oltean (5):
  phy: atheros: Make RGMII Tx delays actually configurable for AR8035
  phy: atheros: Use common functions for RGMII internal delays
  phy: atheros: Clarify the configuration of the CLK_25M output pin
  phy: atheros: Explicitly disable RGMII delays
  phy: atheros: Clarify the intention of ar8021_config

 doc/device-tree-bindings/net/phy/atheros.txt |  35 ++
 drivers/net/phy/atheros.c| 349 ---
 include/dt-bindings/net/qca-ar803x.h |  13 +
 3 files changed, 344 insertions(+), 53 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt
 create mode 100644 include/dt-bindings/net/qca-ar803x.h

-- 
2.20.1



[PATCH v2 06/12] phy: atheros: fix AR8021 PHY ID mask

2019-12-05 Thread Michael Walle
The upper bits are all the OUI.

Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3cc162828c..01953a1390 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -120,7 +120,7 @@ static int ar8035_config(struct phy_device *phydev)
 static struct phy_driver AR8021_driver =  {
.name = "AR8021",
.uid = 0x4dd040,
-   .mask = 0x40,
+   .mask = 0xfff0,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
-- 
2.20.1



[PATCH v2 05/12] phy: atheros: Clarify the intention of ar8021_config

2019-12-05 Thread Michael Walle
From: Vladimir Oltean 

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean 
Acked-by: Joe Hershberger 
---
 drivers/net/phy/atheros.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3e59c3f391..3cc162828c 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device 
*phydev, bool on)
 
 static int ar8021_config(struct phy_device *phydev)
 {
-   phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_5);
-   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+
+   ar803x_enable_tx_delay(phydev, true);
 
phydev->supported = phydev->drv->features;
return 0;
-- 
2.20.1



[PATCH v2 09/12] phy: atheros: move delay config to common function

2019-12-05 Thread Michael Walle
Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 38 ++
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 660dcd9491..22035c2496 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -94,19 +94,32 @@ static int ar8021_config(struct phy_device *phydev)
return 0;
 }
 
-static int ar8031_config(struct phy_device *phydev)
+static int ar803x_delay_config(struct phy_device *phydev)
 {
+   int ret;
+
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-   ar803x_enable_tx_delay(phydev, true);
+   ret = ar803x_enable_tx_delay(phydev, true);
else
-   ar803x_enable_tx_delay(phydev, false);
+   ret = ar803x_enable_tx_delay(phydev, false);
 
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-   ar803x_enable_rx_delay(phydev, true);
+   ret = ar803x_enable_rx_delay(phydev, true);
else
-   ar803x_enable_rx_delay(phydev, false);
+   ret = ar803x_enable_rx_delay(phydev, false);
+
+   return ret;
+}
+
+static int ar8031_config(struct phy_device *phydev)
+{
+   int ret;
+
+   ret = ar803x_delay_config(phydev);
+   if (ret < 0)
+   return ret;
 
phydev->supported = phydev->drv->features;
 
@@ -118,6 +131,7 @@ static int ar8031_config(struct phy_device *phydev)
 
 static int ar8035_config(struct phy_device *phydev)
 {
+   int ret;
int regval;
 
/* Configure CLK_25M output clock at 125 MHz */
@@ -126,17 +140,9 @@ static int ar8035_config(struct phy_device *phydev)
regval |= AR8035_CLK_25M_FREQ_125M;
phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
-   if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-   (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
-   ar803x_enable_tx_delay(phydev, true);
-   else
-   ar803x_enable_tx_delay(phydev, false);
-
-   if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-   (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
-   ar803x_enable_rx_delay(phydev, true);
-   else
-   ar803x_enable_rx_delay(phydev, false);
+   ret = ar803x_delay_config(phydev);
+   if (ret < 0)
+   return ret;
 
phydev->supported = phydev->drv->features;
 
-- 
2.20.1



[PATCH v2 10/12] phy: atheros: add device tree bindings and config

2019-12-05 Thread Michael Walle
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.

By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.

Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.

Signed-off-by: Michael Walle 
---
 doc/device-tree-bindings/net/phy/atheros.txt |  35 +++
 drivers/net/phy/atheros.c| 223 ++-
 include/dt-bindings/net/qca-ar803x.h |  13 ++
 3 files changed, 269 insertions(+), 2 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt
 create mode 100644 include/dt-bindings/net/qca-ar803x.h

diff --git a/doc/device-tree-bindings/net/phy/atheros.txt 
b/doc/device-tree-bindings/net/phy/atheros.txt
new file mode 100644
index 00..97e97b8c13
--- /dev/null
+++ b/doc/device-tree-bindings/net/phy/atheros.txt
@@ -0,0 +1,35 @@
+* Qualcomm Atheros PHY Device Tree binding
+
+Required properties:
+- reg: PHY address
+
+Optional properties:
+- qca,clk-out-frequency: Clock frequency of the CLK_25M pin in Hz.
+   Either 2500, 5000, 6250 or 12500.
+- qca,clk-out-strength: Clock output buffer driver strength.
+Supported values are defined in dt-bindings/net/qca-ar803x.h
+- qca,keep-pll-enabled: Keep the PLL running if no link is present.
+   Don't go into hibernation mode.
+   Only supported on the AR8031/AR8033.
+- vddio-supply: RGMII I/O voltage regulator
+   Only supported on the AR8031/AR8033.
+
+Optional subnodes:
+- vddio-regulator: Initial data for the VDDIO regulator, as covered
+doc/device-tree-bindings/regulator/regulator.txt
+
+Example:
+   #include 
+
+   ethernet-phy@0 {
+   reg = <0>;
+   qca-clk-out-frequency = <12500>;
+   qca,keep-pll-enabled;
+
+   vddio-supply = <&vddio>;
+
+   vddio: vddio-regulator {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+   };
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 22035c2496..79961df9ff 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -4,21 +4,40 @@
  *
  * Copyright 2011, 2013 Freescale Semiconductor, Inc.
  * author Andy Fleming
+ * Copyright (c) 2019 Michael Walle 
  */
 #include 
 #include 
+#include 
+#include 
 
 #define AR803x_PHY_DEBUG_ADDR_REG  0x1d
 #define AR803x_PHY_DEBUG_DATA_REG  0x1e
 
+/* Debug registers */
+#define AR803x_DEBUG_REG_0 0x0
+#define AR803x_RGMII_RX_CLK_DLYBIT(15)
+
 #define AR803x_DEBUG_REG_5 0x5
 #define AR803x_RGMII_TX_CLK_DLYBIT(8)
 
-#define AR803x_DEBUG_REG_0 0x0
-#define AR803x_RGMII_RX_CLK_DLYBIT(15)
+#define AR803x_DEBUG_REG_1F0x1f
+#define AR803x_PLL_ON  BIT(2)
+#define AR803x_RGMII_1V8   BIT(3)
 
 /* CLK_25M register is at MMD 7, address 0x8016 */
 #define AR803x_CLK_25M_SEL_REG 0x8016
+
+#define AR803x_CLK_25M_MASKGENMASK(4, 2)
+#define AR803x_CLK_25M_25MHZ_XTAL  0
+#define AR803x_CLK_25M_25MHZ_DSP   1
+#define AR803x_CLK_25M_50MHZ_PLL   2
+#define AR803x_CLK_25M_50MHZ_DSP   3
+#define AR803x_CLK_25M_62_5MHZ_PLL 4
+#define AR803x_CLK_25M_62_5MHZ_DSP 5
+#define AR803x_CLK_25M_125MHZ_PLL  6
+#define AR803x_CLK_25M_125MHZ_DSP  7
+
 /* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
 #define AR8035_CLK_25M_FREQ_25M(0 | 0)
 #define AR8035_CLK_25M_FREQ_50M(0 | BIT(3))
@@ -26,10 +45,23 @@
 #define AR8035_CLK_25M_FREQ_125M   (BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASKGENMASK(4, 3)
 
+#define AR803x_CLK_25M_DR_MASK GENMASK(8, 7)
+#define AR803x_CLK_25M_DR_FULL 0
+#define AR803x_CLK_25M_DR_HALF 1
+#define AR803x_CLK_25M_DR_QUARTER  2
+
 #define AR8021_PHY_ID 0x004dd040
 #define AR8031_PHY_ID 0x004dd074
 #define AR8035_PHY_ID 0x004dd072
 
+struct ar803x_priv {
+   int flags;
+#define AR803x_FLAG_KEEP_PLL_ENABLED   BIT(0) /* don't turn off internal PLL */
+#define AR803x_FLAG_RGMII_1V8  BIT(1) /* use 1.8V RGMII I/O voltage */
+   u16 clk_25m_reg;
+   u16 clk_25m_mask;
+};
+
 static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 {
int ret;
@@ -113,14 +145,193 @@ static int ar803x_delay_config(struct phy_device *phydev)
return ret;
 }
 
+static int ar803x_regs_config(struct phy_device *phydev)
+{
+   struct ar803x_priv *priv = phydev->priv;
+   u16 set = 0, clear = 0;
+   int val;
+   int ret;
+
+   /* 

[PATCH v2 11/12] phy: atheros: ar8035: remove static clock config

2019-12-05 Thread Michael Walle
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.

If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <12500>" because that value was the hardcoded
value until this commit.

Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 13 -
 1 file changed, 13 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 79961df9ff..208b06d3c7 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -37,12 +37,6 @@
 #define AR803x_CLK_25M_62_5MHZ_DSP 5
 #define AR803x_CLK_25M_125MHZ_PLL  6
 #define AR803x_CLK_25M_125MHZ_DSP  7
-
-/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
-#define AR8035_CLK_25M_FREQ_25M(0 | 0)
-#define AR8035_CLK_25M_FREQ_50M(0 | BIT(3))
-#define AR8035_CLK_25M_FREQ_62M(BIT(4) | 0)
-#define AR8035_CLK_25M_FREQ_125M   (BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASKGENMASK(4, 3)
 
 #define AR803x_CLK_25M_DR_MASK GENMASK(8, 7)
@@ -343,18 +337,11 @@ static int ar8031_config(struct phy_device *phydev)
 static int ar8035_config(struct phy_device *phydev)
 {
int ret;
-   int regval;
 
ret = ar803x_of_init(phydev);
if (ret < 0)
return ret;
 
-   /* Configure CLK_25M output clock at 125 MHz */
-   regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
-   regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
-   regval |= AR8035_CLK_25M_FREQ_125M;
-   phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
-
ret = ar803x_delay_config(phydev);
if (ret < 0)
return ret;
-- 
2.20.1



[PATCH 2/4] buildman: Ask genboardscfg to be quiet

2019-12-05 Thread Simon Glass
Now that this tool has a 'quiet' flag, use it.

Signed-off-by: Simon Glass 
---

 tools/buildman/control.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index c55a65d0c3..3b41d7b26a 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -205,7 +205,7 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 os.makedirs(options.output_dir)
 board_file = os.path.join(options.output_dir, 'boards.cfg')
 genboardscfg = os.path.join(options.git, 'tools/genboardscfg.py')
-status = subprocess.call([genboardscfg, '-o', board_file])
+status = subprocess.call([genboardscfg, '-q', '-o', board_file])
 if status != 0:
 sys.exit("Failed to generate boards.cfg")
 
-- 
2.24.0.393.g34dc348eaf-goog



[PATCH v2 12/12] phy: atheros: consolidate {ar8031|ar8035}_config()

2019-12-05 Thread Michael Walle
The two functions are now exactly the same, remove one of them.

Signed-off-by: Michael Walle 
---
 drivers/net/phy/atheros.c | 30 +++---
 1 file changed, 3 insertions(+), 27 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 208b06d3c7..21e048d8f4 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -310,31 +310,7 @@ static int ar803x_of_init(struct phy_device *phydev)
return 0;
 }
 
-static int ar8031_config(struct phy_device *phydev)
-{
-   int ret;
-
-   ret = ar803x_of_init(phydev);
-   if (ret < 0)
-   return ret;
-
-   ret = ar803x_delay_config(phydev);
-   if (ret < 0)
-   return ret;
-
-   ret = ar803x_regs_config(phydev);
-   if (ret < 0)
-   return ret;
-
-   phydev->supported = phydev->drv->features;
-
-   genphy_config_aneg(phydev);
-   genphy_restart_aneg(phydev);
-
-   return 0;
-}
-
-static int ar8035_config(struct phy_device *phydev)
+static int ar803x_config(struct phy_device *phydev)
 {
int ret;
 
@@ -373,7 +349,7 @@ static struct phy_driver AR8031_driver =  {
.uid = AR8031_PHY_ID,
.mask = 0xffef,
.features = PHY_GBIT_FEATURES,
-   .config = ar8031_config,
+   .config = ar803x_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
 };
@@ -383,7 +359,7 @@ static struct phy_driver AR8035_driver =  {
.uid = AR8035_PHY_ID,
.mask = 0xffef,
.features = PHY_GBIT_FEATURES,
-   .config = ar8035_config,
+   .config = ar803x_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
 };
-- 
2.20.1



[PATCH 1/4] genboardcfg: Support a quiet mode

2019-12-05 Thread Simon Glass
We don't really need buildman to print this every time it runs. Add a flag
to run quietly, that buildman can use.

Signed-off-by: Simon Glass 
---

 tools/genboardscfg.py | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 4ff0bffaef..dffa409317 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -403,18 +403,20 @@ def format_and_output(params_list, output):
 with open(output, 'w', encoding="utf-8") as f:
 f.write(COMMENT_BLOCK + '\n'.join(output_lines) + '\n')
 
-def gen_boards_cfg(output, jobs=1, force=False):
+def gen_boards_cfg(output, jobs=1, force=False, quiet=False):
 """Generate a board database file.
 
 Arguments:
   output: The name of the output file
   jobs: The number of jobs to run simultaneously
   force: Force to generate the output even if it is new
+  quiet: True to avoid printing a message if nothing needs doing
 """
 check_top_directory()
 
 if not force and output_is_new(output):
-print("%s is up to date. Nothing to do." % output)
+if not quiet:
+print("%s is up to date. Nothing to do." % output)
 sys.exit(0)
 
 params_list = scan_defconfigs(jobs)
@@ -435,9 +437,11 @@ def main():
   help='the number of jobs to run simultaneously')
 parser.add_option('-o', '--output', default=OUTPUT_FILE,
   help='output file [default=%s]' % OUTPUT_FILE)
+parser.add_option('-q', '--quiet', help='run silently')
 (options, args) = parser.parse_args()
 
-gen_boards_cfg(options.output, jobs=options.jobs, force=options.force)
+gen_boards_cfg(options.output, jobs=options.jobs, force=options.force,
+   quiet=options.quiet)
 
 if __name__ == '__main__':
 main()
-- 
2.24.0.393.g34dc348eaf-goog



[PATCH 3/4] buildman: Figure out boards before commits

2019-12-05 Thread Simon Glass
At present buildman looks at toolchains, then commits and then boards.
Move the board processing up above the commit processing, since it relates
to the toolchain code. This will make it easier to check the toolchains
needed for a board without processing commits first.

Signed-off-by: Simon Glass 
---

 tools/buildman/control.py | 59 +++
 1 file changed, 29 insertions(+), 30 deletions(-)

diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 3b41d7b26a..a9c5022e48 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -170,35 +170,6 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 print()
 return 0
 
-# Work out how many commits to build. We want to build everything on the
-# branch. We also build the upstream commit as a control so we can see
-# problems introduced by the first commit on the branch.
-count = options.count
-has_range = options.branch and '..' in options.branch
-if count == -1:
-if not options.branch:
-count = 1
-else:
-if has_range:
-count, msg = gitutil.CountCommitsInRange(options.git_dir,
- options.branch)
-else:
-count, msg = gitutil.CountCommitsInBranch(options.git_dir,
-  options.branch)
-if count is None:
-sys.exit(col.Color(col.RED, msg))
-elif count == 0:
-sys.exit(col.Color(col.RED, "Range '%s' has no commits" %
-   options.branch))
-if msg:
-print(col.Color(col.YELLOW, msg))
-count += 1   # Build upstream commit also
-
-if not count:
-str = ("No commits found to process in branch '%s': "
-   "set branch's upstream or use -c flag" % options.branch)
-sys.exit(col.Color(col.RED, str))
-
 # Work out what subset of the boards we are building
 if not boards:
 if not os.path.exists(options.output_dir):
@@ -217,7 +188,6 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 for arg in options.exclude:
 exclude += arg.split(',')
 
-
 if options.boards:
 requested_boards = []
 for b in options.boards:
@@ -230,6 +200,35 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 if not len(selected):
 sys.exit(col.Color(col.RED, 'No matching boards found'))
 
+# Work out how many commits to build. We want to build everything on the
+# branch. We also build the upstream commit as a control so we can see
+# problems introduced by the first commit on the branch.
+count = options.count
+has_range = options.branch and '..' in options.branch
+if count == -1:
+if not options.branch:
+count = 1
+else:
+if has_range:
+count, msg = gitutil.CountCommitsInRange(options.git_dir,
+ options.branch)
+else:
+count, msg = gitutil.CountCommitsInBranch(options.git_dir,
+  options.branch)
+if count is None:
+sys.exit(col.Color(col.RED, msg))
+elif count == 0:
+sys.exit(col.Color(col.RED, "Range '%s' has no commits" %
+   options.branch))
+if msg:
+print(col.Color(col.YELLOW, msg))
+count += 1   # Build upstream commit also
+
+if not count:
+str = ("No commits found to process in branch '%s': "
+   "set branch's upstream or use -c flag" % options.branch)
+sys.exit(col.Color(col.RED, str))
+
 # Read the metadata from the commits. First look at the upstream commit,
 # then the ones in the branch. We would like to do something like
 # upstream/master~..branch but that isn't possible if upstream/master is
-- 
2.24.0.393.g34dc348eaf-goog



[PATCH 4/4] buildman: Add options to get the arch and toolchain info

2019-12-05 Thread Simon Glass
Sometimes it is useful for external tools to use buildman to provide the
toolchain information. Add an -a option which shows the value to use for
the ARCH environment variable, and -A which does the same for
CROSS_COMPILE

Signed-off-by: Simon Glass 
---

 tools/buildman/README   |  3 +++
 tools/buildman/cmdline.py   |  4 
 tools/buildman/control.py   | 35 +++
 tools/buildman/test.py  | 18 ++
 tools/buildman/toolchain.py | 26 ++
 5 files changed, 86 insertions(+)

diff --git a/tools/buildman/README b/tools/buildman/README
index e36619216d..c1ac0d0f58 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -1061,6 +1061,9 @@ Other options
 
 Buildman has various other command line options. Try --help to see them.
 
+To find out what architecture or toolchain prefix buildman will use for a 
build,
+see the -a and -A options.
+
 When doing builds, Buildman's return code will reflect the overall result:
 
 0 (success) No errors or warnings found
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 832a5145d2..b41209373d 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -13,6 +13,10 @@ def ParseArgs():
 args: command lin arguments
 """
 parser = OptionParser()
+parser.add_option('-a', '--print-arch', action='store_true',
+  help='Print the architecture for a board (ARCH=)')
+parser.add_option('-A', '--print-prefix', action='store_true',
+  help='Print the tool-chain prefix for a board (CROSS_COMPILE=)')
 parser.add_option('-b', '--branch', type='string',
   help='Branch name to build, or range of commits to build')
 parser.add_option('-B', '--bloat', dest='show_bloat',
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index a9c5022e48..969d866547 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -107,6 +107,34 @@ def CheckOutputDir(output_dir):
 break
 path = parent
 
+def ShowToolchainInfo(boards, toolchains, print_arch, print_prefix):
+"""Show information about a the tool chain used by one or more boards
+
+The function checks that all boards use the same toolchain.
+
+Args:
+boards: Boards object containing selected boards
+toolchains: Toolchains object containing available toolchains
+print_arch: True to print ARCH value
+print_prefix: True to print CROSS_COMPILE value
+
+Return:
+None on success, string error message otherwise
+"""
+boards = boards.GetSelectedDict()
+tc_set = set()
+for brd in boards.values():
+tc_set.add(toolchains.Select(brd.arch))
+if len(tc_set) != 1:
+return 'Supplied boards must share one toolchain'
+return False
+tc = tc_set.pop()
+if print_arch:
+print(tc.GetEnvArgs(toolchain.VAR_ARCH))
+if print_prefix:
+print(tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+return None
+
 def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
clean_dir=False):
 """The main control code for buildman
@@ -200,6 +228,13 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 if not len(selected):
 sys.exit(col.Color(col.RED, 'No matching boards found'))
 
+if options.print_arch or options.print_prefix:
+err = ShowToolchainInfo(boards, toolchains, options.print_arch,
+options.print_prefix)
+if err:
+sys.exit(col.Color(col.RED, err))
+return 0
+
 # Work out how many commits to build. We want to build everything on the
 # branch. We also build the upstream commit as a control so we can see
 # problems introduced by the first commit on the branch.
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index b4e28d6867..acd862b3b0 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -451,6 +451,24 @@ class TestBuild(unittest.TestCase):
 'crosstool/files/bin/x86_64/.*/'
 'x86_64-gcc-.*-nolibc_arm-.*linux-gnueabi.tar.xz')
 
+def testGetEnvArgs(self):
+"""Test the GetEnvArgs() function"""
+tc = self.toolchains.Select('arm')
+self.assertEqual('arm-linux-',
+ tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+self.assertEqual('', tc.GetEnvArgs(toolchain.VAR_PATH))
+self.assertEqual('arm',
+ tc.GetEnvArgs(toolchain.VAR_ARCH))
+self.assertEqual('', tc.GetEnvArgs(toolchain.VAR_MAKE_ARGS))
+
+self.toolchains.Add('/path/to/x86_64-linux-gcc', test=False)
+tc = self.toolchains.Select('x86')
+self.assertEqual('/path/to',
+ tc.GetEnvArgs(toolchain.VAR_PATH))
+tc.override_toolchain = 'clang'
+self.assertEqual('HOSTCC=clang CC=clang',
+

Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions

2019-12-05 Thread Michael Walle

Am 2019-11-30 02:11, schrieb Joe Hershberger:

On Fri, Oct 25, 2019 at 7:28 PM Michael Walle  wrote:


Provide functions to read and write the Atheros debug registers.

Signed-off-by: Michael Walle 


Acked-by: Joe Hershberger 



Sorry this was superseeded by
https://patchwork.ozlabs.org/project/uboot/list/?series=146771

Unfortunately, I've forgot to add the mailinglist to the original 
series. So it never ended up in the patchwork system :(


-michael


Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions

2019-12-05 Thread Michael Walle

Am 2019-11-30 02:11, schrieb Joe Hershberger:

On Fri, Oct 25, 2019 at 7:28 PM Michael Walle  wrote:


Provide functions to read and write the Atheros debug registers.

Signed-off-by: Michael Walle 


Acked-by: Joe Hershberger 



Sorry this series superseeded by
https://patchwork.ozlabs.org/project/uboot/list/?series=146771

Unfortunately, I've forgot to add the mailinglist to the original 
series. So it never ended up in the patchwork system :(


-michael


Reconfiguring PCIe ranges

2019-12-05 Thread Yusuf Altıparmak
Hello,

I need to reconfigure PCIe settings to connect a GPU. From config header
files, the variables I changed are below.  I did exact same changes to
linux .dts file.

But when I power on the board, u-boot is freezing during gpu driver
initialization (after reading BAR registers). I also tried some other
configs but sometimes I got machine check error, sometimes local access
memory (LAW) error and so on..

My question is, how should I increase the memory map size of PCIE2. I just
want to increase it to 512 MB without crashing some other things ?

And also, I want to know what are these MEM_VIRT, MEM_BUS,_MEM PHYS and
IO_VIRT, IO_BUS and IO_PHYS ?

Thanks,
Regards.

#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 2 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf800
#define CONFIG_SYS_PCIE1_IO_BUS 0x
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */
#endif

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x9000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc1000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE* 0x2000 /* INCREASED TO 512 MB*/*
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf801
#define CONFIG_SYS_PCIE2_IO_BUS 0x
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull
#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */
#endif

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT *0xb000 /* I changed this to
0xb000 instead of 0xa000 because PCIE2 end adress is changed to 512
MB from 256 MB */*
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000
#define CONFIG_SYS_PCIE3_MEM_PHYS *0xc3000ull*
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf802
#define CONFIG_SYS_PCIE3_IO_BUS 0x
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull
#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */
#endif

/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT *0xc000 /* b -> c */*
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000
#define CONFIG_SYS_PCIE4_MEM_PHYS *0xc4000ull*
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf803
#define CONFIG_SYS_PCIE4_IO_BUS 0x
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff83ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */
#endif


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