[U-Boot] [PATCH] Cleanup CONFIG_BOOTDELAY on cl-som-imx7

[Alex Kiernan]

CONFIG_BOOTDELAY has been migrated to Kconfig, but cl-som-imx7 was
missed. We can just delete the assignments as the config already has
the correct value.

Signed-off-by: Alex Kiernan 
---

 include/configs/cl-som-imx7.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index faea6c6b93..e4554ed541 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -64,9 +64,7 @@
 #undef CONFIG_SYS_AUTOLOAD
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOOTCOMMAND
-#undef CONFIG_BOOTDELAY
 
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_SYS_AUTOLOAD"no"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-- 
2.17.1

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[U-Boot] [PATCH 1/4] configs: opos6uldev: undef CONFIG_POWER_DOMAIN when SPL_BUILD

[Peng Fan]

Because CONFIG_POWER_DOMAIN is enabled in defconfig,
however driver/power/domain is not built for SPL, there is build
failure when power_domain_on added to device_probe.
Because power domain is not needed in SPL, let's undef it.

Signed-off-by: Peng Fan 
Cc: "Sébastien Szymanski" 
Cc: Stefano Babic 
---

Need to find a way to avoid SPL build failure in future patch,
but in this patchset let's undef CONFIG_POWER_DOMAIN first,
because it is not needed.

 include/configs/opos6uldev.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index b634d9eb03..75fefec0ac 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -15,6 +15,7 @@
 
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_REGULATOR
+#undef CONFIG_POWER_DOMAIN
 #endif
 #endif
 
-- 
2.14.1

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[U-Boot] [PATCH 3/4] dm: core: device: enable power domain in probe

[Peng Fan]

Enable power domain associated with the device when probe.

Signed-off-by: Peng Fan 
Cc: Simon Glass 
---
 drivers/core/device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index d5f5fc31b0..207d566b71 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -304,6 +305,7 @@ static void *alloc_priv(int size, uint flags)
 
 int device_probe(struct udevice *dev)
 {
+   struct power_domain pd;
const struct driver *drv;
int size = 0;
int ret;
@@ -383,6 +385,11 @@ int device_probe(struct udevice *dev)
if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
pinctrl_select_state(dev, "default");
 
+   if (dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) {
+   if (!power_domain_get(dev, &pd))
+   power_domain_on(&pd);
+   }
+
ret = uclass_pre_probe_device(dev);
if (ret)
goto fail;
-- 
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[U-Boot] [PATCH 2/4] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined

[Peng Fan]

Add dummy functions when CONFIG_POWER_DOMAIN not defined.

Signed-off-by: Peng Fan 
Reviewed-by: Simon Glass 
---
 include/power-domain.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/include/power-domain.h b/include/power-domain.h
index aba8c0f65c..fe2a1c5119 100644
--- a/include/power-domain.h
+++ b/include/power-domain.h
@@ -87,7 +87,14 @@ struct power_domain {
  * @power_domain   A pointer to a power domain struct to initialize.
  * @return 0 if OK, or a negative error code.
  */
+#ifdef CONFIG_POWER_DOMAIN
 int power_domain_get(struct udevice *dev, struct power_domain *power_domain);
+#else
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain)
+{
+   return -EINVAL;
+}
+#endif
 
 /**
  * power_domain_free - Free a previously requested power domain.
@@ -96,7 +103,14 @@ int power_domain_get(struct udevice *dev, struct 
power_domain *power_domain);
  * requested by power_domain_get().
  * @return 0 if OK, or a negative error code.
  */
+#ifdef CONFIG_POWER_DOMAIN
 int power_domain_free(struct power_domain *power_domain);
+#else
+int power_domain_free(struct power_domain *power_domain)
+{
+   return -EINVAL;
+}
+#endif
 
 /**
  * power_domain_on - Enable power to a power domain.
@@ -105,7 +119,14 @@ int power_domain_free(struct power_domain *power_domain);
  * requested by power_domain_get().
  * @return 0 if OK, or a negative error code.
  */
+#ifdef CONFIG_POWER_DOMAIN
 int power_domain_on(struct power_domain *power_domain);
+#else
+int power_domain_on(struct power_domain *power_domain)
+{
+   return -EINVAL;
+}
+#endif
 
 /**
  * power_domain_off - Disable power ot a power domain.
@@ -114,6 +135,13 @@ int power_domain_on(struct power_domain *power_domain);
  * requested by power_domain_get().
  * @return 0 if OK, or a negative error code.
  */
+#ifdef CONFIG_POWER_DOMAIN
 int power_domain_off(struct power_domain *power_domain);
+#else
+int power_domain_off(struct power_domain *power_domain)
+{
+   return -EINVAL;
+}
+#endif
 
 #endif
-- 
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[U-Boot] [PATCH 4/4] dm: power-domain: query power domain after get device

[Peng Fan]

This is to test power_domain_on in device_probe.
If the device has a power-domain property, enable it
when probe the device. So add the test to check
whether it is powered on or not.

Signed-off-by: Peng Fan 
Cc: Simon Glass 
---
 test/dm/power-domain.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
index a1e1df2bb2..48318218a9 100644
--- a/test/dm/power-domain.c
+++ b/test/dm/power-domain.c
@@ -26,6 +26,8 @@ static int dm_test_power_domain(struct unit_test_state *uts)
 
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
  &dev_test));
+   ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+ TEST_POWER_DOMAIN));
ut_assertok(sandbox_power_domain_test_get(dev_test));
 
ut_assertok(sandbox_power_domain_test_on(dev_test));
-- 
2.14.1

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Re: [U-Boot] [PATCH v2 2/5] Revert "dm: led: auto probe() LEDs with "default-state""

[Patrick DELAUNAY]

Hi Simon,

> From: s...@google.com  On Behalf Of Simon Glass
> Sent: mardi 24 juillet 2018 01:48
> 
> Hi Patrick,
> 
> On 23 July 2018 at 03:41, Patrick Delaunay  wrote:
> > This reverts commit bc882f5d5c7b4d6ed5e927bf838863af43c786e7.
> 
> A revert should have a motivation and a discussion of the purpose, just like 
> any
> other patch. Can you add it please?

 I wil add a motivaiton  in v3.

> >
> > Signed-off-by: Patrick Delaunay 
> > ---
> >
> > Changes in v2: None
> >
> >  drivers/led/led_gpio.c | 9 -
> >  1 file changed, 9 deletions(-)
> 
> Regards,
> Simon

Regards

Patrick
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Re: [U-Boot] [PATCH v1 4/6] mmc: arm_pl180_mmci: Update to support CONFIG_BLK

[Patrice CHOTARD]

Hi Simon

On 07/24/2018 01:48 AM, Simon Glass wrote:
> Hi Patrice,
> 
> On 20 July 2018 at 01:44, Patrice Chotard  wrote:
>> Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci
>> to support this config.
>>
>> This driver is used by STM32Fx and by Vexpress platforms.
>> Only STM32Fx are DM ready. No DM code is isolated and will be
>> removed easily when wexpress will be converted to DM.
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>
>>   drivers/mmc/arm_pl180_mmci.c | 85 
>> +++-
>>   1 file changed, 45 insertions(+), 40 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 
> But please see below.
> 
>>
>> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
>> index e267cd782e8b..e988bac62298 100644
>> --- a/drivers/mmc/arm_pl180_mmci.c
>> +++ b/drivers/mmc/arm_pl180_mmci.c
>> @@ -357,13 +357,13 @@ static const struct mmc_ops arm_pl180_mmci_ops = {
>>  .set_ios = host_set_ios,
>>  .init = mmc_host_reset,
>>   };
>> -#endif
>>
>>   /*
>>* mmc_host_init - initialize the mmc controller.
>>* Set initial clock and power for mmc slot.
>>* Initialize mmc struct and register with mmc framework.
>>*/
>> +
>>   int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
>>   {
>>  u32 sdi_u32;
>> @@ -377,9 +377,8 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, 
>> struct mmc **mmc)
>>  writel(sdi_u32, &host->base->mask0);
>>
>>  host->cfg.name = host->name;
>> -#ifndef CONFIG_DM_MMC
>>  host->cfg.ops = &arm_pl180_mmci_ops;
>> -#endif
>> +
>>  /* TODO remove the duplicates */
>>  host->cfg.host_caps = host->caps;
>>  host->cfg.voltages = host->voltages;
>> @@ -393,23 +392,44 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, 
>> struct mmc **mmc)
>>  *mmc = mmc_create(&host->cfg, host);
>>  if (!*mmc)
>>  return -1;
>> -
>>  debug("registered mmc interface number is:%d\n",
>>(*mmc)->block_dev.devnum);
>>
>>  return 0;
>>   }
>> +#endif
>>
>>   #ifdef CONFIG_DM_MMC
> 
> Can you drop this?

I can't as this driver is also used by Vexpress platforms which doesn't 
enable CONFIG_DM_MMC flag.

> 
>> +static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
>> +{
>> +   u32 sdi_u32;
>> +
>> +   writel(host->pwr_init, &host->base->power);
>> +   writel(host->clkdiv_init, &host->base->clock);
>> +   udelay(CLK_CHANGE_DELAY);
>> +
>> +   /* Disable mmc interrupts */
>> +   sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
>> +   writel(sdi_u32, &host->base->mask0);
>> +}
>> +
>>   static int arm_pl180_mmc_probe(struct udevice *dev)
>>   {
>>  struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
>>  struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
>>  struct mmc *mmc = &pdata->mmc;
>> -   struct pl180_mmc_host *host = mmc->priv;
>> +   struct pl180_mmc_host *host = dev->priv;
>> +   struct mmc_config *cfg = &pdata->cfg;
>>  struct clk clk;
>>  u32 bus_width;
>>  int ret;
>> +   fdt_addr_t addr;
>> +
>> +   addr = devfdt_get_addr(dev);
> 
> dev_read_addr()

right, i will update the code

> 
> It is somewhat more correct to read from the DT in
> ofdata_to_platdata() if you can.
> 

Ok, i will reintroduce ofdata_to_platdata()

Thanks

Patrice

>> +   if (addr == FDT_ADDR_T_NONE)
>> +   return -EINVAL;
>> +
>> +   host->base = (void *)addr;
>>
>>  ret = clk_get_by_index(dev, 0, &clk);
>>  if (ret < 0)
>> @@ -421,27 +441,28 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
>>  return ret;
>>  }
>>
>> -   strcpy(host->name, "MMC");
>>  host->pwr_init = INIT_PWR;
>>  host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
>>  SDI_CLKCR_HWFC_EN;
>> -   host->voltages = VOLTAGE_WINDOW_SD;
>> -   host->caps = 0;
>>  host->clock_in = clk_get_rate(&clk);
>> -   host->clock_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 
>> 1));
>> -   host->clock_max = dev_read_u32_default(dev, "max-frequency",
>> -  MMC_CLOCK_MAX);
>>  host->version2 = dev_get_driver_data(dev);
>>
>> +   cfg->name = dev->name;
>> +   cfg->voltages = VOLTAGE_WINDOW_SD;
>> +   cfg->host_caps = 0;
>> +   cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
>> +   cfg->f_max = dev_read_u32_default(dev, "max-frequency", 
>> MMC_CLOCK_MAX);
>> +   cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
>> +
>>  gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, 
>> GPIOD_IS_IN);
>>
>>  bus_width = dev_read_u32_default(dev, "bus-width", 1);
>>  switch (bus_width) {
>>  case 8:
>> -   host->caps |= MMC_MODE_8BIT;
>> +   cfg->host_caps |

Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Dr. Philipp Tomsich]

> On 24 Jul 2018, at 07:12, Marty E. Plummer  wrote:
> 
> On Fri, Jul 13, 2018 at 12:31:49PM +0200, Dr. Philipp Tomsich wrote:
>> 
>>> On 7 May 2018, at 02:20, Marty E. Plummer  wrote:
>>> 
>>> On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com 
>>>  wrote:
 
> On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
> 
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> 
> Signed-off-by: Marty E. Plummer 
> ---
> arch/arm/dts/Makefile |   1 +
> arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
> arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
> board/google/veyron/Kconfig   |  16 ++
> configs/chromebook_speedy_defconfig   |  96 +++
> 6 files changed, 315 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ac7667b1e8..ee04d9bedd 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>   rk3288-veyron-jerry.dtb \
>   rk3288-veyron-mickey.dtb \
>   rk3288-veyron-minnie.dtb \
> + rk3288-veyron-speedy.dtb \
>   rk3288-vyasa.dtb \
>   rk3328-evb.dtb \
>   rk3368-lion.dtb \
> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
> b/arch/arm/dts/rk3288-veyron-speedy.dts
> new file mode 100644
> index 00..d5383cef0d
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
 
 This file looks quite different then the one I see on kernel.org with that 
 revision id. So you are sure you
 imported that one?
>>> Dafuq... it seems I borked something up in doing the patch juggling to
>>> turn my single-commit mess of a patch (you know, the 'get the thing to
>>> work branch') into a good patch series I messed up on this one.
 
> @@ -0,0 +1,189 @@
> +/*
> + * Google Veyron Speedy Rev 1+ board device tree source
> + *
> + * Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:  GPL-2.0
 
 This file is dual licensed upstream, keep it that way.
 The comment will claim it's a X11 license but the license text below
 is actually MIT so you may want to use the MIT SPDX tag for that.
 
>>> Yeah, I was listening in on the convo on irc. So, even though it 'says'
>>> its GPL/X11, the actual license text is MIT, so I should use that tag?
>>> Its not my code, obviously, so I have no dog in that race anyways.
> + */
> +
> +/dts-v1/;
> +#include "rk3288-veyron-chromebook.dtsi"
> +#include "cros-ec-sbs.dtsi"
> +
> +/ {
> + model = "Google Speedy";
> + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> +  "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> +  "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> +  "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> +  "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + panel_regulator: panel-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_enable_h>;
> + regulator-name = "panel_regulator";
> + startup-delay-us = <10>;
> + vin-supply = <&vcc33_sys>;
> + };
> +
> + vcc18_lcd: vcc18-lcd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&avdd_1v8_disp_en>;
> + regulator-name = "vcc18_lcd";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc18_wl>;
> + };
> +
> + backlight_regulator: backlight-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_pwr_en>;
> + regulator-name = "backlight_regulator";
> + vin-supply = <&vcc33_sys>;
> + startup-delay-us = <15000>;
> + };
> 

[U-Boot] [PATCH V2] drivers: regulator: fixed: add u-boot, off-on-delay-us

[Peng Fan]

Add u-boot,off-on-delay-us for fixed regulator.

Depends on board design, the gpio regulator sometimes
connects with a big capacitance. When need to off, then
on the regulator, if there is no enough delay,
the voltage does not drop to 0, so introduce this
property to handle such case.

Signed-off-by: Peng Fan 
Cc: Masahiro Yamada 
Cc: Simon Glass 
---

Simon, I droped your reviewed-by tag in V2, because I changed
"off-on-delay-us" to "u-boot,off-on-delay-us" and
add devicetree bindings.

Thanks,
Peng.

 .../devicetree/bindings/regulator/fixed-regulator.txt| 16 
 drivers/power/regulator/fixed.c  |  6 ++
 2 files changed, 22 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/regulator/fixed-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt 
b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
new file mode 100644
index 00..2b241cf563
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -0,0 +1,16 @@
+Fixed Voltage regulators
+
+Check Linux Kernel
+Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+
+U-Boot Specific:
+Optional properties:
+- u-boot,off-on-delay-us: off delay time in microseconds
+
+Example:
+
+   abc: fixedregulator@0 {
+   ...
+   u-boot,off-on-delay-us = <8>;
+   ...
+   };
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 0be5b7bd51..c5fe0ba43d 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -16,6 +16,7 @@
 struct fixed_regulator_platdata {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
+   unsigned int off_on_delay_us;
 };
 
 static int fixed_regulator_ofdata_to_platdata(struct udevice *dev)
@@ -50,6 +51,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice 
*dev)
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = dev_read_u32_default(dev,
"startup-delay-us", 0);
+   dev_pdata->off_on_delay_us = dev_read_u32_default(dev,
+ 
"u-boot,off-on-delay-us", 0);
 
return 0;
 }
@@ -123,6 +126,9 @@ static int fixed_regulator_set_enable(struct udevice *dev, 
bool enable)
udelay(dev_pdata->startup_delay_us);
debug("%s: done\n", __func__);
 
+   if (!enable && dev_pdata->off_on_delay_us)
+   udelay(dev_pdata->off_on_delay_us);
+
return 0;
 }
 
-- 
2.14.1

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Re: [U-Boot] [PATCH 3/3] rockchip: fix incorrect detection of ram size

[Dr. Philipp Tomsich]

Marty,

> On 6 Jul 2018, at 05:11, Marty E. Plummer  wrote:
> 
> On Sat, May 19, 2018 at 02:08:53PM +0200, Dr. Philipp Tomsich wrote:
>> Marty,
>> 
>>> On 19 May 2018, at 12:40, Marty E. Plummer  wrote:
>>> 
>>> So explain to me what you'd like me to do here, if you would. What I
>>> gather from this is you want me to flip CONFIG_PHYS_64BIT and see if it
>>> works or what? I can flash/reflash u-boot and coreboot pretty easily on
>>> the device, so I'm down for any sort of hardware testing needed to get
>>> this into a usable state.
>> 
>> Yes, just enable PHYS_64BIT and report on how far it goes (activating some
>> debug may be helpful to understand what goes wrong, if it fails).
>> 
>> My gut feeling is that it could work, but there’s a number of pitfalls and 
>> we may
>> not be lucky.
>> 
> Testing flipping CONFIG_PHYS_64BIT, both with and without my 'clamping'
> patch to sdram_common.c, has the same results, in that all that is
> output on the servo console is that wierd  output. Where to from
> here, then?

I have a patchset for changing the relevant fields in U-Boot to allow for 
33bits (i.e. using u64) for the RAM size and it finally passes Travis cleanly.
It will be another round or two of cleanup before I can submit the series — 
once this happens, I’ll copy you so you can give your Tested-by if it works…

Thanks,
Phil.
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Re: [U-Boot] [PATCH] ddr: altera: Add ECC DRAM scrubbing support for Stratix 10

[Chee, Tien Fong]

On Mon, 2018-07-23 at 11:46 +0200, Marek Vasut wrote:
> On 07/23/2018 10:20 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > The SDRAM must first be rewritten by zeroes if ECC is used to
> > initialize
> > the ECC metadata. Make the CPU overwrite the DRAM with zeroes in
> > such a
> > case. This scrubbing implementation turns the caches on
> > temporarily, then
> > overwrites the whole RAM with zeroes, flushes the caches and turns
> > them
> > off again. This provides satisfactory performance.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  drivers/ddr/altera/sdram_s10.c |   44
> > 
> >  1 files changed, 44 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/ddr/altera/sdram_s10.c
> > b/drivers/ddr/altera/sdram_s10.c
> > index 48f4f47..cce261f 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -8,6 +8,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void)
> >      SYSMGR_HMC_CLK_STATUS_MSK, true,
> > 1000, false);
> >  }
> >  
> > +/* Initialize SDRAM ECC bits to avoid false DBE */
> > +static void sdram_init_ecc_bits(unsigned long long size)
> > +{
> > +   /* 1GB per chunk */
> > +   unsigned long long size_byte = SZ_1G;
> > +   unsigned long long remaining_size;
> > +   unsigned long long dst_addr = 0x8000;
> > +   unsigned int start = get_timer(0);
> > +
> > +   icache_enable();
> > +
> > +   memset(0, 0, dst_addr);
> > +   gd->arch.tlb_addr = 0x4000;
> > +   gd->arch.tlb_size = PGTABLE_SIZE;
> Are you sure this is valid on arm64 ? It looks like something copies
> from arria10.
The cache on/off is copied from your implementation on Arria 10. Yes, i
have tested it, it is working on Stratix 10 board.
> 
> > 
> > +   dcache_enable();
> > +
> > +   remaining_size = size - dst_addr;
> > +   printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", (u32)(size
> > >> 20));
> > +
> > +   while (remaining_size) {
> > +   if (remaining_size <= size_byte) {
> > +   memset((void *)dst_addr, 0,
> > remaining_size);
> > +   break;
> > +   } else {
> > +   memset((void *)dst_addr, 0, size_byte);
> > +   dst_addr += size_byte;
> > +   }
> > +
> > +   WATCHDOG_RESET();
> > +   remaining_size -= size_byte;
> > +   }
> How long does this take ?
1359ms for 2GB. But I have no idea why Arria 10 board can't achieve the
same result. Could you try again on your Arria 10 ES board?
> 
> > 
> > +   flush_dcache_all();
> > +   printf("DDRCAL: Scrubbing ECC RAM done.\n");
> > +   dcache_disable();
> > +
> > +   printf("SDRAM-ECC: Initialized success with %d ms\n",
> > +   (unsigned)get_timer(start));
> > +}
> > +
> >  /**
> >   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> >   *
> > @@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused)
> >     setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
> >      (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
> >       DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> > +
> > +   sdram_init_ecc_bits(gd->ram_size);
> >     } else {
> >     clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
> >      (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
> > 
> 
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Re: [U-Boot] [PATCH v2 02/13] sunxi: add basic memory map definitions of H6 SoC

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:21PM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC come with a totally new memory map.
> 
> Add basical definition of the new memory map into a header file, and let
> the cpu.h header include it in the situation of H6.
> 
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Andre Przywara 

Acked-by: Maxime Ripard 

Thanks!
Maxime

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Re: [U-Boot] [PATCH v2 22/26] mmc: Change mode when switching to a boot partition

[Faiz Abbas]

Hi,

On Thursday 21 September 2017 08:00 PM, Jean-Jacques Hiblot wrote:
> Boot partitions do not support HS200. Changing to a lower performance mode
> is required to access them.

I see that the spec says "HS200 and HS400 modes are not supported during
*boot operation*". Can you point out where it says boot partitions are
not accessible in HS200/HS400?

I reverted this patch and was able to access boot0 partition in HS400
mode in U-boot.

Thanks,
Faiz
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Re: [U-Boot] [PATCH v2 04/13] sunxi: change ATF position for H6

[Andre Przywara]

Hi,

On 21/07/18 09:20, Icenowy Zheng wrote:
> H6 has different SRAM A2 address, so the ATF load address is also
> different.
> 
> Add judgment code to sunxi 64-bit FIT generation script. It will judge
> the SoC by the device tree's name.

This might need to become more flexible in the future, where the ATF
might need to reside somewhere else, even for the existing SoCs, but
it's good enough for now.

Reviewed-by: Andre Przywara 

Thanks,
Andre.

> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v2:
> - Use CONFIG_MACH_SUN50I_H6 rather than DT prefix to judge H6.
> 
>  board/sunxi/mksunxi_fit_atf.sh | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh
> index 36abe9efed..88ad719747 100755
> --- a/board/sunxi/mksunxi_fit_atf.sh
> +++ b/board/sunxi/mksunxi_fit_atf.sh
> @@ -13,6 +13,12 @@ if [ ! -f $BL31 ]; then
>   BL31=/dev/null
>  fi
>  
> +if grep -q "^CONFIG_MACH_SUN50I_H6=y" .config; then
> + BL31_ADDR=0x104000
> +else
> + BL31_ADDR=0x44000
> +fi
> +
>  cat << __HEADER_EOF
>  /dts-v1/;
>  
> @@ -35,8 +41,8 @@ cat << __HEADER_EOF
>   type = "firmware";
>   arch = "arm64";
>   compression = "none";
> - load = <0x44000>;
> - entry = <0x44000>;
> + load = <$BL31_ADDR>;
> + entry = <$BL31_ADDR>;
>   };
>  __HEADER_EOF
>  
> 
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Re: [U-Boot] [PATCH v2 03/13] sunxi: change RMR64's RVBAR address for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:22PM +0800, Icenowy Zheng wrote:
> Allwinner H6 has a different RVBAR address with A64/H5.
> 
> Add conditional RVBAR configuration into the code which does RMR switch.
> 
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Andre Przywara 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 04/13] sunxi: change ATF position for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:23PM +0800, Icenowy Zheng wrote:
> H6 has different SRAM A2 address, so the ATF load address is also
> different.
> 
> Add judgment code to sunxi 64-bit FIT generation script. It will judge
> the SoC by the device tree's name.
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 05/13] sunxi: add config for SPL at 0x20000 on H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:24PM +0800, Icenowy Zheng wrote:
> On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address) is
> at 0x2, which is different with any old Allwinner SoCs.
> 
> Add SPL position and size configuration for this.
> 
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Andre Przywara 
> ---
> Changes in v2:
> - Added Andre's Reviewed-by tag.
> 
>  include/configs/sunxi-common.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 1b5daa8928..4db770d69d 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -199,6 +199,11 @@
>  #else
>  #define LOW_LEVEL_SRAM_STACK 0x00018000
>  #endif /* !CONFIG_ARM64 */
> +#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x2
> +#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */
> +#define CONFIG_SPL_MAX_SIZE  0x7fa0  /* 32 KiB */
> +/* end of SRAM A2 on H6 for now */
> +#define LOW_LEVEL_SRAM_STACK 0x00118000

Can't we move those options to Kconfig, and deal with those changes
there instead?

Maxime

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Re: [U-Boot] [PATCH v2 06/13] sunxi: change GIC address on H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:25PM +0800, Icenowy Zheng wrote:
> As the Allwinner H6 chip has a new memory map, its GIC MMIO address is
> thus different.
> 
> Change the address on H6.
> 
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Andre Przywara 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 07/13] sunxi: add clock code for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:26PM +0800, Icenowy Zheng wrote:
> The new Allwinner H6 SoC has a brand new CCU layout.
> 
> Add clock code for it.
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 08/13] sunxi: use sun6i-style watchdog for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:27PM +0800, Icenowy Zheng wrote:
> The H6 SoC has a sun6i-style watchdog in its timer part.
> 
> Enable the usage of it.
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 09/13] sunxi: add UART0 setup for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:28PM +0800, Icenowy Zheng wrote:
> The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
> muxed with SD card).
> 
> Add pinmux configuration.
> 
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Andre Przywara 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [RFC PATCH] gpio: zynq: Setup bank_name to dev->name

[Michal Simek]

On 23.7.2018 20:29, Stefan Herbrechtsmeier wrote:
> Hi Michal,
> 
> 
> Am 23.07.2018 um 11:08 schrieb Michal Simek:
>> On 20.7.2018 21:31, Stefan Herbrechtsmeier wrote:
>>> Am 12.07.2018 um 16:04 schrieb Michal Simek:
 There should be proper bank name setup to distiguish between different
 gpio drivers. Use dev->name for it.

 Signed-off-by: Michal Simek 
 ---

    drivers/gpio/zynq_gpio.c | 2 ++
    1 file changed, 2 insertions(+)

 diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
 index 26f69b1a713f..f793ee5754a8 100644
 --- a/drivers/gpio/zynq_gpio.c
 +++ b/drivers/gpio/zynq_gpio.c
 @@ -337,6 +337,8 @@ static int zynq_gpio_probe(struct udevice *dev)
    struct zynq_gpio_privdata *priv = dev_get_priv(dev);
    struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
    +    uc_priv->bank_name = dev->name;
 +
    if (priv->p_data)
    uc_priv->gpio_count = priv->p_data->ngpio;
    
>>> Does this not lead to ugly names because the gpio number is append to
>>> the bank_name? Have you check the "gpio status -a" output?
>> Yes I was checking it. Names are composed together but also just numbers
>> works as before.
>>
>> gpio@ff0a0: input: 0 [ ]
>> gpio@ff0a1: input: 0 [ ]
>> gpio@ff0a2: input: 0 [ ]
>> gpio@ff0a3: input: 0 [ ]
>> gpio@ff0a4: input: 0 [ ]
>> gpio@ff0a5: input: 0 [ ]
>> gpio@ff0a6: input: 0 [ ]
>> gpio@ff0a7: input: 0 [ ]
>> gpio@ff0a8: input: 0 [ ]
>> gpio@ff0a9: input: 0 [ ]
> 
> Do you think that this are meaningful names? It isn't possible to
> separate the device and pin number as well as it mix hex and decimal
> numbers.
> 
>> If you know better way how to setup a bank name please let me know but I
>> need to distinguish ps gpio from pl one and for pl we need to know the
>> address.
> 
> I know the use case.
> 
> A lot of drivers use the bank_name from the device tree, some drivers
> append an underscore to the bank name and others add the req_seq of the
> device to an alphabetic character.
> 
>>> Other drivers use the gpio-bank-name from the device tree.
>> I can't see this property inside Linux kernel. If this has been reviewed
>> by dt guys please let me know.
> 
> This property is only used by u-boot. I think it isn't needed by the
> Linux kernel.

I am happy to use consistent solution but what's that?
Mixing name with hex and int is not nice but adding "_" or something
else is just a pain in driver code. If this is done in core I am fine
with that but adding this code to all drivers don't look like generic
solution at all.
Using additional u-boot property is not good too.

I have mentioned in "gpio: xilinx: Convert driver to DM"
(sha1:10441ec9224d0d269dc512819a32c0785a6338d3)
that uc-priv->name is completely unused. Maybe this should be dev->name
and bank_name should be really used for banks.
Then in gpio status -a can be

Device gpio@a0001000:
Bank:
...

but not sure how gpio commands will work to address exact pin from
prompt. Because this is normally working
gpio toggle gpio@a00010001

Thanks,
Michal

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Re: [U-Boot] [PATCH V3 1/2] mmc: add HS400 support

[Faiz Abbas]

Hi,

On Saturday 19 May 2018 06:24 PM, Peng Fan wrote:
> Add HS400 support.
> Selecting HS400 needs first select HS199 according to spec, so use
> a dedicated function for HS400.
> Add HS400 related macros.
> Remove the restriction of only using the low 6 bits of
> EXT_CSD_CARD_TYPE, using all the 8 bits.
> 
> Signed-off-by: Peng Fan 
> Cc: Jaehoon Chung 
> Cc: Jean-Jacques Hiblot 
> Cc: Stefano Babic 
> Cc: Simon Glass 
> Cc: Kishon Vijay Abraham I 
> Cc: Bin Meng 
> ---
> 
> V3:
>  Simplify code
>  add error msg
> 
> V2:
>  remove 4bits support from HS400, as HS400 does not support 4bits per spec.
> 
>  drivers/mmc/Kconfig |   7 +++
>  drivers/mmc/mmc.c   | 137 
> +---
>  include/mmc.h   |  11 +
>  3 files changed, 128 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 3f15f85efd..a535a87a8e 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT
> cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
> frequency can go up to 208MHz (SDR104)
>  
> +config MMC_HS400_SUPPORT
> + bool "enable HS400 support"
> + select MMC_HS200_SUPPORT
> + help
> +   The HS400 mode is support by some eMMC. The bus frequency is up to
> +   200MHz. This mode requires tuning the IO.
> +

Please add SPL_MMC_HS400_SUPPORT also.

Thanks,
Faiz
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Re: [U-Boot] [PATCH v2 05/13] sunxi: add config for SPL at 0x20000 on H6

[Icenowy Zheng]

于 2018年7月24日 GMT+08:00 下午4:34:52, Maxime Ripard  写到:
>On Sat, Jul 21, 2018 at 04:20:24PM +0800, Icenowy Zheng wrote:
>> On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address)
>is
>> at 0x2, which is different with any old Allwinner SoCs.
>> 
>> Add SPL position and size configuration for this.
>> 
>> Signed-off-by: Icenowy Zheng 
>> Reviewed-by: Andre Przywara 
>> ---
>> Changes in v2:
>> - Added Andre's Reviewed-by tag.
>> 
>>  include/configs/sunxi-common.h | 5 +
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/include/configs/sunxi-common.h
>b/include/configs/sunxi-common.h
>> index 1b5daa8928..4db770d69d 100644
>> --- a/include/configs/sunxi-common.h
>> +++ b/include/configs/sunxi-common.h
>> @@ -199,6 +199,11 @@
>>  #else
>>  #define LOW_LEVEL_SRAM_STACK0x00018000
>>  #endif /* !CONFIG_ARM64 */
>> +#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x2
>> +#define CONFIG_SPL_TEXT_BASE0x20060 /* sram 
>> start+header */
>> +#define CONFIG_SPL_MAX_SIZE 0x7fa0  /* 32 KiB */
>> +/* end of SRAM A2 on H6 for now */
>> +#define LOW_LEVEL_SRAM_STACK0x00118000
>
>Can't we move those options to Kconfig, and deal with those changes
>there instead?

It's possible, but not any cleaner.

It will still be a hugh set of default xxx if xxx.

>
>Maxime
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Re: [U-Boot] [PATCH v2 10/13] sunxi: add MMC support for H6

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:29PM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
> the MMC2 come with the capability to do crypto by EMCE.
> 
> Add MMC support for H6. EMCE support is not added yet.
> 
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/include/asm/arch-sunxi/mmc.h |  2 +-
>  board/sunxi/board.c   |  7 +++
>  drivers/mmc/sunxi_mmc.c   | 13 -
>  3 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h 
> b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 1574b8e8fe..d98c53faaa 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -45,7 +45,7 @@ struct sunxi_mmc {
>   u32 chda;   /* 0x90 */
>   u32 cbda;   /* 0x94 */
>   u32 res2[26];
> -#ifdef CONFIG_SUNXI_GEN_SUN6I
> +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
>   u32 res3[64];
>  #endif
>   u32 fifo;   /* 0x100 / 0x200 FIFO access address */
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 5ed1b8bae1..857d5ff010 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -443,6 +443,13 @@ static void mmc_pinmux_setup(int sdc)
>   sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
>   sunxi_gpio_set_drv(pin, 2);
>   }
> +#elif defined(CONFIG_MACH_SUN50I_H6)
> + /* SDC2: PC4-PC14 */
> + for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
> + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> + sunxi_gpio_set_drv(pin, 2);
> + }
>  #elif defined(CONFIG_MACH_SUN9I)
>   /* SDC2: PC6-PC16 */
>   for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 7fa1ae8b16..39f15eb423 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
>   priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
>   priv->mclkreg = &ccm->sd2_clk_cfg;
>   break;
> +#ifdef SUNXI_MMC3_BASE
>   case 3:
>   priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
>   priv->mclkreg = &ccm->sd3_clk_cfg;
>   break;
> +#endif
>   default:
>   printf("Wrong mmc number %d\n", sdc_no);
>   return -1;
> @@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, 
> unsigned int hz)
>  #ifdef CONFIG_MACH_SUN9I
>   pll = CCM_MMC_CTRL_PLL_PERIPH0;
>   pll_hz = clock_get_pll4_periph0();
> +#elif defined(CONFIG_MACH_SUN50I_H6)
> + pll = CCM_MMC_CTRL_PLL6X2;
> + pll_hz = clock_get_pll6() * 2;
>  #else
>   pll = CCM_MMC_CTRL_PLL6;
>   pll_hz = clock_get_pll6();
> @@ -494,7 +499,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>  
>   cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
>   cfg->host_caps = MMC_MODE_4BIT;
> -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || 
> defined(CONFIG_MACH_SUN50I_H6)
>   if (sdc_no == 2)
>   cfg->host_caps = MMC_MODE_8BIT;
>  #endif
> @@ -509,6 +514,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>  
>   /* config ahb clock */
>   debug("init mmc %d clock and io\n", sdc_no);
> +#if !defined(CONFIG_MACH_SUN50I_H6)
>   setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
>  
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
> @@ -519,6 +525,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>   /* sun9i has a mmc-common module, also set the gate and reset there */
>   writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
>  SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
> +#endif
> +#else /* CONFIG_MACH_SUN50I_H6 */
> + setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
> + /* unassert reset */
> + setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
>  #endif
>   ret = mmc_set_mod_clk(priv, 2400);
>   if (ret)

You should use the DM instead.

Maxime

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Re: [U-Boot] [linux-sunxi] Re: [PATCH v2 10/13] sunxi: add MMC support for H6

[Icenowy Zheng]

于 2018年7月24日 GMT+08:00 下午4:37:43, Maxime Ripard  写到:
>On Sat, Jul 21, 2018 at 04:20:29PM +0800, Icenowy Zheng wrote:
>> The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
>> the MMC2 come with the capability to do crypto by EMCE.
>> 
>> Add MMC support for H6. EMCE support is not added yet.
>> 
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  arch/arm/include/asm/arch-sunxi/mmc.h |  2 +-
>>  board/sunxi/board.c   |  7 +++
>>  drivers/mmc/sunxi_mmc.c   | 13 -
>>  3 files changed, 20 insertions(+), 2 deletions(-)
>> 
>> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
>b/arch/arm/include/asm/arch-sunxi/mmc.h
>> index 1574b8e8fe..d98c53faaa 100644
>> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
>> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
>> @@ -45,7 +45,7 @@ struct sunxi_mmc {
>>  u32 chda;   /* 0x90 */
>>  u32 cbda;   /* 0x94 */
>>  u32 res2[26];
>> -#ifdef CONFIG_SUNXI_GEN_SUN6I
>> +#if defined(CONFIG_SUNXI_GEN_SUN6I) ||
>defined(CONFIG_MACH_SUN50I_H6)
>>  u32 res3[64];
>>  #endif
>>  u32 fifo;   /* 0x100 / 0x200 FIFO access address */
>> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
>> index 5ed1b8bae1..857d5ff010 100644
>> --- a/board/sunxi/board.c
>> +++ b/board/sunxi/board.c
>> @@ -443,6 +443,13 @@ static void mmc_pinmux_setup(int sdc)
>>  sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
>>  sunxi_gpio_set_drv(pin, 2);
>>  }
>> +#elif defined(CONFIG_MACH_SUN50I_H6)
>> +/* SDC2: PC4-PC14 */
>> +for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
>> +sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
>> +sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
>> +sunxi_gpio_set_drv(pin, 2);
>> +}
>>  #elif defined(CONFIG_MACH_SUN9I)
>>  /* SDC2: PC6-PC16 */
>>  for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
>> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>> index 7fa1ae8b16..39f15eb423 100644
>> --- a/drivers/mmc/sunxi_mmc.c
>> +++ b/drivers/mmc/sunxi_mmc.c
>> @@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
>>  priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
>>  priv->mclkreg = &ccm->sd2_clk_cfg;
>>  break;
>> +#ifdef SUNXI_MMC3_BASE
>>  case 3:
>>  priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
>>  priv->mclkreg = &ccm->sd3_clk_cfg;
>>  break;
>> +#endif
>>  default:
>>  printf("Wrong mmc number %d\n", sdc_no);
>>  return -1;
>> @@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
>*priv, unsigned int hz)
>>  #ifdef CONFIG_MACH_SUN9I
>>  pll = CCM_MMC_CTRL_PLL_PERIPH0;
>>  pll_hz = clock_get_pll4_periph0();
>> +#elif defined(CONFIG_MACH_SUN50I_H6)
>> +pll = CCM_MMC_CTRL_PLL6X2;
>> +pll_hz = clock_get_pll6() * 2;
>>  #else
>>  pll = CCM_MMC_CTRL_PLL6;
>>  pll_hz = clock_get_pll6();
>> @@ -494,7 +499,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>>  
>>  cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
>>  cfg->host_caps = MMC_MODE_4BIT;
>> -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
>> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) ||
>defined(CONFIG_MACH_SUN50I_H6)
>>  if (sdc_no == 2)
>>  cfg->host_caps = MMC_MODE_8BIT;
>>  #endif
>> @@ -509,6 +514,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>>  
>>  /* config ahb clock */
>>  debug("init mmc %d clock and io\n", sdc_no);
>> +#if !defined(CONFIG_MACH_SUN50I_H6)
>>  setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
>>  
>>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>> @@ -519,6 +525,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>>  /* sun9i has a mmc-common module, also set the gate and reset there
>*/
>>  writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
>> SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
>> +#endif
>> +#else /* CONFIG_MACH_SUN50I_H6 */
>> +setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
>> +/* unassert reset */
>> +setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
>>  #endif
>>  ret = mmc_set_mod_clk(priv, 2400);
>>  if (ret)
>
>You should use the DM instead.

Then we still need the DM-less ver for SPL.

>
>Maxime
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Re: [U-Boot] [PATCH v2 12/13] sunxi: add support for Allwinner H6 SoC

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:31PM +0800, Icenowy Zheng wrote:
> Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
> interfaces.
> 
> This patch adds support for it.
> 
> The corresponding DTSI file, from Linux next-20180720, is also
> introduced.
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

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Re: [U-Boot] [PATCH v2.1 11/13] sunxi: add DRAM support to H6

[Maxime Ripard]

On Mon, Jul 23, 2018 at 06:13:34AM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
> Both the controller and the PHY seem to be originate from DesignWare,
> and are similar to the ones in ZynqMP SoCs.
> 
> This commit introduces an initial DRAM driver for H6, which contains
> only LPDDR3 support. The currently known SBCs with H6 all come with
> LPDDR3 memory, including Pine H64 and several Orange Pi's.
> 
> The BSP DRAM initialization code is closed source and violates GPL. Code
> in this commit is written by experimenting, referring the code/document
> of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
> reference) and disassebling the BSP blob.
> 
> Thanks for Jernej Skrabec for review and fix some issues in this driver
> (including the most critical one which made it to work), and rewrite
> some code from register dump!
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH v2 13/13] sunxi: add support for Pine H64 board

[Maxime Ripard]

On Sat, Jul 21, 2018 at 04:20:32PM +0800, Icenowy Zheng wrote:
> Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features
> 1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port
> and a mPCIE slot.
> 
> Add support for it.
> 
> The device tree is from Linux next-20180720.
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH V3 1/2] mmc: add HS400 support

[Peng Fan]

Hi Faiz,

It's 2 months since this patchset out (:
> 
> On Saturday 19 May 2018 06:24 PM, Peng Fan wrote:
> > Add HS400 support.
> > Selecting HS400 needs first select HS199 according to spec, so use a
> > dedicated function for HS400.
> > Add HS400 related macros.
> > Remove the restriction of only using the low 6 bits of
> > EXT_CSD_CARD_TYPE, using all the 8 bits.
> >
> > Signed-off-by: Peng Fan 
> > Cc: Jaehoon Chung 
> > Cc: Jean-Jacques Hiblot 
> > Cc: Stefano Babic 
> > Cc: Simon Glass 
> > Cc: Kishon Vijay Abraham I 
> > Cc: Bin Meng 
> > ---
> >
> > V3:
> >  Simplify code
> >  add error msg
> >
> > V2:
> >  remove 4bits support from HS400, as HS400 does not support 4bits per spec.
> >
> >  drivers/mmc/Kconfig |   7 +++
> >  drivers/mmc/mmc.c   | 137
> +---
> >  include/mmc.h   |  11 +
> >  3 files changed, 128 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> > 3f15f85efd..a535a87a8e 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT
> >   cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
> >   frequency can go up to 208MHz (SDR104)
> >
> > +config MMC_HS400_SUPPORT
> > +   bool "enable HS400 support"
> > +   select MMC_HS200_SUPPORT
> > +   help
> > + The HS400 mode is support by some eMMC. The bus frequency is up to
> > + 200MHz. This mode requires tuning the IO.
> > +
> 
> Please add SPL_MMC_HS400_SUPPORT also.

What issue do you see? I did not test SPL MMC with HS400 support.  You mean 
only add a Kconfig
entry SPL_MMC_HS400_SUPPORT?

Regards,
Peng.

> 
> Thanks,
> Faiz
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Re: [U-Boot] [UBOOT PATCH] gpio: zynq: Used platdata structure for storing static data instead of priv

[Michal Simek]

On 24.7.2018 01:48, Simon Glass wrote:
> On 20 July 2018 at 03:06, Vipul Kumar  wrote:
>> This patch used platdata structure instead of priv for storing static
>> information read from DT.
>>
>> Signed-off-by: Vipul Kumar 
>> ---
>>  drivers/gpio/zynq_gpio.c | 67 
>> 
>>  1 file changed, 34 insertions(+), 33 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 

Applied.
M
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Re: [U-Boot] [PATCH] sunxi: enable SATA on Banana Pi M2 Berry

[Maxime Ripard]

On Tue, Jul 24, 2018 at 12:22:19AM +0200, Simon Baatz wrote:
> Banana Pi M2 Ultra and M2 Berry are very similar boards.  SATA can be
> enabled exactly the same as for M2 Ultra introduced in
> commit daa8b75a5527 ("sunxi: enable SATA on Banana Pi M2 Ultra").
> 
> Signed-off-by: Simon Baatz 

Acked-by: Maxime Ripard 

Thanks!
Maxime

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Re: [U-Boot] [PATCH V3 1/2] mmc: add HS400 support

[Faiz Abbas]

Hi Peng,

On Tuesday 24 July 2018 02:14 PM, Peng Fan wrote:
> Hi Faiz,
> 
> It's 2 months since this patchset out (:

Has it already been accepted?

> drivers/mmc/Kconfig
>>
>> On Saturday 19 May 2018 06:24 PM, Peng Fan wrote:
>>> Add HS400 support.
>>> Selecting HS400 needs first select HS199 according to spec, so use a
>>> dedicated function for HS400.
>>> Add HS400 related macros.
>>> Remove the restriction of only using the low 6 bits of
>>> EXT_CSD_CARD_TYPE, using all the 8 bits.
>>>
>>> Signed-off-by: Peng Fan 
>>> Cc: Jaehoon Chung 
>>> Cc: Jean-Jacques Hiblot 
>>> Cc: Stefano Babic 
>>> Cc: Simon Glass 
>>> Cc: Kishon Vijay Abraham I 
>>> Cc: Bin Meng 
>>> ---
>>>
>>> V3:
>>>  Simplify code
>>>  add error msg
>>>
>>> V2:
>>>  remove 4bits support from HS400, as HS400 does not support 4bits per spec.
>>>
>>>  drivers/mmc/Kconfig |   7 +++
>>>  drivers/mmc/mmc.c   | 137
>> +---
>>>  include/mmc.h   |  11 +
>>>  3 files changed, 128 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
>>> 3f15f85efd..a535a87a8e 100644
>>> --- a/drivers/mmc/Kconfig
>>> +++ b/drivers/mmc/Kconfig
>>> @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT
>>>   cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
>>>   frequency can go up to 208MHz (SDR104)
>>>
>>> +config MMC_HS400_SUPPORT
>>> +   bool "enable HS400 support"
>>> +   select MMC_HS200_SUPPORT
>>> +   help
>>> + The HS400 mode is support by some eMMC. The bus frequency is up to
>>> + 200MHz. This mode requires tuning the IO.
>>> +
>>
>> Please add SPL_MMC_HS400_SUPPORT also.
> 
> What issue do you see? I did not test SPL MMC with HS400 support.  You mean 
> only add a Kconfig
> entry SPL_MMC_HS400_SUPPORT?

Yes only a Kconfig. It helps people who want to include/exclude it from
SPL. You are implicitly checking for the config in
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) below.

I was just using your patch for some out of tree development and figured
it would be useful to have the CONFIG.

Thanks,
Faiz
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Re: [U-Boot] [UBOOT PATCH v2] net: zynq_gem: convert to use livetree

[Michal Simek]

Hi,

On 23.7.2018 07:48, Siva Durga Prasad Paladugu wrote:
> Hi Joe/Michal,
> 
> Can you please take it up if it is fine.

joe: Can you please take it via your tree?
There are some patches before this.

Thanks,
Michal
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[U-Boot] [PATCH v3 0/5] dm: led: remove auto probe in binding function

[Patrick Delaunay]

Hi,

The commit bc882f5d5c7b4d6ed5e927bf838863af43c786e7
introduce auto probe of LED in binding function
but that cause issue on my board.

This first patch of this patchset activateis the LED on my board
to explain the issue, the second patch revert this commit and
the third one propose an other solution.

For me, this commit is a error because in README of doc/driver-model/
it is indicated:

  The device's bind() method is permitted to perform simple actions, but
  should not scan the device tree node, not initialise hardware, nor set up
  structures or allocate memory. All of these tasks should be left for
  the probe() method.

And in the patch the LED driver is probed during the binding scan.

When I activated the LED in my ARM target with the patch
"stm32mp1: add gpio led support", I have the sequence:

dm_init_and_scan() :

1/ dm_scan_fdt_node()
=> loop on all the node

2/ scan for LED node
=> probe of LED driver is forced by "default-state" detection
LED1 - "red"
=> probe of father of "red" node
A - led
B - soc
C - root
=> probe of node needed by GPIO
1 - pin-controller
2 - gpio@50002000
3 - rcc-clk@5000
4 - rcc@5000

=> probe forced by default state for other led
LED2 - green
LED3 - orange

=> probe of node needed by GPIO (other bank)
5 - gpio@50009000

3/ dm_extended_scan_fdt scan continue...
   scan node "fixed-clock" under "/clocks"
clk-hse
clk-hsi
clk-lse
clk-lsi
clk-csi

4/ probe of all the used devices after dm_extended_scan_fdt()

So many driver are probed before the end of the scan binding loop !

And that cause issue in my board (boot failed) because the rcc-clk clock
driver found the input frequency with these fixed-clock, which are binded
only after the stm32mp1 clock driver probe.

For me probe in forbidden in binding function and
thus uclass_get_device_tail() is not allowed in the commit
bc882f5d5c7b4d6ed5e927bf838863af43c786e7 which need to be reverted.

In the third patch I proposed an other solution based
on the existing solution in u-class regulator used to enable
regulator with "boot on" property (see regulators_enable_boot_on function).

I think that adding a function is the  better solution in the driver model
to force probe for some node according binding information
(after dm_init_and_scan call).

This new function should be called in board_init function for each board
but it could be also added in init_sequence_r[] in future.


Changes in v3:
- add motivation in revert commit
- minor update after Simon review
- include led.h to avoid compilation warning on stm32mp1 board

Changes in v2:
  - add sandbox impact and test update

Patrick Delaunay (5):
  stm32mp1: add gpio led support
  Revert "dm: led: auto probe() LEDs with "default-state""
  dm: led: move default state support in led uclass
  stm32mp1: use new function led default state
  sandbox: led: use new function to configure default state

 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 24 ++
 board/sandbox/sandbox.c  |  9 ++
 board/st/stm32mp1/stm32mp1.c |  4 +++
 common/board_r.c |  3 +-
 configs/stm32mp15_basic_defconfig|  2 ++
 drivers/led/led-uclass.c | 54 
 drivers/led/led_gpio.c   | 17 --
 include/led.h| 23 ++
 test/dm/led.c|  3 ++
 9 files changed, 121 insertions(+), 18 deletions(-)

-- 
2.7.4

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Re: [U-Boot] [PATCH V3 1/2] mmc: add HS400 support

[Peng Fan]

> 
> On Tuesday 24 July 2018 02:14 PM, Peng Fan wrote:
> > Hi Faiz,
> >
> > It's 2 months since this patchset out (:
> 
> Has it already been accepted?

No. I did not receive response from Jaehoon.

> 
> > drivers/mmc/Kconfig
> >>
> >> On Saturday 19 May 2018 06:24 PM, Peng Fan wrote:
> >>> Add HS400 support.
> >>> Selecting HS400 needs first select HS199 according to spec, so use a
> >>> dedicated function for HS400.
> >>> Add HS400 related macros.
> >>> Remove the restriction of only using the low 6 bits of
> >>> EXT_CSD_CARD_TYPE, using all the 8 bits.
> >>>
> >>> Signed-off-by: Peng Fan 
> >>> Cc: Jaehoon Chung 
> >>> Cc: Jean-Jacques Hiblot 
> >>> Cc: Stefano Babic 
> >>> Cc: Simon Glass 
> >>> Cc: Kishon Vijay Abraham I 
> >>> Cc: Bin Meng 
> >>> ---
> >>>
> >>> V3:
> >>>  Simplify code
> >>>  add error msg
> >>>
> >>> V2:
> >>>  remove 4bits support from HS400, as HS400 does not support 4bits per
> spec.
> >>>
> >>>  drivers/mmc/Kconfig |   7 +++
> >>>  drivers/mmc/mmc.c   | 137
> >> +---
> >>>  include/mmc.h   |  11 +
> >>>  3 files changed, 128 insertions(+), 27 deletions(-)
> >>>
> >>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> >>> 3f15f85efd..a535a87a8e 100644
> >>> --- a/drivers/mmc/Kconfig
> >>> +++ b/drivers/mmc/Kconfig
> >>> @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT
> >>> cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
> >>> frequency can go up to 208MHz (SDR104)
> >>>
> >>> +config MMC_HS400_SUPPORT
> >>> + bool "enable HS400 support"
> >>> + select MMC_HS200_SUPPORT
> >>> + help
> >>> +   The HS400 mode is support by some eMMC. The bus frequency is up
> to
> >>> +   200MHz. This mode requires tuning the IO.
> >>> +
> >>
> >> Please add SPL_MMC_HS400_SUPPORT also.
> >
> > What issue do you see? I did not test SPL MMC with HS400 support.  You
> > mean only add a Kconfig entry SPL_MMC_HS400_SUPPORT?
> 
> Yes only a Kconfig. It helps people who want to include/exclude it from SPL. 
> You
> are implicitly checking for the config in
> CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) below.
> 
> I was just using your patch for some out of tree development and figured it
> would be useful to have the CONFIG.

Ok. I'll add it and post out V4 patchset.

Thanks,
Peng

> 
> Thanks,
> Faiz
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[U-Boot] [PATCH v2 1/6] configs: stm32f429-evaluation: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v2: None

 configs/stm32f429-evaluation_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f429-evaluation_defconfig 
b/configs/stm32f429-evaluation_defconfig
index 1b14a4964067..3ddd5c50fb1d 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD_NOR_FLASH=y
-- 
1.9.1

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[U-Boot] [PATCH v2 0/6] Add support of CONFIG_BLK for STM32Fx platforms

[Patrice Chotard]

This series :
  _ adds support of CONFIG_BLK flag to STM32Fx platforms
  _ enables CONFIG_BLK flag for STM32Fx based boards
  _ adds missing clk_free() call in error path
  _ adds read of "cd_inverted" DT property

Changes in v2:
 - replace devfdt_get_addr() by dev_read_addr()
 - re-introduce arm_pl180_mmc_ofdata_to_platdata()

Patrice Chotard (6):
  configs: stm32f429-evaluation: Enable CONFIG_BLK
  configs: stm32f746-disco: Enable CONFIG_BLK
  configs: stm32f469-disco: Enable CONFIG_BLK
  mmc: arm_pl180_mmci: Update to support CONFIG_BLK
  mmc: arm_pl180_mmci: Add missing clk_free
  mmc: arm_pl180_mmci: Add "cd_inverted" DT property read

 configs/stm32f429-evaluation_defconfig |  1 -
 configs/stm32f469-discovery_defconfig  |  1 -
 configs/stm32f746-disco_defconfig  |  1 -
 drivers/mmc/arm_pl180_mmci.c   | 69 +-
 4 files changed, 42 insertions(+), 30 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v2 2/6] configs: stm32f746-disco: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v2: None

 configs/stm32f746-disco_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f746-disco_defconfig 
b/configs/stm32f746-disco_defconfig
index aa7403f3c516..6f07ff155862 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -40,7 +40,6 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 # CONFIG_SPL_DM_MMC is not set
 CONFIG_ARM_PL180_MMCI=y
-- 
1.9.1

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[U-Boot] [PATCH v2 5/6] mmc: arm_pl180_mmci: Add missing clk_free

[Patrice Chotard]

Add missing clk_free() call in case of failure
when enabling the clock.

Signed-off-by: Patrice Chotard 
---

Changes in v2: None

 drivers/mmc/arm_pl180_mmci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index c4d94d102cc1..1cd780b3eec0 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -430,6 +430,7 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
 
ret = clk_enable(&clk);
if (ret) {
+   clk_free(&clk);
dev_err(dev, "failed to enable clock\n");
return ret;
}
-- 
1.9.1

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[U-Boot] [PATCH v2 4/6] mmc: arm_pl180_mmci: Update to support CONFIG_BLK

[Patrice Chotard]

Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci
to support this config.

This driver is used by STM32Fx and by Vexpress platforms.
Only STM32Fx are DM ready. No DM code is isolated and will be
removed easily when wexpress will be converted to DM.

Signed-off-by: Patrice Chotard 
---

Changes in v2:
 - replace devfdt_get_addr() by dev_read_addr()
 - re-introduce arm_pl180_mmc_ofdata_to_platdata()

 drivers/mmc/arm_pl180_mmci.c | 67 ++--
 1 file changed, 40 insertions(+), 27 deletions(-)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index e267cd782e8b..c4d94d102cc1 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -357,13 +357,13 @@ static const struct mmc_ops arm_pl180_mmci_ops = {
.set_ios = host_set_ios,
.init = mmc_host_reset,
 };
-#endif
 
 /*
  * mmc_host_init - initialize the mmc controller.
  * Set initial clock and power for mmc slot.
  * Initialize mmc struct and register with mmc framework.
  */
+
 int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
 {
u32 sdi_u32;
@@ -377,9 +377,8 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct 
mmc **mmc)
writel(sdi_u32, &host->base->mask0);
 
host->cfg.name = host->name;
-#ifndef CONFIG_DM_MMC
host->cfg.ops = &arm_pl180_mmci_ops;
-#endif
+
/* TODO remove the duplicates */
host->cfg.host_caps = host->caps;
host->cfg.voltages = host->voltages;
@@ -393,20 +392,34 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, 
struct mmc **mmc)
*mmc = mmc_create(&host->cfg, host);
if (!*mmc)
return -1;
-
debug("registered mmc interface number is:%d\n",
  (*mmc)->block_dev.devnum);
 
return 0;
 }
+#endif
 
 #ifdef CONFIG_DM_MMC
+static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
+{
+   u32 sdi_u32;
+
+   writel(host->pwr_init, &host->base->power);
+   writel(host->clkdiv_init, &host->base->clock);
+   udelay(CLK_CHANGE_DELAY);
+
+   /* Disable mmc interrupts */
+   sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
+   writel(sdi_u32, &host->base->mask0);
+}
+
 static int arm_pl180_mmc_probe(struct udevice *dev)
 {
struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
-   struct pl180_mmc_host *host = mmc->priv;
+   struct pl180_mmc_host *host = dev->priv;
+   struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
int ret;
@@ -421,27 +434,28 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
return ret;
}
 
-   strcpy(host->name, "MMC");
host->pwr_init = INIT_PWR;
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
SDI_CLKCR_HWFC_EN;
-   host->voltages = VOLTAGE_WINDOW_SD;
-   host->caps = 0;
host->clock_in = clk_get_rate(&clk);
-   host->clock_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
-   host->clock_max = dev_read_u32_default(dev, "max-frequency",
-  MMC_CLOCK_MAX);
host->version2 = dev_get_driver_data(dev);
 
+   cfg->name = dev->name;
+   cfg->voltages = VOLTAGE_WINDOW_SD;
+   cfg->host_caps = 0;
+   cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+   cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
+   cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
 
bus_width = dev_read_u32_default(dev, "bus-width", 1);
switch (bus_width) {
case 8:
-   host->caps |= MMC_MODE_8BIT;
+   cfg->host_caps |= MMC_MODE_8BIT;
/* Hosts capable of 8-bit transfers can also do 4 bits */
case 4:
-   host->caps |= MMC_MODE_4BIT;
+   cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
@@ -449,19 +463,21 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
dev_err(dev, "Invalid bus-width value %u\n", bus_width);
}
 
-   ret = arm_pl180_mmci_init(host, &mmc);
-   if (ret) {
-   dev_err(dev, "arm_pl180_mmci init failed\n");
-   return ret;
-   }
-
+   arm_pl180_mmc_init(host);
+   mmc->priv = host;
mmc->dev = dev;
-   dev->priv = host;
upriv->mmc = mmc;
 
return 0;
 }
 
+int arm_pl180_mmc_bind(struct udevice *dev)
+{
+   struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
+
+   return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
 static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
   struct mmc_data *data)
 {
@@ -479,

[U-Boot] [PATCH v2 3/6] configs: stm32f469-disco: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v2: None

 configs/stm32f469-discovery_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f469-discovery_defconfig 
b/configs/stm32f469-discovery_defconfig
index 4de03edcc2ca..a55476f2f323 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD_NOR_FLASH=y
-- 
1.9.1

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[U-Boot] [PATCH v2 6/6] mmc: arm_pl180_mmci: Add "cd_inverted" DT property read

[Patrice Chotard]

Add missing read of "cd_inverted" property in DT.

Signed-off-by: Patrice Chotard 
---

Changes in v2: None

 drivers/mmc/arm_pl180_mmci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index 1cd780b3eec0..75d1a367ceb6 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -440,6 +440,7 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
SDI_CLKCR_HWFC_EN;
host->clock_in = clk_get_rate(&clk);
host->version2 = dev_get_driver_data(dev);
+   host->cd_inverted = dev_read_bool(dev, "cd-inverted");
 
cfg->name = dev->name;
cfg->voltages = VOLTAGE_WINDOW_SD;
-- 
1.9.1

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[U-Boot] [PATCH v3 2/5] Revert "dm: led: auto probe() LEDs with "default-state""

[Patrick Delaunay]

This reverts commit bc882f5d5c7b4d6ed5e927bf838863af43c786e7.
because this patch adds the probe of LED driver during the
binding phasis. It is not allowed in driver model because
the drivers (clock, pincontrol) needed by the LED driver can
be also probed before the binding of all the device and
it is a source of problems.

Signed-off-by: Patrick Delaunay 
---

Changes in v3:
- add motivation in revert commit

Changes in v2: None

 drivers/led/led_gpio.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index a36942b..533587d 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -10,7 +10,6 @@
 #include 
 #include 
 #include 
-#include 
 
 struct led_gpio_priv {
struct gpio_desc gpio;
@@ -118,14 +117,6 @@ static int led_gpio_bind(struct udevice *parent)
return ret;
uc_plat = dev_get_uclass_platdata(dev);
uc_plat->label = label;
-
-   if (ofnode_read_bool(node, "default-state")) {
-   struct udevice *devp;
-
-   ret = uclass_get_device_tail(dev, 0, &devp);
-   if (ret)
-   return ret;
-   }
}
 
return 0;
-- 
2.7.4

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[U-Boot] [PATCH v3 3/5] dm: led: move default state support in led uclass

[Patrick Delaunay]

This patch save common LED property "default-state" value
in post bind of LED uclass.
The configuration for this default state is only performed when
led_default_state() is called;
It can be called in your board_init()
or it could added in init_sequence_r[] in future.

Reviewed-by: Simon Glass 
Signed-off-by: Patrick Delaunay 
---

Changes in v3: None
Changes in v2: None

 drivers/led/led-uclass.c | 54 
 drivers/led/led_gpio.c   |  8 ---
 include/led.h| 23 +
 3 files changed, 77 insertions(+), 8 deletions(-)

diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 2f4d69e..141401d 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -63,8 +64,61 @@ int led_set_period(struct udevice *dev, int period_ms)
 }
 #endif
 
+static int led_post_bind(struct udevice *dev)
+{
+   struct led_uc_plat *uc_pdata;
+   const char *default_state;
+
+   uc_pdata = dev_get_uclass_platdata(dev);
+
+   /* common optional properties */
+   uc_pdata->default_state = LED_DEF_NO;
+   default_state = dev_read_string(dev, "default-state");
+   if (default_state) {
+   if (!strncmp(default_state, "on", 2))
+   uc_pdata->default_state = LED_DEF_ON;
+   else if (!strncmp(default_state, "off", 3))
+   uc_pdata->default_state = LED_DEF_OFF;
+   else if (!strncmp(default_state, "keep", 4))
+   uc_pdata->default_state = LED_DEF_KEEP;
+   }
+
+   return 0;
+}
+
+int led_default_state(void)
+{
+   struct udevice *dev;
+   struct uclass *uc;
+   struct led_uc_plat *uc_pdata;
+   int ret;
+
+   ret = uclass_get(UCLASS_LED, &uc);
+   if (ret)
+   return ret;
+   for (uclass_find_first_device(UCLASS_LED, &dev);
+dev;
+uclass_find_next_device(&dev)) {
+   uc_pdata = dev_get_uclass_platdata(dev);
+   if (!uc_pdata || uc_pdata->default_state == LED_DEF_NO)
+   continue;
+   ret = device_probe(dev);
+   if (ret)
+   return ret;
+   if (uc_pdata->default_state == LED_DEF_ON)
+   led_set_state(dev, LEDST_ON);
+   else if (uc_pdata->default_state == LED_DEF_OFF)
+   led_set_state(dev, LEDST_OFF);
+   printf("%s: default_state=%d\n",
+  uc_pdata->label, uc_pdata->default_state);
+   }
+
+   return ret;
+}
+
 UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name   = "led",
+   .post_bind  = led_post_bind,
.per_device_platdata_auto_alloc_size = sizeof(struct led_uc_plat),
 };
diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index 533587d..93f6b91 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -57,7 +57,6 @@ static int led_gpio_probe(struct udevice *dev)
 {
struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
struct led_gpio_priv *priv = dev_get_priv(dev);
-   const char *default_state;
int ret;
 
/* Ignore the top-level LED node */
@@ -68,13 +67,6 @@ static int led_gpio_probe(struct udevice *dev)
if (ret)
return ret;
 
-   default_state = dev_read_string(dev, "default-state");
-   if (default_state) {
-   if (!strncmp(default_state, "on", 2))
-   gpio_led_set_state(dev, LEDST_ON);
-   else if (!strncmp(default_state, "off", 3))
-   gpio_led_set_state(dev, LEDST_OFF);
-   }
return 0;
 }
 
diff --git a/include/led.h b/include/led.h
index 940b97f..ff45f03 100644
--- a/include/led.h
+++ b/include/led.h
@@ -8,12 +8,27 @@
 #define __LED_H
 
 /**
+ * enum led_default_state - The initial state of the LED.
+ * see Documentation/devicetree/bindings/leds/common.txt
+ */
+enum led_def_state_t {
+   LED_DEF_NO,
+   LED_DEF_ON,
+   LED_DEF_OFF,
+   LED_DEF_KEEP
+};
+
+/**
  * struct led_uc_plat - Platform data the uclass stores about each device
  *
  * @label: LED label
+ * @default_state* - The initial state of the LED.
+  see Documentation/devicetree/bindings/leds/common.txt
+ * * - set automatically on device bind by the uclass's '.post_bind' method.
  */
 struct led_uc_plat {
const char *label;
+   enum led_def_state_t default_state;
 };
 
 /**
@@ -106,4 +121,12 @@ enum led_state_t led_get_state(struct udevice *dev);
  */
 int led_set_period(struct udevice *dev, int period_ms);
 
+/**
+ * led_default_state() - set the default state for all the LED
+ *
+ * This enables all leds which have default state.
+ *
+ */
+int led_default_state(void);
+
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v3 4/5] stm32mp1: use new function led default state

[Patrick Delaunay]

Initialize the led with the default state defined in device tree.

Reviewed-by: Simon Glass 

Signed-off-by: Patrick Delaunay 
---

Changes in v3:
- minor update after Simon review
- include led.h to avoid compilation warning on stm32mp1 board

Changes in v2: None

 board/st/stm32mp1/stm32mp1.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index cc39fa6..bfc8ab6 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -4,6 +4,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 
 /*
@@ -22,5 +23,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
 
+   if (IS_ENABLED(CONFIG_LED))
+   led_default_state();
+
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v3 1/5] stm32mp1: add gpio led support

[Patrick Delaunay]

This patch add the 4 LED available on the ED1 board and activated
gpio led driver.

Reviewed-by: Simon Glass 
Signed-off-by: Patrick Delaunay 
---

Changes in v3: None
Changes in v2: None

 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 24 
 configs/stm32mp15_basic_defconfig|  2 ++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi 
b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 39a0ebc..4898483 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -13,6 +13,30 @@
mmc1 = &sdmmc2;
i2c3 = &i2c4;
};
+
+   led {
+   compatible = "gpio-leds";
+
+   red {
+   label = "stm32mp:red:status";
+   gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+   default-state = "off";
+   };
+   green {
+   label = "stm32mp:green:user";
+   gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+   default-state = "on";
+   };
+   orange {
+   label = "stm32mp:orange:status";
+   gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+   blue {
+   label = "stm32mp:blue:user";
+   gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+   };
+   };
 };
 
 &uart4_pins_a {
diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index c72a440..2cac114 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -29,6 +29,8 @@ CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_STM32_SDMMC2=y
 # CONFIG_PINCTRL_FULL is not set
-- 
2.7.4

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[U-Boot] [PATCH v3 5/5] sandbox: led: use new function to configure default state

[Patrick Delaunay]

Initialize the led with the default state defined in device tree
in board_init and solve issue with test for led default state.

Reviewed-by: Simon Glass 


Signed-off-by: Patrick Delaunay 
---
Led default-state is correctly handle in Sandbox, tested with:
  ./u-boot -d ./arch/sandbox/dts/test.dtb
  => led list
  sandbox:red 
  sandbox:green   
  sandbox:default_on on
  sandbox:default_off off

This patch solve "make tests" issue introduced by
http://patchwork.ozlabs.org/patch/943651/

Changes in v3: None
Changes in v2:
  - add sandbox impact and test update

 board/sandbox/sandbox.c | 9 +
 common/board_r.c| 3 ++-
 test/dm/led.c   | 3 +++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 195f620..66b5f24 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -47,6 +48,14 @@ int dram_init(void)
return 0;
 }
 
+int board_init(void)
+{
+#ifdef CONFIG_LED
+   led_default_state();
+#endif /* CONFIG_LED */
+   return 0;
+}
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/common/board_r.c b/common/board_r.c
index 64f2574..9402c0e 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -690,7 +690,8 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_DM
initr_dm,
 #endif
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV)
+#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
+   defined(CONFIG_SANDBOX)
board_init, /* Setup chipselects */
 #endif
/*
diff --git a/test/dm/led.c b/test/dm/led.c
index 0071f21..00de7b3 100644
--- a/test/dm/led.c
+++ b/test/dm/led.c
@@ -32,6 +32,9 @@ static int dm_test_led_default_state(struct unit_test_state 
*uts)
 {
struct udevice *dev;
 
+   /* configure the default state (auto-probe) */
+   led_default_state();
+
/* Check that we handle the default-state property correctly. */
ut_assertok(led_get_by_label("sandbox:default_on", &dev));
ut_asserteq(LEDST_ON, led_get_state(dev));
-- 
2.7.4

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Re: [U-Boot] [PATCH 3/4] gpio: xilinx: Not read output values via regs

[Michal Simek]

On 23.7.2018 20:42, Stefan Herbrechtsmeier wrote:
> Hi Michal,
> 
> Am 23.07.2018 um 13:43 schrieb Michal Simek:
>> Reading registers for finding out output value is not working because
>> input value is read instead in case of tristate.
>>
>> Reported-by: Stefan Herbrechtsmeier 
>> Signed-off-by: Michal Simek 
>> ---
>>
>>   drivers/gpio/xilinx_gpio.c | 38 +-
>>   1 file changed, 33 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
>> index 4da9ae114d87..9d3e9379d0e5 100644
>> --- a/drivers/gpio/xilinx_gpio.c
>> +++ b/drivers/gpio/xilinx_gpio.c
>> @@ -358,6 +358,11 @@ struct xilinx_gpio_platdata {
>>   int bank_max[XILINX_GPIO_MAX_BANK];
>>   int bank_input[XILINX_GPIO_MAX_BANK];
>>   int bank_output[XILINX_GPIO_MAX_BANK];
>> +    u32 dout_default[XILINX_GPIO_MAX_BANK];
>> +};
>> +
>> +struct xilinx_gpio_privdata {
>> +    u32 output_val[XILINX_GPIO_MAX_BANK];
>>   };
>>     static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
>> @@ -387,6 +392,7 @@ static int xilinx_gpio_set_value(struct udevice
>> *dev, unsigned offset,
>>    int value)
>>   {
>>   struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
>> +    struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
>>   int val, ret;
>>   u32 bank, pin;
>>   @@ -394,19 +400,21 @@ static int xilinx_gpio_set_value(struct
>> udevice *dev, unsigned offset,
>>   if (ret)
>>   return ret;
>>   -    debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
>> -  __func__, (ulong)platdata->regs, value, offset, bank, pin);
>> +    val = priv->output_val[bank];
>> +
>> +    debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out
>> %x\n",
>> +  __func__, (ulong)platdata->regs, value, offset, bank, pin,
>> val);
>>     if (value) {
>> -    val = readl(&platdata->regs->gpiodata + bank * 2);
>>   val = val | (1 << pin);
>>   writel(val, &platdata->regs->gpiodata + bank * 2);
>>   } else {
>> -    val = readl(&platdata->regs->gpiodata + bank * 2);
>>   val = val & ~(1 << pin);
>>   writel(val, &platdata->regs->gpiodata + bank * 2);
>>   }
> 
> You could replace the two writel function calls by one.
> 

Will update this in v2.

>>   +    priv->output_val[bank] = val;
>> +
>>   return val;
>>   };
>>   @@ -441,6 +449,7 @@ static int xilinx_gpio_get_function(struct
>> udevice *dev, unsigned offset)
>>   static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
>>   {
>>   struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
>> +    struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
>>   int val, ret;
>>   u32 bank, pin;
>>   @@ -451,7 +460,14 @@ static int xilinx_gpio_get_value(struct udevice
>> *dev, unsigned offset)
>>   debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
>>     (ulong)platdata->regs, offset, bank, pin);
>>   -    val = readl(&platdata->regs->gpiodata + bank * 2);
>> +    if (xilinx_gpio_get_function(dev, offset) == GPIOF_INPUT) {
>> +    debug("%s: Read input value from reg\n", __func__);
>> +    val = readl(&platdata->regs->gpiodata + bank * 2);
>> +    } else {
>> +    debug("%s: Read saved output value\n", __func__);
>> +    val = priv->output_val[bank];
>> +    }
> 
> Why you don't always read the data register? This doesn't work for three
> state outputs.

In three state register every bit/pin is 0 - output, 1 input.
It means else part is output and I read saved value in priv->output_val.
If pin is setup as INPUT then I need read data reg to find out input value.
Maybe you are commenting something else but please let me know if there
is any other bug.

Thanks,
Michal
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[U-Boot] [PATCH] arm64: zynqmp: Enable soft gpio driver for zcu102 and zcu100

[Michal Simek]

Enable soft gpio driver for zcu102 and zcu100.

Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_zcu100_revC_defconfig   | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig   | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig   | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig 
b/configs/xilinx_zynqmp_zcu100_revC_defconfig
index 2e9a1108fb6a..9f84f5e8a176 100644
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -49,6 +49,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C1=y
 CONFIG_LED=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1dfbf71c7931..0ca141b740a6 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -61,6 +61,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 09ae9e872101..abc8cf5d180a 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -60,6 +60,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 907cd105919e..09e6f798c579 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -60,6 +60,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
-- 
1.9.1

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[U-Boot] [PATCH] mailmap: Fix broken email from fit_image.c

[Michal Simek]

The patch
"tools/mkimage: Fix DTC run command to handle file names with space"
(sha1: a6e9810495bc929b6beafb88f557cdaadf87fc83) contains comma in name
which is confusing patman. Fix it by defining Mirza's email in mailmap.

Signed-off-by: Michal Simek 
---

 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index bd7267241a8e..d29703058dbe 100644
--- a/.mailmap
+++ b/.mailmap
@@ -34,3 +34,4 @@ Wolfgang Denk 
 York Sun 
 York Sun 
 Łukasz Majewski 
+Mirza 
-- 
1.9.1

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Re: [U-Boot] ext4: massive corruption with ext4write

[Aaron Williams]

On Monday, July 23, 2018 11:25:41 PM PDT Aaron Williams wrote:
> External Email
> 
> On Monday, July 23, 2018 11:15:59 PM PDT Aaron Williams wrote:
> 
> > External Email
> >
> >
> >
> > Hi all,
> >
> >
> >
> > It looks like after a certain amount of data has been written that all
> > hell
 breaks loose with the ext4 filesystem.
> >
> >
> >
> > In my case, I have the following files on a 64G USB thumb drive with two
> > partitions, a small FAT partition with the rest of the space dedicated to
> > ext4
> 
>  created using mkfs.ext4 /dev/sdg2
> 
> >
> >
> > total 477632
> > -rwxr-xr-x 1 root root 152777216 Jul 23 18:11 Image
> > drwx-- 2 root root 16384 Jul 23 18:10 lost+found
> > -rwxr-xr-x 1 root root  90706976 Dec 31  1969 test.64
> > -rwxr-xr-x 1 root root 152777216 Dec 31  1969 test.img
> > -rwxr-xr-x 1 root root50 Dec 31  1969 test.txt
> > -rwxr-xr-x 1 root root   1841408 Jul 23 18:12 u-boot-octeon_ebb7304.bin
> > -rwxr-xr-x 1 root root  90706976 Jul 23 18:11 vmlinux.64
> >
> >
> >
> > Everything is fine until I wrote the file test.64, which is basically a
> > copy
> 
>  of vmlinux.64.
> 
> >
> >
> > The first few files were written using my host Linux system, namely
> > Image,
> > u-
> 
>  boot-octeon_ebb7304.bin and vmlinux.64.
> 
> >
> >
> > From within U-Boot I performed the following commands:
> >
> >
> >
> > # ext4load usb 0:2 $loadaddr Image
> > # ext4write usb 0:2 $fileaddr /test.img $filesize
> > # tftpboot $loadaddr test.txt
> > # ext4write usb 0:2 $fileaddr /test.txt $filesize
> > # ext4load usb 0:2 $loadaddr vmlinux.64
> > # ext4write usb 0:2 $fileaddr /test.64 $filesize
> >
> >
> >
> > Everything is fine on the drive until I write test.64. At this point, I
> > get
 a
> 
>  huge list of errors:
> 
> >
> >
> > # fsck.ext4 -v -n /dev/sdg2
> > e2fsck 1.42.11 (09-Jul-2014)
> > Group descriptor 0 has invalid unused inodes count 57374.  Fix? no
> >
> >
> >
> > /dev/sdg2 contains a file system with errors, check forced.
> > Pass 1: Checking inodes, blocks, and sizes
> > Deleted inode 130913 has zero dtime.  Fix? no
> >
> >
> >
> > Inode 130915 is in use, but has dtime set.  Fix? no
> >
> >
> >
> > Inode 130915 has imagic flag set.  Clear? no
> >
> >
> >
> > Inode 130915 has a extra size (8223) which is invalid
> > Fix? no
> >
> >
> >
> > Inode 130916 is in use, but has dtime set.  Fix? no
> >
> >
> >
> > Inode 130916 has imagic flag set.  Clear? no
> >
> >
> >
> > Inode 130916 has a extra size (8223) which is invalid
> > Fix? no
> >
> >
> >
> > ...
> > Illegal block #11 (2435760161) in inode 131070.  IGNORED.
> > Illegal indirect block (4026556192) in inode 131070.  IGNORED.
> > Illegal double indirect block (2433138721) in inode 131070.  IGNORED.
> > Illegal triple indirect block (2434195456) in inode 131070.  IGNORED.
> > Error while iterating over blocks in inode 131070: Illegal triply
> > indirect
> > block found
> >
> >
> >
> >
> > and many many more errors.
> >
> >
> >
> > Note that I am using the very latest ext4 code from the master branch.
> > This
> 
>  is not a USB problem because I can reproduce this problem with an SD
> 
> > card. This problem also occurs on two different platforms, one being
> > aarch64 little endian and the other being MIPS64 big endian.  The
> > filesystem code is identical since the latest code has been backported to
> > our older MIPS bootloader.
> >
> >
> >
> > My guess is that all hell is breaking loose when a file spans multiple
> > block
> 
>  groups.
> 
> >
> >
> > -Aaron Williams
> >
> >
> >
> > On Thursday, July 19, 2018 7:35:46 PM PDT Aaron Williams wrote:
> >
> >
> >
> > >
> > >
> > >
> > > Hi all,
> > >
> > >
> > >
> > >
> > >
> > > I am sometimes seeing issues when using ext4write where fsck later
> > > complains
> >
> >
> >
> >  that the group descriptor has an invalid number of unused
> >
> >
> >
> > > inodes. Is this a known problem?
> > >
> > >
> > >
> > >
> > >
> > > Also, I think the assert(offset == sizeof(*desc)); in
> > > ext4fs_checksum_update()
> >
> >
> >
> >  is invalid since with ext4 the descriptor is
> >
> >
> >
> > > larger than the offset. When debugging was enabled I'd always hit this
> > > assert.
> > >
> > >
> > >
> > >
> > >
> > > Also, in ext4fs_write, the debug statement should say blocks and not
> > > bytes.
> >
> >
> >
> > >
> > >
> > >
> > > -Aaron
> > >
> > >
> > >
> > >
> > >
> > > --
> > > Aaron Williams
> > > Senior Software Engineer
> > > Cavium, Inc.
> > > (408) 943-7198  (510) 789-8988 (cell)
> > > ___
> > > U-Boot mailing list
> > > U-Boot@lists.denx.de
> > > https://lists.denx.de/listinfo/u-boot
> >
> >
> >
> >
> > --
> > Aaron Williams
> > Senior Software Engineer
> > Cavium, Inc.
> > (408) 943-7198  (510) 789-8988 (cell)
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
> 
> 
> Here is the output after the write operation from fsck.ext4 -v /dev/sdg2
> 
> fsck.ext4 -

Re: [U-Boot] [PATCH v2 6/6] mmc: arm_pl180_mmci: Add "cd_inverted" DT property read

[Tuomas Tynkkynen]

Hi Patrice,


On 07/24/2018 12:39 PM, Patrice Chotard wrote:

Add missing read of "cd_inverted" property in DT.



If your platform uses GPIOs for card detection, it's
simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH)
in the gpio flags instead of using the cd-inverted
property. See Linux commit 45e01f401a2a16a8d7 where this
was done for sunxi). Then this commit isn't needed.

- Tuomas
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Re: [U-Boot] [PATCH v2 6/6] mmc: arm_pl180_mmci: Add "cd_inverted" DT property read

[Patrice CHOTARD]

Hi Tuomas

On 07/24/2018 01:22 PM, Tuomas Tynkkynen wrote:
> Hi Patrice,
> 
> 
> On 07/24/2018 12:39 PM, Patrice Chotard wrote:
>> Add missing read of "cd_inverted" property in DT.
>>
> 
> If your platform uses GPIOs for card detection, it's
> simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH)
> in the gpio flags instead of using the cd-inverted
> property. See Linux commit 45e01f401a2a16a8d7 where this
> was done for sunxi). Then this commit isn't needed.

Thanks for pointing this ;-)
I will submit a v3

Patrice

> 
> - Tuomas
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[U-Boot] [PATCH v3 0/6] Add support of CONFIG_BLK for STM32Fx platforms

[Patrice Chotard]

This series :
  - adds support of CONFIG_BLK flag to STM32Fx platforms
  - enables CONFIG_BLK flag for STM32Fx based boards
  - adds missing clk_free() call in error path


Changes in v3:
  - remove usage of "cd_inverted" DT property in dm_mmc_getcd()

Changes in v2:
 - replace devfdt_get_addr() by dev_read_addr()
 - re-introduce arm_pl180_mmc_ofdata_to_platdata()

Patrice Chotard (6):
  configs: stm32f429-evaluation: Enable CONFIG_BLK
  configs: stm32f746-disco: Enable CONFIG_BLK
  configs: stm32f469-disco: Enable CONFIG_BLK
  mmc: arm_pl180_mmci: Update to support CONFIG_BLK
  mmc: arm_pl180_mmci: Add missing clk_free
  mmc: arm_pl180_mmci: Remove cd_inverted host's struct field

 configs/stm32f429-evaluation_defconfig |  1 -
 configs/stm32f469-discovery_defconfig  |  1 -
 configs/stm32f746-disco_defconfig  |  1 -
 drivers/mmc/arm_pl180_mmci.c   | 73 +++---
 drivers/mmc/arm_pl180_mmci.h   |  1 -
 5 files changed, 42 insertions(+), 35 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v3 2/6] configs: stm32f746-disco: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v3: None
Changes in v2: None

 configs/stm32f746-disco_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f746-disco_defconfig 
b/configs/stm32f746-disco_defconfig
index aa7403f3c516..6f07ff155862 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -40,7 +40,6 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 # CONFIG_SPL_DM_MMC is not set
 CONFIG_ARM_PL180_MMCI=y
-- 
1.9.1

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[U-Boot] [PATCH v3 1/6] configs: stm32f429-evaluation: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v3: None
Changes in v2: None

 configs/stm32f429-evaluation_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f429-evaluation_defconfig 
b/configs/stm32f429-evaluation_defconfig
index 1b14a4964067..3ddd5c50fb1d 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD_NOR_FLASH=y
-- 
1.9.1

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[U-Boot] [PATCH v3 4/6] mmc: arm_pl180_mmci: Update to support CONFIG_BLK

[Patrice Chotard]

Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci
to support this config.

This driver is used by STM32Fx and by Vexpress platforms.
Only STM32Fx are DM ready. No DM code is isolated and will be
removed easily when wexpress will be converted to DM.

Signed-off-by: Patrice Chotard 
---

Changes in v3: None
Changes in v2:
 - replace devfdt_get_addr() by dev_read_addr()
 - re-introduce arm_pl180_mmc_ofdata_to_platdata()

 drivers/mmc/arm_pl180_mmci.c | 67 ++--
 1 file changed, 40 insertions(+), 27 deletions(-)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index e267cd782e8b..c4d94d102cc1 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -357,13 +357,13 @@ static const struct mmc_ops arm_pl180_mmci_ops = {
.set_ios = host_set_ios,
.init = mmc_host_reset,
 };
-#endif
 
 /*
  * mmc_host_init - initialize the mmc controller.
  * Set initial clock and power for mmc slot.
  * Initialize mmc struct and register with mmc framework.
  */
+
 int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
 {
u32 sdi_u32;
@@ -377,9 +377,8 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct 
mmc **mmc)
writel(sdi_u32, &host->base->mask0);
 
host->cfg.name = host->name;
-#ifndef CONFIG_DM_MMC
host->cfg.ops = &arm_pl180_mmci_ops;
-#endif
+
/* TODO remove the duplicates */
host->cfg.host_caps = host->caps;
host->cfg.voltages = host->voltages;
@@ -393,20 +392,34 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host, 
struct mmc **mmc)
*mmc = mmc_create(&host->cfg, host);
if (!*mmc)
return -1;
-
debug("registered mmc interface number is:%d\n",
  (*mmc)->block_dev.devnum);
 
return 0;
 }
+#endif
 
 #ifdef CONFIG_DM_MMC
+static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
+{
+   u32 sdi_u32;
+
+   writel(host->pwr_init, &host->base->power);
+   writel(host->clkdiv_init, &host->base->clock);
+   udelay(CLK_CHANGE_DELAY);
+
+   /* Disable mmc interrupts */
+   sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
+   writel(sdi_u32, &host->base->mask0);
+}
+
 static int arm_pl180_mmc_probe(struct udevice *dev)
 {
struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
-   struct pl180_mmc_host *host = mmc->priv;
+   struct pl180_mmc_host *host = dev->priv;
+   struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
int ret;
@@ -421,27 +434,28 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
return ret;
}
 
-   strcpy(host->name, "MMC");
host->pwr_init = INIT_PWR;
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
SDI_CLKCR_HWFC_EN;
-   host->voltages = VOLTAGE_WINDOW_SD;
-   host->caps = 0;
host->clock_in = clk_get_rate(&clk);
-   host->clock_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
-   host->clock_max = dev_read_u32_default(dev, "max-frequency",
-  MMC_CLOCK_MAX);
host->version2 = dev_get_driver_data(dev);
 
+   cfg->name = dev->name;
+   cfg->voltages = VOLTAGE_WINDOW_SD;
+   cfg->host_caps = 0;
+   cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+   cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
+   cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
 
bus_width = dev_read_u32_default(dev, "bus-width", 1);
switch (bus_width) {
case 8:
-   host->caps |= MMC_MODE_8BIT;
+   cfg->host_caps |= MMC_MODE_8BIT;
/* Hosts capable of 8-bit transfers can also do 4 bits */
case 4:
-   host->caps |= MMC_MODE_4BIT;
+   cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
@@ -449,19 +463,21 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
dev_err(dev, "Invalid bus-width value %u\n", bus_width);
}
 
-   ret = arm_pl180_mmci_init(host, &mmc);
-   if (ret) {
-   dev_err(dev, "arm_pl180_mmci init failed\n");
-   return ret;
-   }
-
+   arm_pl180_mmc_init(host);
+   mmc->priv = host;
mmc->dev = dev;
-   dev->priv = host;
upriv->mmc = mmc;
 
return 0;
 }
 
+int arm_pl180_mmc_bind(struct udevice *dev)
+{
+   struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
+
+   return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
 static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
   struct mmc_dat

[U-Boot] [PATCH v3 5/6] mmc: arm_pl180_mmci: Add missing clk_free

[Patrice Chotard]

Add missing clk_free() call in case of failure
when enabling the clock.

Signed-off-by: Patrice Chotard 
---

Changes in v3: None
Changes in v2: None

 drivers/mmc/arm_pl180_mmci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index c4d94d102cc1..1cd780b3eec0 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -430,6 +430,7 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
 
ret = clk_enable(&clk);
if (ret) {
+   clk_free(&clk);
dev_err(dev, "failed to enable clock\n");
return ret;
}
-- 
1.9.1

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Re: [U-Boot] [U-Boot, v1, 1/2] spi: stm32_qspi: assign functional operation mode in _stm32_qspi_gen_ccr

[Tom Rini]

On Mon, Jul 09, 2018 at 03:32:37PM +0200, Patrice Chotard wrote:

> From: Christophe Kerello 
> 
> This patch assigns the functional operation mode in _stm32_qspi_gen_ccr
> function.
> 
> Signed-off-by: Christophe Kerello 
> Signed-off-by: Patrice Chotard 

Applied to u-boot/master, thanks!

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Re: [U-Boot] m68k: m5253evbe: Remove this board

[Tom Rini]

On Mon, Jul 09, 2018 at 10:44:51AM -0400, Tom Rini wrote:

> The m5253evbe board has been marked as orphan since June of 2014 and
> should have been dropped a while ago.  Do so now.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 2/2] ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4

[Tom Rini]

On Mon, Jul 09, 2018 at 08:18:44PM -0500, Adam Ford wrote:

> There have been some significant changes to the DM37 SOM-LV device
> tree.  This patch re-syncs it with Linux.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts 
> b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
> index 1702b9e3db..2428373952 100644

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH v3 6/6] mmc: arm_pl180_mmci: Remove cd_inverted host's struct field

[Patrice Chotard]

As platform uses GPIOs for card detection, it's
simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH)
in the gpio flags instead of using the cd-inverted
property.


Reported-by: Tuomas Tynkkynen 
Signed-off-by: Patrice Chotard 
---

Changes in v3:
  - remove usage of "cd_inverted" DT property in dm_mmc_getcd()

Changes in v2: None

 drivers/mmc/arm_pl180_mmci.c | 5 +
 drivers/mmc/arm_pl180_mmci.h | 1 -
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index 1cd780b3eec0..f71d79ecd6ba 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -499,11 +499,8 @@ static int dm_mmc_getcd(struct udevice *dev)
struct pl180_mmc_host *host = dev->priv;
int value = 1;
 
-   if (dm_gpio_is_valid(&host->cd_gpio)) {
+   if (dm_gpio_is_valid(&host->cd_gpio))
value = dm_gpio_get_value(&host->cd_gpio);
-   if (host->cd_inverted)
-   return !value;
-   }
 
return value;
 }
diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h
index 6b98db6cd978..36487be288b2 100644
--- a/drivers/mmc/arm_pl180_mmci.h
+++ b/drivers/mmc/arm_pl180_mmci.h
@@ -192,7 +192,6 @@ struct pl180_mmc_host {
struct mmc_config cfg;
 #ifdef CONFIG_DM_MMC
struct gpio_desc cd_gpio;
-   bool cd_inverted;
 #endif
 };
 
-- 
1.9.1

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Re: [U-Boot] [U-Boot, v1, 2/2] spi: stm32_qspi: rework mode management

[Tom Rini]

On Mon, Jul 09, 2018 at 03:32:38PM +0200, Patrice Chotard wrote:

> From: Christophe Kerello 
> 
> This patch solves quad read issue with Macronix/Micron spi nor.
> 
> Signed-off-by: Christophe Kerello 
> Signed-off-by: Patrice Chotard 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH v3 3/6] configs: stm32f469-disco: Enable CONFIG_BLK

[Patrice Chotard]

CONFIG_BLK config flag becomes mandatory, enable it.

Signed-off-by: Patrice Chotard 
---

Changes in v3: None
Changes in v2: None

 configs/stm32f469-discovery_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/stm32f469-discovery_defconfig 
b/configs/stm32f469-discovery_defconfig
index 4de03edcc2ca..a55476f2f323 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
 CONFIG_DM_MMC=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD_NOR_FLASH=y
-- 
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Re: [U-Boot] Convert CONFIG_DA8XX_GPIO to Kconfig

[Tom Rini]

On Tue, Jul 10, 2018 at 07:01:20AM -0500, Adam Ford wrote:

> This converts the following to Kconfig:
>CONFIG_DA8XX_GPIO
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
> index 7908cfcc34..bc704ff7bd 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] mtd: nand: add new enum for storing ECC algorithm

[Tom Rini]

On Tue, Jul 10, 2018 at 11:48:08AM +0200, Philippe Reynes wrote:

> From: Rafał Miłecki 
> 
> Our nand_ecc_modes_t is already a bit abused by value NAND_ECC_SOFT_BCH.
> This enum should store ECC mode only and putting algorithm details there
> is a bad idea. It would result in too many values impossible to support
> in a sane way.
> 
> To solve this problem let's add a new enum. We'll have to modify all
> drivers to set it properly but once it's done it'll be possible to drop
> NAND_ECC_SOFT_BCH. That will result in a cleaner design and more
> possibilities like setting ECC algorithm for hardware ECC mode.
> 
> Signed-off-by: Rafał Miłecki 
> Signed-off-by: Boris Brezillon 
> [Linux commit: b0fcd8ab7b3c89b5da7fff5224d06ed73e7a33cc]
> [Philippe Reynes: adapt code to u-boot]
> Signed-off-by: Philippe Reynes 

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: dts: am3517-evm-uboot: Add reg-shift for UART

[Tom Rini]

On Tue, Jul 10, 2018 at 05:04:38AM -0500, Adam Ford wrote:

> With the resync of the omap3.dtsi file, the reg-shift was removed
> so it breaks the UART.  Adding the reg-shift into the
> am3517-evm-u-boot.dtsi keeps the reg-shift for U-Boot, but keeps
> the dts/dtsi files clean from Linux.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi 
> b/arch/arm/dts/am3517-evm-u-boot.dtsi
> index f049a6452e..59df819f9d 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/2] ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.18-RC4

[Tom Rini]

On Mon, Jul 09, 2018 at 08:18:14PM -0500, Adam Ford wrote:

> There have been some refactoring of the DTS files for the Logic PD
> DM37 Torpedo.  This patch re-sync's the DTS files with Linux
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts 
> b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
> index 43e9364083..234afd6d60 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: dts: Resync OMAP3 and omap36xx with Linux 4.18-RC4

[Tom Rini]

On Mon, Jul 09, 2018 at 08:14:25PM -0500, Adam Ford wrote:

> There have been several minor changes to the OMAP3.dtsi, so this
> patch re-syncs it with Linux.  An addition include/dt-binding was
> also brought with it.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi
> index 56c94729bb..4043ecb380 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] doc: Replace DocBook with sphinx-based docs

[Tom Rini]

On Tue, Jul 10, 2018 at 08:40:17AM +0200, Mario Six wrote:

> The Linux kernel moved to sphinx-based documentation and got rid of the
> DocBook based documentation quite a while ago. Hence, the DocBook
> documentation for U-Boot should be converted as well.
> 
> To achieve this, import the necessary files from Linux v4.17, and
> convert the current DocBook documentation (three files altogether) to
> sphinx/reStructuredText.
> 
> For now, all old DocBook documentation was merged into a single
> handbook, tentatively named "U-Boot Hacker Manual".
> 
> For some source files, the documentation style was changed to comply
> with kernel-doc; no functional changes were applied.
> 
> Signed-off-by: Mario Six 

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: DTS: am3517-evm-u-boot: Mark MMC1 with cd-inverted

[Tom Rini]

On Tue, Jul 10, 2018 at 05:23:37AM -0500, Adam Ford wrote:

> In order to use the device tree for MMC, the card-detect pin
> needs to be inverted.  This patch places this into the
> am3517-evm-u-boot.dtsi file to keep the main DTS and DTSI files
> clean and in-sync with Linux
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi 
> b/arch/arm/dts/am3517-evm-u-boot.dtsi
> index 59df819f9d..c02beaad77 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/1] bios_emulator: remove assignment without effect

[Tom Rini]

On Sun, Mar 18, 2018 at 11:01:23AM +0100, Heinrich Schuchardt wrote:

> Assigning a parameter which is not used afterwards has not effect.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Simon Glass 

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Re: [U-Boot] ARM: DTS: Resync am3517-evm.dts with Linux 4.18-rc4

[Tom Rini]

On Mon, Jul 09, 2018 at 07:52:48PM -0500, Adam Ford wrote:

> Several changes have been made to the AM3517-evm and the underlying
> am3517.dtsi file.  This patch re-sync's the DTS and DTSI files with
> Linux.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
> index 0e4a125f78..98aadb0f81 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: configs: omap3_logic: remove Legacy OMAP3 USB driver

[Tom Rini]

On Fri, Jul 13, 2018 at 03:27:13PM -0500, Adam Ford wrote:

> Only the MUSB driver is currently supported on the omap3_logic
> boards.  The driver is using the new-musb and not the legacy
> version, so this patch removes the dead code references.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
> index cd8ffd5adf..ed9f454a5d 100644

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH] kconfig: Replace spaces with tabs

[Michal Simek]

Trivial Kconfig cleanup. Use tabs instead of spaces.

Signed-off-by: Michal Simek 
---

 Kconfig | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/Kconfig b/Kconfig
index cb953144c9da..db0f545e459b 100644
--- a/Kconfig
+++ b/Kconfig
@@ -144,24 +144,24 @@ config SYS_MALLOC_LEN
  TODO: Use for other architectures
 
 config SPL_SYS_MALLOC_F_LEN
-hex "Size of malloc() pool in SPL before relocation"
-depends on SYS_MALLOC_F
-default SYS_MALLOC_F_LEN
-help
-  Before relocation, memory is very limited on many platforms. Still,
-  we can provide a small malloc() pool if needed. Driver model in
-  particular needs this to operate, so that it can allocate the
-  initial serial device and any others that are needed.
+   hex "Size of malloc() pool in SPL before relocation"
+   depends on SYS_MALLOC_F
+   default SYS_MALLOC_F_LEN
+   help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
 
 config TPL_SYS_MALLOC_F_LEN
-hex "Size of malloc() pool in TPL before relocation"
-depends on SYS_MALLOC_F
-default SYS_MALLOC_F_LEN
-help
-  Before relocation, memory is very limited on many platforms. Still,
-  we can provide a small malloc() pool if needed. Driver model in
-  particular needs this to operate, so that it can allocate the
-  initial serial device and any others that are needed.
+   hex "Size of malloc() pool in TPL before relocation"
+   depends on SYS_MALLOC_F
+   default SYS_MALLOC_F_LEN
+   help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
 
 menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
-- 
1.9.1

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Re: [U-Boot] [PATCH v2] arm: zynq: add support for the zybo z7 board

[Michal Simek]

On 24.7.2018 08:10, Luis Araneda wrote:
> The board is manufactured by Digilent
> Main features:
> - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
> - RAM: 1 GB DDR3L
> - FLASH: 16 MB QSPI
> - 1 Gbps Ethernet
> - USB 2.0
> - microSD slot
> - Pcam camera connector
> - HDMI Tx and Rx
> - Audio codec: stereo out, stereo in, mic
> - 5 (Z7-10) or 6 (Z7-20) Pmod ports
> - 6 push-buttons, 4 switches, 5 LEDs
> - 1 (Z7-10) or 2 (Z7-20) RGB LEDs
> 
> Signed-off-by: Luis Araneda 
> ---
> 
> This patch adds support for the Digilent Zybo Z7 board
> 
> The only thing that I tested and is not working yet, is reading the
> MAC address from the OTP region of the SPI flash memory, but I'm trying
> to find a solution
> 
> Changes from v1:
> - Rebased on u-boot/master
> - Removed comments and indented ps7_init_gpl.c
> - Removed CONFIG_DISPLAY from defconfig
> - Replaced the cadence I2C driver by zynq_i2c
> - Squashed the patches as they are less than 100kB now
> ---
>  arch/arm/dts/Makefile |   3 +-
>  arch/arm/dts/zynq-zybo-z7.dts |  81 ++
>  board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c | 809 ++
>  configs/zynq_zybo_z7_defconfig|  68 ++
>  4 files changed, 960 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/zynq-zybo-z7.dts
>  create mode 100644 board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
>  create mode 100644 configs/zynq_zybo_z7_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 09adf5eab1..07d8729104 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -149,7 +149,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
>   zynq-zc770-xm013.dtb \
>   zynq-zed.dtb \
>   zynq-zturn.dtb \
> - zynq-zybo.dtb
> + zynq-zybo.dtb \
> + zynq-zybo-z7.dtb
>  dtb-$(CONFIG_ARCH_ZYNQMP) += \
>   zynqmp-mini-emmc0.dtb   \
>   zynqmp-mini-emmc1.dtb   \
> diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts
> new file mode 100644
> index 00..3f8a3bfa0f
> --- /dev/null
> +++ b/arch/arm/dts/zynq-zybo-z7.dts
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  Copyright (C) 2011 - 2015 Xilinx
> + *  Copyright (C) 2012 National Instruments Corp.
> + */
> +/dts-v1/;
> +#include "zynq-7000.dtsi"
> +#include 
> +
> +/ {
> + model = "Digilent Zybo Z7 board";
> + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
> +
> + aliases {
> + ethernet0 = &gem0;
> + serial0 = &uart1;
> + spi0 = &qspi;
> + mmc0 = &sdhci0;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x4000>;
> + };
> +
> + chosen {
> + bootargs = "";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> +
> + ld4 {
> + label = "zynq-zybo-z7:green:ld4";
> + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + usb_phy0: phy0 {
> + #phy-cells = <0>;
> + compatible = "usb-nop-xceiv";
> + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&clkc {
> + ps-clk-frequency = <>;
> +};
> +
> +&gem0 {
> + status = "okay";
> + phy-mode = "rgmii-id";
> + phy-handle = <ðernet_phy>;
> +
> + ethernet_phy: ethernet-phy@0 {
> + reg = <0>;
> + device_type = "ethernet-phy";
> + };
> +};
> +
> +&qspi {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&sdhci0 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&uart1 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&usb0 {
> + status = "okay";
> + dr_mode = "host";
> + usb-phy = <&usb_phy0>;
> +};
> diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c 
> b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> new file mode 100644
> index 00..5da4941338
> --- /dev/null
> +++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> @@ -0,0 +1,809 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
> + *
> + * Procedure to generate this file (using Vivado Webpack 2018.2):
> + * + Install board files from digilent/vivado-boards repository
> + *   (commit 6a45981 from 2018-06-05)
> + * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
> + * + Create a block design
> + *   - Add "ZYNQ7 Processing System" IP
> + *   - Run "Block Automation" (Check "Apply Board Preset")
> + *   - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
> + *   - Save diagram changes
> + *   - Go to sources view, select the block diagram,
> + * and select "Generate Output Products"
> + * + Copy the generated "ps7_init_gpl.c" file
> + * + Perform manual editions based on existing Zynq boards
> + *   and the checkpatch.pl script
> + *
> 

Re: [U-Boot] [UBOOT PATCH] Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq

[Michal Simek]

On 20.7.2018 11:41, Vipul Kumar wrote:
> From: Siva Durga Prasad Paladugu 
> 
> This patch moves the the config SYS_MALLOC_LEN to
> Kconfig. It will be just for Zynq arch and to do
> will be for all other archs.
> 
> Signed-off-by: Siva Durga Prasad Paladugu 
> Signed-off-by: Vipul Kumar 
> ---
>  Kconfig | 7 +++
>  arch/arm/mach-zynq/Kconfig  | 3 +++
>  configs/zynq_cse_nand_defconfig | 1 +
>  configs/zynq_cse_nor_defconfig  | 1 +
>  configs/zynq_cse_qspi_defconfig | 1 +
>  include/configs/zynq-common.h   | 2 --
>  include/configs/zynq_cse.h  | 3 ---
>  7 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/Kconfig b/Kconfig
> index c8b86cd..61795e3 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -136,6 +136,13 @@ config SYS_MALLOC_F_LEN
> particular needs this to operate, so that it can allocate the
> initial serial device and any others that are needed.
>  
> +config SYS_MALLOC_LEN
> + hex "Define memory for Dynamic allocation"
> + depends on ARCH_ZYNQ
> + help
> +   This defines memory to be allocated for Dynamic allocation
> +   TODO: Use for other architectures
> +
>  config SPL_SYS_MALLOC_F_LEN
>  hex "Size of malloc() pool in SPL before relocation"
>  depends on SYS_MALLOC_F
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> index 1352359..a599ed6 100644
> --- a/arch/arm/mach-zynq/Kconfig
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -57,6 +57,9 @@ config SYS_CONFIG_NAME
>  config SYS_MALLOC_F_LEN
>   default 0x600
>  
> +config SYS_MALLOC_LEN
> + default 0x140
> +
>  config BOOT_INIT_FILE
>   string "boot.bin init register filename"
>   default ""
> diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
> index eb7e574..d228f9a 100644
> --- a/configs/zynq_cse_nand_defconfig
> +++ b/configs/zynq_cse_nand_defconfig
> @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x10
>  CONFIG_ENV_SIZE=0x190
>  CONFIG_SPL=y
>  CONFIG_SPL_STACK_R_ADDR=0x20
> +CONFIG_SYS_MALLOC_LEN=0x1000
>  CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_SPL_STACK_R=y
> diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
> index 95b31a0..3052c5b 100644
> --- a/configs/zynq_cse_nor_defconfig
> +++ b/configs/zynq_cse_nor_defconfig
> @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0xFFFC
>  CONFIG_ENV_SIZE=0x190
>  CONFIG_SPL=y
>  CONFIG_SPL_STACK_R_ADDR=0x20
> +CONFIG_SYS_MALLOC_LEN=0x1000
>  CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
>  CONFIG_BOOTDELAY=-1
>  # CONFIG_DISPLAY_CPUINFO is not set
> diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
> index c094a5e..2410806 100644
> --- a/configs/zynq_cse_qspi_defconfig
> +++ b/configs/zynq_cse_qspi_defconfig
> @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART_BASE=0x0
>  CONFIG_DEBUG_UART_CLOCK=0
>  CONFIG_SPL_STACK_R_ADDR=0x20
>  # CONFIG_ZYNQ_DDRC_INIT is not set
> +CONFIG_SYS_MALLOC_LEN=0x1000
>  # CONFIG_CMD_ZYNQ is not set
>  CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
>  CONFIG_DEBUG_UART=y
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index c41dc2c..3c2987b 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -236,8 +236,6 @@
>  #define CONFIG_SYS_MEMTEST_START 0
>  #define CONFIG_SYS_MEMTEST_END   0x1000
>  
> -#define CONFIG_SYS_MALLOC_LEN0x140
> -
>  #define CONFIG_SYS_INIT_RAM_ADDR 0x
>  #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
>  #define CONFIG_SYS_INIT_SP_ADDR  (CONFIG_SYS_INIT_RAM_ADDR + \
> diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
> index 36fbe0e..c4587a1 100644
> --- a/include/configs/zynq_cse.h
> +++ b/include/configs/zynq_cse.h
> @@ -36,7 +36,4 @@
>  #define CONFIG_SPL_BSS_START_ADDR0x2
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x8000
>  
> -#undef CONFIG_SYS_MALLOC_LEN
> -#define CONFIG_SYS_MALLOC_LEN0x1000
> -
>  #endif /* __CONFIG_ZYNQ_CSE_H */
> 

Applied.
M
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Re: [U-Boot] ext4: massive corruption with ext4write

[Marek Vasut]

On 07/24/2018 08:25 AM, Aaron Williams wrote:
> On Monday, July 23, 2018 11:15:59 PM PDT Aaron Williams wrote:
>> External Email
>>
>> Hi all,
>>
>> It looks like after a certain amount of data has been written that all hell
>> breaks loose with the ext4 filesystem.
>>
>> In my case, I have the following files on a 64G USB thumb drive with two
>> partitions, a small FAT partition with the rest of the space dedicated to
>> ext4
>  created using mkfs.ext4 /dev/sdg2
>>
>> total 477632
>> -rwxr-xr-x 1 root root 152777216 Jul 23 18:11 Image
>> drwx-- 2 root root 16384 Jul 23 18:10 lost+found
>> -rwxr-xr-x 1 root root  90706976 Dec 31  1969 test.64
>> -rwxr-xr-x 1 root root 152777216 Dec 31  1969 test.img
>> -rwxr-xr-x 1 root root50 Dec 31  1969 test.txt
>> -rwxr-xr-x 1 root root   1841408 Jul 23 18:12 u-boot-octeon_ebb7304.bin
>> -rwxr-xr-x 1 root root  90706976 Jul 23 18:11 vmlinux.64
>>
>> Everything is fine until I wrote the file test.64, which is basically a
>> copy
>  of vmlinux.64.
>>
>> The first few files were written using my host Linux system, namely Image,
>> u-
>  boot-octeon_ebb7304.bin and vmlinux.64.
>>
>> From within U-Boot I performed the following commands:
>>
>> # ext4load usb 0:2 $loadaddr Image
>> # ext4write usb 0:2 $fileaddr /test.img $filesize
>> # tftpboot $loadaddr test.txt
>> # ext4write usb 0:2 $fileaddr /test.txt $filesize
>> # ext4load usb 0:2 $loadaddr vmlinux.64
>> # ext4write usb 0:2 $fileaddr /test.64 $filesize
>>
>> Everything is fine on the drive until I write test.64. At this point, I get
>> a
>  huge list of errors:
>>
>> # fsck.ext4 -v -n /dev/sdg2
>> e2fsck 1.42.11 (09-Jul-2014)
>> Group descriptor 0 has invalid unused inodes count 57374.  Fix? no
>>
>> /dev/sdg2 contains a file system with errors, check forced.
>> Pass 1: Checking inodes, blocks, and sizes
>> Deleted inode 130913 has zero dtime.  Fix? no
>>
>> Inode 130915 is in use, but has dtime set.  Fix? no
>>
>> Inode 130915 has imagic flag set.  Clear? no
>>
>> Inode 130915 has a extra size (8223) which is invalid
>> Fix? no
>>
>> Inode 130916 is in use, but has dtime set.  Fix? no
>>
>> Inode 130916 has imagic flag set.  Clear? no
>>
>> Inode 130916 has a extra size (8223) which is invalid
>> Fix? no
>>
>> ...
>> Illegal block #11 (2435760161) in inode 131070.  IGNORED.
>> Illegal indirect block (4026556192) in inode 131070.  IGNORED.
>> Illegal double indirect block (2433138721) in inode 131070.  IGNORED.
>> Illegal triple indirect block (2434195456) in inode 131070.  IGNORED.
>> Error while iterating over blocks in inode 131070: Illegal triply indirect
>> block found
>>
>>
>> and many many more errors.
>>
>> Note that I am using the very latest ext4 code from the master branch. 
>> This
>  is not a USB problem because I can reproduce this problem with an SD
>> card. This problem also occurs on two different platforms, one being
>> aarch64 little endian and the other being MIPS64 big endian.  The
>> filesystem code is identical since the latest code has been backported to
>> our older MIPS bootloader.
>>
>> My guess is that all hell is breaking loose when a file spans multiple
>> block
>  groups.
>>
>> -Aaron Williams
>>
>> On Thursday, July 19, 2018 7:35:46 PM PDT Aaron Williams wrote:
>>
>>>
>>>
>>> Hi all,
>>>
>>>
>>>
>>> I am sometimes seeing issues when using ext4write where fsck later
>>> complains
>>
>>  that the group descriptor has an invalid number of unused
>>
>>> inodes. Is this a known problem?
>>>
>>>
>>>
>>> Also, I think the assert(offset == sizeof(*desc)); in
>>> ext4fs_checksum_update()
>>
>>  is invalid since with ext4 the descriptor is
>>
>>> larger than the offset. When debugging was enabled I'd always hit this
>>> assert.
>>>
>>>
>>>
>>> Also, in ext4fs_write, the debug statement should say blocks and not
>>> bytes.
>>
>>>
>>>
>>> -Aaron
>>>
>>>
>>>
>>> --
>>> Aaron Williams
>>> Senior Software Engineer
>>> Cavium, Inc.
>>> (408) 943-7198  (510) 789-8988 (cell)
>>> ___
>>> U-Boot mailing list
>>> U-Boot@lists.denx.de
>>> https://lists.denx.de/listinfo/u-boot
>>
>>
>> --
>> Aaron Williams
>> Senior Software Engineer
>> Cavium, Inc.
>> (408) 943-7198  (510) 789-8988 (cell)
>> ___
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
> 
> Here is the output after the write operation from fsck.ext4 -v /dev/sdg2
> 
> fsck.ext4 -v  /dev/sdg2
> e2fsck 1.42.11 (09-Jul-2014)
> Group descriptor 0 has invalid unused inodes count 57374.  Fix? yes
> Pass 1: Checking inodes, blocks, and sizes
> 
> Running additional passes to resolve blocks claimed by more than one inode...
> Pass 1B: Rescanning for multiply-claimed blocks
> Multiply-claimed block(s) in inode 7: 98307 98308 98309 98310 98311 98312 
> 98313 98314 98315 98316 98317 98318 98319 98320 98321 98322 98323 98324 98325 
> 98326 98327 98328 98329 98330 98331 98332 98333 98334 98335 98336 98337 98338 
> 98339 9834

Re: [U-Boot] [PATCH] ddr: altera: Add ECC DRAM scrubbing support for Stratix 10

[Marek Vasut]

On 07/24/2018 10:10 AM, Chee, Tien Fong wrote:
> On Mon, 2018-07-23 at 11:46 +0200, Marek Vasut wrote:
>> On 07/23/2018 10:20 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> The SDRAM must first be rewritten by zeroes if ECC is used to
>>> initialize
>>> the ECC metadata. Make the CPU overwrite the DRAM with zeroes in
>>> such a
>>> case. This scrubbing implementation turns the caches on
>>> temporarily, then
>>> overwrites the whole RAM with zeroes, flushes the caches and turns
>>> them
>>> off again. This provides satisfactory performance.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  drivers/ddr/altera/sdram_s10.c |   44
>>> 
>>>  1 files changed, 44 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/drivers/ddr/altera/sdram_s10.c
>>> b/drivers/ddr/altera/sdram_s10.c
>>> index 48f4f47..cce261f 100644
>>> --- a/drivers/ddr/altera/sdram_s10.c
>>> +++ b/drivers/ddr/altera/sdram_s10.c
>>> @@ -8,6 +8,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void)
>>>      SYSMGR_HMC_CLK_STATUS_MSK, true,
>>> 1000, false);
>>>  }
>>>  
>>> +/* Initialize SDRAM ECC bits to avoid false DBE */
>>> +static void sdram_init_ecc_bits(unsigned long long size)
>>> +{
>>> +   /* 1GB per chunk */
>>> +   unsigned long long size_byte = SZ_1G;
>>> +   unsigned long long remaining_size;
>>> +   unsigned long long dst_addr = 0x8000;
>>> +   unsigned int start = get_timer(0);
>>> +
>>> +   icache_enable();
>>> +
>>> +   memset(0, 0, dst_addr);
>>> +   gd->arch.tlb_addr = 0x4000;
>>> +   gd->arch.tlb_size = PGTABLE_SIZE;
>> Are you sure this is valid on arm64 ? It looks like something copies
>> from arria10.
> The cache on/off is copied from your implementation on Arria 10. Yes, i
> have tested it, it is working on Stratix 10 board.

Right, except S10 is arm64, A10 is arm32, which is why I wonder whether
careless copying is enough.

>>>
>>> +   dcache_enable();
>>> +
>>> +   remaining_size = size - dst_addr;
>>> +   printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", (u32)(size
> 20));
>>> +
>>> +   while (remaining_size) {
>>> +   if (remaining_size <= size_byte) {
>>> +   memset((void *)dst_addr, 0,
>>> remaining_size);
>>> +   break;
>>> +   } else {
>>> +   memset((void *)dst_addr, 0, size_byte);
>>> +   dst_addr += size_byte;
>>> +   }
>>> +
>>> +   WATCHDOG_RESET();
>>> +   remaining_size -= size_byte;
>>> +   }
>> How long does this take ?
> 1359ms for 2GB.

So why do you need this watchdog reset hack ?

> But I have no idea why Arria 10 board can't achieve the
> same result. Could you try again on your Arria 10 ES board?

There's nothing to try, the scrubbing works fine on A10.

>>>
>>> +   flush_dcache_all();
>>> +   printf("DDRCAL: Scrubbing ECC RAM done.\n");
>>> +   dcache_disable();
>>> +
>>> +   printf("SDRAM-ECC: Initialized success with %d ms\n",
>>> +   (unsigned)get_timer(start));
>>> +}
>>> +
>>>  /**
>>>   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
>>>   *
>>> @@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused)
>>>     setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
>>>      (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
>>>       DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
>>> +
>>> +   sdram_init_ecc_bits(gd->ram_size);
>>>     } else {
>>>     clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
>>>      (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
>>>


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] spl: fit: Enable GZIP compression also for no kernel partitions

[Michal Simek]

There is no reason to limit gzip usage only for OS_BOOT and kernel image
type.

Signed-off-by: Michal Simek 
---

 common/spl/spl_fit.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 9eabb1c1058b..dbf5ac33a845 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -257,10 +257,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
board_fit_image_post_process(&src, &length);
 #endif
 
-   if (IS_ENABLED(CONFIG_SPL_OS_BOOT)  &&
-   IS_ENABLED(CONFIG_SPL_GZIP) &&
-   image_comp == IH_COMP_GZIP  &&
-   type == IH_TYPE_KERNEL) {
+   if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
size = length;
if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
   src, &size)) {
-- 
1.9.1

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Re: [U-Boot] [PATCH] ARM: mx6ul: Apply ERR011115 errata workaround

[Marcin Niestroj]

Hi Stefano,

On 23.07.2018 10:09, Stefano Babic wrote:

Hi Marcin,

On 19/07/2018 13:37, Marcin Niestroj wrote:

ERR05 in IMX6UL errata says to use OCRAM memory above
0x908000 (instead of 0x907000) for silicon revision 1.2 shipped
prior date code 1740.

As we cannot check affected targets in runtime, apply that
workaround by default for all IMX6UL platforms. Leave possibility
to disable that workaround for non-affected targets, so more OCRAM
area can be used by SPL (e.g. for featureful SPL images).




I had a project with this issue - anyway, I disagree to apply the
work-around for all MX6UL.

Rather, we have no possibilities to detect and solve this at runtime.
SPL is already loaded. But NXP has already fixed this in later
production. Companies already know if there production is affected or
not, and they can enable MX6UL_ERR05 for their products.


I am not sure companies know about affected chips. We already know (you
and me) that such issue exists, because we've already run into it.
Unfortunately it took time to figure out what was the real reason of
non-functional device. Our client has manufactured devices (prototypes,
but still...) with affected chips in last two weeks, so in my opinion it
is easy to run into problems. So the idea of this patch was to prevent
that in future for all i.MX6UL boards.

In my opinion it is easier to figure out that ERR05 workaround
can be disabled (after verifying that we do not use affected chips)
instead of figuring out why we have non-functional device (because we
were not aware of ERR05 issue).



We are already fighting with the OCRAM size, specially if other features
(HAB and secure boot, further filesystems) are enabled. Reducing size is
ok for some products (they cannot do in other way if they have some of
these broken devices), it is not ok for other ones.

I will propose to not set it as default for MX6UL.


Signed-off-by: Marcin Niestroj 
---
  arch/arm/mach-imx/mx6/Kconfig |  9 +
  include/configs/imx6_spl.h| 11 +--
  2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 521fad74b5..61708a0526 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -58,6 +58,15 @@ config MX6UL
select SYSCOUNTER_TIMER
bool
  
+config MX6UL_ERR05

+   bool "Workaround for ERR05 in IMX6UL Errata"
+   depends on MX6UL
+   default MX6UL
+   help
+ Say N here if you are sure that your platform is not affected
+ with ERR05. Doing so might be useful in case of featureful
+ (big) SPL images.


Boards Maintainer should decide themselves instead of setting this as
default.


As written above, I do not think that board maintainer is usually
the person that knows which chip revision will be used in production.




+
  config MX6UL_LITESOM
bool
select MX6UL
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 720ff045a7..42d12c7503 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -19,16 +19,23 @@
   *which consists of a 4K header in front of us that contains the IVT, DCD
   *and some padding thus 'our' max size is really 0x00908000 - 0x00918000
   *or 64KB
+ *  - Use 0x00909000 as start of OCRAM Free Area as a workaround for
+ *ERR05 in IMX6UL Errata
   */
+#ifdef CONFIG_MX6UL_ERR05
+#define CONFIG_SPL_TEXT_BASE   0x00909000
+#else
  #define CONFIG_SPL_TEXT_BASE  0x00908000
-#define CONFIG_SPL_MAX_SIZE0x1
+#endif
+
+#define CONFIG_SPL_MAX_SIZE(0x00918000 - CONFIG_SPL_TEXT_BASE)


Sebastian has already reported that this is wrong. Anyway, even if this
was correct, it would be another issue and should be fixed in a separate
patch. The issue in the commit messsage is fixed just moving
CONFIG_MX6UL_ERR05.


Sebastian reported CONFIG_SPL_PAD_TO to be wrong and I agree with that.
However CONFIG_SPL_MAX_SIZE in my opinion should be set as I proposed.
It is only used in linker scripts, mainly to check that we fit our code
within maximum SPL size.

Regards,
Marcin




  #define CONFIG_SPL_STACK  0x0091FFB8
  /*
   * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
   * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
   * boot media (given that boot media specific offset is configured properly).
   */
-#define CONFIG_SPL_PAD_TO  0x11000
+#define CONFIG_SPL_PAD_TO  (CONFIG_SPL_MAX_SIZE + 0x1000)
  
  /* MMC support */

  #if defined(CONFIG_SPL_MMC_SUPPORT)



Best regards,
Stefano Babic



--
Marcin Niestroj
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Re: [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL

[Michal Simek]

Hi,

On 20.7.2018 18:17, Luis Araneda wrote:
> Hi Michal,
> 
> On Fri, Jul 20, 2018 at 6:38 AM Michal Simek  wrote:
>> On 20.7.2018 01:37, Luis Araneda wrote:
>>> Hi Michal,
>>>
>>> On Thu, Jul 19, 2018 at 2:23 AM Michal Simek  
>>> wrote:
>> We need that functionality first but then enable it for all boards is
>> fine for me and via one patch.
> 
> Ok
> 
>> Can you please be more specific what time1/time2 and time3 means?
> 
> The exact location of time 1/2/3 are on the attached diff file, and
> they are placed within the spl_load_simple_fit() function.
> They represent, roughly:
> - time1: Time to load the the FIT image
> - time2: Time to extract (and decompress)
>   the FPGA image from the FIT image
> - time3: Time to program the FPGA

Sorry I missed that attachment.

First of all I have sent patch for that gzip.

On zc706 with 13MB bitstream size this looks much better.

file size (bytes) time1 time2 time3
uncompressed  138696132533  2694  4422
compressed -9   599149144   765   2491

This is SD boot mode and initial time depends on SD you use.

Thanks,
Michal
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[U-Boot] [PATCH v4 0/8] LS1046A SMMU enabling patches

[laurentiu . tudor]

From: Laurentiu Tudor 

This patch series adds the required devices setup and device tree
fixups for SMMU enablement on LS1046A chips. The approach taken tries
to mimic the implementation of PAMU LIODN setup on booke powerpc.

First 4 patches contain some fixes and add some missing bits & pieces.
Last 3 patches add the actual infrastructure for ICID setup, qman
portal and fman ICID configuration.

Changes in v4:
 - added missing SEC ICID config
 - updated macro params to match arguments
 - supplemental comments

Changes in v3:
 - cleaner QMAN_BAR setup
 - moved SoC specific bits from generic ICID arch setup to board code

Changes in v2:
 - drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/7]

Laurentiu Tudor (8):
  armv8: fsl-layerscape: add missing register blocks base address
defines
  armv8: ls1046a: advertise QMan v3 in configuration
  misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
  armv8: fsl-layerscape: add missing debug stream ID
  armv8: ls1046a: initial icid setup support
  armv8: ls1046a: add icid setup for qman portals
  armv8: ls1046a: setup fman ports ICIDs and device tree
  armv8: ls1046a: setup SEC ICIDs and fix up device tree

 arch/arm/cpu/armv8/fsl-layerscape/Makefile|   1 +
 arch/arm/cpu/armv8/fsl-layerscape/icid.c  | 192 ++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  90 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   |   3 +
 .../include/asm/arch-fsl-layerscape/config.h  |   1 +
 .../asm/arch-fsl-layerscape/fsl_icid.h| 114 +++
 .../asm/arch-fsl-layerscape/fsl_portals.h |  24 +++
 .../asm/arch-fsl-layerscape/immap_lsch2.h |  18 +-
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h |   1 +
 board/freescale/ls1046aqds/ls1046aqds.c   |   2 +
 board/freescale/ls1046ardb/ls1046ardb.c   |   3 +
 drivers/crypto/fsl/jr.c   |   2 +-
 drivers/misc/fsl_portals.c|  45 +++-
 scripts/config_whitelist.txt  |   2 -
 14 files changed, 480 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h

-- 
2.17.1

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[U-Boot] [PATCH v4 2/8] armv8: ls1046a: advertise QMan v3 in configuration

[laurentiu . tudor]

From: Laurentiu Tudor 

The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 23faffd9fc..8a05148136 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -257,6 +257,7 @@
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN1
 #define CONFIG_SYS_NUM_FM1_DTSEC   8
 #define CONFIG_SYS_NUM_FM1_10GEC   2
-- 
2.17.1

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[U-Boot] [PATCH v4 1/8] armv8: fsl-layerscape: add missing register blocks base address defines

[laurentiu . tudor]

From: Laurentiu Tudor 

Add defines for the edma and qdma register block base addresses.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5b4767e0fe..644a16dd30 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -88,8 +88,12 @@
 
 #define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
 
+#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c0)
+
 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
 
+#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738)
+
 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x50ULL
-- 
2.17.1

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[U-Boot] [PATCH v4 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree

[laurentiu . tudor]

From: Laurentiu Tudor 

Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Also included in this patch, while adding the new required JR
defines sanitize the preexisting ones by dropping the CONFIG_
prefixes.

Signed-off-by: Laurentiu Tudor 
---
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 15 
 .../asm/arch-fsl-layerscape/fsl_icid.h| 24 +++
 .../asm/arch-fsl-layerscape/immap_lsch2.h | 11 ++---
 drivers/crypto/fsl/jr.c   |  2 +-
 scripts/config_whitelist.txt  |  2 --
 5 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 30c7d8d28a..84f7665929 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
 struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
@@ -40,6 +41,20 @@ struct icid_id_table icid_tbl[] = {
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+   SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
+   SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
+#endif
 };
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 5be50a17ab..bd613219b6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -82,6 +82,30 @@ void fdt_fixup_icid(void *blob);
 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
 
+#define SET_SEC_QI_ICID(streamid) \
+   SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+   (((streamid) << 16) | (streamid)), \
+   offsetof(struct ccsr_sec, qilcr_ls) + \
+   CONFIG_SYS_FSL_SEC_ADDR, \
+   CONFIG_SYS_FSL_SEC_ADDR)
+
+#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
+   SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+   (((streamid) << 16) | (streamid)), \
+   offsetof(struct ccsr_sec, jrliodnr[jr_num].ls) + \
+   CONFIG_SYS_FSL_SEC_ADDR, \
+   FSL_SEC_JR##jr_num##_BASE_ADDR)
+
+#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
+   SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+   offsetof(struct ccsr_sec, decoliodnr[deco_num].ls) + \
+   CONFIG_SYS_FSL_SEC_ADDR, 0)
+
+#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
+   SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+   offsetof(struct ccsr_sec, rticliodnr[rtic_num].ls) + \
+   CONFIG_SYS_FSL_SEC_ADDR, 0)
+
 extern struct icid_id_table icid_tbl[];
 extern struct fman_icid_id_table fman_icid_tbl[];
 extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d22ec70aa5..0dd09a5d81 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -199,11 +199,16 @@ struct sys_info {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET  0x70ull
-#define CONFIG_SYS_FSL_JR0_OFFSET  0x71ull
+#define FSL_SEC_JR0_OFFSET 0x71ull
+#define FSL_SEC_JR1_OFFSET 0x72ull
+#define FSL_SEC_JR2_OFFSET 0x73ull
+#define FSL_SEC_JR3_OFFSET 0x74ull
 #define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-   (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
 
 /

[U-Boot] [PATCH v4 7/8] armv8: ls1046a: setup fman ports ICIDs and device tree

[laurentiu . tudor]

From: Laurentiu Tudor 

Add support for ICID setting of fman ports and the required device
tree fixups.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/cpu/armv8/fsl-layerscape/icid.c  | 82 +++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
 .../asm/arch-fsl-layerscape/fsl_icid.h| 10 +++
 3 files changed, 122 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c 
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ae3b8daa95..bada5040a8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static void set_icid(struct icid_id_table *tbl, int size)
 {
@@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
 }
 
+#ifdef CONFIG_SYS_FMAN_V3
+void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+{
+   int i;
+   ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+
+   for (i = 0; i < size; i++) {
+   out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
+tbl[i].icid);
+   }
+}
+#endif
+
 void set_icids(void)
 {
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_FMAN_V3
+   set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
+#endif
 }
 
 int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
@@ -75,6 +93,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
return 0;
 }
 
+#ifdef CONFIG_SYS_FMAN_V3
+int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+  const int size)
+{
+   int i;
+
+   for (i = 0; i < size; i++) {
+   if (tbl[i].port_id == port_id)
+   return tbl[i].icid;
+   }
+
+   return -1;
+}
+
+void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+   const char *compat)
+{
+   int noff, len, icid;
+   const u32 *prop;
+
+   noff = fdt_node_offset_by_compatible(blob, -1, compat);
+   while (noff > 0) {
+   prop = fdt_getprop(blob, noff, "cell-index", &len);
+   if (!prop) {
+   printf("WARNING missing cell-index for fman port\n");
+   continue;
+   }
+   if (len != 4) {
+   printf("WARNING bad cell-index size for fman port\n");
+   continue;
+   }
+
+   icid = get_fman_port_icid(fdt32_to_cpu(*prop),
+ fman_icid_tbl, fman_icid_tbl_sz);
+   if (icid < 0) {
+   printf("WARNING unknown ICID for fman port %d\n",
+  *prop);
+   continue;
+   }
+
+   fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
+
+   noff = fdt_node_offset_by_compatible(blob, noff, compat);
+   }
+}
+
+void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+{
+   static const char * const compats[] = {
+   "fsl,fman-v3-port-oh",
+   "fsl,fman-v3-port-rx",
+   "fsl,fman-v3-port-tx",
+   };
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(compats); i++)
+   fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]);
+}
+#endif
+
 int fdt_get_smmu_phandle(void *blob)
 {
int noff, smmu_ph;
@@ -107,4 +185,8 @@ void fdt_fixup_icid(void *blob)
return;
 
fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_FMAN_V3
+   fdt_fixup_fman_icids(blob, smmu_ph);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 80e1ceadc0..30c7d8d28a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = {
 };
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+   /* port id, icid */
+   SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+   SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_E

[U-Boot] [PATCH v4 6/8] armv8: ls1046a: add icid setup for qman portals

[laurentiu . tudor]

From: Laurentiu Tudor 

Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor 
---
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
 .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++
 drivers/misc/fsl_portals.c| 43 +++
 3 files changed, 75 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 1c528ab751..80e1ceadc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -6,6 +6,22 @@
 #include 
 #include 
 #include 
+#include 
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+   SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
 
 struct icid_id_table icid_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
new file mode 100644
index 00..1577e935a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+struct qportal_info {
+   u16 dicid;  /* DQRR ICID */
+   u16 ficid;  /* frame data ICID */
+   u16 icid;
+   u8  sdest;
+};
+
+#define SET_QP_INFO(streamid, dest) \
+   { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
+   .sdest = (dest) }
+
+extern struct qportal_info qp_info[];
+void fdt_portal(void *blob, const char *compat, const char *container,
+   u64 addr, u32 size);
+
+#endif
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 22faf16751..a524510707 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_PPC
 #include 
 #include 
+#else
+#include 
+#include 
 #endif
 #include 
 
@@ -45,6 +48,22 @@ void setup_qbman_portals(void)
/* set frame liodn */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
+#else
+#ifdef CONFIG_ARM
+   int i;
+
+   for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+   u8 sdest = qp_info[i].sdest;
+   u16 ficid = qp_info[i].ficid;
+   u16 dicid = qp_info[i].dicid;
+   u16 icid = qp_info[i].icid;
+
+   out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
+   dicid);
+   /* set frame icid */
+   out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
+   }
+#endif
 #endif
 
/* Change default state of BMan ISDR portals to all 1s */
@@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
char compat[64];
int compat_len;
 
+#ifndef CONFIG_PPC
+   int smmu_ph = fdt_get_smmu_phandle(blob);
+#endif
+
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
ip_cfg = rev_2 & 0xff;
@@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
 
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_PPC
 #ifdef CONFIG_FSL_CORENET
u32 liodns[2];
 #endif
@@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
if (!ci)
goto err;
 
-   i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
-   int j;
-#endif
-
-#endif /* CONFIG_PPC */
+   i = fdt32_to_cpu(*ci);
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
@@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-   for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+   for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
char name[] = "fman@0";
 
name[sizeof(name) - 2] = '0' + j;
@@ -251,6 +268,16 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
 #endif
+#else
+   if (smmu_ph >= 0) {
+   u32 icids[3];
+
+   icids[0] = qp_info[i].icid;
+   icids[1] = qp_inf

[U-Boot] [PATCH v4 5/8] armv8: ls1046a: initial icid setup support

[laurentiu . tudor]

From: Laurentiu Tudor 

Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile|   1 +
 arch/arm/cpu/armv8/fsl-layerscape/icid.c  | 110 ++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   |   3 +
 .../asm/arch-fsl-layerscape/fsl_icid.h|  80 +
 board/freescale/ls1046aqds/ls1046aqds.c   |   2 +
 board/freescale/ls1046ardb/ls1046ardb.c   |   3 +
 7 files changed, 228 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 1e9e4680fe..5d6f68aad6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -37,6 +37,7 @@ endif
 
 ifneq ($(CONFIG_ARCH_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+obj-y += icid.o ls1046_ids.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1088A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c 
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
new file mode 100644
index 00..ae3b8daa95
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+static void set_icid(struct icid_id_table *tbl, int size)
+{
+   int i;
+
+   for (i = 0; i < size; i++)
+   out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+}
+
+void set_icids(void)
+{
+   /* setup general icid offsets */
+   set_icid(icid_tbl, icid_tbl_sz);
+}
+
+int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
+{
+   int i, ret;
+   u32 prop[8];
+
+   /*
+* Note: The "iommus" property definition mentions Stream IDs while
+* this code handles ICIDs. The current implementation assumes that
+* ICIDs and Stream IDs are equal.
+*/
+   for (i = 0; i < num_ids; i++) {
+   prop[i * 2] = cpu_to_fdt32(smmu_ph);
+   prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
+   }
+   ret = fdt_setprop(blob, off, "iommus",
+ prop, sizeof(u32) * num_ids * 2);
+   if (ret) {
+   printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret));
+   return ret;
+   }
+
+   return 0;
+}
+
+int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+  struct icid_id_table *tbl, int size)
+{
+   int i, err, off;
+
+   for (i = 0; i < size; i++) {
+   if (!tbl[i].compat)
+   continue;
+
+   off = fdt_node_offset_by_compat_reg(blob,
+   tbl[i].compat,
+   tbl[i].compat_addr);
+   if (off > 0) {
+   err = fdt_set_iommu_prop(blob, off, smmu_ph,
+&tbl[i].id, 1);
+   if (err)
+   return err;
+   } else {
+   printf("WARNING could not find node %s: %s.\n",
+  tbl[i].compat, fdt_strerror(off));
+   }
+   }
+
+   return 0;
+}
+
+int fdt_get_smmu_phandle(void *blob)
+{
+   int noff, smmu_ph;
+
+   noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
+   if (noff < 0) {
+   printf("WARNING failed to get smmu node: %s\n",
+  fdt_strerror(noff));
+   return noff;
+   }
+
+   smmu_ph = fdt_get_phandle(blob, noff);
+   if (!smmu_ph) {
+   smmu_ph = fdt_create_phandle(blob, noff);
+   if (!smmu_ph) {
+   printf("WARNING failed to get smmu phandle\n");
+   return -1;
+   }
+   }
+
+   return smmu_ph;
+}
+
+void fdt_fixup_icid(void *blob)
+{
+   int smmu_ph;
+
+   smmu_ph = fdt_get_smmu_phandle(blob);
+   if (smmu_ph < 0)
+   return;
+
+   fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
new file mode 100644
index 00..1c528ab751
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include 
+#include 
+#include 
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+   SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+   SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+

[U-Boot] [PATCH v4 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms

[laurentiu . tudor]

From: Laurentiu Tudor 

QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
 drivers/misc/fsl_portals.c | 2 --
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 644a16dd30..d22ec70aa5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -57,8 +57,7 @@
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
 #define CONFIG_SYS_QMAN_NUM_PORTALS10
 #define CONFIG_SYS_QMAN_MEM_BASE   0x5
-#define CONFIG_SYS_QMAN_MEM_PHYS   (0xfull + \
-   CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_PHYS   CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_MEM_SIZE   0x0800
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE0x1
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE0x1
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 7c22b8d209..22faf16751 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -24,7 +24,6 @@ void setup_qbman_portals(void)
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_PPC
struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
 
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
@@ -32,7 +31,6 @@ void setup_qbman_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
 #endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-#endif
 #ifdef CONFIG_FSL_CORENET
int i;
 
-- 
2.17.1

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[U-Boot] [PATCH v4 4/8] armv8: fsl-layerscape: add missing debug stream ID

[laurentiu . tudor]

From: Laurentiu Tudor 

Add a define with a value for the missing debug stream ID.

Signed-off-by: Laurentiu Tudor 
---
 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
index 61c6e533c6..1b02d484d9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -50,6 +50,7 @@
 #define FSL_QDMA_STREAM_ID 7
 #define FSL_EDMA_STREAM_ID 8
 #define FSL_ETR_STREAM_ID  9
+#define FSL_DEBUG_STREAM_ID10
 
 /* PCI - programmed in PEXn_LUT */
 #define FSL_PEX_STREAM_ID_START11
-- 
2.17.1

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[U-Boot] [PATCH] arm64: zynqmp: Add support for Avnet Ultra96

[Michal Simek]

Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files
and point to origin internal board name.

Signed-off-by: Michal Simek 
---

 MAINTAINERS|  1 +
 arch/arm/dts/Makefile  |  1 +
 arch/arm/dts/avnet-ultra96-rev1.dts| 19 +++
 board/xilinx/zynqmp/avnet-ultra96-rev1 |  1 +
 configs/avnet_ultra96_rev1_defconfig   | 92 ++
 5 files changed, 114 insertions(+)
 create mode 100644 arch/arm/dts/avnet-ultra96-rev1.dts
 create mode 12 board/xilinx/zynqmp/avnet-ultra96-rev1
 create mode 100644 configs/avnet_ultra96_rev1_defconfig

diff --git a/MAINTAINERS b/MAINTAINERS
index a2293b7c88d4..aee2c3841f5e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -316,6 +316,7 @@ F:  drivers/usb/host/ehci-zynq.c
 F: drivers/watchdog/cdns_wdt.c
 F: include/zynqmppl.h
 F: tools/zynqmp*
+N: ultra96
 N: zynqmp
 
 ARM ZYNQMP R5
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 09adf5eab1da..ae54b5335ecb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -151,6 +151,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
+   avnet-ultra96-rev1.dtb  \
zynqmp-mini-emmc0.dtb   \
zynqmp-mini-emmc1.dtb   \
zynqmp-mini-nand.dtb\
diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts 
b/arch/arm/dts/avnet-ultra96-rev1.dts
new file mode 100644
index ..88aa06fa78a8
--- /dev/null
+++ b/arch/arm/dts/avnet-ultra96-rev1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet Ultra96 rev1
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu100-revC.dts"
+
+/ {
+   model = "Avnet Ultra96 Rev1";
+   compatible = "avnet,ultra96-rev1", "avnet,ultra96",
+"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
+"xlnx,zynqmp";
+};
diff --git a/board/xilinx/zynqmp/avnet-ultra96-rev1 
b/board/xilinx/zynqmp/avnet-ultra96-rev1
new file mode 12
index ..f2beed309a21
--- /dev/null
+++ b/board/xilinx/zynqmp/avnet-ultra96-rev1
@@ -0,0 +1 @@
+zynqmp-zcu100-revC
\ No newline at end of file
diff --git a/configs/avnet_ultra96_rev1_defconfig 
b/configs/avnet_ultra96_rev1_defconfig
new file mode 100644
index ..0b5281a25021
--- /dev/null
+++ b/configs/avnet_ultra96_rev1_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x800
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff01
+CONFIG_DEBUG_UART_CLOCK=1
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=1500
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_MP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
1.9.1

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Re: [U-Boot] [PATCH v2] arm: zynq: add support for the zybo z7 board

[Luis Araneda]

Hi Michal,

On Tue, Jul 24, 2018 at 8:39 AM Michal Simek  wrote:
> [...]
> This should be tuned more. That file is long because you support all
> silicon version which is not needed at all. z7 is quite new product
> where 3_0 tables are used. It means just manually remove that
> PCW_SILICON_VERSION_1, PCW_SILICON_VERSION_2 and all that tables and we
> are ready for applying.
> Take a look at board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c.

Yes, I already read the topic-miamiplus file, in fact, I removed
silicon version 1_0 and 2_0 from v1, but I decided to include them
with v2 because the patch were less tha 100 kB.
I'll remove silicon version 1_0 and 2_0 with v3, which I'll send in a bit.

Thanks,

Luis Araneda.
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Re: [U-Boot] [PATCH 11/20] w1: enumerate sandbox driver if configured

[Simon Glass]

Hi Maxime,

On 24 July 2018 at 00:58, Maxime Ripard  wrote:
> On Mon, Jul 23, 2018 at 05:48:25PM -0600, Simon Glass wrote:
>> Hi,
>>
>> On 20 July 2018 at 08:01, Lukasz Majewski  wrote:
>> > Hi Eugen,
>> >
>> > Thanks for (re-)bringing the One wire support to u-boot.
>> >
>> >> Add a sandbox eeprom on the bus as a device, if sandbox driver is
>> >> configured.
>> >>
>> >> Signed-off-by: Eugen Hristev 
>> >> ---
>> >>  drivers/w1/w1-uclass.c | 5 +
>> >>  1 file changed, 5 insertions(+)
>> >>
>> >> diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c
>> >> index cfddda3..e58c1ca 100644
>> >> --- a/drivers/w1/w1-uclass.c
>> >> +++ b/drivers/w1/w1-uclass.c
>> >> @@ -142,6 +142,11 @@ static int w1_enumerate(struct udevice *bus)
>> >>   }
>> >>   }
>> >>
>> >> +#ifdef CONFIG_W1_EEPROM_SANDBOX
>> >> + /* before we are finished, add a sandbox device if we can */
>> >> + w1_new_device(bus, W1_FAMILY_EEP_SANDBOX);
>> >> +#endif
>> >
>> > IMHO we shouldn't mix the sandbox code with production (on boards) code.
>> >
>> > Maybe Simon (+CCed) could provide some more input here?
>>
>> I have not seen this series. But new devices should be created
>> automatically based on them being in the device tree. So you should
>> just be able to add them there.
>
> 1-Wire is discoverable, so there's no device nodes in the DT.

Well there should be. See for example PCI, USB, I2C and SPI :-)

Regards,
Simon
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[U-Boot] [PATCH v3] arm: zynq: add support for the zybo z7 board

[Luis Araneda]

The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs

Signed-off-by: Luis Araneda 
---

This patch adds support for the Digilent Zybo Z7 board

The only thing that I tested and is not working yet, is reading the
MAC address from the OTP region of the SPI flash memory, but I'm trying
to find a solution

Changes from v2:
- Removed silicon version 2_0 and 1_0 from ps7_init_gpl.c

Changes from v1:
- Rebased on u-boot/master
- Removed comments and indented ps7_init_gpl.c
- Removed CONFIG_DISPLAY from defconfig
- Replaced the cadence I2C driver by zynq_i2c
- Squashed the patches as they are less than 100kB now
---
 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/zynq-zybo-z7.dts |  81 +
 board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c | 297 ++
 configs/zynq_zybo_z7_defconfig|  68 
 4 files changed, 448 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/zynq-zybo-z7.dts
 create mode 100644 board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
 create mode 100644 configs/zynq_zybo_z7_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 09adf5eab1..07d8729104 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -149,7 +149,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
-   zynq-zybo.dtb
+   zynq-zybo.dtb \
+   zynq-zybo-z7.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc0.dtb   \
zynqmp-mini-emmc1.dtb   \
diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts
new file mode 100644
index 00..3f8a3bfa0f
--- /dev/null
+++ b/arch/arm/dts/zynq-zybo-z7.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include 
+
+/ {
+   model = "Digilent Zybo Z7 board";
+   compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+   aliases {
+   ethernet0 = &gem0;
+   serial0 = &uart1;
+   spi0 = &qspi;
+   mmc0 = &sdhci0;
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x4000>;
+   };
+
+   chosen {
+   bootargs = "";
+   stdout-path = "serial0:115200n8";
+   };
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   ld4 {
+   label = "zynq-zybo-z7:green:ld4";
+   gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   usb_phy0: phy0 {
+   #phy-cells = <0>;
+   compatible = "usb-nop-xceiv";
+   reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&clkc {
+   ps-clk-frequency = <>;
+};
+
+&gem0 {
+   status = "okay";
+   phy-mode = "rgmii-id";
+   phy-handle = <ðernet_phy>;
+
+   ethernet_phy: ethernet-phy@0 {
+   reg = <0>;
+   device_type = "ethernet-phy";
+   };
+};
+
+&qspi {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&sdhci0 {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&uart1 {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&usb0 {
+   status = "okay";
+   dr_mode = "host";
+   usb-phy = <&usb_phy0>;
+};
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
new file mode 100644
index 00..f1b9357780
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ *   (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ *   - Add "ZYNQ7 Processing System" IP
+ *   - Run "Block Automation" (Check "Apply Board Preset")
+ *   - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ *   - Save diagram changes
+ *   - Go to sources view, select the block diagram,
+ * and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ *   and the checkpatch.pl script
+ *
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_WRITE(0xF808, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT

Re: [U-Boot] [PATCH] armv8: layerscape: Enable EHCI access for LS1012A

[York Sun]

On 07/10/2018 07:11 PM, Ran Wang wrote:
> Hi York,
> 
>> -Original Message-
>> From: York Sun
>> Sent: Wednesday, July 11, 2018 05:06
>> To: Ran Wang ; Albert Aribaud
>> 
>> Cc: u-boot@lists.denx.de
>> Subject: Re: [PATCH] armv8: layerscape: Enable EHCI access for LS1012A
>>
>> On 07/02/2018 10:34 PM, Ran Wang wrote:
>>> Program Central Security Unit (CSU) to grant access permission for USB
>>> 2.0 controller, otherwiase EHCI funciton will down.
>>>
>>> Signed-off-by: Ran Wang 
>>> ---
>>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c  | 8 
>>>  arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 +
>>>  2 files changed, 9 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> index 6a56269..2c4cf7f 100644
>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> @@ -14,6 +14,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
>>>  #include 
>>>  #endif
>>> @@ -668,6 +669,13 @@ void fsl_lsch2_early_init_f(void)
>>>  CCI400_DVM_MESSAGE_REQ_EN |
>> CCI400_SNOOP_REQ_EN);
>>> }
>>>
>>> +   /*
>>> +* Program Central Security Unit (CSU) to grant access
>>> +* permission for USB 2.0 controller
>>> +*/
>>> +#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
>>> +   set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); #endif
>>
>> Is this LS1012A specific?
>>
> For Layerscape platforms, only LS1012A and LS1021A have USB2.0(EHCI) 
> controller,
> Others have USB3.0 controller only. For now I can only verify on LS1012A, so 
> didn't
> cover LS1021A yet.
> 

Ran,

I think calling function set_devices_ns_access() may have an issue. It
is not EL2 safe, is it? Please check enable_layerscape_ns_access(). It
detects exception level before accessing EL3-only registers.

York
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Re: [U-Boot] [PATCH] spl: fit: Enable GZIP compression also for no kernel partitions

[York Sun]

On 07/24/2018 06:07 AM, Michal Simek wrote:
> There is no reason to limit gzip usage only for OS_BOOT and kernel image
> type.
> 
> Signed-off-by: Michal Simek 
> ---
> 
>  common/spl/spl_fit.c | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index 9eabb1c1058b..dbf5ac33a845 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -257,10 +257,7 @@ static int spl_load_fit_image(struct spl_load_info 
> *info, ulong sector,
>   board_fit_image_post_process(&src, &length);
>  #endif
>  
> - if (IS_ENABLED(CONFIG_SPL_OS_BOOT)  &&
> - IS_ENABLED(CONFIG_SPL_GZIP) &&
> - image_comp == IH_COMP_GZIP  &&
> - type == IH_TYPE_KERNEL) {
> + if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
>   size = length;
>   if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
>  src, &size)) {
> 

This will uncompress ramdisk unnecessarily.

York
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Re: [U-Boot] [PATCH v2] cmd: fastboot: Validate user input

[Sam Protsenko]

On Sat, Jun 30, 2018 at 7:20 AM, Simon Glass  wrote:
> On 29 June 2018 at 11:59, Sam Protsenko  wrote:
>> In case when user provides '-' as USB controller index, like this:
>>
>> => fastboot -
>>
>> data abort occurs in strcmp() function in do_fastboot(), here:
>>
>> if (!strcmp(argv[1], "udp"))
>>
>> (tested on BeagleBone Black).
>>
>> That's because argv[1] is NULL when user types in the '-', and null
>> pointer dereference occurs in strcmp() (which is ok according to C
>> standard specification). So we must validate user input to prevent such
>> behavior.
>>
>> While at it, check also the result of strtoul() function and handle
>> error cases properly.
>>
>> Signed-off-by: Sam Protsenko 
>> ---
>> Changes for v2:
>>   - replace argv check with argc check
>>   - add mentioning of testing platform in commit message
>>
>>  cmd/fastboot.c | 13 -
>>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass 

Hi Lukasz,

Can you please review and merge?

Thanks!
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Re: [U-Boot] [PATCH v2 1/3] dfu: Fix data abort in dfu_free_entities()

[Sam Protsenko]

On Fri, Jul 13, 2018 at 4:35 PM, Sam Protsenko
 wrote:
> Commit 5d8fae79163e ("dfu: avoid memory leak") brings a regression which
> described below. This patch is effectively reverting that commit, adding
> corresponding comment to avoid such regressions in future.
>
> In case of error in dfu_config_entities(), it frees "dfu" array, which
> leads to "data abort" in dfu_free_entities(), which tries to free the
> same array (and even tries to access it from linked list first). The
> issue occurs e.g. when partition table on device does not match
> $dfu_alt_info layout:
>
> => dfu 0 mmc 1
> Couldn't find part #2 on mmc device #1
> DFU entities configuration failed!
> data abort
>
> To fix this issue, do not free "dfu" array in dfu_config_entities(). It
> will be freed later in dfu_free_entities().
>
> Tested on BeagleBone Black (where this regression was originally found).
>
> Signed-off-by: Sam Protsenko 
> ---
> Changes in v2:
>   - Improve commit message by mentioning regression commit
>

Hi Lukasz,

Can you please review and merge this whole series?

Thanks!

>  drivers/dfu/dfu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
> index e7c91193b9..a3c09334b7 100644
> --- a/drivers/dfu/dfu.c
> +++ b/drivers/dfu/dfu.c
> @@ -462,7 +462,7 @@ int dfu_config_entities(char *env, char *interface, char 
> *devstr)
> ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface,
>   devstr);
> if (ret) {
> -   free(dfu);
> +   /* We will free "dfu" in dfu_free_entities() */
> return -1;
> }
>
> --
> 2.18.0
>
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