Re: [U-Boot] [PATCH v2] bootm: Align cache flush begin address

2018-04-17 Thread Bryan O'Donoghue



On 16/04/18 17:49, Simon Glass wrote:

On 15 April 2018 at 04:48, Bryan O'Donoghue  wrote:

commit b4d956f6bc0f ("bootm: Align cache flush end address correctly")
aligns the end address of the cache flush operation to a cache-line size to
ensure lower-layers in the code accept the range provided and flush.

A similar action should be taken for the begin address of a cache flush
operation. The load address may not be aligned to a cache-line boundary, so
ensure the passed address is aligned.

Signed-off-by: Bryan O'Donoghue 
Reported-by: Breno Matheus Lima 
Suggested-by: Tom Rini 
Cc: Simon Glass 
---
  common/bootm.c | 8 +++-
  1 file changed, 7 insertions(+), 1 deletion(-)


I feel that using an unaligned start address should probably be an
error. Why would that be useful?

Apart from that:

Reviewed-by: Simon Glass 

Regards,
Simon



We are booting a kernel that has an entry point aligned a cacheline 
boundary with a header prefix/load-address that is a negative offset 
from that.


We could go about trying to move the load/ep address of that kernel but, 
my feeling is that's probably the wrong thing to do, we can just as 
easily align-down and add to the flush length.


---
bod
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Re: [U-Boot] [PATCH] reset: fix bulk API when DM_RESET is disabled

2018-04-17 Thread Neil Armstrong
On 12/04/2018 18:41, Simon Glass wrote:
> On 12 April 2018 at 02:03, Neil Armstrong  wrote:
>> In the commit "reset: Add get/assert/deassert/release for bulk of reset 
>> signals"
>> the disabled reset_release_bulk() and reset_get_bulk() used the wrong
>> struct clk_bulk instead of struct reset_ctl_bulk.
>>
>> Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of 
>> reset signals")
>> Reported-by: Jean-Jacques Hiblot 
>> Signed-off-by: Neil Armstrong 
>> ---
>>  include/reset.h | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 
> We don't have build coverage for this at the moment I suppose. It
> would be a bit of pain to add that with sandbox, although I wonder if
> it could be done with some horrible #define hackery in a C file that
> includes this header?
> 
> - Simon
> 

It could but it will be horrible indeed.

Neil
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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread See, Chin Liang
Hi Marek,

On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> The Arria10 uses slightly different boot image header than the Gen5
> SoCs,
> in particular the header itself contains an offset from the start of
> the
> header to which the Arria10 jumps. This offset must not be negative,
> yet
> the header is placed at offset 0x40 of the bootable binary.
> Therefore, to
> jump into U-Boot, add a trampoline just past the Arria10 boot header
> and
> point to this trampoline at fixed offset from the header generated
> using
> the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump
> back
> to offset 0x0 of the image, it is possible to jump directly at the
> reset
> label and save processing two instructions.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> b/arch/arm/mach-socfpga/include/mach/boot0.h
> index d6b9435d33..06bbe27d2c 100644
> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> @@ -18,10 +18,10 @@ _start:
>   .word   0xcafec0d3; /* Checksum, zero-pad */
>   nop;
>  
> - b reset;/* SoCFPGA jumps here */
> - nop;
> + b reset;/* SoCFPGA Gen5 jumps here */
>   nop;
>   nop;
> + b reset;/* SoCFPGA Gen10 trampoline */

Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder can we
standardize that by using 0x14 instead of proposed 0x18 in this patch?

Thanks
Chin Liang

>  #endif
>  
>  #endif /* __BOOT0_H */
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Re: [U-Boot] [PATCH 2/5] image: socfpga: Add SFP image version 1 definition

2018-04-17 Thread See, Chin Liang
On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> Add support for the SoCFPGA header v1, which is used on Arria 10.
> The layout of the v0 and v1 header is similar, yet there are a few
> differences which make it incompatible with previous v0 header, so
> add a new entry.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  common/image.c  | 3 ++-
>  include/image.h | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 

Acked-by: Chin Liang See 
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Re: [U-Boot] [PATCH 3/5] tools: socfpga: Stop using global struct socfpga_image

2018-04-17 Thread See, Chin Liang
On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> The structure is passed around correctly, create local instances
> where necessary and zap the global struct socfpga_image instance.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  tools/socfpgaimage.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

Acked-by: Chin Liang See 
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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread Marek Vasut
On 04/17/2018 10:40 AM, See, Chin Liang wrote:
> Hi Marek,
> 
> On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
>> The Arria10 uses slightly different boot image header than the Gen5
>> SoCs,
>> in particular the header itself contains an offset from the start of
>> the
>> header to which the Arria10 jumps. This offset must not be negative,
>> yet
>> the header is placed at offset 0x40 of the bootable binary.
>> Therefore, to
>> jump into U-Boot, add a trampoline just past the Arria10 boot header
>> and
>> point to this trampoline at fixed offset from the header generated
>> using
>> the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump
>> back
>> to offset 0x0 of the image, it is possible to jump directly at the
>> reset
>> label and save processing two instructions.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Dinh Nguyen 
>> Cc: Chin Liang See 
>> ---
>>  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
>> b/arch/arm/mach-socfpga/include/mach/boot0.h
>> index d6b9435d33..06bbe27d2c 100644
>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
>> @@ -18,10 +18,10 @@ _start:
>>  .word   0xcafec0d3; /* Checksum, zero-pad */
>>  nop;
>>  
>> -b reset;/* SoCFPGA jumps here */
>> -nop;
>> +b reset;/* SoCFPGA Gen5 jumps here */
>>  nop;
>>  nop;
>> +b reset;/* SoCFPGA Gen10 trampoline */
> 
> Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder can we
> standardize that by using 0x14 instead of proposed 0x18 in this patch?

What difference does it make, the entire image is generated during the
build anyway ? This patch uses offset 0x1c, but what is the reason for
address 0x14 in your proprietary tool, is there one ?

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] mmc: mv_sdhci: zero out sdhci_host structure

2018-04-17 Thread Stefan Roese

On 16.04.2018 17:13, Stefan Roese wrote:

On 16.04.2018 16:08, Matt Pelland wrote:

The mv_sdhci driver was not zeroing the sdhci_host structure it
allocates causing random access violations in parts of the mmc core
where the "ops" member pointers are checked and called if not NULL.

Signed-off-by: Matt Pelland 
---
  drivers/mmc/mv_sdhci.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 69aa87babe..0ed0d38c90 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -68,7 +68,7 @@ static char *MVSDH_NAME = "mv_sdh";
  int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 
quirks)

  {
  struct sdhci_host *host = NULL;
-    host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+    host = calloc(1, sizeof(*host));
  if (!host) {
  printf("sdh_host malloc fail!\n");
  return -ENOMEM;



Looks good, so:

Reviewed-by: Stefan Roese 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread See, Chin Liang
On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote:
> On 04/17/2018 10:40 AM, See, Chin Liang wrote:
> > 
> > Hi Marek,
> > 
> > On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> > > 
> > > The Arria10 uses slightly different boot image header than the
> > > Gen5
> > > SoCs,
> > > in particular the header itself contains an offset from the start
> > > of
> > > the
> > > header to which the Arria10 jumps. This offset must not be
> > > negative,
> > > yet
> > > the header is placed at offset 0x40 of the bootable binary.
> > > Therefore, to
> > > jump into U-Boot, add a trampoline just past the Arria10 boot
> > > header
> > > and
> > > point to this trampoline at fixed offset from the header
> > > generated
> > > using
> > > the mkimage -T socfpgaimage_v1 . Note that it is not needed to
> > > jump
> > > back
> > > to offset 0x0 of the image, it is possible to jump directly at
> > > the
> > > reset
> > > label and save processing two instructions.
> > > 
> > > Signed-off-by: Marek Vasut 
> > > Cc: Dinh Nguyen 
> > > Cc: Chin Liang See 
> > > ---
> > >  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > index d6b9435d33..06bbe27d2c 100644
> > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > @@ -18,10 +18,10 @@ _start:
> > >   .word   0xcafec0d3; /* Checksum, zero-pad */
> > >   nop;
> > >  
> > > - b reset;/* SoCFPGA jumps here */
> > > - nop;
> > > + b reset;/* SoCFPGA Gen5 jumps here */
> > >   nop;
> > >   nop;
> > > + b reset;/* SoCFPGA Gen10 trampoline */
> > Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder can
> > we
> > standardize that by using 0x14 instead of proposed 0x18 in this
> > patch?
> What difference does it make, the entire image is generated during
> the
> build anyway ? This patch uses offset 0x1c, but what is the reason
> for
> address 0x14 in your proprietary tool, is there one ?

Our A10 header ended at 0x13 today. Hence we are continuing the code at
0x14 without any spacing.

While for 0x1c, should it be 3 nop?

Thanks
Chin Liang

> 
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[U-Boot] Please pull u-boot-marvell/master

2018-04-17 Thread Stefan Roese
Hi Tom,

please pull the small mv_sdhci fix from Matt from the Marvell
repo.

Thanks,
Stefan


The following changes since commit 8c0a17be0a632b9a823e14628c42f85c3e64f08e:

  Prepare v2018.05-rc2 (2018-04-16 20:00:14 -0400)

are available in the Git repository at:

  git://www.denx.de/git/u-boot-marvell.git 

for you to fetch changes up to ca4e7d674ee6931c7a4effd697e644d7646cfac0:

  mmc: mv_sdhci: zero out sdhci_host structure (2018-04-17 10:39:30 +0200)


Matt Pelland (1):
  mmc: mv_sdhci: zero out sdhci_host structure

 drivers/mmc/mv_sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Re: [U-Boot] [PATCH 5/5] spl: socfpga: Generate Arria10 SFP header V1

2018-04-17 Thread See, Chin Liang
On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> Generate SoCFPGA boot header version 1 instead of version 0 for
> Arria10.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  scripts/Makefile.spl | 4 
>  1 file changed, 4 insertions(+)
> 

Acked-by: Chin Liang See 
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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread Marek Vasut
On 04/17/2018 10:52 AM, See, Chin Liang wrote:
> On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote:
>> On 04/17/2018 10:40 AM, See, Chin Liang wrote:
>>>
>>> Hi Marek,
>>>
>>> On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:

 The Arria10 uses slightly different boot image header than the
 Gen5
 SoCs,
 in particular the header itself contains an offset from the start
 of
 the
 header to which the Arria10 jumps. This offset must not be
 negative,
 yet
 the header is placed at offset 0x40 of the bootable binary.
 Therefore, to
 jump into U-Boot, add a trampoline just past the Arria10 boot
 header
 and
 point to this trampoline at fixed offset from the header
 generated
 using
 the mkimage -T socfpgaimage_v1 . Note that it is not needed to
 jump
 back
 to offset 0x0 of the image, it is possible to jump directly at
 the
 reset
 label and save processing two instructions.

 Signed-off-by: Marek Vasut 
 Cc: Dinh Nguyen 
 Cc: Chin Liang See 
 ---
  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
 b/arch/arm/mach-socfpga/include/mach/boot0.h
 index d6b9435d33..06bbe27d2c 100644
 --- a/arch/arm/mach-socfpga/include/mach/boot0.h
 +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
 @@ -18,10 +18,10 @@ _start:
    .word   0xcafec0d3; /* Checksum, zero-pad */
    nop;
  
 -  b reset;/* SoCFPGA jumps here */
 -  nop;
 +  b reset;/* SoCFPGA Gen5 jumps here */
    nop;
    nop;
 +  b reset;/* SoCFPGA Gen10 trampoline */
>>> Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder can
>>> we
>>> standardize that by using 0x14 instead of proposed 0x18 in this
>>> patch?
>> What difference does it make, the entire image is generated during
>> the
>> build anyway ? This patch uses offset 0x1c, but what is the reason
>> for
>> address 0x14 in your proprietary tool, is there one ?
> 
> Our A10 header ended at 0x13 today. Hence we are continuing the code at
> 0x14 without any spacing.
> 
> While for 0x1c, should it be 3 nop?

Yes, gives enough space were the header grow for whatever reason. Mind
you, the NOPs are not executed, the socfpga jumps to 0x1c directly via
0x0c -- Image entry offset

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread See, Chin Liang
On Tue, 2018-04-17 at 11:01 +0200, Marek Vasut wrote:
> On 04/17/2018 10:52 AM, See, Chin Liang wrote:
> > 
> > On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote:
> > > 
> > > On 04/17/2018 10:40 AM, See, Chin Liang wrote:
> > > > 
> > > > 
> > > > Hi Marek,
> > > > 
> > > > On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > The Arria10 uses slightly different boot image header than
> > > > > the
> > > > > Gen5
> > > > > SoCs,
> > > > > in particular the header itself contains an offset from the
> > > > > start
> > > > > of
> > > > > the
> > > > > header to which the Arria10 jumps. This offset must not be
> > > > > negative,
> > > > > yet
> > > > > the header is placed at offset 0x40 of the bootable binary.
> > > > > Therefore, to
> > > > > jump into U-Boot, add a trampoline just past the Arria10 boot
> > > > > header
> > > > > and
> > > > > point to this trampoline at fixed offset from the header
> > > > > generated
> > > > > using
> > > > > the mkimage -T socfpgaimage_v1 . Note that it is not needed
> > > > > to
> > > > > jump
> > > > > back
> > > > > to offset 0x0 of the image, it is possible to jump directly
> > > > > at
> > > > > the
> > > > > reset
> > > > > label and save processing two instructions.
> > > > > 
> > > > > Signed-off-by: Marek Vasut 
> > > > > Cc: Dinh Nguyen 
> > > > > Cc: Chin Liang See 
> > > > > ---
> > > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
> > > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > index d6b9435d33..06bbe27d2c 100644
> > > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > @@ -18,10 +18,10 @@ _start:
> > > > >   .word   0xcafec0d3; /* Checksum, zero-
> > > > > pad */
> > > > >   nop;
> > > > >  
> > > > > - b reset;/* SoCFPGA jumps here */
> > > > > - nop;
> > > > > + b reset;/* SoCFPGA Gen5 jumps here
> > > > > */
> > > > >   nop;
> > > > >   nop;
> > > > > + b reset;/* SoCFPGA Gen10 trampoline
> > > > > */
> > > > Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder
> > > > can
> > > > we
> > > > standardize that by using 0x14 instead of proposed 0x18 in this
> > > > patch?
> > > What difference does it make, the entire image is generated
> > > during
> > > the
> > > build anyway ? This patch uses offset 0x1c, but what is the
> > > reason
> > > for
> > > address 0x14 in your proprietary tool, is there one ?
> > Our A10 header ended at 0x13 today. Hence we are continuing the
> > code at
> > 0x14 without any spacing.
> > 
> > While for 0x1c, should it be 3 nop?
> Yes, gives enough space were the header grow for whatever reason.
> Mind
> you, the NOPs are not executed, the socfpga jumps to 0x1c directly
> via
> 0x0c -- Image entry offset

Ok, I don't have strong objection on this. We can claim that we don't
support use case where we use mkpimage tools from SCOEDS to sign SPL
binary from mainstream.

Acked-By: Chin Liang See 


Thanks
Chin Liang
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Re: [U-Boot] [PATCH 1/1] sunxi: R40: add support for gigabit ethernet

2018-04-17 Thread Maxime Ripard
Hi Lothar,

On Thu, Apr 12, 2018 at 08:19:03PM +0200, Lothar Felten wrote:
> This patch adds support for the gigabit interface found on the
> Allwinner R40/V40 CPU.
> It does not support the 100Mbit interface (EMAC).
> 
> Fixes:
> - add GMAC gating clock and reset control
> - GPIO mux settings
> - device tree entries
> 
> Tested on BananaPi M2 Berry (R40), custom board (V40).
> 
> Signed-off-by: Lothar Felten 
> ---
>  arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts  | 14 ++
>  arch/arm/dts/sun8i-r40.dtsi   | 37 
> +++
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++-
>  board/sunxi/gmac.c|  5 +++-
>  configs/Bananapi_M2_Ultra_defconfig   |  4 +++
>  drivers/net/sun8i_emac.c  |  2 ++
>  6 files changed, 70 insertions(+), 2 deletions(-)

This patch looks mostly correct, but it should be split into multiple,
smaller patches, one per logical change. This would mean something like:
  - One to add the clock / reset changes
  - One to add the pinctrl change
  - One to add the DTSI bits
  - And one to enable it on the BPI M2-U (with the config and DTS changes).

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com


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Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

2018-04-17 Thread Marek Vasut
On 04/17/2018 11:11 AM, See, Chin Liang wrote:
> On Tue, 2018-04-17 at 11:01 +0200, Marek Vasut wrote:
>> On 04/17/2018 10:52 AM, See, Chin Liang wrote:
>>>
>>> On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote:

 On 04/17/2018 10:40 AM, See, Chin Liang wrote:
>
>
> Hi Marek,
>
> On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
>>
>>
>> The Arria10 uses slightly different boot image header than
>> the
>> Gen5
>> SoCs,
>> in particular the header itself contains an offset from the
>> start
>> of
>> the
>> header to which the Arria10 jumps. This offset must not be
>> negative,
>> yet
>> the header is placed at offset 0x40 of the bootable binary.
>> Therefore, to
>> jump into U-Boot, add a trampoline just past the Arria10 boot
>> header
>> and
>> point to this trampoline at fixed offset from the header
>> generated
>> using
>> the mkimage -T socfpgaimage_v1 . Note that it is not needed
>> to
>> jump
>> back
>> to offset 0x0 of the image, it is possible to jump directly
>> at
>> the
>> reset
>> label and save processing two instructions.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Dinh Nguyen 
>> Cc: Chin Liang See 
>> ---
>>  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
>> b/arch/arm/mach-socfpga/include/mach/boot0.h
>> index d6b9435d33..06bbe27d2c 100644
>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
>> @@ -18,10 +18,10 @@ _start:
>>  .word   0xcafec0d3; /* Checksum, zero-
>> pad */
>>  nop;
>>  
>> -b reset;/* SoCFPGA jumps here */
>> -nop;
>> +b reset;/* SoCFPGA Gen5 jumps here
>> */
>>  nop;
>>  nop;
>> +b reset;/* SoCFPGA Gen10 trampoline
>> */
> Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder
> can
> we
> standardize that by using 0x14 instead of proposed 0x18 in this
> patch?
 What difference does it make, the entire image is generated
 during
 the
 build anyway ? This patch uses offset 0x1c, but what is the
 reason
 for
 address 0x14 in your proprietary tool, is there one ?
>>> Our A10 header ended at 0x13 today. Hence we are continuing the
>>> code at
>>> 0x14 without any spacing.
>>>
>>> While for 0x1c, should it be 3 nop?
>> Yes, gives enough space were the header grow for whatever reason.
>> Mind
>> you, the NOPs are not executed, the socfpga jumps to 0x1c directly
>> via
>> 0x0c -- Image entry offset
> 
> Ok, I don't have strong objection on this. We can claim that we don't
> support use case where we use mkpimage tools from SCOEDS to sign SPL
> binary from mainstream.

Which you can, why wouldn't it work ?

What is the benefit of using mkpimage if mkimage does the same thing
though ?

And what do you mean by "signing" ?

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] reset: fix reset_get_bulk when phandle error

2018-04-17 Thread Neil Armstrong
This fixes the Coverity Defect CID 175348 when dev_count_phandle_with_args()
returns a negative value.

Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset 
signals")
Signed-off-by: Neil Armstrong 
---
 drivers/reset/reset-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 9a5c9c9..fa4f653 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -88,8 +88,8 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk 
*bulk)
bulk->count = 0;
 
count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
-   if (!count)
-   return 0;
+   if (count < 1)
+   return count;
 
bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
GFP_KERNEL);
-- 
2.7.4

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[U-Boot] [PATCH] clk: fix clk_get_bulk when phandle error

2018-04-17 Thread Neil Armstrong
This fixes the Coverity Defect CID 175347 when dev_count_phandle_with_args()
returns a negative value.

Fixes: a855be87da49 ("clk: Add get/enable/disable/release for a bulk of clocks")
Signed-off-by: Neil Armstrong 
---
 drivers/clk/clk-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 6e99b3b..53f418b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -111,8 +111,8 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
bulk->count = 0;
 
count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
-   if (!count)
-   return 0;
+   if (count < 1)
+   return count;
 
bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
if (!bulk->clks)
-- 
2.7.4

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[U-Boot] Booting Jerry chromebook from eMMC

2018-04-17 Thread Carlo Caione
Hi,
I'm trying to boot a Veyron Jerry chromebook using U-Boot placed in
the eMMC. Booting from SPI using 'chromebook_jerry_defconfig' works
perfectly fine, but I'm hitting a wall when moving from SPI to eMMC
(mostly related to the limited space for the SPL).

Has anyone managed to boot this platform directly from eMMC? Reading
sources and documentation there is explicitly nothing related to boot
this platform from eMMC so I was wondering if this is feasible at all.

Thank you,

-- 
Carlo Caione  |  +44.7384.69.16.04  |  Endless
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Re: [U-Boot] [PATCHv1 02/14] reset: sti: remove request and free functions

2018-04-17 Thread Patrice CHOTARD
Hi Dinh

On 04/14/2018 08:51 PM, Dinh Nguyen wrote:
> The request and free reset functions are not really used for any useful
> purpose but for debugging. We can safely remove them.
> 
> Signed-off-by: Dinh Nguyen 
> ---
>   drivers/reset/sti-reset.c   | 12 
>   drivers/reset/stm32-reset.c | 12 
>   2 files changed, 24 deletions(-)
> 
> diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
> index 0fc5a28..672dd97 100644
> --- a/drivers/reset/sti-reset.c
> +++ b/drivers/reset/sti-reset.c
> @@ -277,16 +277,6 @@ static int sti_reset_program_hw(struct reset_ctl 
> *reset_ctl, int assert)
>   return 0;
>   }
>   
> -static int sti_reset_request(struct reset_ctl *reset_ctl)
> -{
> - return 0;
> -}
> -
> -static int sti_reset_free(struct reset_ctl *reset_ctl)
> -{
> - return 0;
> -}
> -
>   static int sti_reset_assert(struct reset_ctl *reset_ctl)
>   {
>   return sti_reset_program_hw(reset_ctl, true);
> @@ -298,8 +288,6 @@ static int sti_reset_deassert(struct reset_ctl *reset_ctl)
>   }
>   
>   struct reset_ops sti_reset_ops = {
> - .request = sti_reset_request,
> - .free = sti_reset_free,
>   .rst_assert = sti_reset_assert,
>   .rst_deassert = sti_reset_deassert,
>   };
> diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
> index e98f34b..efde745 100644
> --- a/drivers/reset/stm32-reset.c
> +++ b/drivers/reset/stm32-reset.c
> @@ -23,16 +23,6 @@ struct stm32_reset_priv {
>   fdt_addr_t base;
>   };
>   
> -static int stm32_reset_request(struct reset_ctl *reset_ctl)
> -{
> - return 0;
> -}
> -
> -static int stm32_reset_free(struct reset_ctl *reset_ctl)
> -{
> - return 0;
> -}
> -
>   static int stm32_reset_assert(struct reset_ctl *reset_ctl)
>   {
>   struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> @@ -68,8 +58,6 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
>   }
>   
>   static const struct reset_ops stm32_reset_ops = {
> - .request= stm32_reset_request,
> - .free   = stm32_reset_free,
>   .rst_assert = stm32_reset_assert,
>   .rst_deassert   = stm32_reset_deassert,
>   };
> 

Reviewed-by: Patrice Chotard 

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Re: [U-Boot] [PATCHv1 12/14] usb: ehci/ohci: remove reset_free function

2018-04-17 Thread Patrice CHOTARD
Hi Dinh

On 04/14/2018 08:51 PM, Dinh Nguyen wrote:
> The call to free the reset control line is a deadend call that doesn't
> lead to any reset control functionality.
> 
> Also the reset_free() function will be remove in a subsequent patch, so
> remove it here.
> 
> Signed-off-by: Dinh Nguyen 
> ---
>   drivers/usb/host/ehci-generic.c | 1 -
>   drivers/usb/host/ohci-generic.c | 1 -
>   2 files changed, 2 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
> index b012d86..8ed6a27 100644
> --- a/drivers/usb/host/ehci-generic.c
> +++ b/drivers/usb/host/ehci-generic.c
> @@ -133,7 +133,6 @@ static int ehci_usb_probe(struct udevice *dev)
>   if (reset_deassert(&priv->resets[i])) {
>   dev_err(dev, "failed to deassert reset %d\n",
>   i);
> - reset_free(&priv->resets[i]);
>   goto reset_err;
>   }
>   priv->reset_count++;
> diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
> index 5bdd799..f61c0fc 100644
> --- a/drivers/usb/host/ohci-generic.c
> +++ b/drivers/usb/host/ohci-generic.c
> @@ -125,7 +125,6 @@ static int ohci_usb_probe(struct udevice *dev)
>   err = reset_deassert(&priv->resets[i]);
>   if (err) {
>   dev_err(dev, "failed to deassert reset %d\n", 
> i);
> - reset_free(&priv->resets[i]);
>   goto reset_err;
>   }
>   priv->reset_count++;
> 


Reviewed-by: Patrice Chotard 
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[U-Boot] [PATCH] ARC: HSDK: fix cpu frequency value

2018-04-17 Thread Eugeniy Paltsev
CPU on HSDK board runs at 500MHz after preloader so fix
wrong cpu orequency value in hsdk_defconfig in hsdk.

Signed-off-by: Eugeniy Paltsev 
---
 configs/hsdk_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 37f61902d3..844decad2d 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
 CONFIG_TARGET_HSDK=y
 CONFIG_SYS_TEXT_BASE=0x8100
-CONFIG_SYS_CLK_FREQ=10
+CONFIG_SYS_CLK_FREQ=5
 CONFIG_DEFAULT_DEVICE_TREE="hsdk"
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200n8"
-- 
2.14.3

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[U-Boot] [PATCH 1/2] imx6ul: opos6ul: add SPL_DM support

2018-04-17 Thread Sébastien Szymanski
Since commit commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL
support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support
makes the board boot again.

Fixes: commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support")
Signed-off-by: Sébastien Szymanski 
---
 arch/arm/dts/imx6ul-opos6ul.dtsi|  4 ++-
 arch/arm/dts/imx6ul-opos6uldev.dts  |  2 ++
 arch/arm/dts/imx6ul.dtsi|  1 +
 arch/arm/include/asm/arch-mx6/opos6ul.h |  4 ---
 arch/arm/mach-imx/mx6/Kconfig   |  4 +++
 arch/arm/mach-imx/mx6/opos6ul.c | 50 -
 board/armadeus/opos6uldev/board.c   | 20 +
 configs/opos6uldev_defconfig|  5 
 include/configs/opos6uldev.h|  9 ++
 9 files changed, 25 insertions(+), 74 deletions(-)

diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi
index 51095df33a..d51ad4de20 100644
--- a/arch/arm/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/dts/imx6ul-opos6ul.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 Armadeus Systems 
+ * Copyright 2018 Armadeus Systems 
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -99,6 +99,7 @@
 
 /* eMMC */
 &usdhc1 {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
@@ -161,6 +162,7 @@
};
 
pinctrl_usdhc1: usdhc1grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD   0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK   0x10059
diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts 
b/arch/arm/dts/imx6ul-opos6uldev.dts
index 0e59ee57fd..9a51d1e54f 100644
--- a/arch/arm/dts/imx6ul-opos6uldev.dts
+++ b/arch/arm/dts/imx6ul-opos6uldev.dts
@@ -228,6 +228,7 @@
 };
 
 &uart1 {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
@@ -373,6 +374,7 @@
};
 
pinctrl_uart1: uart1grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index b63f5a53ac..d5ce3f13c2 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -194,6 +194,7 @@
#size-cells = <1>;
reg = <0x0200 0x4>;
ranges;
+   u-boot,dm-spl;
 
ecspi1: ecspi@02008000 {
#address-cells = <1>;
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h 
b/arch/arm/include/asm/arch-mx6/opos6ul.h
index b5363850d2..8adff67cea 100644
--- a/arch/arm/include/asm/arch-mx6/opos6ul.h
+++ b/arch/arm/include/asm/arch-mx6/opos6ul.h
@@ -9,8 +9,4 @@
 
 int opos6ul_board_late_init(void);
 
-#ifdef CONFIG_SPL_BUILD
-void opos6ul_setup_uart_debug(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index aa6f5facbf..98ea1f566c 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -73,6 +73,10 @@ config MX6UL_OPOS6UL
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
+   select SPL_DM if SPL
+   select SPL_OF_CONTROL if SPL
+   select SPL_SEPARATE_BSS if SPL
+   select SPL_PINCTRL if SPL
 
 config MX6ULL
select SYS_L2CACHE_OFF
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index 2de1321b56..ef70a7d323 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017 Armadeus Systems
+ * Copyright (C) 2018 Armadeus Systems
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -9,15 +9,12 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -138,12 +135,6 @@ int board_late_init(void)
return opos6ul_board_late_init();
 }
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-   return cfg->esdhc_base == USDHC1_BASE_ADDR;
-}
-
 int dram_init(void)
 {
gd->ram_size = imx_ddr_size();
@@ -153,32 +144,9 @@ int dram_init(void)
 
 #ifdef CONFIG_SPL_BUILD
 #include 
-#include 
 #include 
 #include 
 
-#define USDHC_PAD_CTRL (   \
-   PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
-   PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST   \
-)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-   {USDHC1_BASE_ADDR, 0, 8},
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-   MX6_PAD_SD1_CLK__USDHC

[U-Boot] [PATCH 2/2] imx6ul: opos6ul: in Serial Downloader boot mode use ymodem

2018-04-17 Thread Sébastien Szymanski
Signed-off-by: Sébastien Szymanski 
---
 arch/arm/mach-imx/mx6/opos6ul.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index ef70a7d323..5d39c0bc1b 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -208,6 +208,16 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trasmin = 3750,
 };
 
+void board_boot_order(u32 *spl_boot_list)
+{
+   unsigned int bmode = readl(&src_base->sbmr2);
+
+   if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
+   spl_boot_list[0] = BOOT_DEVICE_UART;
+   else
+   spl_boot_list[0] = spl_boot_device();
+}
+
 static void ccgr_init(void)
 {
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-- 
2.16.1

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[U-Boot] [PATCH v2 1/5] sunxi: R40: add gigabit ethernet clocks

2018-04-17 Thread Lothar Felten
Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU

Signed-off-by: Lothar Felten 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..3ea473c302 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -61,7 +61,11 @@ struct sunxi_ccm_reg {
u32 reserved11;
u32 sata_clk_cfg;   /* 0xc8 SATA clock control (R40 only) */
u32 usb_clk_cfg;/* 0xcc USB clock control */
-   u32 gmac_clk_cfg;   /* 0xd0 GMAC clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+   u32 cir0_clk_cfg;   /* 0xd0 CIR0 clock control (R40 only) */
+#else
+   u32 gmac_clk_cfg;   /* 0xd0 GMAC clock control (not for R40) */
+#endif
u32 reserved12[7];
u32 mdfs_clk_cfg;   /* 0xf0 MDFS clock control */
u32 dram_clk_cfg;   /* 0xf4 DRAM configuration clock control */
@@ -104,7 +108,11 @@ struct sunxi_ccm_reg {
u32 mtc_clk_cfg;/* 0x158 MTC module clock */
u32 mbus0_clk_cfg;  /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg;  /* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+   u32 gmac_clk_cfg;   /* 0x164 GMAC clock control (R40 only) */
+#else
u32 reserved16;
+#endif
u32 mipi_dsi_clk_cfg;   /* 0x168 MIPI DSI clock control */
u32 mipi_csi_clk_cfg;   /* 0x16c MIPI CSI clock control */
u32 reserved17[4];
-- 
2.14.1

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[U-Boot] [PATCH v2 3/5] sunxi: R40: add gigabit ethernet gpio pinmux

2018-04-17 Thread Lothar Felten
Add gpio mux settings for the Allwinner R40/V40 CPU.
The gigabit ethernet interface can only be routed to a fixed set of pins.

Signed-off-by: Lothar Felten 
---
 arch/arm/dts/sun8i-r40.dtsi | 9 +
 drivers/net/sun8i_emac.c| 2 ++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 48ec2e855a..ee22f6eb3a 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -126,6 +126,15 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
 
+   gmac_pins_rgmii: gmac_rgmii {
+   pins =  "PA0", "PA1", "PA2",
+   "PA3", "PA4", "PA5", "PA6",
+   "PA7", "PA8", "PA10",
+   "PA11", "PA12", "PA13",
+   "PA15", "PA16";
+   function = "gmac";
+   };
+
i2c0_pins: i2c0_pins {
pins = "PB0", "PB1";
function = "i2c0";
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index b6e5dafe83..0cb1a697f3 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -68,6 +68,8 @@
 
 #if defined(CONFIG_MACH_SUNXI_H3_H5)
 #define SUN8I_GPD8_GMAC2
+#elif defined(CONFIG_MACH_SUN8I_R40)
+#define SUN8I_GPD8_GMAC5
 #else
 #define SUN8I_GPD8_GMAC4
 #endif
-- 
2.14.1

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[U-Boot] [PATCH v2 2/5] sunxi: R40: add gigabit ethernet reset

2018-04-17 Thread Lothar Felten
Add reset control for the gigabit interface of the Allwinner R40/V40 CPU

Signed-off-by: Lothar Felten 
---
 board/sunxi/gmac.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 826650c89b..b2ede37dc3 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,7 +13,10 @@ void eth_init_board(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
/* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_MACH_SUN8I_R40)
+   setbits_le32(&ccm->ahb_reset1_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+   setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#elif defined(CONFIG_SUNXI_GEN_SUN6I)
setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
 #else
-- 
2.14.1

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[U-Boot] [PATCH v2 4/5] sunxi: R40: add gigabit ethernet devicetree node

2018-04-17 Thread Lothar Felten
Add a device tree node for the Allwinner R40/V40 CPU.
The syscon node is required by the gmac driver.

Signed-off-by: Lothar Felten 
---
 arch/arm/dts/sun8i-r40.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index ee22f6eb3a..93bf811014 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -114,6 +114,12 @@
#size-cells = <1>;
ranges;
 
+   syscon: syscon@1c0 {
+   compatible = "allwinner,sun8i-r40-system-controller",
+   "syscon";
+   reg = <0x01c0 0x1000>;
+   };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
@@ -168,6 +174,28 @@
#size-cells = <0>;
};
 
+   gmac: ethernet@01c5 {
+   compatible = "allwinner,sun8i-h3-emac";
+   syscon = <&syscon>;
+   reg = <0x01c5 0x2000>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   clocks = <&osc24M>, <&osc24M>;
+   clock-names = "stmmaceth", "allwinner_gmac_tx";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_pins_rgmii>;
+   phy-mode = "rgmii";
+   status = "disabled";
+
+   mdio: mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   };
+   };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
-- 
2.14.1

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[U-Boot] [PATCH v2 5/5] configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi M2U

2018-04-17 Thread Lothar Felten
Enable the gigabit ethernet for the Bananapi M2 Ultra board.
Tested on BananaPi M2 Berry (R40), custom board (V40).

Signed-off-by: Lothar Felten 
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++
 configs/Bananapi_M2_Ultra_defconfig  |  4 
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
index ab471ab0bf..25f2112fbf 100644
--- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -67,3 +67,17 @@
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
 };
+
+&gmac {
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_pins_rgmii>;
+   status = "okay";
+   phy-handle = <&rgmii_phy>;
+};
+
+&mdio {
+   rgmii_phy: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <1>;
+   };
+};
diff --git a/configs/Bananapi_M2_Ultra_defconfig 
b/configs/Bananapi_M2_Ultra_defconfig
index 37cc2df5dc..e4e943dc49 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -17,3 +17,7 @@ CONFIG_AXP_DLDO4_VOLT=2500
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_MACPWR="PA17"
-- 
2.14.1

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Re: [U-Boot] [PATCH 2/2] imx6ul: opos6ul: in Serial Downloader boot mode use ymodem

2018-04-17 Thread Fabio Estevam
Hi Sébastien

On Tue, Apr 17, 2018 at 10:41 AM, Sébastien Szymanski
 wrote:
> Signed-off-by: Sébastien Szymanski 

Please provide a commit log.
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[U-Boot] [PATCH] ARC: AXS10x: enable hush shell

2018-04-17 Thread Eugeniy Paltsev
Signed-off-by: Eugeniy Paltsev 
---
 configs/axs101_defconfig | 1 +
 configs/axs103_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 174b80aeed..25b10888ce 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS3,115200n8"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 9530061568..b9d387b88a 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS3,115200n8"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
-- 
2.14.3

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[U-Boot] [PATCH] timer: Add Cadence TTC timer counter support

2018-04-17 Thread Michal Simek
This driver was tested on Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek 
---

 MAINTAINERS |  1 +
 drivers/timer/Kconfig   |  7 +++
 drivers/timer/Makefile  |  1 +
 drivers/timer/cadence-ttc.c | 91 +
 4 files changed, 100 insertions(+)
 create mode 100644 drivers/timer/cadence-ttc.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 44eeefa635ac..227765682160 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,7 @@ F:  drivers/net/zynq_gem.c
 F: drivers/serial/serial_zynq.c
 F: drivers/spi/zynq_qspi.c
 F: drivers/spi/zynq_spi.c
+F: drivers/timer/cadence-ttc.c
 F: drivers/usb/host/ehci-zynq.c
 F: drivers/watchdog/cdns_wdt.c
 F: include/zynqmppl.h
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2c9689672627..8a31397553df 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -52,6 +52,13 @@ config ATMEL_PIT_TIMER
  it is designed to offer maximum accuracy and efficient management,
  even for systems with long response time.
 
+config CADENCE_TTC_TIMER
+   bool "Cadence TTC (Triple Timer Counter)"
+   depends on TIMER
+   help
+ Enables support for the cadence ttc driver. This driver is present
+ on Xilinx Zynq and ZynqMP SoCs.
+
 config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index a6e7832154a1..b8bd68aea0e9 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += timer-uclass.o
 obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
+obj-$(CONFIG_CADENCE_TTC_TIMER)+= cadence-ttc.o
 obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
 obj-$(CONFIG_OMAP_TIMER)   += omap-timer.o
diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c
new file mode 100644
index ..25ba688f1a05
--- /dev/null
+++ b/drivers/timer/cadence-ttc.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CNT_CNTRL_RESETBIT(4)
+
+struct cadence_ttc_regs {
+   u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
+   u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
+   u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
+   u32 counter_cntrl1; /* 0xC - Counter Control 1 */
+   u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
+   u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
+   u32 counter_val1; /* 0x18 - Counter Control 1 */
+   u32 counter_val2; /* 0x1C - Counter Control 2 */
+   u32 counter_val3; /* 0x20 - Counter Control 3 */
+   u32 reserved[15];
+   u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
+   u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
+   u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
+};
+
+struct cadence_ttc_priv {
+   struct cadence_ttc_regs *regs;
+};
+
+static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
+{
+   struct cadence_ttc_priv *priv = dev_get_priv(dev);
+
+   *count = readl(&priv->regs->counter_val1);
+
+   return 0;
+}
+
+static int cadence_ttc_probe(struct udevice *dev)
+{
+   struct cadence_ttc_priv *priv = dev_get_priv(dev);
+
+   /* Disable interrupts for sure */
+   writel(0, &priv->regs->interrupt_enable1);
+   writel(0, &priv->regs->interrupt_enable2);
+   writel(0, &priv->regs->interrupt_enable3);
+
+   /* Make sure that clocks are configured properly without prescaller */
+   writel(0, &priv->regs->clk_cntrl1);
+   writel(0, &priv->regs->clk_cntrl2);
+   writel(0, &priv->regs->clk_cntrl3);
+
+   /* Reset and enable this counter */
+   writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
+
+   return 0;
+}
+
+static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
+{
+   struct cadence_ttc_priv *priv = dev_get_priv(dev);
+
+   priv->regs = map_physmem(devfdt_get_addr(dev),
+sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
+
+   return 0;
+}
+
+static const struct timer_ops cadence_ttc_ops = {
+   .get_count = cadence_ttc_get_count,
+};
+
+static const struct udevice_id cadence_ttc_ids[] = {
+   { .compatible = "cdns,ttc" },
+   {}
+};
+
+U_BOOT_DRIVER(cadence_ttc) = {
+   .name   = "cadence_ttc",
+   .id = UCLASS_TIMER,
+   .of_match = cadence_ttc_ids,
+   .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
+   .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
+   .probe = cadence_ttc_probe,
+   .ops= &cadence_ttc_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.17.0

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[U-Boot] [PATCH] ARC: update ARC architecture maintainers

2018-04-17 Thread Eugeniy Paltsev
Update ARC architecture maintainers and add
uboot-snps-...@synopsys.com mailing list.

Signed-off-by: Eugeniy Paltsev 
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 44eeefa635..9f653a0137 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -55,7 +55,9 @@ Maintainers List (try to look for most precise areas first)
---
 ARC
 M: Alexey Brodkin 
+M: Eugeniy Paltsev 
 S: Maintained
+L: uboot-snps-...@synopsys.com
 T: git git://git.denx.de/u-boot-arc.git
 F: arch/arc/
 
-- 
2.14.3

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[U-Boot] [PATCH] db410c: set clk node to be probed before relocation

2018-04-17 Thread Ramon Fried
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.

Signed-off-by: Ramon Fried 
---
 arch/arm/dts/dragonboard410c.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 5ccfe7f8c8..f37ef5d523 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -38,12 +38,14 @@
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0x>;
compatible = "simple-bus";
+   u-boot,dm-pre-reloc;
 
clkc: qcom,gcc@180 {
compatible = "qcom,gcc-apq8016";
reg = <0x180 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
+   u-boot,dm-pre-reloc;
};
 
serial@78b {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[U-Boot] [PATCH] mach-snapdragon: Fix UART clock flow

2018-04-17 Thread Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried 
---
 arch/arm/mach-snapdragon/clock-apq8016.c  | 19 ---
 arch/arm/mach-snapdragon/clock-apq8096.c  |  4 ++--
 arch/arm/mach-snapdragon/clock-snapdragon.c   | 17 -
 arch/arm/mach-snapdragon/clock-snapdragon.h   |  9 +++--
 .../arm/mach-snapdragon/include/mach/sysmap-apq8016.h |  1 +
 5 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
index a2424178c6..f3c486182f 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -18,7 +18,6 @@
 
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(17)
-#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
 static const struct bcr_regs sdc_regs[] = {
{
@@ -37,11 +36,17 @@ static const struct bcr_regs sdc_regs[] = {
}
 };
 
-static struct gpll0_ctrl gpll0_ctrl = {
+static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
-   .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+   .vote_bit = BIT(0),
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+   .cbcr_reg = BLSP1_AHB_CBCR,
+   .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+   .vote_bit = BIT(10),
 };
 
 /* SDHCI */
@@ -56,7 +61,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, 
uint rate)
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, &gpll0_ctrl);
+   clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
 
return rate;
@@ -73,12 +78,12 @@ static const struct bcr_regs uart2_regs = {
 /* UART: 115200 */
 static int clk_init_uart(struct msm_clk_priv *priv)
 {
-   /* Enable iface clk */
-   clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+   /* Enable AHB clock */
+   clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, &gpll0_ctrl);
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
 
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c 
b/arch/arm/mach-snapdragon/clock-apq8096.c
index 3d363d4d66..bc99572a4c 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -28,7 +28,7 @@ static const struct bcr_regs sdc_regs = {
.D = SDCC2_D,
 };
 
-static const struct gpll0_ctrl gpll0_ctrl = {
+static const struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
@@ -42,7 +42,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, &gpll0_ctrl);
+   clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
 
return rate;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c 
b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 899b5ba6ce..20902088f3 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -31,7 +31,7 @@ void clk_enable_cbc(phys_addr_t cbcr)
;
 }
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
 {
if (readl(base + gpll0->status) & gpll0->status_bit)
return; /* clock already enabled */
@@ -42,6 +42,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct 
gpll0_ctrl *gpll0)
;
 }
 
+#define BRANCH_ON_VAL (0)
+#define BRANCH_NOC_FSM_ON_VAL BIT(29)
+#define BRANCH_CHECK_MASK GENMASK(31, 28)
+
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
+{
+   u32 val;
+
+   setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
+   do {
+   val = readl(base + vclk->cbcr_reg);
+   val &= BRANCH_CHECK_MASK;
+   } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+}
+
 #define APPS_CMD_RGCR_UPDATE BIT(0)
 
 /* Update clock command via CMD_RGCR */
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h 
b/arch/arm/mach-snapdragon/clock-snapdragon.h
index d7026aa867..1023324e1a 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -12,13 +

Re: [U-Boot] [PATCH] fit: skip signature verification if board request

2018-04-17 Thread Quentin Schulz
Hi,

On Wed, Apr 11, 2018 at 11:13:05PM +0800, Jun Nie wrote:
> It may be unnecessary to check signature on unlocked board.
> Get the hint from platform specific code to support secure boot
> and non-secure boot with the same binary, so that boot is not
> blocked if board is not locked and has no key for signature
> verification.
> 

Isn't it what the environment variable `verify` is made for?

i.e. setting verify=no will skip checks and boot an image even though it
isn't signed or hash/signature does not match.

I may be missing some context here, so please ignore if it's not what
you're after.

BTW, I saw that you were speaking of reading the lock fuse to decide
whether to check the signature or not. I'd like to have at least a
bypass option for this as it would be horribly tedious for
debugging/development purposes. E.g. I want to be able to boot from an
unverified U-Boot binary a signed (and checked) fitImage so that I can
validate everything works as it should before locking down the
bootloader.

Regards,
Quentin

> Signed-off-by: Jun Nie 
> ---
>  common/image-sig.c | 17 +
>  1 file changed, 17 insertions(+)
> 
> diff --git a/common/image-sig.c b/common/image-sig.c
> index d9f712f..f3d1252 100644
> --- a/common/image-sig.c
> +++ b/common/image-sig.c
> @@ -151,6 +151,11 @@ struct image_region *fit_region_make_list(const void 
> *fit,
>   return region;
>  }
>  
> +int __attribute__((weak)) fit_board_skip_sig_verification(void)
> +{
> + return 0;
> +}
> +
>  static int fit_image_setup_verify(struct image_sign_info *info,
>   const void *fit, int noffset, int required_keynode,
>   char **err_msgp)
> @@ -188,6 +193,12 @@ int fit_image_check_sig(const void *fit, int noffset, 
> const void *data,
>   uint8_t *fit_value;
>   int fit_value_len;
>  
> + /* Skip verification if board says that */
> + if (fit_board_skip_sig_verification()) {
> + printf("signature check skipped\n");
> + return 0;
> + }
> +
>   *err_msgp = NULL;
>   if (fit_image_setup_verify(&info, fit, noffset, required_keynode,
>  err_msgp))
> @@ -438,6 +449,12 @@ int fit_config_verify_required_sigs(const void *fit, int 
> conf_noffset,
>   int noffset;
>   int sig_node;
>  
> + /* Skip verification if board says that */
> + if (fit_board_skip_sig_verification()) {
> + printf("signature check skipped\n");
> + return 0;
> + }
> +
>   /* Work out what we need to verify */
>   sig_node = fdt_subnode_offset(sig_blob, 0, FIT_SIG_NODENAME);
>   if (sig_node < 0) {
> -- 
> 2.7.4
> 
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Re: [U-Boot] [PATCH] kbuild: use -fmacro-prefix-map to make __FILE__ a relative path

2018-04-17 Thread Simon Glass
On 15 April 2018 at 22:18, Masahiro Yamada
 wrote:
>
> The __FILE__ macro is used everywhere in U-Boot to locate the file
> printing the log message, such as WARN_ON(), etc.  If U-Boot is
> built out of tree, this can be a long absolute path.
>
> This is because Kbuild runs in the objtree instead of the srctree,
> then __FILE__ is expanded to a file path prefixed with $(srctree)/.
>
> A brand-new option from GCC, -fmacro-prefix-map, solves this problem.
> If your compiler supports it, __FILE__ is the relative path from the
> srctree regardless of O= option.  This provides more readable log,
> more reproducible builds, and smaller image size.
>
> [ Linux commit: a73619a845d5625079cc1b3b820f44c899618388 ]
>
> Signed-off-by: Masahiro Yamada 
> ---
>
> GCC 8 is required to use this new option.
>
>
>  Makefile | 3 +++
>  1 file changed, 3 insertions(+)
>

Great!

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v4] arm64: Add SMC and HVC commands

2018-04-17 Thread Simon Glass
On 13 April 2018 at 01:40, Michalis Pappas  wrote:
> This patch adds smc and hvc commands, that allow issuing Secure Monitor
> Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.
>
> Add Kconfig items to allow each command can be individually enabled.
>
> Signed-off-by: Michalis Pappas 
> ---
>
> Changes for v2:
>   - Update help message with additional information on usefulness
>   - Remove default=n from Kconfig
>
> Changes for v3:
>   - Replace dependency on ARM64 with ARM_SMCCC in Kconfig
>
> Changes for v4:
>   - Add list of changes
>
>  cmd/Kconfig  | 14 ++
>  cmd/Makefile |  2 ++
>  cmd/smccc.c  | 72 
>  3 files changed, 88 insertions(+)
>  create mode 100644 cmd/smccc.c

Thanks.

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/1] env: mmc/fat/ext4: undefined reference to `mmc_initialize'

2018-04-17 Thread Simon Glass
On 14 April 2018 at 07:41, Heinrich Schuchardt  wrote:
> For CONFIG_ENV_FAT_INTERFACE != 'mmc' a link error
> env/fat.c:93: undefined reference to `mmc_initialize'
> occurs if CONFIG_MMC_SUPPORT is not enabled.
>
> Fixes: 26862b4a40c3 ("env: mmc/fat/ext4: make sure that the MMC sub-system
> is initialized before using it")
> Signed-off-by: Heinrich Schuchardt 
> ---
>  env/ext4.c | 2 ++
>  env/fat.c  | 2 ++
>  2 files changed, 4 insertions(+)

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Re: [U-Boot] [PATCH v5 2/2] timer: Add High Precision Event Timers (HPET) support

2018-04-17 Thread Simon Glass
Hi Bin,

On 15 April 2018 at 23:06, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Apr 13, 2018 at 12:42 AM, Simon Glass  wrote:
>> Hi,
>>
>> On 8 April 2018 at 19:22, Bin Meng  wrote:
>>> Hi Ivan,
>>>
>>> On Sat, Apr 7, 2018 at 3:18 AM, Ivan Gorinov  wrote:
 Add HPET driver as an alternative timer for x86 (default is TSC).
 HPET counter has constant frequency and does not need calibration.
 This change also makes TSC timer driver optional on x86.
 New HPET driver can also be selected as the early timer on x86.

 HPET can be selected as the tick timer in the Device Tree "chosen" node:

 /include/ "hpet.dtsi"

 ...

 chosen {
 tick-timer = "/hpet";
 };

 Signed-off-by: Ivan Gorinov 
 ---
  arch/Kconfig   |   2 +-
  arch/x86/Kconfig   |  21 ++
  arch/x86/dts/hpet.dtsi |   7 ++
  drivers/timer/Kconfig  |   9 +++
  drivers/timer/Makefile |   1 +
  drivers/timer/hpet_timer.c | 179 
 +
  drivers/timer/tsc_timer.c  |   8 ++
  7 files changed, 226 insertions(+), 1 deletion(-)
  create mode 100644 arch/x86/dts/hpet.dtsi
  create mode 100644 drivers/timer/hpet_timer.c

>>
>> [..]
 diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
 index 9296de6..bd0e75c 100644
 --- a/drivers/timer/tsc_timer.c
 +++ b/drivers/timer/tsc_timer.c
 @@ -277,6 +277,8 @@ success:
 return delta / 1000;
  }

 +#ifdef CONFIG_X86_EARLY_TIMER_TSC
>>>
>>> Why do we surround the following APIs with CONFIG_X86_EARLY_TIMER_TSC?
>>> These APIs are generic U-Boot timer APIs. If we select
>>> CONFIG_X86_EARLY_TIMER_HPET, these APIs are not available and will
>>> cause build error.
>>>
>>> Simon, do you think we should fix such in the timer uclass driver?
>>
>> We should not have arch-specific code in the uclass, or in any generic 
>> driver.
>
> What I meant is these APIs like get_timer(). Can such APIs be moved to
> timer uclass driver? To avoid conflicts with other timer drivers, in
> this patch it was solved by using the config option
> CONFIG_X86_EARLY_TIMER_TSC to hide this in the TSC driver, which does

Well get_timer() just calls get_ticks() which uses DM, so what exactly
are you proposing here?

> not make sense.
>
> Regards,
> Bin

Regards,
Simon
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Re: [U-Boot] [PATCH v10 3/3] Adding wget

2018-04-17 Thread Simon Glass
Hi Duncan,

On 14 April 2018 at 17:43,   wrote:
> From: Duncan Hare 
>
> Why http and wget:
>
> HTTP is the most efficient file retrieval protocol in common
> use. The client send a single request, after TCP connection,
> to receive a file of any length.
>
> WGET is the application which implements http file transfer
> outside browsers as a file transfer protocol. Versions of
> wget exists on many operating systems.
> END

Why END?

>
> Signed-off-by: Duncan Hare 
> ---
>
> Changes in v10: None

There is no change log here. Has nothing changed since v1?

This code looks OK to me, but please can you run it through patman? I
see what look like some style errors.

How can we create a test for this? Can we add something to test_net.py ?

Regards,
Simon
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Re: [U-Boot] [RFC][PATCH] cmd: fdt: Fix fdt address information after the movement

2018-04-17 Thread Simon Glass
Hi Marek,

On 13 April 2018 at 16:07, Marek Vasut  wrote:
> On 04/01/2018 04:14 PM, Simon Glass wrote:
>> Hi Marek,
>
> Hi,
>
>> On 24 February 2018 at 19:09, Marek Vasut  wrote:
>>> From: Hiroyuki Yokoyama 
>>>
>>> This patch fixes the address information of fdt.
>>>
>>> wrong case:
>>>  => fdt addr 0x4800
>>>  => fdt move 0x4800 0x4100 0xa000
>>>  => fdt addr
>>> The address of the fdt is 4800
>>>
>>> Active address in this case is 0x4100.
>>>
>>> Signed-off-by: Hiroyuki Yokoyama 
>>> Signed-off-by: Marek Vasut 
>>> Cc: Hiroyuki Yokoyama 
>>> Cc: Nobuhiro Iwamatsu 
>>> Cc: Pantelis Antoniou 
>>> ---
>>>  cmd/fdt.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/cmd/fdt.c b/cmd/fdt.c
>>> index b783b0df42..1245bc24eb 100644
>>> --- a/cmd/fdt.c
>>> +++ b/cmd/fdt.c
>>> @@ -204,6 +204,8 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, 
>>> char * const argv[])
>>> return 1;
>>> }
>>> working_fdt = newaddr;
>>> +   env_set_hex("fdtaddr", (ulong)working_fdt);
>>
>> Shouldn't this be map_to_sysmem(working_fdt)?
>
> Should it ?

Yes, because you are converting a pointer to a ulong address. That's
what that function is for. If you use it, you will allow this code to
work on sandbox.

>
> The other question I have is, is this possibly changing the U-Boot API
> and is that a problem ?

Probably this code should use set_working_fdt_addr() instead. Then we
have all the env_sets in one place.

But no I don't think it is a problem to make this change. After all,
working_fdt should match the 'fdtaddr' environment variable, right?

>
> btw sorry, must've missed this mail.

That's OK, I do that a lot I suspect...

Regards,
Simon
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[U-Boot] [PATCH v2 2/2] imx6ul: opos6ul: in Serial Downloader boot mode use ymodem

2018-04-17 Thread Sébastien Szymanski
When booting in Serial Downloader mode load the U-Boot image using
ymodem.

Signed-off-by: Sébastien Szymanski 
---

Changes for v2:
 - Add commit log.

 arch/arm/mach-imx/mx6/opos6ul.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index ef70a7d323..5d39c0bc1b 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -208,6 +208,16 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trasmin = 3750,
 };
 
+void board_boot_order(u32 *spl_boot_list)
+{
+   unsigned int bmode = readl(&src_base->sbmr2);
+
+   if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
+   spl_boot_list[0] = BOOT_DEVICE_UART;
+   else
+   spl_boot_list[0] = spl_boot_device();
+}
+
 static void ccgr_init(void)
 {
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-- 
2.16.1

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[U-Boot] [PATCH v2 1/2] imx6ul: opos6ul: add SPL_DM support

2018-04-17 Thread Sébastien Szymanski
Since commit commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL
support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support
makes the board boot again.

Fixes: commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support")
Signed-off-by: Sébastien Szymanski 
---

Changes for v2:
 - none

 arch/arm/dts/imx6ul-opos6ul.dtsi|  4 ++-
 arch/arm/dts/imx6ul-opos6uldev.dts  |  2 ++
 arch/arm/dts/imx6ul.dtsi|  1 +
 arch/arm/include/asm/arch-mx6/opos6ul.h |  4 ---
 arch/arm/mach-imx/mx6/Kconfig   |  4 +++
 arch/arm/mach-imx/mx6/opos6ul.c | 50 -
 board/armadeus/opos6uldev/board.c   | 20 +
 configs/opos6uldev_defconfig|  5 
 include/configs/opos6uldev.h|  9 ++
 9 files changed, 25 insertions(+), 74 deletions(-)

diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi
index 51095df33a..d51ad4de20 100644
--- a/arch/arm/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/dts/imx6ul-opos6ul.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 Armadeus Systems 
+ * Copyright 2018 Armadeus Systems 
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -99,6 +99,7 @@
 
 /* eMMC */
 &usdhc1 {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
@@ -161,6 +162,7 @@
};
 
pinctrl_usdhc1: usdhc1grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD   0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK   0x10059
diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts 
b/arch/arm/dts/imx6ul-opos6uldev.dts
index 0e59ee57fd..9a51d1e54f 100644
--- a/arch/arm/dts/imx6ul-opos6uldev.dts
+++ b/arch/arm/dts/imx6ul-opos6uldev.dts
@@ -228,6 +228,7 @@
 };
 
 &uart1 {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
@@ -373,6 +374,7 @@
};
 
pinctrl_uart1: uart1grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index b63f5a53ac..d5ce3f13c2 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -194,6 +194,7 @@
#size-cells = <1>;
reg = <0x0200 0x4>;
ranges;
+   u-boot,dm-spl;
 
ecspi1: ecspi@02008000 {
#address-cells = <1>;
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h 
b/arch/arm/include/asm/arch-mx6/opos6ul.h
index b5363850d2..8adff67cea 100644
--- a/arch/arm/include/asm/arch-mx6/opos6ul.h
+++ b/arch/arm/include/asm/arch-mx6/opos6ul.h
@@ -9,8 +9,4 @@
 
 int opos6ul_board_late_init(void);
 
-#ifdef CONFIG_SPL_BUILD
-void opos6ul_setup_uart_debug(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index aa6f5facbf..98ea1f566c 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -73,6 +73,10 @@ config MX6UL_OPOS6UL
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
+   select SPL_DM if SPL
+   select SPL_OF_CONTROL if SPL
+   select SPL_SEPARATE_BSS if SPL
+   select SPL_PINCTRL if SPL
 
 config MX6ULL
select SYS_L2CACHE_OFF
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index 2de1321b56..ef70a7d323 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017 Armadeus Systems
+ * Copyright (C) 2018 Armadeus Systems
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -9,15 +9,12 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -138,12 +135,6 @@ int board_late_init(void)
return opos6ul_board_late_init();
 }
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-   return cfg->esdhc_base == USDHC1_BASE_ADDR;
-}
-
 int dram_init(void)
 {
gd->ram_size = imx_ddr_size();
@@ -153,32 +144,9 @@ int dram_init(void)
 
 #ifdef CONFIG_SPL_BUILD
 #include 
-#include 
 #include 
 #include 
 
-#define USDHC_PAD_CTRL (   \
-   PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
-   PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST   \
-)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-   {USDHC1_BASE_ADDR, 0, 8},
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-   

[U-Boot] [PATCH] ARC: remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c

2018-04-17 Thread Eugeniy Paltsev
Signed-off-by: Eugeniy Paltsev 
---
 arch/arc/lib/init_helpers.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
index 435fe96ef4..822318ff43 100644
--- a/arch/arc/lib/init_helpers.c
+++ b/arch/arc/lib/init_helpers.c
@@ -7,8 +7,6 @@
 #include 
 #include 
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int init_cache_f_r(void)
 {
sync_n_cleanup_cache_all();
-- 
2.14.3

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Re: [U-Boot] [U-Boot, v2] Kconfig: Enlarge default SYS_MALLOC_F_LEN for AM33XX

2018-04-17 Thread Tom Rini
On Mon, Apr 16, 2018 at 09:22:51PM -0400, Tom Rini wrote:
> On Thu, Apr 12, 2018 at 06:09:58PM +0200, Sjoerd Simons wrote:
> 
> > Since commit 8e14ba7bd524 ("gpio: omap_gpio: Add DM_FLAG_PRE_RELOC
> > flag") omap GPIO gets bound before relocation.  Unfortunately due to
> > this, on at least the beaglebone black, the pre-relocation memory pool
> > gets exhausted before probing the serial port. This then causes u-boot
> > to panic as CONFIG_REQUIRE_SERIAL_CONSOLE is set...
> > 
> > Resolve this by resizing the default size of the pre-relocation malloc
> > pool for AM335X platforms.
> > 
> > Signed-off-by: Sjoerd Simons 
> 
> Applied to u-boot/master, thanks!

That done, a patch on top of this to move ARCH_OMAP2PLUS to 0x2000
instead would be greatly appreciated for post v2018.05, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] ARC: remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c

2018-04-17 Thread Tom Rini
On Tue, Apr 17, 2018 at 07:01:15PM +0300, Eugeniy Paltsev wrote:

> Signed-off-by: Eugeniy Paltsev 
> ---
>  arch/arc/lib/init_helpers.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
> index 435fe96ef4..822318ff43 100644
> --- a/arch/arc/lib/init_helpers.c
> +++ b/arch/arc/lib/init_helpers.c
> @@ -7,8 +7,6 @@
>  #include 
>  #include 
>  
> -DECLARE_GLOBAL_DATA_PTR;
> -
>  int init_cache_f_r(void)
>  {
>   sync_n_cleanup_cache_all();

Interesting.  A quick git grep shows a lot of files like this.  I'm
going to take a stab at a more comprehensive patch.

-- 
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[U-Boot] Please pull ARC fixes for RC3

2018-04-17 Thread Alexey Brodkin
Hi Tom,

The following changes since commit 8c0a17be0a632b9a823e14628c42f85c3e64f08e:

  Prepare v2018.05-rc2 (2018-04-16 20:00:14 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-arc.git tags/arc-for-2018.05-rc3

for you to fetch changes up to 474e9312a803ee36dc984217b6e9b7190eca9865:

  ARC: Remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c (2018-04-17 
20:52:17 +0300)


Subtle ARC fixes for v2018.05-RC3

These are only very subtle clean-ups here and there including:

 * Correctly specified CPU freq for HSDK
   (production boards are all shipped with 500MHZ as opposed
to early batch running at 1GHz)

 * Addition of SNPS internal group email to MAINTAINERS file
 * Switch to Hush shell on AXS10x boards


Eugeniy Paltsev (4):
  ARC: HSDK: Fix CPU frequency value
  ARC: AXS10x: Enable hush shell
  ARC: Update ARC architecture maintainers
  ARC: Remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c

 MAINTAINERS | 2 ++
 arch/arc/lib/init_helpers.c | 2 --
 configs/axs101_defconfig| 1 +
 configs/axs103_defconfig| 1 +
 configs/hsdk_defconfig  | 2 +-
 5 files changed, 5 insertions(+), 3 deletions(-)

-Alexey
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[U-Boot] [PATCH] ARM: rmobile: Update M2 Koelsch

2018-04-17 Thread Marek Vasut
The M2 Koelsch port was broken since some time. This patch updates
the M2 Koelsch port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/r8a7791-koelsch-u-boot.dts |   4 +
 arch/arm/mach-rmobile/Kconfig.32|   3 +
 board/renesas/koelsch/Makefile  |   6 +-
 board/renesas/koelsch/koelsch.c | 187 ---
 board/renesas/koelsch/koelsch_spl.c | 410 
 configs/koelsch_defconfig   |  49 +++-
 include/configs/koelsch.h   |  58 ++---
 7 files changed, 532 insertions(+), 185 deletions(-)
 create mode 100644 board/renesas/koelsch/koelsch_spl.c

diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts 
b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
index 9de45bb52d..58e15a4044 100644
--- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts
+++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
@@ -8,3 +8,7 @@
 
 #include "r8a7791-koelsch.dts"
 #include "r8a7791-u-boot.dtsi"
+
+&scif0 {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index bcadb21ba9..fe123f86ef 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -47,6 +47,9 @@ config TARGET_KOELSCH
bool "Koelsch board"
select DM
select DM_SERIAL
+   select SUPPORT_SPL
+   select USE_TINY_PRINTF
+   select SPL_TINY_MEMSET
 
 config TARGET_LAGER
bool "Lager board"
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
index 15f111c504..77cf067406 100644
--- a/board/renesas/koelsch/Makefile
+++ b/board/renesas/koelsch/Makefile
@@ -6,4 +6,8 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := koelsch.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y  := koelsch_spl.o
+else
+obj-y  := koelsch.o qos.o
+endif
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index e7b47ae299..4a4007b7a3 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -48,13 +48,7 @@ void s_init(void)
qos_init();
 }
 
-#define TMU0_MSTP125   (1 << 25)
-#define SCIF0_MSTP721  (1 << 21)
-#define ETHER_MSTP813  (1 << 13)
-
-#define SDHI0_MSTP314  (1 << 14)
-#define SDHI1_MSTP312  (1 << 12)
-#define SDHI2_MSTP311  (1 << 11)
+#define TMU0_MSTP125   BIT(25)
 
 #define SD1CKCR0xE6150078
 #define SD2CKCR0xE615026C
@@ -64,16 +58,6 @@ int board_early_init_f(void)
 {
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 
-   /* SCIF0 */
-   mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
-   /* ETHER */
-   mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
-   /* SDHI  */
-   mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
- SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
-
/*
 * SD0 clock is set to 97.5MHz by default.
 * Set SD1 and SD2 to the 97.5MHz as well.
@@ -84,133 +68,40 @@ int board_early_init_f(void)
return 0;
 }
 
-/* LSI pin pull-up control */
-#define PUPR5 0xe6060114
-#define PUPR5_ETH 0x3FFC
-#define PUPR5_ETH_MAGIC(1 << 27)
+#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
+
 int board_init(void)
 {
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-   /* Init PFC controller */
-   r8a7791_pinmux_init();
-
-   /* ETHER Enable */
-   gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
-   gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-   gpio_request(GPIO_FN_ETH_RXD0, NULL);
-   gpio_request(GPIO_FN_ETH_RXD1, NULL);
-   gpio_request(GPIO_FN_ETH_LINK, NULL);
-   gpio_request(GPIO_FN_ETH_REFCLK, NULL);
-   gpio_request(GPIO_FN_ETH_MDIO, NULL);
-   gpio_request(GPIO_FN_ETH_TXD1, NULL);
-   gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-   gpio_request(GPIO_FN_ETH_TXD0, NULL);
-   gpio_request(GPIO_FN_ETH_MDC, NULL);
-   gpio_request(GPIO_FN_IRQ0, NULL);
-
-   mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
-   gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
-   mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
-   gpio_direction_output(GPIO_GP_5_22, 0);
-   mdelay(20);
-   gpio_set_value(GPIO_GP_5_22, 1);
-   udelay(1);
+   /* Force ethernet PHY out of reset */
+   gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+   gpio_direction_output(ETHERNET_PHY_RESET, 0);
+   mdelay(10);
+   gpio_direction_output(ETHERNET_PHY_RESET, 1);
 
return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
 {
-#ifdef CONFIG_SH_ETHER
-   int ret = -ENODEV;
-   u32 val;
-   unsigned char enetaddr[6];
-
-   ret = sh_eth_initialize(bis);
-   if (!eth_env_get

[U-Boot] u-boot-usb/master build failure on dra7xx_evm

2018-04-17 Thread Marek Vasut
Hi,

can you look at this build problem in u-boot-usb/master on dra7xx_evm
and send me a patch?

https://travis-ci.org/marex/u-boot-usb/jobs/367566783

u-boot-usb$ bu dra7xx_evm
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:62: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or declaration
 static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
  ^~~~
include/reset.h:287:45: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or declaration
 static inline int reset_release_bulk(struct clk_bulk *bulk)
 ^~~~
drivers/usb/host/dwc3-of-simple.c: In function ‘dwc3_of_simple_reset_init’:
drivers/usb/host/dwc3-of-simple.c:32:28: warning: passing argument 2 of
‘reset_get_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
  ret = reset_get_bulk(dev, &simple->resets);
^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
 static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
   ^~
drivers/usb/host/dwc3-of-simple.c:40:22: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
   reset_release_bulk(&simple->resets);
  ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
 static inline int reset_release_bulk(struct clk_bulk *bulk)
   ^~
drivers/usb/host/dwc3-of-simple.c: In function ‘dwc3_of_simple_remove’:
drivers/usb/host/dwc3-of-simple.c:89:21: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
  reset_release_bulk(&simple->resets);
 ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
 static inline int reset_release_bulk(struct clk_bulk *bulk)

-- 
Best regards,
Marek Vasut
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[U-Boot] [PULL] u-boot-socfpga/master

2018-04-17 Thread Marek Vasut
The following changes since commit 8c0a17be0a632b9a823e14628c42f85c3e64f08e:

  Prepare v2018.05-rc2 (2018-04-16 20:00:14 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to f369e1564cf4f81654b8a806fdc325b62b6627dc:

  configs: socfpga: disable EFI and ISO partition types (2018-04-17
11:39:50 +0200)


Chin Liang See (1):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC

Dinh Nguyen (9):
  ARM64: stratix10: add reset manager includes
  ARM: dts: stratix10: Add base dtsi and devkit dts
  reset: socfpga: add reset driver for SoCFPGA platform
  configs: socfpga: convert i2c to dm
  arm: dts: socfpga: enables i2c0 in socfpga_de0_nano
  arm: dts: socfpga: add reset property
  i2c: designware: add reset ctrl to driver
  configs: socfpga: add DM_RESET
  configs: socfpga: disable EFI and ISO partition types

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/socfpga.dtsi  |  12 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts |  12 +
 arch/arm/dts/socfpga_stratix10.dtsi| 381

 arch/arm/dts/socfpga_stratix10_socdk.dts   |  92
+
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  33 
 configs/socfpga_arria10_defconfig  |   2 +
 configs/socfpga_arria5_defconfig   |   4 ++
 configs/socfpga_cyclone5_defconfig |   4 ++
 configs/socfpga_dbm_soc1_defconfig |   4 ++
 configs/socfpga_de0_nano_soc_defconfig |   4 ++
 configs/socfpga_de10_nano_defconfig|   4 ++
 configs/socfpga_de1_soc_defconfig  |   4 ++
 configs/socfpga_is1_defconfig  |   4 ++
 configs/socfpga_mcvevk_defconfig   |   4 ++
 configs/socfpga_sockit_defconfig   |   4 ++
 configs/socfpga_socrates_defconfig |   4 ++
 configs/socfpga_sr1500_defconfig   |   4 ++
 configs/socfpga_vining_fpga_defconfig  |   3 ++
 drivers/i2c/designware_i2c.c   |  10 
 drivers/reset/Kconfig  |   7 +++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-socfpga.c  | 105
++
 include/configs/socfpga_common.h   |   2 +
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97
+++
 25 files changed, 802 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 drivers/reset/reset-socfpga.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h
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Re: [U-Boot] u-boot-usb/master build failure on dra7xx_evm

2018-04-17 Thread Jean-Jacques Hiblot

Hi Marek,

that should be fixed by applying https://patchwork.ozlabs.org/patch/897532/

JJ

On 17/04/2018 20:25, Marek Vasut wrote:

Hi,

can you look at this build problem in u-boot-usb/master on dra7xx_evm
and send me a patch?

https://travis-ci.org/marex/u-boot-usb/jobs/367566783

u-boot-usb$ bu dra7xx_evm
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:62: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or declaration
  static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
   ^~~~
include/reset.h:287:45: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or declaration
  static inline int reset_release_bulk(struct clk_bulk *bulk)
  ^~~~
drivers/usb/host/dwc3-of-simple.c: In function ‘dwc3_of_simple_reset_init’:
drivers/usb/host/dwc3-of-simple.c:32:28: warning: passing argument 2 of
‘reset_get_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
   ret = reset_get_bulk(dev, &simple->resets);
 ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
^~
drivers/usb/host/dwc3-of-simple.c:40:22: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
reset_release_bulk(&simple->resets);
   ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_release_bulk(struct clk_bulk *bulk)
^~
drivers/usb/host/dwc3-of-simple.c: In function ‘dwc3_of_simple_remove’:
drivers/usb/host/dwc3-of-simple.c:89:21: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
   reset_release_bulk(&simple->resets);
  ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_release_bulk(struct clk_bulk *bulk)



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Re: [U-Boot] u-boot-usb/master build failure on dra7xx_evm

2018-04-17 Thread Jean-Jacques Hiblot



On 17/04/2018 20:35, Jean-Jacques Hiblot wrote:

Hi Marek,

that should be fixed by applying 
https://patchwork.ozlabs.org/patch/897532/

You should also apply https://patchwork.ozlabs.org/patch/897537/
Without it the probe fails on dra7xx-evm


JJ

On 17/04/2018 20:25, Marek Vasut wrote:

Hi,

can you look at this build problem in u-boot-usb/master on dra7xx_evm
and send me a patch?

https://travis-ci.org/marex/u-boot-usb/jobs/367566783

u-boot-usb$ bu dra7xx_evm
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:62: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or 
declaration

  static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
^~~~
include/reset.h:287:45: warning: ‘struct clk_bulk’ declared inside
parameter list will not be visible outside of this definition or 
declaration

  static inline int reset_release_bulk(struct clk_bulk *bulk)
  ^~~~
drivers/usb/host/dwc3-of-simple.c: In function 
‘dwc3_of_simple_reset_init’:

drivers/usb/host/dwc3-of-simple.c:32:28: warning: passing argument 2 of
‘reset_get_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
   ret = reset_get_bulk(dev, &simple->resets);
 ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:246:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk
*bulk)
    ^~
drivers/usb/host/dwc3-of-simple.c:40:22: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
    reset_release_bulk(&simple->resets);
   ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_release_bulk(struct clk_bulk *bulk)
    ^~
drivers/usb/host/dwc3-of-simple.c: In function ‘dwc3_of_simple_remove’:
drivers/usb/host/dwc3-of-simple.c:89:21: warning: passing argument 1 of
‘reset_release_bulk’ from incompatible pointer type
[-Wincompatible-pointer-types]
   reset_release_bulk(&simple->resets);
  ^
In file included from drivers/usb/host/dwc3-of-simple.c:17:0:
include/reset.h:287:19: note: expected ‘struct clk_bulk *’ but argument
is of type ‘struct reset_ctl_bulk *’
  static inline int reset_release_bulk(struct clk_bulk *bulk)



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Re: [U-Boot] [PATCH] x86: Use microcode update from device tree for all processors

2018-04-17 Thread Ivan Gorinov
On Thu, Apr 05, 2018 at 09:31:34AM -0600, Bin Meng wrote:
> > The microcode update data block encoded in Device Tree is used by
> > the bootstrap processor (BSP) but not passed to the other CPUs (AP).
> 
> I don't understand what the bug is here. The AP microcode update is
> done in sipi_vector.S.

I have found how it works. When a ROM image is built, the binman tool
looks for symbol '_dt_ucode_base_size' and updates position and size
of the microcode update data in the ucode_base and ucode_size variables.
The ucode_base pointer is used to update the bootstrap CPU very early,
and the other CPUs later in the multiprocessing code.

On x86, binman is called from Makefile only if a ROM image is created:

u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
...
$(call if_changed,binman)

If there is no ROM image, ucode_base and ucode_size are not initialized and
the microcode update data from DTB applied by microcode_update_intel() to the
bootstrap CPU is not used by the multiprocessing code.
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Re: [U-Boot] u-boot-usb/master build failure on dra7xx_evm

2018-04-17 Thread Marek Vasut
On 04/17/2018 08:38 PM, Jean-Jacques Hiblot wrote:
> 
> 
> On 17/04/2018 20:35, Jean-Jacques Hiblot wrote:
>> Hi Marek,
>>
>> that should be fixed by applying
>> https://patchwork.ozlabs.org/patch/897532/
> You should also apply https://patchwork.ozlabs.org/patch/897537/
> Without it the probe fails on dra7xx-evm

That one is already applied.

The reset fix is for Tom to pick I think.

-- 
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Marek Vasut
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[U-Boot] Network Packet Buffers: raspberrypi: variable uchar *net_rx_packets[PKTBUFSRX] in net/net.c

2018-04-17 Thread Duncan Hare
Simon

Is it possible to modify the network driver for the raspberry pi to use
the buffer pool defined in net.c?

It appears to have a single buffer, defined in the driver.

In addition the buffer pool should be defined in memory outside the
u-boot image. With the current definition is the buffer pool a
part of the u-boot image?

Thanks
Duncan Hare

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[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

2018-04-17 Thread Ronak Desai
Corrected the chip selection in IFC_NAND_CSEL register. Due to this
issue in multi-chip nand use-case, IFC was always pointing to the last
probed chip even though user select another device through "nand device
" command.

Also, updated the driver to remove usage of ifc_ctrl->cs_nand as it's
the property of chip not the controller.

Signed-off-by: Ronak Desai 
---
 drivers/mtd/nand/fsl_ifc_nand.c |   15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 495e3aa..2d0ca54 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -48,7 +48,6 @@ struct fsl_ifc_ctrl {
/* device info */
struct fsl_ifc regs;
void __iomem *addr;  /* Address of assigned IFC buffer*/
-   unsigned int cs_nand;/* On which chipsel NAND is connected*/
unsigned int page;   /* Last page written to / read from  */
unsigned int read_bytes; /* Number of bytes read during command   */
unsigned int column; /* Saved column from SEQIN   */
@@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
int i;

/* set the chip select for NAND Transaction */
-   ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+   ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);

/* start read/write seq */
ifc_out32(&ifc->ifc_nand.nandseq_strt,
@@ -821,7 +820,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int 
chip)
 {
 }

-static int fsl_ifc_sram_init(uint32_t ver)
+static int fsl_ifc_sram_init(uint32_t ver, struct fsl_ifc_mtd *priv)
 {
struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
@@ -846,7 +845,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
return 1;
}

-   cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
+   cs = priv->bank;

/* Save CSOR and CSOR_ext */
csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
@@ -873,7 +872,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
ifc_out32(&ifc->ifc_nand.col0, 0x0);

/* set the chip select for NAND Transaction */
-   ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+   ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);

/* start read seq */
ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
@@ -934,10 +933,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);

if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
-   (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
-   ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
+   (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
break;
-   }
}

if (priv->bank >= MAX_BANKS) {
@@ -1052,7 +1049,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)

ver = ifc_in32(&gregs->ifc_rev);
if (ver >= FSL_IFC_V1_1_0)
-   ret = fsl_ifc_sram_init(ver);
+   ret = fsl_ifc_sram_init(ver, priv);
if (ret)
return ret;

--
1.7.9.5

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[U-Boot] [PATCH] Added set feature command in FSL IFC nand controller driver for ONFI nand

2018-04-17 Thread Ronak Desai
This patch adds set feature command (EFh) support in Freescale IFC nand
controller driver.

The SET FEATURES (EFh) command is used to modify the target's default
power-on behavior. This command uses one-byte feature address to
determine which sub-feature parameters will be modified.

Signed-off-by: Ronak Desai 
---
 drivers/mtd/nand/fsl_ifc_nand.c |   51 +++
 1 file changed, 51 insertions(+)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index c93dbb0..45cba52 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -596,6 +596,23 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned 
int command,
fsl_ifc_run_command(mtd);
return;

+   case NAND_CMD_SET_FEATURES: {
+   ifc_out32(&ifc->ifc_nand.nand_fir0,
+   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+   (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
+   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP2_SHIFT));
+
+   ifc_out32(&ifc->ifc_nand.nand_fcr0,
+   (NAND_CMD_SET_FEATURES << IFC_NAND_FCR0_CMD0_SHIFT));
+
+   ifc_out32(&ifc->ifc_nand.row3, column);
+
+/* Write only 4 bytes from flash buffer */
+   ifc_out32(&ifc->ifc_nand.nand_fbcr, 4);
+   fsl_ifc_run_command(mtd);
+   return;
+   }
+
case NAND_CMD_RNDOUT: {
__le16 Tccs = 0;
chip->onfi_version ? (Tccs = chip->onfi_params.t_ccs)
@@ -899,6 +916,39 @@ static int fsl_ifc_sram_init(uint32_t ver, struct 
fsl_ifc_mtd *priv)

return 0;
 }
+/**
+ * fsl_ifc_onfi_set_features- set features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int fsl_ifc_onfi_set_features(struct mtd_info *mtd, struct nand_chip 
*chip,
+   int addr, uint8_t *subfeature_param)
+{
+   int status;
+   int i;
+
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+   if (!chip->onfi_version ||
+   !(le16_to_cpu(chip->onfi_params.opt_cmd)
+ & ONFI_OPT_CMD_SET_GET_FEATURES))
+   return -EINVAL;
+#endif
+
+   /* Want data from start of the buffer */
+   set_addr(mtd, 0, 0, 0);
+
+   for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
+   chip->write_byte(mtd, subfeature_param[i]);
+
+   chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, 0);
+
+   status = chip->waitfunc(mtd, chip);
+   if (status & NAND_STATUS_FAIL)
+   return -EIO;
+   return 0;
+}

 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 {
@@ -957,6 +1007,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
nand->select_chip = fsl_ifc_select_chip;
nand->cmdfunc = fsl_ifc_cmdfunc;
nand->waitfunc = fsl_ifc_wait;
+   nand->onfi_set_features = fsl_ifc_onfi_set_features;

/* set up nand options */
nand->bbt_td = &bbt_main_descr;
--
1.7.9.5

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Re: [U-Boot] [PATCH] xilinx: Sync defconfigs based on latest NET Kconfig changes

2018-04-17 Thread Tom Rini
On Tue, Apr 17, 2018 at 08:32:31AM +0200, Michal Simek wrote:

> Sync CMD_MII, CMD_NFS, CMD_TFTPPUT and BOOTP options.
> 
> Signed-off-by: Michal Simek 

I forgot to sync everyone before tagging, oops.  I'll do that now.

-- 
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Re: [U-Boot] Please pull u-boot-marvell/master

2018-04-17 Thread Tom Rini
On Tue, Apr 17, 2018 at 10:53:21AM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull the small mv_sdhci fix from Matt from the Marvell
> repo.
> 
> Thanks,
> Stefan
> 
> 
> The following changes since commit 8c0a17be0a632b9a823e14628c42f85c3e64f08e:
> 
>   Prepare v2018.05-rc2 (2018-04-16 20:00:14 -0400)
> 
> are available in the Git repository at:
> 
>   git://www.denx.de/git/u-boot-marvell.git 
> 
> for you to fetch changes up to ca4e7d674ee6931c7a4effd697e644d7646cfac0:
> 
>   mmc: mv_sdhci: zero out sdhci_host structure (2018-04-17 10:39:30 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 0/5] Use Android DT image format for TI boards

2018-04-17 Thread Andrew F. Davis
On 04/16/2018 03:32 PM, Sam Protsenko wrote:
> Android documentation recommends using new image format for storing dtb
> and dtbo files: [1]. Using that format, we can pack several dtb files to
> dtb.img, and also pack several dtbo files to dtbo.img. Then those images
> should be flashed to eMMC partitions, called "dtb" and "dtbo"
> respectively.
> 


I'm not convinced adding yet another one-off Android specific partition
format is what we need right now. With FIT images this is a solved
problem, why does Android need to go down a different path here?


> This patch series introduces support for mentioned Android DT image
> format, adds "dtimg" command to deal with that image format from U-Boot
> shell, and provides new Android boot scheme to TI boards (AM57x and DRA7
> boards). So with this patch series we will have next procedure for
> Android boot:
>  1. Read next images from eMMC partitions to RAM:
> - boot.img
> - dtb.img
> - dtbo.img
>  2. Take addresses of desired dtb/dtbo files from that images (for
> current board)
>  3. Apply dtbo overlays to main dtb, if needed
>  4. Boot the kernel from Android boot image, using resulting dtb
> 


All the above logic ends up adding more to our environment scripting at
a time when we are working to reduce that..

Andrew


> It was tested on X15 and AM57x EVM boards.
> 
> [1] https://source.android.com/devices/architecture/dto/partitions
> 
> Sam Protsenko (5):
>   common: Add support for Android DT image
>   cmd: Add dtimg command
>   arm: ti: boot: Extract PARTS_DEFAULT to boot.h
>   arm: ti: boot: Add dtbo partition for Android boot
>   arm: ti: boot: Implement Android boot using DT image format
> 
>  board/ti/common/Kconfig   |   1 +
>  cmd/Kconfig   |   8 ++
>  cmd/Makefile  |   1 +
>  cmd/dtimg.c   | 142 ++
>  common/Makefile   |   4 +
>  common/image-android-dt.c | 134 
>  configs/am57xx_evm_defconfig  |   1 +
>  configs/am57xx_hs_evm_defconfig   |   1 +
>  configs/dra7xx_evm_defconfig  |   1 +
>  configs/dra7xx_hs_evm_defconfig   |   1 +
>  include/configs/am57xx_evm.h  |  25 --
>  include/configs/cl-som-am57x.h|   2 +
>  include/configs/cm_t54.h  |   2 +
>  include/configs/dra7xx_evm.h  |  25 --
>  include/configs/ti_armv7_common.h |   1 +
>  include/dt_table.h|  46 ++
>  include/environment/ti/boot.h |  68 --
>  include/image-android-dt.h|  18 
>  18 files changed, 422 insertions(+), 59 deletions(-)
>  create mode 100644 cmd/dtimg.c
>  create mode 100644 common/image-android-dt.c
>  create mode 100644 include/dt_table.h
>  create mode 100644 include/image-android-dt.h
> 
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Re: [U-Boot] [PATCH 3/5] arm: ti: boot: Extract PARTS_DEFAULT to boot.h

2018-04-17 Thread Andrew F. Davis
On 04/16/2018 03:32 PM, Sam Protsenko wrote:
> Eliminate code duplication: the same PARTS_DEFAULT was defined in
> am57xx_evm.h and in dra7xx_evm.h. Extract it to environment/boot.h and
> use in all OMAP5-based boards.
> 
> Signed-off-by: Sam Protsenko 
> ---


This patch can be taken independent of my objections to the others in
this series.

Acked-by: Andrew F. Davis 


>  include/configs/am57xx_evm.h   | 25 -
>  include/configs/cl-som-am57x.h |  2 ++
>  include/configs/cm_t54.h   |  2 ++
>  include/configs/dra7xx_evm.h   | 25 -
>  include/environment/ti/boot.h  | 27 +--
>  5 files changed, 29 insertions(+), 52 deletions(-)
> 
> diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
> index d1f73f76a4..886a5696f5 100644
> --- a/include/configs/am57xx_evm.h
> +++ b/include/configs/am57xx_evm.h
> @@ -38,31 +38,6 @@
>  
>  #define CONFIG_SYS_OMAP_ABE_SYSCK
>  
> -/* Define the default GPT table for eMMC */
> -#define PARTS_DEFAULT \
> - /* Linux partitions */ \
> - "uuid_disk=${uuid_gpt_disk};" \
> - "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \
> - "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
> - /* Android partitions */ \
> - "partitions_android=" \
> - "uuid_disk=${uuid_gpt_disk};" \
> - "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
> - "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
> - "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
> - "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
> - "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
> - "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
> - "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
> - "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
> - "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
> - "name=system,size=768M,uuid=${uuid_gpt_system};" \
> - "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
> - "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
> - "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
> - "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
> - "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
> -
>  #define DFUARGS \
>   "dfu_bufsiz=0x1\0" \
>   DFU_ALT_INFO_MMC \
> diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
> index 9c70cf0b37..709e0375b3 100644
> --- a/include/configs/cl-som-am57x.h
> +++ b/include/configs/cl-som-am57x.h
> @@ -18,6 +18,8 @@
>  
>  #define CONFIG_SYS_OMAP_ABE_SYSCK
>  
> +#define PARTS_DEFAULT
> +
>  #include 
>  
>  /* misc */
> diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
> index 6123cd374d..f0d76ed806 100644
> --- a/include/configs/cm_t54.h
> +++ b/include/configs/cm_t54.h
> @@ -14,6 +14,8 @@
>  #define CONFIG_CM_T54
>  #define CONFIG_DRAM_2G
>  
> +#define PARTS_DEFAULT
> +
>  #include 
>  
>  /* EEPROM related defines */
> diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
> index 917a05d701..9b3fb2c913 100644
> --- a/include/configs/dra7xx_evm.h
> +++ b/include/configs/dra7xx_evm.h
> @@ -45,31 +45,6 @@
>  #define CONFIG_SYS_OMAP_ABE_SYSCK
>  
>  #ifndef CONFIG_SPL_BUILD
> -/* Define the default GPT table for eMMC */
> -#define PARTS_DEFAULT \
> - /* Linux partitions */ \
> - "uuid_disk=${uuid_gpt_disk};" \
> - "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \
> - "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
> - /* Android partitions */ \
> - "partitions_android=" \
> - "uuid_disk=${uuid_gpt_disk};" \
> - "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
> - "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
> - "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
> - "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
> - "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
> - "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
> - "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
> - "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
> - "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
> - "name=system,size=768M,uuid=${uuid_gpt_system};" \
> - "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
> - "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
> - "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
> - "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
> - "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
> -
>  #define DFUARGS \
>   "dfu_bufsiz=0x1\0" \
>   DFU_ALT_INFO_MMC \
> diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
> index 24b7783f88..4f3d748b5c 100644
> --- a/include/environment/ti/boot.h
> +++ b/include/environment/ti/boot.h
> @@ -15,8 +15,31 @@
>  #endif
>  
>  #ifndef PARTS_DEFAULT
> -#define PARTS_DEFAULT
> -#endif
> +/* Define the default GPT table for eMMC */
> +#define PARTS_DEFAUL

Re: [U-Boot] [PATCH 4/5] arm: ti: boot: Add dtbo partition for Android boot

2018-04-17 Thread Andrew F. Davis
On 04/16/2018 03:32 PM, Sam Protsenko wrote:
> New Android boot scheme looks like this [1], and it involves adding new
> partition for storing Device Tree Overlays. This patch adds dtbo
> partition. While at it, let's revise Android partition table a bit.
> 
> List of changes:
>  - rename "misc" to "hole" (not used for anything, just a guard hole)

Could we instead expand the bootloader partition and just remove this
hole partition?

>  - rename "reserved" to "uenv" (because it hold U-Boot environment)

This is fine.

>  - rename "environment" to "dtb" (because it actually holds .dtb file)


We are working to move to FIT with our Android releases, so the
"boot.img" image will now be a FIT image that contains kernel, dtb,
dtbo, op-tee, ipu, ipu2, etc...

The end result is all these custom partitions we had before all just get
folded into the one boot partition.

Andrew


>  - move "dtb" after "uenv" (so that changes of dtb size won't affect
>"uenv" offset)
>  - make "hole" size twice as bigger (to keep "uenv" offset the same,
>because "dtb" was moved after "uenv")
>  - add "dtbo" partition (after "dtb", to not affect "uenv" offset)
>  - while at it, increase "boot" partition size up to 20 MiB; that's
>needed because while playing with some additional drivers built-in
>and different compression techniques, and also for HS signing, we
>have seen the boot partition size reach close to border and
>sometimes reach over the limit of 10 MiB
> 
> Now eMMC layout looks like this:
> 
> offset   content size  partition
> (KiB)(KiB)
> 
> ===
> 
> 0   ++
> | MBR/GPT header |   128   -
> 128 ++
> | MLO|   256   xloader
> 384 ++
> | u-boot.img |   1792  bootloader
> 2176++
> |  hole  |   256   hole
> 2432++
> | U-Boot environment |   256   uenv
> | (+ redundant)  |
> 2688++
> | dtb files  |   1024  dtb
> 3712++
> | dtbo files |   1024  dtbo
> 4736++
>   Android partitions remaining *
> 
> ===
> 
> "hole" partition is needed just to keep U-Boot environment at 2432 KiB
> offset, because:
>  - this offset is used in DFU_ALT_INFO_EMMC:
> 
>"u-env.raw raw 0x1300 0x200;"
>0x1300 = 4864 sectors = 2432 KiB
> 
>  - which in turn relies on CONFIG_ENV_OFFSET:
> 
>CONFIG_ENV_OFFSET = 0x26 = 2432 KiB
> 
> We are using "hole" partition instead of specifying "start" property to
> "uenv" partition, because this way it's easier to maintain change of
> preceding partitions.
> 
> Also fix Android boot commands appropriately.
> 
> [1] https://source.android.com/devices/architecture/dto/partitions
> 
> Signed-off-by: Sam Protsenko 
> ---
>  include/environment/ti/boot.h | 13 +++--
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
> index 4f3d748b5c..f2d91f5298 100644
> --- a/include/environment/ti/boot.h
> +++ b/include/environment/ti/boot.h
> @@ -26,13 +26,14 @@
>   "uuid_disk=${uuid_gpt_disk};" \
>   "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
>   "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
> - "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
> - "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
> - "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
> + "name=hole,size=256K,uuid=${uuid_gpt_hole};" \
> + "name=uenv,size=256K,uuid=${uuid_gpt_uenv};" \
> + "name=dtb,size=1M,uuid=${uuid_gpt_dtb};" \
> + "name=dtbo,size=1M,uuid=${uuid_gpt_dtbo};" \
>   "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
>   "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
>   "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
> - "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
> + "name=boot,size=20M,uuid=${uuid_gpt_boot};" \
>   "name=system,size=768M,uuid=${uuid_gpt_system};" \
>   "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
>   "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
> @@ -66,8 +67,8 @@
>   "setenv machid fe6; " \
>   "mmc dev $mmcdev; " \
>   "mmc rescan; " \
> - "part start mmc ${mmcdev} environment fdt_start; " \
> - "part size mmc ${mmcdev} environment fdt_size; " \
> + "part start mmc ${mmcdev} dtb fdt_start; "

Re: [U-Boot] [PATCH v2 2/2] imx6ul: opos6ul: in Serial Downloader boot mode use ymodem

2018-04-17 Thread Fabio Estevam
Hi Sébastien,

On Tue, Apr 17, 2018 at 12:29 PM, Sébastien Szymanski
 wrote:
> When booting in Serial Downloader mode load the U-Boot image using
> ymodem.

Not sure if you are aware, but it is possible to use imx_usb_loader to
also load SPL + u-boot.img as described at:
doc/README.sdp

Your patch looks good, but just wanted to point out this alternative
in case it fits your needs.
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Re: [U-Boot] [PATCH v2] bootm: Align cache flush begin address

2018-04-17 Thread Simon Glass
Hi Bryan,

On 17 April 2018 at 03:27, Bryan O'Donoghue  wrote:
>
>
>
> On 16/04/18 17:49, Simon Glass wrote:
>>
>> On 15 April 2018 at 04:48, Bryan O'Donoghue  
>> wrote:
>>>
>>> commit b4d956f6bc0f ("bootm: Align cache flush end address correctly")
>>> aligns the end address of the cache flush operation to a cache-line size to
>>> ensure lower-layers in the code accept the range provided and flush.
>>>
>>> A similar action should be taken for the begin address of a cache flush
>>> operation. The load address may not be aligned to a cache-line boundary, so
>>> ensure the passed address is aligned.
>>>
>>> Signed-off-by: Bryan O'Donoghue 
>>> Reported-by: Breno Matheus Lima 
>>> Suggested-by: Tom Rini 
>>> Cc: Simon Glass 
>>> ---
>>>   common/bootm.c | 8 +++-
>>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>
>>
>> I feel that using an unaligned start address should probably be an
>> error. Why would that be useful?
>>
>> Apart from that:
>>
>> Reviewed-by: Simon Glass 
>>
>> Regards,
>> Simon
>>
>
> We are booting a kernel that has an entry point aligned a cacheline boundary 
> with a header prefix/load-address that is a negative offset from that.
>
> We could go about trying to move the load/ep address of that kernel but, my 
> feeling is that's probably the wrong thing to do, we can just as easily 
> align-down and add to the flush length.

What header is this? Perhaps it should be updated to be a cache-line
multiple in size?

I suspect the impact of this patch is minimal, since people hopefully
don't put data just before the image is loaded. But if they did, and
the image is loaded using DMA behind the cache, we might have tricky
bugs. That's why in general I'm not keen on silently messing with the
cache outside the expected range.

Regards,
Simon
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Re: [U-Boot] [PATCHv1 14/14] reset: remove request and free functions

2018-04-17 Thread Simon Glass
H Dinh,

On 16 April 2018 at 16:41, Dinh Nguyen  wrote:
>
>
> On 04/16/2018 01:51 PM, Stephen Warren wrote:
>> On 04/16/2018 12:43 PM, Simon Glass wrote:
>>> +Stephen for comment
>>>
>>> Hi Dinh,
>>>
>>> On 14 April 2018 at 12:51, Dinh Nguyen  wrote:
 The request and free reset functions are not really used for any useful
 purpose but for debugging. We can safely remove them.
>>>
>>> The API is set to line up with clocks. I think in general we do want
>>> to be able to request and free these devices, just as we do for GPIOs.
>>> What is the goal of removing these methods?
>>
>> Many of the request methods do in fact do something; they check the
>> validity of the reset ID so that check doesn't need to be duplicated
>> everywhere. Even ignoring that, any resource management API should have
>> explicit request/free APIs so that lifetime can be tracked if needed.
>
> Agreed, that the checks were in some of the request functions, but the
> majority did not do any checks, just a debug() statement. All of the
> platforms that did the checks, I just moved them to reset_assert and
> reset_deassert.

OK. Please can resend the series without removing those methods?

Regards,
Simon
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[U-Boot] [PATCH] clk: uniphier: add ethernet clock control support

2018-04-17 Thread Kunihiko Hayashi
Add clock control for ethernet controller on each SoC.

Signed-off-by: Kunihiko Hayashi 
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c 
b/drivers/clk/uniphier/clk-uniphier-sys.c
index c852c78..0230a18 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] 
= {
 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) 
||\
 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
UNIPHIER_LD4_SYS_CLK_NAND(2),
+   UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12),/* ether (Pro4, PXs2) */
+   UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10),/* stdmac */
+   UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0),/* ether-phy (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6),/* gio (Pro4, Pro5) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16),   /* usb30 (Pro4, Pro5, 
PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),   /* usb31 (Pro4, Pro5, 
PXs2) */
@@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = 
{
 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+   UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),   /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),   /* usb30-phy0 (LD20) */
@@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = 
{
 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+   UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
+   UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10),/* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),/* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5),/* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6),/* usb31-1 (gio1-1) */
-- 
2.7.4

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[U-Boot] [PATCH] reset: uniphier: add ethernet reset control support

2018-04-17 Thread Kunihiko Hayashi
Add reset lines for ethernet controller on each SoC.

Signed-off-by: Kunihiko Hayashi 
---
 drivers/reset/reset-uniphier.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index a40cea5..e7a7da7 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -43,6 +43,7 @@ struct uniphier_reset_data {
 /* System reset data */
 static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x2000, 2),  /* NAND */
+   UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
UNIPHIER_RESETX(14, 0x2000, 17),/* USB30 */
@@ -52,6 +53,7 @@ static const struct uniphier_reset_data 
uniphier_pro4_sys_reset_data[] = {
 
 static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x2000, 2),  /* NAND */
+   UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
UNIPHIER_RESETX(14, 0x2000, 17),/* USB30 */
UNIPHIER_RESETX(15, 0x2004, 17),/* USB31 */
@@ -68,6 +70,7 @@ static const struct uniphier_reset_data 
uniphier_pxs2_sys_reset_data[] = {
 static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x200c, 0),  /* NAND */
UNIPHIER_RESETX(4, 0x200c, 2),  /* eMMC */
+   UNIPHIER_RESETX(6, 0x200c, 6),  /* ETHER */
UNIPHIER_RESETX(8, 0x200c, 8),  /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */
UNIPHIER_RESETX(16, 0x200c, 12),/* USB30-PHY0 */
@@ -80,6 +83,8 @@ static const struct uniphier_reset_data 
uniphier_ld20_sys_reset_data[] = {
 static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x200c, 0),  /* NAND */
UNIPHIER_RESETX(4, 0x200c, 2),  /* eMMC */
+   UNIPHIER_RESETX(6, 0x200c, 9),  /* ETHER0 */
+   UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */
UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */
-- 
2.7.4

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[U-Boot] [PATCH 1/4] regmap: clean up regmap allocation

2018-04-17 Thread Masahiro Yamada
Putting zero length array at the end of struct is a common technique
to embed arbitrary length of members.  There is no good reason to let
regmap_alloc_count() branch by "if (count <= 1)".

As far as I understood the code, regmap->base is an alias of
regmap->ranges[0].start, but it is not helpful but make the code
just ugly.

Rename regmap_alloc_count() to regmap_alloc() because the _count
suffix seems pointless.

Signed-off-by: Masahiro Yamada 
---

 drivers/core/regmap.c | 31 +--
 include/regmap.h  |  7 ++-
 2 files changed, 11 insertions(+), 27 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 8a0e00f..6c3dbe9 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -18,22 +18,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct regmap *regmap_alloc_count(int count)
+static struct regmap *regmap_alloc(int count)
 {
struct regmap *map;
 
-   map = malloc(sizeof(struct regmap));
+   map = malloc(sizeof(*map) + sizeof(map->ranges[0]) * count);
if (!map)
return NULL;
-   if (count <= 1) {
-   map->range = &map->base_range;
-   } else {
-   map->range = malloc(count * sizeof(struct regmap_range));
-   if (!map->range) {
-   free(map);
-   return NULL;
-   }
-   }
map->range_count = count;
 
return map;
@@ -46,12 +37,11 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t 
*reg, int count,
struct regmap_range *range;
struct regmap *map;
 
-   map = regmap_alloc_count(count);
+   map = regmap_alloc(count);
if (!map)
return -ENOMEM;
 
-   map->base = *reg;
-   for (range = map->range; count > 0; reg += 2, range++, count--) {
+   for (range = map->ranges; count > 0; reg += 2, range++, count--) {
range->start = *reg;
range->size = reg[1];
}
@@ -84,11 +74,11 @@ int regmap_init_mem(struct udevice *dev, struct regmap 
**mapp)
if (!count)
return -EINVAL;
 
-   map = regmap_alloc_count(count);
+   map = regmap_alloc(count);
if (!map)
return -ENOMEM;
 
-   for (range = map->range, index = 0; count > 0;
+   for (range = map->ranges, index = 0; count > 0;
 count--, range++, index++) {
fdt_size_t sz;
if (of_live_active()) {
@@ -102,7 +92,6 @@ int regmap_init_mem(struct udevice *dev, struct regmap 
**mapp)
range->size = sz;
}
}
-   map->base = map->range[0].start;
 
*mapp = map;
 
@@ -116,15 +105,13 @@ void *regmap_get_range(struct regmap *map, unsigned int 
range_num)
 
if (range_num >= map->range_count)
return NULL;
-   range = &map->range[range_num];
+   range = &map->ranges[range_num];
 
return map_sysmem(range->start, range->size);
 }
 
 int regmap_uninit(struct regmap *map)
 {
-   if (map->range_count > 1)
-   free(map->range);
free(map);
 
return 0;
@@ -132,7 +119,7 @@ int regmap_uninit(struct regmap *map)
 
 int regmap_read(struct regmap *map, uint offset, uint *valp)
 {
-   uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+   u32 *ptr = map_physmem(map->ranges[0].start + offset, 4, MAP_NOCACHE);
 
*valp = le32_to_cpu(readl(ptr));
 
@@ -141,7 +128,7 @@ int regmap_read(struct regmap *map, uint offset, uint *valp)
 
 int regmap_write(struct regmap *map, uint offset, uint val)
 {
-   uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+   u32 *ptr = map_physmem(map->ranges[0].start + offset, 4, MAP_NOCACHE);
 
writel(cpu_to_le32(val), ptr);
 
diff --git a/include/regmap.h b/include/regmap.h
index 493a5d8..858aa7e 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -22,15 +22,12 @@ struct regmap_range {
 /**
  * struct regmap - a way of accessing hardware/bus registers
  *
- * @base:  Base address of register map
  * @range_count: Number of ranges available within the map
- * @range: Pointer to the list of ranges, allocated if @range_count > 1
- * @base_range:If @range_count is <= 1, @range points here
+ * @ranges:Array of ranges
  */
 struct regmap {
-   phys_addr_t base;
int range_count;
-   struct regmap_range *range, base_range;
+   struct regmap_range ranges[];
 };
 
 /*
-- 
2.7.4

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[U-Boot] [PATCH 4/4] syscon: add Linux-compatible syscon API

2018-04-17 Thread Masahiro Yamada
The syscon implementation in U-Boot is different from that in Linux.
Thus, DT files imported from Linux do not work for U-Boot.

In U-Boot driver model, each node is bound to a dedicated driver
that is the most compatible to it.  This design gets along with the
concept of DT, and the syscon in Linux originally worked like that.

However, Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon
interface from platform devices") changed the behavior because it is
useful to let a device bind to another driver, but still works as a
syscon provider.

That change had happened before U-Boot initially supported the syscon
driver by commit 6f98b7504f70 ("dm: Add support for generic system
controllers (syscon)").  So, the U-Boot's syscon works differently
from the beginning.  I'd say this is mis-implementation given that
DT is not oriented to a particular project, but Linux is the canon
of DT in practice.

The problem typically arises in the combination of "syscon" and
"simple-mfd" compatibles.

In Linux, they are orthogonal, i.e., the order between "syscon" and
"simple-mfd" does not matter at all.

Assume the following compatible.

   compatible = "foo,bar-syscon", "syscon", "simple-mfd";

In U-Boot, this device node is bound to the syscon driver
(driver/core/syscon-uclass.c) since the "syscon" is found to be the
most compatible.  Then, syscon_get_regmap() succeeds.

However,

   compatible = "foo,bar-syscon", "simple-mfd", "syscon";

does not work because this node is bound to the simple-bus driver
(drivers/core/simple-bus.c) in the favor of "simple-mfd" compatible.
The compatible string "syscon" is just dismissed.

Moreover,

   compatible = "foo,bar-syscon", "syscon";

works like the first case because the syscon driver populates the
child devices.  This is wrong because populating children is the job
of "simple-mfd" (or "simple-bus").

This commit ports syscon_node_to_regmap() from Linux.  This API
does not require the given node to be bound to a driver in any way.

Reported-by: Kunihiko Hayashi 
Signed-off-by: Masahiro Yamada 
---

 drivers/core/syscon-uclass.c | 63 
 include/syscon.h |  8 ++
 2 files changed, 71 insertions(+)

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index c99409b..bd2f681 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -15,6 +15,14 @@
 #include 
 #include 
 
+/*
+ * Caution:
+ * This API requires the given node has already been bound to "syscon".
+ *compatible = "syscon", "simple-mfd";
+ * works, but
+ *compatible = "simple-mfd", "syscon";
+ * does not.  This behavior is different from Linux.
+ */
 struct regmap *syscon_get_regmap(struct udevice *dev)
 {
struct syscon_uc_info *priv;
@@ -109,3 +117,58 @@ U_BOOT_DRIVER(generic_syscon) = {
 #endif
.of_match = generic_syscon_ids,
 };
+
+/*
+ * Linux-compatible syscon-to-regmap
+ * The syscon node can be bound to another driver, but still works
+ * as a syscon provider.
+ */
+static LIST_HEAD(syscon_list);
+
+struct syscon {
+   ofnode node;
+   struct regmap *regmap;
+   struct list_head list;
+};
+
+static struct syscon *of_syscon_register(ofnode node)
+{
+   struct syscon *syscon;
+   int ret;
+
+   if (!ofnode_device_is_compatible(node, "syscon"))
+   return ERR_PTR(-EINVAL);
+
+   syscon = malloc(sizeof(*syscon));
+   if (!syscon)
+   return ERR_PTR(-ENOMEM);
+
+   ret = regmap_init_mem(node, &syscon->regmap);
+   if (ret) {
+   free(syscon);
+   return ERR_PTR(ret);
+   }
+
+   list_add_tail(&syscon->list, &syscon_list);
+
+   return syscon;
+}
+
+struct regmap *syscon_node_to_regmap(ofnode node)
+{
+   struct syscon *entry, *syscon = NULL;
+
+   list_for_each_entry(entry, &syscon_list, list)
+   if (ofnode_equal(entry->node, node)) {
+   syscon = entry;
+   break;
+   }
+
+   if (!syscon)
+   syscon = of_syscon_register(node);
+
+   if (IS_ERR(syscon))
+   return ERR_CAST(syscon);
+
+   return syscon->regmap;
+}
diff --git a/include/syscon.h b/include/syscon.h
index 5d52b1c..a019345 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -8,6 +8,7 @@
 #ifndef __SYSCON_H
 #define __SYSCON_H
 
+#include 
 #include 
 
 /**
@@ -82,4 +83,11 @@ struct regmap *syscon_get_regmap_by_driver_data(ulong 
driver_data);
  */
 void *syscon_get_first_range(ulong driver_data);
 
+/**
+ * syscon_node_to_regmap - Linux-compat syscon lookup
+ *
+ * @node:  Device node of syscon
+ */
+struct regmap *syscon_node_to_regmap(ofnode node);
+
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 2/4] dm: ofnode: add ofnode_device_is_compatible() helper

2018-04-17 Thread Masahiro Yamada
device_is_compatible() takes udevice, but there is no such a helper
that takes ofnode.

Signed-off-by: Masahiro Yamada 
---

 drivers/core/device.c |  8 +---
 drivers/core/ofnode.c | 11 +++
 include/dm/ofnode.h   | 11 +++
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 940a153..8d95787 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -709,13 +709,7 @@ int device_set_name(struct udevice *dev, const char *name)
 
 bool device_is_compatible(struct udevice *dev, const char *compat)
 {
-   const void *fdt = gd->fdt_blob;
-   ofnode node = dev_ofnode(dev);
-
-   if (ofnode_is_np(node))
-   return of_device_is_compatible(ofnode_to_np(node), compat, 
NULL, NULL);
-   else
-   return !fdt_node_check_compatible(fdt, ofnode_to_offset(node), 
compat);
+   return ofnode_device_is_compatible(dev_ofnode(dev), compat);
 }
 
 bool of_machine_is_compatible(const char *compat)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 5909a25..ee2109b 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -687,3 +687,14 @@ u64 ofnode_translate_address(ofnode node, const fdt32_t 
*in_addr)
else
return fdt_translate_address(gd->fdt_blob, 
ofnode_to_offset(node), in_addr);
 }
+
+int ofnode_device_is_compatible(ofnode node, const char *compat)
+{
+   if (ofnode_is_np(node))
+   return of_device_is_compatible(ofnode_to_np(node), compat,
+  NULL, NULL);
+   else
+   return !fdt_node_check_compatible(gd->fdt_blob,
+ ofnode_to_offset(node),
+ compat);
+}
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0d00840..a2c6a50 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -681,4 +681,15 @@ int ofnode_read_resource_byname(ofnode node, const char 
*name,
  * @return the translated address; OF_BAD_ADDR on error
  */
 u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr);
+
+/**
+ * ofnode_device_is_compatible() - check if the node is compatible with compat
+ *
+ * This allows to check whether the node is comaptible with the compat.
+ *
+ * @node:  Device tree node for which compatible needs to be verified.
+ * @compat:Compatible string which needs to verified in the given node.
+ * @return true if OK, false if the compatible is not found
+ */
+int ofnode_device_is_compatible(ofnode node, const char *compat);
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 0/4] Add Linux-compatible syscon_to_regmap API

2018-04-17 Thread Masahiro Yamada
The current syscon in U-Boot works differently from Linux.
Therefore, DT files imported from Linux do not work for U-Boot.

The current usage of syscon in U-Boot should be discouraged because
using different DT-binding across projects is a significant problem.



Masahiro Yamada (4):
  regmap: clean up regmap allocation
  dm: ofnode: add ofnode_device_is_compatible() helper
  regmap: change regmap_init_mem() to take ofnode instead udevice
  syscon: add Linux-compatible syscon API

 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
 drivers/core/device.c|  8 +---
 drivers/core/ofnode.c| 11 +
 drivers/core/regmap.c| 42 ++
 drivers/core/syscon-uclass.c | 65 +++-
 drivers/phy/meson-gxl-usb2.c |  2 +-
 drivers/phy/meson-gxl-usb3.c |  2 +-
 drivers/ram/rockchip/dmc-rk3368.c|  2 +-
 drivers/ram/rockchip/sdram_rk3188.c  |  2 +-
 drivers/ram/rockchip/sdram_rk322x.c  |  2 +-
 drivers/ram/rockchip/sdram_rk3288.c  |  2 +-
 drivers/ram/rockchip/sdram_rk3399.c  |  2 +-
 drivers/ram/stm32mp1/stm32mp1_ram.c  |  2 +-
 drivers/reset/reset-meson.c  |  2 +-
 include/dm/ofnode.h  | 11 +
 include/regmap.h | 11 ++---
 include/syscon.h |  8 
 17 files changed, 123 insertions(+), 53 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH 3/4] regmap: change regmap_init_mem() to take ofnode instead udevice

2018-04-17 Thread Masahiro Yamada
Currently, regmap_init_mem() takes udevice. This requires the node
has already been associated with a device. It prevents syscon/regmap
from behaving like those in Linux.

Change the first argumenet to take the device node.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
 drivers/core/regmap.c| 11 +--
 drivers/core/syscon-uclass.c |  2 +-
 drivers/phy/meson-gxl-usb2.c |  2 +-
 drivers/phy/meson-gxl-usb3.c |  2 +-
 drivers/ram/rockchip/dmc-rk3368.c|  2 +-
 drivers/ram/rockchip/sdram_rk3188.c  |  2 +-
 drivers/ram/rockchip/sdram_rk322x.c  |  2 +-
 drivers/ram/rockchip/sdram_rk3288.c  |  2 +-
 drivers/ram/rockchip/sdram_rk3399.c  |  2 +-
 drivers/ram/stm32mp1/stm32mp1_ram.c  |  2 +-
 drivers/reset/reset-meson.c  |  2 +-
 include/regmap.h |  4 ++--
 13 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c 
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index 6383f72..f267c58 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -392,7 +392,7 @@ static int ast2500_sdrammc_ofdata_to_platdata(struct 
udevice *dev)
struct regmap *map;
int ret;
 
-   ret = regmap_init_mem(dev, &map);
+   ret = regmap_init_mem(dev_ofnode(dev), &map);
if (ret)
return ret;
 
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 6c3dbe9..1185a44 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -51,7 +51,7 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t 
*reg, int count,
return 0;
 }
 #else
-int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
+int regmap_init_mem(ofnode node, struct regmap **mapp)
 {
struct regmap_range *range;
struct regmap *map;
@@ -59,14 +59,13 @@ int regmap_init_mem(struct udevice *dev, struct regmap 
**mapp)
int addr_len, size_len, both_len;
int len;
int index;
-   ofnode node = dev_ofnode(dev);
struct resource r;
 
-   addr_len = dev_read_simple_addr_cells(dev->parent);
-   size_len = dev_read_simple_size_cells(dev->parent);
+   addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
+   size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
both_len = addr_len + size_len;
 
-   len = dev_read_size(dev, "reg");
+   len = ofnode_read_size(node, "reg");
if (len < 0)
return len;
len /= sizeof(fdt32_t);
@@ -87,7 +86,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
range->size = r.end - r.start + 1;
} else {
range->start = fdtdec_get_addr_size_fixed(gd->fdt_blob,
-   dev_of_offset(dev), "reg", index,
+   ofnode_to_offset(node), "reg", index,
addr_len, size_len, &sz, true);
range->size = sz;
}
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index a69937e..c99409b 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -41,7 +41,7 @@ static int syscon_pre_probe(struct udevice *dev)
return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg),
&priv->regmap);
 #else
-   return regmap_init_mem(dev, &priv->regmap);
+   return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
 #endif
 }
 
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
index 15c9c89..7242bf6 100644
--- a/drivers/phy/meson-gxl-usb2.c
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -195,7 +195,7 @@ int meson_gxl_usb2_phy_probe(struct udevice *dev)
struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
int ret;
 
-   ret = regmap_init_mem(dev, &priv->regmap);
+   ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
if (ret)
return ret;
 
diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c
index a385fbd..47a41fd 100644
--- a/drivers/phy/meson-gxl-usb3.c
+++ b/drivers/phy/meson-gxl-usb3.c
@@ -166,7 +166,7 @@ int meson_gxl_usb3_phy_probe(struct udevice *dev)
struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
int ret;
 
-   ret = regmap_init_mem(dev, &priv->regmap);
+   ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
if (ret)
return ret;

diff --git a/drivers/ram/rockchip/dmc-rk3368.c 
b/drivers/ram/rockchip/dmc-rk3368.c
index bfcb1dd..9bf64bf 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -880,7 +880,7 @@ static int rk3368_dmc_ofdata_to_platdata(struct ud

[U-Boot] [PATCH 1/3] rockchip: rk3188: add -u-boot.dtsi for rock-rk3188

2018-04-17 Thread Kever Yang
We should a -u-boot.dtsi for those config need by U-Boot only,
and other part sync with kernel.

Signed-off-by: Kever Yang 
---

 arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 18 ++
 arch/arm/dts/rk3188-radxarock.dts |  6 +-
 arch/arm/dts/rk3188.dtsi  |  2 --
 3 files changed, 19 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/dts/rk3188-radxarock-u-boot.dtsi

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi 
b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
new file mode 100644
index 000..5d650b1
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+&cru {
+   u-boot,dm-spl;
+};
+
+&pinctrl {
+   u-boot,dm-spl;
+};
+
+&uart2 {
+   status = "okay";
+   u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3188-radxarock.dts 
b/arch/arm/dts/rk3188-radxarock.dts
index 5f5b5e9..0fc4f54 100644
--- a/arch/arm/dts/rk3188-radxarock.dts
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 #include 
 #include "rk3188.dtsi"
+#include "rk3188-radxarock-u-boot.dtsi"
 
 / {
model = "Radxa Rock";
@@ -356,11 +357,6 @@
status = "okay";
 };
 
-&uart2 {
-   status = "okay";
-   u-boot,dm-spl;
-};
-
 &uart3 {
status = "okay";
 };
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index f4d438e..1a06843 100644
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -105,7 +105,6 @@
compatible = "rockchip,rk3188-cru";
reg = <0x2000 0x1000>;
rockchip,grf = <&grf>;
-   u-boot,dm-spl;
 
#clock-cells = <1>;
#reset-cells = <1>;
@@ -156,7 +155,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
-   u-boot,dm-spl;
 
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";
-- 
1.9.1

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[U-Boot] [PATCH 2/3] rockchip: rk3188: add timer3 node

2018-04-17 Thread Kever Yang
Add dts node for timer3.
Because of the rockchip timer can only KNOWN "dtd_rockchip_rk3368_timer"
with OF_PLATDATA enable, so we override its compatible to
"rockchip,rk3368-timer".

Signed-off-by: Kever Yang 
---

 arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 6 ++
 arch/arm/dts/rk3188.dtsi  | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi 
b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
index 5d650b1..26f5707 100644
--- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -16,3 +16,9 @@
status = "okay";
u-boot,dm-spl;
 };
+
+&timer3 {
+   compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+   u-boot,dm-spl;
+   clock-frequency = <2400>;
+};
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index 1a06843..aeb5b80 100644
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -123,6 +123,12 @@
};
};
 
+   timer3: timer@2000e000 {
+   compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+   reg = <0x2000e000 0x20>;
+   interrupts = ;
+   };
+
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", 
"rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
-- 
1.9.1

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[U-Boot] [PATCH 3/3] rockchip: rk3188: use DM timer instead of rk_timer

2018-04-17 Thread Kever Yang
Disable rk_timer as SYS timer and use DM timer instead,
so that we can get a better timer framework, the rk_timer
is going to be clean after we conver to use DM timer or
ARM arch/generic timer.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Makefile   | 2 ++
 arch/arm/mach-rockchip/rk3188-board-spl.c | 2 --
 configs/rock_defconfig| 3 +++
 include/configs/rk3188_common.h   | 5 -
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index e1b0519..096dbac 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -40,8 +40,10 @@ endif
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
 ifndef CONFIG_ARM64
+ifndef CONFIG_ROCKCHIP_RK3188
 obj-y += rk_timer.o
 endif
+endif
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c 
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 74771d3..3ccc4f1 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -131,8 +131,6 @@ void board_init_f(ulong dummy)
hang();
}
 
-   rockchip_timer_init();
-
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index f4882a8..e46cc29 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -5,6 +5,9 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x6000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3188=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK=y
 CONFIG_SPL_STACK_R_ADDR=0x6008
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 94f8cda..e07facd 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -17,11 +17,6 @@
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE  0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
-- 
1.9.1

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[U-Boot] [PATCH] rockchip: rk322x: update TPL_TEXT_BASE

2018-04-17 Thread Kever Yang
The boot0 hook including the 4-byte TAG which is at the beginning
of the TEXT_BASE, now we can use a aligned TEXT BASE.

Signed-off-by: Kever Yang 
---

 include/configs/rk322x_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index da2868f..8f8a1ef 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -22,7 +22,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR0x6010
 #define CONFIG_SYS_LOAD_ADDR   0x60800800
 #define CONFIG_SPL_STACK   0x10088000
-#define CONFIG_SPL_TEXT_BASE   0x10081004
+#define CONFIG_SPL_TEXT_BASE   0x10081000
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE  (28 << 10)
 #define CONFIG_ROCKCHIP_CHIP_TAG   "RK32"
-- 
1.9.1

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[U-Boot] [PATCH] rockchip: rk322x: update MACRO for back-to-brom

2018-04-17 Thread Kever Yang
The MACRO has been update after:
ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
We need to update the C code for it.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk322x-board-spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c 
b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 206abfa..d3d0446 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -95,7 +95,7 @@ void board_init_f(ulong dummy)
 
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
+#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
 #endif
 }
-- 
1.9.1

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[U-Boot] [PATCH] armv8: ls1088: Update 1900MT/s DDR timing to bring consistency

2018-04-17 Thread Ashish Kumar
Signed-off-by: Ashish Kumar 
---
 board/freescale/ls1088a/ddr.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h
index a1ad709..18d420e 100644
--- a/board/freescale/ls1088a/ddr.h
+++ b/board/freescale/ls1088a/ddr.h
@@ -31,12 +31,12 @@ static const struct board_specific_parameters udimm0[] = {
 #if defined(CONFIG_TARGET_LS1088ARDB)
 
{2,  1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
-   {2,  1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+   {2,  1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
{2,  2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
{}
 #elif defined(CONFIG_TARGET_LS1088AQDS)
{2,  1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
-   {2,  1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+   {2,  1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
{2,  2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
{}
 
-- 
2.7.4

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Re: [U-Boot] [PATCH] xilinx: Sync defconfigs based on latest NET Kconfig changes

2018-04-17 Thread Michal Simek
On 17.4.2018 21:39, Tom Rini wrote:
> On Tue, Apr 17, 2018 at 08:32:31AM +0200, Michal Simek wrote:
> 
>> Sync CMD_MII, CMD_NFS, CMD_TFTPPUT and BOOTP options.
>>
>> Signed-off-by: Michal Simek 
> 
> I forgot to sync everyone before tagging, oops.  I'll do that now.
> 

Wonderful. This patch can be skipped.

Thanks,
Michal
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Re: [U-Boot] u-boot 2018 SPI SPL

2018-04-17 Thread Mehmet Ali İPİN
Dear Fabio,

I manually set spl_boot_list[]  array with SPI, eMMCx, USB RAM etc. 
For SPI NOR flash loader = spl_ll_find_loader(spl_boot_list[i]) 
function (in spl.c) is returning a negative loader->boot_device number  
-442503140

May be there is a definition in u-boot/SPL config files to make file to 
generate SPI NOR flash boot code, instead of MMC,
Which enable this SPL function to return positive correct value for SPI NOR 
Flash?

eMMC is working, but I did not put SPL and u-boot in eMMC;
May be you can give me a link explaining how to SPL+u-boot.img to eMMC flash 
commands.


I added puts() messages to trace the execution;

These are the messages at terminal.


U-Boot SPL 2018.05-rc1 (Apr 17 2018 - 22:43:50 -0700)
SPL set_bd()
SPL DRAM initialized
SPL Malloc; gd flags
board boot order spl boot list
spl_boot_list:8
spl_boot_list:8
Trying to boot from -442503140
SPL: Unsupported Boot Device!
spl_boot_list:8
Trying to boot from 1
Trying to boot from MMC1

U-Boot SPL 2018.05-rc1 (Apr 17 2018 - 22:43:50 -0700)
SPL set_bd()
SPL DRAM initialized
SPL Malloc; gd flags
board boot order spl boot list
spl_boot_list:12
spl_boot_list:12
Trying to boot from 12
Trying to boot from USB SDP
SDP: initialize...
SDP: handle requests...
Downloading file of size 349576 to 0x177fffc0... done
Jumping to header at 0x177fffc0
Header Tag is not an IMX image



-Original Message-
From: Fabio Estevam [mailto:feste...@gmail.com] 
Sent: Monday, April 16, 2018 2:50 PM
To: Mehmet Ali İPİN 
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] u-boot 2018 SPI SPL

Hi Mehmet,

On Mon, Apr 16, 2018 at 8:36 AM, Mehmet Ali İPİN  
wrote:

> U-Boot SPL 2018.05-rc1 (Apr 16 2018 - 00:31:02 -0700)
> SPL: Unsupported Boot Device!

You need to debug why you are getting this message when booting from SPI.
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