[U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Michal Simek]

AArch32 Linux should start in EL1 instead of EL2.

Signed-off-by: Michal Simek 
---

 arch/arm/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 5c62d9c14406..e83d13de6749 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -339,7 +339,7 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
 #else
if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
(images->os.arch == IH_ARCH_ARM))
-   armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number,
+   armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number,
(u64)images->ft_addr, 0,
(u64)images->ep,
ES_TO_AARCH32);
-- 
1.9.1

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Re: [U-Boot] [PATCH 1/1] arm64: zynqmp: remove unnecessary logical constraint

[Michal Simek]

On 13.10.2017 01:14, Heinrich Schuchardt wrote:
> In
> 
> if (a || b)
> else if (!a)
> 
> the constraint (!a) is always true if else is reached and
> can be removed.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
> index 1b5066a826..9b83e51885 100644
> --- a/arch/arm/cpu/armv8/zynqmp/cpu.c
> +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
> @@ -198,7 +198,7 @@ int zynqmp_mmio_write(const u32 address,
>  {
>   if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
>   return zynqmp_mmio_rawwrite(address, mask, value);
> - else if (!IS_ENABLED(CONFIG_SPL_BUILD))
> + else
>   return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
> value, 0, NULL);
>  
> @@ -215,7 +215,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
>  
>   if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
>   ret = zynqmp_mmio_rawread(address, value);
> - } else if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
> + } else {
>   ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
>0, ret_payload);
>   *value = ret_payload[1];
> 

Applied.

Thanks,
Michal
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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Alexander Graf]

On 13.10.17 09:08, Michal Simek wrote:
> AArch32 Linux should start in EL1 instead of EL2.

Why? There is KVM on AArch32 as well.


Alex

> 
> Signed-off-by: Michal Simek 
> ---
> 
>  arch/arm/lib/bootm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
> index 5c62d9c14406..e83d13de6749 100644
> --- a/arch/arm/lib/bootm.c
> +++ b/arch/arm/lib/bootm.c
> @@ -339,7 +339,7 @@ static void boot_jump_linux(bootm_headers_t *images, int 
> flag)
>  #else
>   if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
>   (images->os.arch == IH_ARCH_ARM))
> - armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number,
> + armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number,
>   (u64)images->ft_addr, 0,
>   (u64)images->ep,
>   ES_TO_AARCH32);
> 
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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Michal Simek]

On 13.10.2017 09:19, Alexander Graf wrote:
> 
> 
> On 13.10.17 09:08, Michal Simek wrote:
>> AArch32 Linux should start in EL1 instead of EL2.
> 
> Why? There is KVM on AArch32 as well.

Is AArch32 without KVM able to start from EL2?
At least based on my tests this is not working.

M
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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Alexander Graf]

On 13.10.17 09:26, Michal Simek wrote:
> On 13.10.2017 09:19, Alexander Graf wrote:
>>
>>
>> On 13.10.17 09:08, Michal Simek wrote:
>>> AArch32 Linux should start in EL1 instead of EL2.
>>
>> Why? There is KVM on AArch32 as well.
> 
> Is AArch32 without KVM able to start from EL2?
> At least based on my tests this is not working.

I'll leave it to Marc to answer that. I'd say if it's unable to boot
from EL2 that's a bug though.


Alex
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[U-Boot] [PATCH v3 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console

[tien . fong . chee]

From: Tien Fong Chee 

This patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA
, SPL loading U-boot and booting to U-boot console. This version mainly resolved
comments from Marek in [v2].
This series is working on top of u-boot-socfpga.git -
 http://git.denx.de/u-boot-socfpga.git .

[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg265192.html

v2 -> v3 changes:
-
- Fixed the commit header tags.
- Added return -EINVAL when loader could not be started.
- Fixed yoda programming style.
- Created generic firmware loader.
- Used regular macros instead bitfields.
- re-orderd some patches.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg261831.html

Tien Fong Chee (20):
  ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA
manager
  dts: Add FPGA bitstream properties to Arria 10 DTS
  arm: socfpga: Add Arria 10 SoCFPGA programming interface
  dts: Enable fpga-mgr node build for Arria 10 SPL
  fs: Enable generic filesystems interface support in SPL.
  common: Generic firmware loader for file system
  arm: socfpga: Fix with the correct polling status bit
  arm: socfpga: Add drivers for programing FPGA from flash
  arm: socfpga: Rename the gen5 sdram driver to more specific name
  arm: socfpga: Add DRAM bank size initialization function
  arm: socfpga: Add DDR driver for Arria 10
  configs: Add DDR Kconfig support for Arria 10
  arm: socfpga: Enable SPL memory allocation
  arm: socfpga: Improve comments for Intel SoCFPGA program header
  arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10
  arm: socfpga: Adding clock frequency info for U-boot
  arm: socfpga: Adding SoCFPGA info for both SPL and U-boot
  arm: socfpga: Enable function visible to other file
  arm: socfpga: Enable DDR working
  arm: socfpga: Enable SPL booting U-boot

 arch/arm/dts/socfpga_arria10.dtsi  |   6 +
 arch/arm/mach-socfpga/Kconfig  |   1 +
 arch/arm/mach-socfpga/board.c  |  18 +
 arch/arm/mach-socfpga/include/mach/boot0.h |  11 +-
 .../include/mach/fpga_manager_arria10.h|  28 +
 arch/arm/mach-socfpga/include/mach/sdram.h | 434 +---
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
 arch/arm/mach-socfpga/misc_arria10.c   |   5 -
 arch/arm/mach-socfpga/spl.c|  62 ++
 cmd/fpga.c |   2 +-
 common/Makefile|   2 +
 common/load_fs.c   | 163 +
 common/spl/Kconfig |   8 +
 common/spl/spl_mmc.c   |   2 +-
 configs/socfpga_arria10_defconfig  |  57 +-
 doc/README.SPL |   1 +
 .../fpga/altera-socfpga-a10-fpga-mgr.txt   |  11 +
 drivers/ddr/altera/Kconfig |   2 +-
 drivers/ddr/altera/Makefile|   3 +-
 drivers/ddr/altera/sdram_arria10.c | 736 +
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
 drivers/fpga/altera.c  |  40 +-
 drivers/fpga/fpga.c|   8 +
 drivers/fpga/socfpga_arria10.c | 442 -
 fs/Makefile|   1 +
 include/altera.h   |   6 +
 include/configs/socfpga_common.h   |  23 +-
 include/fpga.h |   2 +
 include/load_fs.h  |  40 ++
 include/spl.h  |   2 +
 31 files changed, 1659 insertions(+), 465 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 create mode 100644 common/load_fs.c
 create mode 100644 drivers/ddr/altera/sdram_arria10.c
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
 create mode 100644 include/load_fs.h

-- 
2.2.0

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[U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager

[tien . fong . chee]

From: Tien Fong Chee 

This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.

Signed-off-by: Tien Fong Chee 
---
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt 
b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..47c695b 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,14 @@ Required properties:
- The second index is for writing FPGA configuration data.
 - resets : Phandle and reset specifier for the device's reset.
 - clocks : Clocks used by the device.
+- altr,bitstream_periph : FPGA peripheral raw binary file which is used to
+  initialize FPGA IOs, PLL, IO48 and DDR.
+- altr,bitstream_core : FPGA core raw binary file contains FPGA design which is
+   used to program FPGA CRAM and ERAM.
+- altr,bitstream_devpart : Partition of flash device where bitstream files are
+  stored.
+- dev is flash device number, part is
+ flash device partition.
 
 Example:
 
@@ -16,4 +24,7 @@ Example:
   0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+   altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+   altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+   altr,bitstream_devpart = "0:1";
};
-- 
2.2.0

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[U-Boot] [PATCH v3 05/20] fs: Enable generic filesystems interface support in SPL.

[tien . fong . chee]

From: Tien Fong Chee 

Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Simon Glass 
---
 common/spl/Kconfig | 8 
 doc/README.SPL | 1 +
 fs/Makefile| 1 +
 3 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b05ec21..ca25a2d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -304,6 +304,14 @@ config SPL_ETH_SUPPORT
  is required since the network stack uses a number of environment
  variables. See also SPL_NET_SUPPORT.
 
+config SPL_FS_GENERIC
+   bool "Support Generic filesystems interface driver"
+   help
+ Enable support for generic filesystems interface with SPL. This
+ permits U-Boot (or Linux in Falcon mode) to be loaded from a generic
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
 config SPL_EXT_SUPPORT
bool "Support EXT filesystems"
help
diff --git a/doc/README.SPL b/doc/README.SPL
index 3ba313c..32628a4 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -55,6 +55,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_EXT_SUPPORT
+CONFIG_SPL_FS_GENERIC (fs/fs.o fat/)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/fs/Makefile b/fs/Makefile
index 5770f41..fdacac8 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -7,6 +7,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FS_GENERIC) += fs.o fat/
 obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
 obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
 else
-- 
2.2.0

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[U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct polling status bit

[tien . fong . chee]

From: Tien Fong Chee 

Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling the wrong status bit. Fix with correct polling status bit.

Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")

Signed-off-by: Tien Fong Chee 
---
 drivers/fpga/socfpga_arria10.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a..e076bda 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -112,13 +112,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-   /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until 
de-asserted,
-* timeout at 1000ms
+   /*
+* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+* de-asserted, timeout at 1000ms
 */
return wait_for_bit(__func__,
&fpga_manager_base->imgcfg_stat,
mask,
-   false, FPGA_TIMEOUT_MSEC, false);
+   true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
-- 
2.2.0

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[U-Boot] [PATCH v3 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS

[tien . fong . chee]

From: Tien Fong Chee 

These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/dts/socfpga_arria10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index 377700d..aeb2be8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -538,6 +538,11 @@
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
reset-names = "fpgamgr";
+   altr,bitstream_periph =
+"ghrd_10as066n2.periph.rbf.mkimage";
+   altr,bitstream_core =
+"ghrd_10as066n2.core.rbf.mkimage";
+   altr,bitstream_devpart = "0:1";
};
 
i2c0: i2c@ffc02200 {
-- 
2.2.0

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[U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface

[tien . fong . chee]

From: Tien Fong Chee 

Add code necessary into the FPGA driver framework in U-Boot
so it can be used via the 'fpga' command for programing Arria 10
SoCFPGA.

Signed-off-by: Tien Fong Chee 
---
 cmd/fpga.c|  2 +-
 drivers/fpga/altera.c | 40 
 drivers/fpga/fpga.c   |  8 
 include/fpga.h|  2 ++
 4 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/cmd/fpga.c b/cmd/fpga.c
index ac6f504..3cb0bcd 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
   "(Xilinx only)\n"
 #endif
 #if defined(CONFIG_CMD_FPGA_LOADFS)
-  "Load device from filesystem (FAT by default) (Xilinx only)\n"
+  "Load device from filesystem (FAT by default)\n"
   "  loadfs [dev] [address] [image size] [blocksize] \n"
   "[] \n"
 #endif
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 135a357..a03e835 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -23,25 +23,31 @@ static const struct altera_fpga {
enum altera_family  family;
const char  *name;
int (*load)(Altera_desc *, const void *, size_t);
+   int (*loadfs)(Altera_desc *, const void *, size_t, fpga_fs_info *);
int (*dump)(Altera_desc *, const void *, size_t);
int (*info)(Altera_desc *);
 } altera_fpga[] = {
 #if defined(CONFIG_FPGA_ACEX1K)
-   { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
-   { Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+   { Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+ACEX1K_info },
+   { Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+ACEX1K_info },
 #elif defined(CONFIG_FPGA_CYCLON2)
-   { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
-   { Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+   { Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
+   { Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_II)
-   { Altera_StratixII, "StratixII", StratixII_load,
+   { Altera_StratixII, "StratixII", StratixII_load, NULL,
  StratixII_dump, StratixII_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_V)
-   { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+   { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL },
 #endif
-#if defined(CONFIG_FPGA_SOCFPGA)
-   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)
+   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL,
+NULL },
+#elif defined(CONFIG_FPGA_SOCFPGA)
+   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL },
 #endif
 };
 
@@ -174,3 +180,21 @@ int altera_info(Altera_desc *desc)
 
return FPGA_SUCCESS;
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+  fpga_fs_info *fpga_fsinfo)
+{
+   const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+   if (!fpga)
+   return FPGA_FAIL;
+
+   debug_cond(FPGA_DEBUG, "%s: Launching the %s FS Loader...\n",
+  __func__, fpga->name);
+   if (fpga->loadfs)
+   return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
+
+   return -EINVAL;
+}
+#endif
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index e0fb1b4..42e901e 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
break;
+#if defined(CONFIG_FPGA_ALTERA)
+   case fpga_altera:
+   ret_val = altera_loadfs(desc->devdesc, buf, size,
+   fpga_fsinfo);
+#else
+   fpga_no_sup((char *)__func__, "Altera devices");
+#endif
+   break;
default:
printf("%s: Invalid or unsupported device type %d\n",
   __func__, desc->devtype);
diff --git a/include/fpga.h b/include/fpga.h
index d768fb1..8920016 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -56,8 +56,10 @@ int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_load(int devnum, const void *buf, size_t bsize,
  bitstream_type bstype);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
 int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
+#endif
 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
   bitstream_type bstype);
 int fpga_dump(int devnum, const void *buf, s

[U-Boot] [PATCH v3 08/20] arm: socfpga: Add drivers for programing FPGA from flash

[tien . fong . chee]

From: Tien Fong Chee 

These drivers handle FPGA program operation from flash loading
RBF to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee 
---
 .../include/mach/fpga_manager_arria10.h|  28 ++
 drivers/fpga/socfpga_arria10.c | 435 -
 include/altera.h   |   6 +
 3 files changed, 467 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..1fc5b92 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -8,6 +8,8 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include 
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   BIT(2)
@@ -89,11 +91,37 @@ struct socfpga_fpga_manager {
u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+   enum rbf_type section;
+   enum rbf_security security;
+};
+
+struct flash_info {
+   char *interface;
+   char *dev_part;
+   char *filename;
+   int fstype;
+   u32 remaining;
+   u32 flash_offset;
+   struct rbf_info rbfinfo;
+   struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+#endif
+void set_flash_devpart(char *name, char *devpart);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index e076bda..bfc8700 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -13,6 +13,13 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #include 
 
@@ -22,6 +29,10 @@
 #define COMPRESSION_OFFSET 229
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
+#define RBF_UNENCRYPTED0xa65c
+#define RBF_ENCRYPTED  0xa65d
+#define ARRIA10RBF_PERIPH  0x0001
+#define ARRIA10RBF_CORE0x8001
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,6 +44,32 @@ static const struct socfpga_system_manager 
*system_manager_base =
 
 static void fpgamgr_set_cd_ratio(unsigned long ratio);
 
+static struct flash_location default_flash_locations[] = {
+   {
+   .name = "mmc",
+   .storage = FLASH_STORAGE_MMC,
+   .flags = FLASH_STORAGE_FS,
+   .devpart = "0:1",
+   },
+};
+
+void set_flash_devpart(char *name, char *devpart)
+{
+   int i;
+   u32 size;
+
+   size = ARRAY_SIZE(default_flash_locations);
+
+   for (i = 0; i < size; i++) {
+   if (!strcmp(default_flash_locations[i].name, name))
+   default_flash_locations[i].devpart = devpart;
+   return;
+   }
+
+   printf("No flash is found\n");
+   return;
+}
+
 static uint32_t fpgamgr_get_msel(void)
 {
u32 reg;
@@ -181,7 +218,8 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int 
cfg_width, u32 *rbf_data,
 
debug("header word %d = %08x\n", 69, rbf_data[69]);
debug("header word %d = %08x\n", 229, rbf_data[229]);
-   debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, 
compress);
+   debug("read from rbf header: encrypt=%d compress=%d\n", encrypt,
+compress);
 
/*
 * from the register map description of cdratio in imgcfg_ctrl_02:
@@ -362,7 +400,8 @@ static int fpgamgr_program_poll_cd(void)
if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
return 0;
 
-   if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 
0) {
+   if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) ==
+0) {
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
@@ -470,6 +509,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+
if (status)
return status;
 
@@ -478,3 +518,394 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
 
return fpgamgr_program_finish();
 }
+
+#if define

[U-Boot] [PATCH v3 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h 
b/arch/arm/mach-socfpga/include/mach/boot0.h
index e06b548..b21b871 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -12,6 +12,13 @@
 
.word   0x1337c0d3; /* SoCFPGA preloader validation word */
.word   0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   .word   0xfeedface; /* Program length(4B) */
+   .word   0xf00dcafe; /*
+* Program entry offset(4B),relative to
+* the start of program header
+*/
+#endif
.word   0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */
nop;
 
-- 
2.2.0

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[U-Boot] [PATCH v3 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name

[tien . fong . chee]

From: Tien Fong Chee 

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 432 +
 .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
 drivers/ddr/altera/Makefile|   2 +-
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
 4 files changed, 7 insertions(+), 433 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index b11228f..137e073 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -8,435 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;   /* 0x10 */
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 __padding0[3];
-   u32 dram_addrw; /* 0x2c */
-   u32 dram_if_width;  /* 0x30 */
-   u32 dram_dev_width;
-   u32 dram_sts;
-   u32 dram_intr;
-   u32 sbe_count;  /* 0x40 */
-   u32 dbe_count;
-   u32 err_addr;
-   u32 drop_count;
-   u32 drop_addr;  /* 0x50 */
-   u32 lowpwr_eq;
-   u32 lowpwr_ack;
-   u32 static_cfg;
-   u32 ctrl_width; /* 0x60 */
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap; /* 0x70 */
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;   /* 0x80 */
-   u32 __padding1;
-   u32 fifo_cfg;
-   u32 protport_default;
-   u32 prot_rule_addr; /* 0x90 */
-   u32 prot_rule_id;
-   u32 prot_rule_data;
-   u32 prot_rule_rdwr;
-   u32 __padding2[3];
-   u32 mp_priority;/* 0xac */
-   u32 mp_weight0; /* 0xb0 */
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0; /* 0xc0 */
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;  /* 0xd0 */
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 __padding3[29];
-   u32 phy_ctrl0;  /* 0x150 */
-   u32 phy_ctrl1;
-   u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 dram_addrw;
-   u32 dram_if_width;
-   u32 dram_dev_width;
-   u32 dram_intr;
-   u32 lowpwr_eq;
-   u32 static_cfg;
-   u32 ctrl_width;
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap;
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;
-   u32 fifo_cfg;
-   u32 mp_priority;
-   u32 mp_weight0;
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0;
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-   u8  activate_0_and_1;
-   u8  activate_0_and_1_wait1;
-   u8  activate_0_and_1_wait2;
-   u8  activate_1;
-   u8  clear_dqs_enable;
-   u8  guaranteed_read;
-   u8  guaranteed_read_cont;
-   u8  guaranteed_write;
-   u8  guaranteed_write_wait0;
-   u8  guaranteed_write_wait1;
-   u8  guaranteed_write_wait2;
-   u8  guaranteed_writ

[U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system

[tien . fong . chee]

From: Tien Fong Chee 

Generic firmware loader framework contains some common functionality
which is reusable by any specific file system firmware loader.

Signed-off-by: Tien Fong Chee 
---
 common/Makefile   |   2 +
 common/load_fs.c  | 163 ++
 include/load_fs.h |  40 ++
 3 files changed, 205 insertions(+)
 create mode 100644 common/load_fs.c
 create mode 100644 include/load_fs.h

diff --git a/common/Makefile b/common/Makefile
index 801ea31..0e591c0 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -130,3 +130,5 @@ obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
 obj-y += s_record.o
 obj-y += xyzModem.o
+
+obj-y += load_fs.o
diff --git a/common/load_fs.c b/common/load_fs.c
new file mode 100644
index 000..9f9ca88
--- /dev/null
+++ b/common/load_fs.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int flash_select_fs_dev(struct flash_location *location)
+{
+   int res;
+
+   switch (location->storage) {
+   case FLASH_STORAGE_MMC:
+   res = fs_set_blk_dev("mmc", location->devpart, FS_TYPE_ANY);
+   break;
+   case FLASH_STORAGE_USB:
+   res = fs_set_blk_dev("usb", location->devpart, FS_TYPE_ANY);
+   break;
+   case FLASH_STORAGE_SATA:
+   res = fs_set_blk_dev("sata", location->devpart, FS_TYPE_ANY);
+   break;
+   case FLASH_STORAGE_NAND:
+   if (location->ubivol != NULL)
+   res = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS);
+   else
+   res = -ENODEV;
+   break;
+   default:
+   printf("Error: unsupported location storage.\n");
+   return -ENODEV;
+   }
+
+   if (res)
+   printf("Error: could not access storage.\n");
+
+   return res;
+}
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_USB_STORAGE
+static int flash_init_usb(void)
+{
+   int err;
+
+   err = usb_init();
+   if (err)
+   return err;
+
+#ifndef CONFIG_DM_USB
+   err = usb_stor_scan(1) < 0 ? -ENODEV : 0;
+#endif
+
+   return err;
+}
+#else
+static inline int flash_init_usb(void)
+{
+   printf("Cannot load flash image: no USB support\n");
+   return -ENOSYS;
+}
+#endif
+#endif
+
+#ifdef CONFIG_SATA
+static int flash_init_sata(void)
+{
+   return sata_probe(0);
+}
+#else
+static inline int flash_init_sata(void)
+{
+   printf("Cannot load flash image: no SATA support\n");
+   return -ENOSYS;
+}
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+static int flash_mount_ubifs(struct flash_location *location)
+{
+   int res;
+   char cmd[32];
+
+   sprintf(cmd, "ubi part %s", location->mtdpart);
+   res = run_command(cmd, 0);
+   if (res)
+   return res;
+
+   sprintf(cmd, "ubifsmount %s", location->ubivol);
+   res = run_command(cmd, 0);
+
+   return res;
+}
+
+static inline int flash_umount_ubifs(void)
+{
+   return run_command("ubifsumount", 0);
+}
+#else
+static inline int flash_mount_ubifs(struct flash_location *location)
+{
+   printf("Cannot load flash image: no UBIFS support\n");
+   return -ENOSYS;
+}
+
+static inline int flash_umount_ubifs(void)
+{
+   printf("Cannot unmount UBIFS: no UBIFS support\n");
+   return -ENOSYS;
+}
+#endif
+
+__weak char *get_file(void *file_info)
+{
+   return NULL;
+}
+
+__weak int fs_loading(void *file_info, const void *load_addr, size_t bsize)
+{
+   return 0;
+}
+
+int load_fs(struct flash_location *location, void *file_info,
+   const void *load_addr, size_t bsize)
+{
+   int res = 0;
+   char *flash_file;
+
+   flash_file = get_file(file_info);
+   if (!flash_file) {
+   printf("no filename specified.\n");
+   return -EINVAL;
+   }
+
+#ifndef CONFIG_SPL_BUILD
+   if (location->storage == FLASH_STORAGE_USB)
+   res = flash_init_usb();
+#endif
+
+   if (location->storage == FLASH_STORAGE_SATA)
+   res = flash_init_sata();
+
+   if (location->ubivol != NULL)
+   res = flash_mount_ubifs(location);
+
+   if (res)
+   return res;
+
+   res = fs_loading(file_info, load_addr, bsize);
+
+   if (location->ubivol != NULL)
+   flash_umount_ubifs();
+
+   return res;
+}
diff --git a/include/load_fs.h b/include/load_fs.h
new file mode 100644
index 000..a26d630
--- /dev/null
+++ b/include/load_fs.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+
+#ifndef _LOAD_FS_H_
+#define _LOAD_FS_H_
+
+#include 
+
+enum flash_storage {
+   FLASH_STORAGE_NAND,
+   FLASH_STORAGE_SF,
+   FLASH_STORAGE_MMC,
+   FLASH_STORAGE_USB,
+   F

[U-Boot] [PATCH v3 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header

[tien . fong . chee]

From: Tien Fong Chee 

Adding some details about size in bytes to each section.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h 
b/arch/arm/mach-socfpga/include/mach/boot0.h
index 22d9e7f..e06b548 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -11,8 +11,8 @@
.balignl 64,0xf33db33f;
 
.word   0x1337c0d3; /* SoCFPGA preloader validation word */
-   .word   0xc01df00d; /* Version, flags, length */
-   .word   0xcafec0d3; /* Checksum, zero-pad */
+   .word   0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+   .word   0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */
nop;
 
b reset;/* SoCFPGA jumps here */
-- 
2.2.0

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[U-Boot] [PATCH v3 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL

[tien . fong . chee]

From: Tien Fong Chee 

fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index aeb2be8..1848710 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -532,6 +532,7 @@
};
 
fpga_mgr: fpga-mgr@ffd03000 {
+   u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-fpga-mgr";
reg = <0xffd03000 0x100
   0xffcfe400 0x20>;
-- 
2.2.0

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[U-Boot] [PATCH v3 10/20] arm: socfpga: Add DRAM bank size initialization function

[tien . fong . chee]

From: Tien Fong Chee 

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee 
Tested-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/board.c| 7 +++
 include/configs/socfpga_common.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index a41d089..965f9dc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -29,6 +29,13 @@ int board_init(void)
return 0;
 }
 
+int dram_init_banksize(void)
+{
+   fdtdec_setup_memory_banksize();
+
+   return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
.usb_gusbcfg= 0x1417,
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 7b5417a..0d1cde6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -43,6 +43,7 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE  PHYS_SDRAM_1_SIZE
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE   0x0840
 #else
-- 
2.2.0

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[U-Boot] [PATCH v3 18/20] arm: socfpga: Enable function visible to other file

[tien . fong . chee]

From: Tien Fong Chee 

Enable function visible to other file, so it can be used by other
functions from other file.

Signed-off-by: Tien Fong Chee 
---
 common/spl/spl_mmc.c | 2 +-
 include/spl.h| 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index b26..159443f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev;
diff --git a/include/spl.h b/include/spl.h
index ce4cf0a..e24433d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include 
 #include 
+#include 
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL  0x13578642
@@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
-- 
2.2.0

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[U-Boot] [PATCH v3 12/20] configs: Add DDR Kconfig support for Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/Kconfig | 1 +
 drivers/ddr/altera/Kconfig| 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..3e7a68a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5
 config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+   select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d..2b28a97 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
 config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
-   depends on TARGET_SOCFPGA_GEN5
+   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
  Enable DDR SDRAM controller for the SoCFPGA devices.
-- 
2.2.0

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[U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working

[tien . fong . chee]

From: Tien Fong Chee 

SPL configures DDR by programming peripheral raw binary file
and calibrating DDR.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/spl.c | 56 +
 1 file changed, 56 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index aba116d..6c9bf81 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -22,6 +23,10 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
@@ -29,6 +34,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE  4096
+#define PERIPH_RBF 0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+   int rval = 0;
+   int len = 0;
+   u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+   struct spl_boot_device bootdev;
+   fpga_fs_info fpga_fsinfo;
+
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
WATCHDOG_RESET();
@@ -214,6 +228,48 @@ void spl_board_init(void)
 
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
+
+   bootdev.boot_device = spl_boot_device();
+
+   if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+   struct mmc *mmc = NULL;
+   int err = 0;
+
+   spl_mmc_find_device(&mmc, bootdev.boot_device);
+
+   err = mmc_init(mmc);
+
+   if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("spl: mmc init failed with error: %d\n", err);
+#endif
+   return;
+   }
+
+   fpga_fsinfo.interface = "mmc";
+   fpga_fsinfo.fstype = FS_TYPE_FAT;
+   }
+
+   fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+   &len);
+
+   fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+&len,
+PERIPH_RBF);
+
+   /* Program peripheral RBF */
+   if (fpga_fsinfo.filename)
+   rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+   else {
+   printf("Failed to find peripheral RBF file from DTS\n");
+   return;
+   }
+
+   if (!rval) {
+   config_pins(gd->fdt_blob, "shared");
+
+   ddr_calibration_sequence();
+   }
 }
 
 void board_init_f(ulong dummy)
-- 
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[U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

Add DDR driver suppport for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_arria10.c | 736 +
 4 files changed, 741 insertions(+)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index 137e073..33f830b 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..e7a2503 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
u32 ip_rev_id;
@@ -204,6 +205,7 @@ struct socfpga_io48_mmr {
u32 niosreserve1;
u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1F00
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
diff --git a/drivers/ddr/altera/sdram_arria10.c 
b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 000..be8aff3
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static unsigned long long sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK   (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+   (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTSARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE0xFFD0507C
+#define DDR_REG_CORE2SEQ0xFFD05078
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_SIZE_2GB_HEX   0x8000
+#define DDR_MAX_TRIES  0x0010
+
+#define IO48_MMR_DRAMSTS   0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE00xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE10xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE20xFFCFA118
+
+#define SEQ2CORE_MASK  0xF
+#define CORE2SEQ_INT_REQ   0xF
+#define SEQ2CORE_INT_RESP_BIT  3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+   (void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+   (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+   *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+   (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The followring are the supported configurations */
+static u32 ddr_config[] = {
+   /* Chip - Row - Bank - Column Style */
+   /* All Types */
+   ARRIA_DDR_CONFIG(0, 3, 10, 12),
+   ARRIA_DDR_CONFIG(0, 3, 10, 13),
+   ARRIA_DDR_CONFIG(0, 3, 10, 14),
+   ARRIA_DDR_CONFIG(0, 3, 10, 15),
+   ARRIA_DDR_CONFIG(0, 3, 10, 16),
+   ARRIA_DDR_CONFIG(0, 3, 10, 17),
+   /* LPDDR x16 */
+   ARRIA_DDR_CONFIG(0, 3, 11, 14),
+   ARRIA_DDR_CONFIG(0, 3, 11, 15),
+   ARRIA_DDR_CONFIG(0, 3, 11, 16),
+   ARRIA_DDR_CONFIG(0, 3, 12, 15),
+   /* DDR4 Only */
+   ARRIA_DDR_CONFIG(0, 4, 10, 14),
+   ARRIA_DDR_CONFIG(0, 4, 10, 15),
+   ARRIA_DDR_CONFIG(0, 4, 10, 16),
+   ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+   /* Chip - Bank - Row - Column Style */
+   ARRIA_DDR_CONFIG(1, 3, 10, 12),
+   ARRIA_DDR_CONFIG(1, 3, 10, 13),
+   ARRIA_DDR_CONFIG(1, 3, 10, 14),
+   ARRIA_DDR_CONFIG(1, 3, 10, 15),
+   ARRIA_DDR_CONFIG(1, 3, 10, 16),
+   ARRIA_DDR_CONFIG(1, 3, 10, 17),
+   ARRIA_DDR_CONFIG(1, 3, 11, 14),
+   ARRIA_DDR_CONFIG(1, 3, 11, 15),
+   ARRIA_DDR_CONFIG(1, 3, 11, 16),
+   ARR

[U-Boot] [PATCH v3 13/20] arm: socfpga: Enable SPL memory allocation

[tien . fong . chee]

From: Tien Fong Chee 

Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee 
---
 include/configs/socfpga_common.h | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0d1cde6..218eb05 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -274,17 +274,33 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0x_ .. Start of SRAM
  * 0x_ .. Top of stack (grows down)
  * 0x_ .. Malloc area
  * 0x_ .. Global Data
  * 0x_FF00 .. End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_ .. Start of SRAM (bottom)
+ * 0xFFEx_ .. Top of stack (grows down to bottom)
+ * 0xFFEy_ .. Global Data
+ * 0xFFEz_ .. Malloc area (grows up to top)
+ * 0xFFE3_ .. End of SRAM (top)
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SIZE - \
+CONFIG_SYS_SPL_MALLOC_SIZE + \
+CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -314,7 +330,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK   CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-- 
2.2.0

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[U-Boot] [PATCH v3 20/20] arm: socfpga: Enable SPL booting U-boot

[tien . fong . chee]

From: Tien Fong Chee 

Enable SPL successfully boot to U-boot.

Signed-off-by: Tien Fong Chee 
---
 configs/socfpga_arria10_defconfig | 57 +--
 1 file changed, 49 insertions(+), 8 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 4c73d73..c59d054 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,34 +1,75 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DOS_PARTITION=y
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DOS_PARTITION=y
+CONFIG_SPL_FS_GENERIC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.0

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[U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot

[tien . fong . chee]

From: Tien Fong Chee 

SoC FPGA info is required in both SPL and U-boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c| 3 +++
 arch/arm/mach-socfpga/misc_arria10.c | 5 -
 arch/arm/mach-socfpga/spl.c  | 6 ++
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 9a96f52..7beb347 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -32,6 +32,9 @@ int board_init(void)
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 #endif
 
return 0;
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index 9d751f6..8760ac9 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -94,11 +94,6 @@ int arch_early_init_r(void)
/* assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
 
-   /* configuring the clock based on handoff */
-   /* TODO: Add call to cm_basic_init() */
-
-   /* Add device descriptor to FPGA device table */
-   socfpga_fpga_add();
return 0;
 }
 #else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 71bae82..aba116d 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -208,6 +209,11 @@ void spl_board_init(void)
 
/* enable console uart printing */
preloader_console_init();
+
+   WATCHDOG_RESET();
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)
-- 
2.2.0

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[U-Boot] [PATCH v3 16/20] arm: socfpga: Adding clock frequency info for U-boot

[tien . fong . chee]

From: Tien Fong Chee 

Clock frequency info is required in U-boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..9a96f52 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -8,7 +8,10 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
+#include 
 #include 
 
 #include 
@@ -26,6 +29,11 @@ int board_init(void)
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+#endif
+
return 0;
 }
 
-- 
2.2.0

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Re: [U-Boot] fsl_esdhc driver is broken with DM

[Lukasz Majewski]

On Wed, 11 Oct 2017 14:41:38 -0400
Tom Rini  wrote:

> On Wed, Oct 11, 2017 at 01:09:04PM -0300, Fabio Estevam wrote:
> > On Wed, Oct 11, 2017 at 1:06 PM, Jagan Teki
> >  wrote:
> > 
> > > I've observed here, u-boot is unable to relocate. So when I build
> > > U-Boot with removing u-boot,dm-spl from dts it works fine, but
> > > idea here I need to use SPL_OF_CONTROL and it is not related to
> > > DM_MMC I suppose.
> > 
> > Ok,  a different bug then.
> > 
> > I was wondering if we could have some automated boot tests in
> > U-Boot mainline?
> > 
> > Something like https://kernelci.org/ for U-Boot?
> 
> The problem(s) there are related to lack of hardware support for
> testing firmware in a CI type environment.  For example, I do
> test/py/test.py on real hardware before every push cycle.  The
> problem for iMX in this case at least is that I haven't seen (nor had
> a chance to come up with) the scripting to update u-boot from within
> u-boot, to catch the kind of failures that we don't see when doing
> the USB recovery boot method.  I can test sabrelite via u-boot.imx
> (and in theory I could test my hummingboard with SPL, but my quick
> pass at enabling USB 
> gadget support there didn't seem to work).

If possible you can update SPL and u-boot.img via TFTP

> 
> I would very much welcome more labs running tests however.  There's
> already a few, but I guess the gap we see right here and now is that
> there's none for iMX.
> 

There is some ongoing work to provide such facility. for imx6
boards. I will keep you informed. 


Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 05/11] efi_loader: move efi_search_obj up in code

[Alexander Graf]

On 13.10.17 02:15, Heinrich Schuchardt wrote:
> On 10/09/2017 06:49 AM, Simon Glass wrote:
>> On 7 October 2017 at 22:57, Heinrich Schuchardt  wrote:
>>> To avoid a forward declaration move efi_search_obj before
>>> all protocol services functions.
>>>
>>> Signed-off-by: Heinrich Schuchardt 
>>> ---
>>>  lib/efi_loader/efi_boottime.c | 41 
>>> +
>>>  1 file changed, 21 insertions(+), 20 deletions(-)
>>
>> Reviewed-by: Simon Glass 
>>
> Hello Alex,
> 
> could this patch be merged?
> 
> You merged all preceding patches of the series.

This patch is only needed as prerequisite for SetWatchdogTimer. I think
it's ok to push that out to post-2017.11? We should probably focus on
stability for the release by now...

That doesn't mean the patches will rot on the list - I'll just apply
them to a different branch once the next version of the patch set hits
the ML.


Alex
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[U-Boot] [PATCH 1/3] x86: fsp: Consolidate Azalia header file

[Bin Meng]

So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng 
---

 arch/x86/cpu/baytrail/fsp_configs.c  | 13 
 arch/x86/include/asm/arch-baytrail/fsp/azalia.h  | 39 
 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 26 
 arch/x86/include/asm/fsp/fsp_azalia.h| 39 
 arch/x86/include/asm/fsp/fsp_support.h   |  1 +
 5 files changed, 46 insertions(+), 72 deletions(-)
 delete mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
 create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 45f9bf9..926f26b 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -8,13 +8,12 @@
 
 #include 
 #include 
-#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ALC262 Verb Table - 10EC0262 */
-static const uint32_t verb_table_data13[] = {
+static const u32 verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
0x01171cf0,
0x01171d11,
@@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = {
  * Codec Address: CAd value (0/1/2)
  * Codec Vendor: 0x10EC0262
  */
-static const struct pch_azalia_verb_table azalia_verb_table[] = {
+static const struct azalia_verb_table azalia_verb_table[] = {
{
{
0x10ec0262,
@@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table 
azalia_verb_table[] = {
}
 };
 
-const struct pch_azalia_config azalia_config = {
+const struct azalia_config azalia_config = {
.pme_enable = 1,
.docking_supported = 1,
.docking_attached = 0,
.hdmi_codec_enable = 1,
.azalia_v_ci_enable = 1,
.rsvdbits = 0,
-   .azalia_verb_table_num = 1,
-   .azalia_verb_table = azalia_verb_table,
-   .reset_wait_timer_us = 300
+   .verb_table_num = 1,
+   .verb_table = azalia_verb_table,
+   .reset_wait_timer_ms = 300
 };
 
 /**
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h 
b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
deleted file mode 100644
index d96a20f..000
--- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier:Intel
- */
-
-#ifndef _FSP_AZALIA_H_
-#define _FSP_AZALIA_H_
-
-struct __packed pch_azalia_verb_table_header {
-   uint32_t vendor_device_id;
-   uint16_t sub_system_id;
-   uint8_t revision_id;/* 0xff applies to all steppings */
-   uint8_t front_panel_support;
-   uint16_t number_of_rear_jacks;
-   uint16_t number_of_front_jacks;
-};
-
-struct __packed pch_azalia_verb_table {
-   struct pch_azalia_verb_table_header verb_table_header;
-   const uint32_t *verb_table_data;
-};
-
-struct __packed pch_azalia_config {
-   uint8_t pme_enable:1;
-   uint8_t docking_supported:1;
-   uint8_t docking_attached:1;
-   uint8_t hdmi_codec_enable:1;
-   uint8_t azalia_v_ci_enable:1;
-   uint8_t rsvdbits:3;
-   /* number of verb tables provided by platform */
-   uint8_t azalia_verb_table_num;
-   const struct pch_azalia_verb_table *azalia_verb_table;
-   /* delay timer after azalia reset */
-   uint16_t reset_wait_timer_us;
-};
-
-#endif
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h 
b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
index ecb01fa..99c4c0a 100644
--- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
@@ -29,32 +29,6 @@ struct __packed memory_upd {
u8 reserved[189];   /* Offset 0x0043 */
 };
 
-struct __packed azalia_verb_table_header {
-   u32 vendor_device_id;
-   u16 sub_system_id;
-   u8 revision_id;
-   u8 front_panel_support;
-   u16 number_of_rear_jacks;
-   u16 number_of_front_jacks;
-};
-
-struct __packed azalia_verb_table {
-   struct azalia_verb_table_header header;
-   u32 *data;
-};
-
-struct __packed azalia_config {
-   u8 pme_enable:1;
-   u8 docking_supported:1;
-   u8 docking_attached:1;
-   u8 hdmi_codec_enable:1;
-   u8 azalia_v_ci_enable:1;
-   u8 reserved:3;
-   u8 verb_table_num;
-   struct azalia_verb_table *verb_table;
-   u16 reset_wait_timer_ms;
-};
-
 struct gpio_family {
u32 confg;
u32 confg_changes;
diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h 
b/arch/x86/include/asm/fsp/fsp_azalia.h
new file mode 100644
index 000..a1467bf
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_azalia.h
@@ -0,0

[U-Boot] [PATCH 3/3] x86: baytrail: fsp: Move Azalia update codes to board

[Bin Meng]

Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng 
---

 arch/x86/cpu/baytrail/fsp_configs.c| 111 +
 .../som-db5800-som-6867/som-db5800-som-6867.c  | 111 +
 2 files changed, 113 insertions(+), 109 deletions(-)

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 3052fb6..6b762e5 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -12,122 +12,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* ALC262 Verb Table - 10EC0262 */
-static const u32 verb_table_data13[] = {
-   /* Pin Complex (NID 0x11) */
-   0x01171cf0,
-   0x01171d11,
-   0x01171e11,
-   0x01171f41,
-   /* Pin Complex (NID 0x12) */
-   0x01271cf0,
-   0x01271d11,
-   0x01271e11,
-   0x01271f41,
-   /* Pin Complex (NID 0x14) */
-   0x01471c10,
-   0x01471d40,
-   0x01471e01,
-   0x01471f01,
-   /* Pin Complex (NID 0x15) */
-   0x01571cf0,
-   0x01571d11,
-   0x01571e11,
-   0x01571f41,
-   /* Pin Complex (NID 0x16) */
-   0x01671cf0,
-   0x01671d11,
-   0x01671e11,
-   0x01671f41,
-   /* Pin Complex (NID 0x18) */
-   0x01871c20,
-   0x01871d98,
-   0x01871ea1,
-   0x01871f01,
-   /* Pin Complex (NID 0x19) */
-   0x01971c21,
-   0x01971d98,
-   0x01971ea1,
-   0x01971f02,
-   /* Pin Complex (NID 0x1A) */
-   0x01a71c2f,
-   0x01a71d30,
-   0x01a71e81,
-   0x01a71f01,
-   /* Pin Complex */
-   0x01b71c1f,
-   0x01b71d40,
-   0x01b71e21,
-   0x01b71f02,
-   /* Pin Complex */
-   0x01c71cf0,
-   0x01c71d11,
-   0x01c71e11,
-   0x01c71f41,
-   /* Pin Complex */
-   0x01d71c01,
-   0x01d71dc6,
-   0x01d71e14,
-   0x01d71f40,
-   /* Pin Complex */
-   0x01e71cf0,
-   0x01e71d11,
-   0x01e71e11,
-   0x01e71f41,
-   /* Pin Complex */
-   0x01f71cf0,
-   0x01f71d11,
-   0x01f71e11,
-   0x01f71f41,
-};
-
-/*
- * This needs to be in ROM since if we put it in CAR, FSP init loses it when
- * it drops CAR.
- *
- * TODO(s...@chromium.org): Move to device tree when FSP allows it
- *
- * VerbTable: (RealTek ALC262)
- * Revision ID = 0xFF, support all steps
- * Codec Verb Table For AZALIA
- * Codec Address: CAd value (0/1/2)
- * Codec Vendor: 0x10EC0262
- */
-static const struct azalia_verb_table azalia_verb_table[] = {
-   {
-   {
-   0x10ec0262,
-   0x,
-   0xff,
-   0x01,
-   0x000b,
-   0x0002,
-   },
-   verb_table_data13
-   }
-};
-
-const struct azalia_config azalia_config = {
-   .pme_enable = 1,
-   .docking_supported = 1,
-   .docking_attached = 0,
-   .hdmi_codec_enable = 1,
-   .azalia_v_ci_enable = 1,
-   .rsvdbits = 0,
-   .verb_table_num = 1,
-   .verb_table = azalia_verb_table,
-   .reset_wait_timer_ms = 300
-};
-
 /**
  * Override the FSP's Azalia configuration data
  *
  * @azalia:pointer to be updated to point to a ROM address where Azalia
  * configuration data is stored
  */
-static void update_fsp_azalia_configs(struct azalia_config **azalia)
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
 {
-   *azalia = (struct azalia_config *)&azalia_config;
+   *azalia = NULL;
 }
 
 /**
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c 
b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
index 6158795..202e9875 100644
--- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -6,6 +6,117 @@
  */
 
 #include 
+#include 
+
+/* ALC262 Verb Table - 10EC0262 */
+static const u32 verb_table_data13[] = {
+   /* Pin Complex (NID 0x11) */
+   0x01171cf0,
+   0x01171d11,
+   0x01171e11,
+   0x01171f41,
+   /* Pin Complex (NID 0x12) */
+   0x01271cf0,
+   0x01271d11,
+   0x01271e11,
+   0x01271f41,
+   /* Pin Complex (NID 0x14) */
+   0x01471c10,
+   0x01471d40,
+   0x01471e01,
+   0x01471f01,
+   /* Pin Complex (NID 0x15) */
+   0x01571cf0,
+   0x01571d11,
+   0x01571e11,
+   0x01571f41,
+   /* Pin Complex (NID 0x16) */
+   0x01671cf0,
+   0x01671d11,
+   0x01671e11,
+   0x01671f41,
+   /* Pin Complex (NID 0x18) */
+   0x01871c20,
+   0x01871d98,
+   0x01871ea1,
+   0x01871f01,
+   /* Pin Co

[U-Boot] [PATCH 2/3] x86: baytrail: fsp: Use a function to update the Azalia config pointer

[Bin Meng]

At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng 
---

 arch/x86/cpu/baytrail/fsp_configs.c  | 15 +--
 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 926f26b..3052fb6 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -120,6 +120,17 @@ const struct azalia_config azalia_config = {
 };
 
 /**
+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia:pointer to be updated to point to a ROM address where Azalia
+ * configuration data is stored
+ */
+static void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+   *azalia = (struct azalia_config *)&azalia_config;
+}
+
+/**
  * Override the FSP's configuration data.
  * If the device tree does not specify an integer setting, use the default
  * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf 
file.
@@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config,
rt_buf->common.boot_mode = config->common.boot_mode;
rt_buf->common.upd_data = &config->fsp_upd;
 
-   fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
-
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
if (node < 0) {
debug("%s: Cannot find FSP node\n", __func__);
@@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config,
SATA_MODE_AHCI);
fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
 "fsp,enable-azalia");
+   if (fsp_upd->enable_azalia)
+   update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr);
fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
   LPE_MODE_PCI);
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h 
b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
index 8c07b37..e2f0e39 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -45,7 +45,7 @@ struct __packed upd_region {
uint8_t enable_sata;/* Offset 0x002d */
uint8_t sata_mode;  /* Offset 0x002e */
uint8_t enable_azalia;  /* Offset 0x002f */
-   uint32_t azalia_config_ptr; /* Offset 0x0030 */
+   struct azalia_config *azalia_cfg_ptr;   /* Offset 0x0030 */
uint8_t enable_xhci;/* Offset 0x0034 */
uint8_t lpe_mode;   /* Offset 0x0035 */
uint8_t lpss_sio_mode;  /* Offset 0x0036 */
-- 
2.7.4

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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Marc Zyngier]

On 13/10/17 08:26, Michal Simek wrote:
> On 13.10.2017 09:19, Alexander Graf wrote:
>>
>>
>> On 13.10.17 09:08, Michal Simek wrote:
>>> AArch32 Linux should start in EL1 instead of EL2.
>>
>> Why? There is KVM on AArch32 as well.
> 
> Is AArch32 without KVM able to start from EL2?
> At least based on my tests this is not working.

Then someone broke it. Please report the bug on LAKML.

Thanks,

M.
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[U-Boot] [PULL] efi patch queue 2017-10-13

[Alexander Graf]

Hi Tom,

This is my current patch queue for efi.  Please pull.

Alex


The following changes since commit 39dd65a059e503883dbf16d4c00ac083d15837da:

  sandbox: Enable btrfs support (2017-10-03 08:44:55 -0400)

are available in the git repository at:

  git://github.com/agraf/u-boot.git tags/signed-efi-next

for you to fetch changes up to abe994633b2ad56c5eea87c9253873f41dab477d:

  efi_selftest: correctly check return values (2017-10-13 10:24:22 +0200)


Patch queue for efi - 2017-10-13

This is the second batch of amazing improvements for efi_loader in 2017.11:

  - New self tests to verify our own code
  - A few bug fixes
  - colored text support
  - event and SNP improvements, should get us close to iPXE working


Heinrich Schuchardt (32):
  efi_loader: support 16 protocols per efi_object
  efi_loader: allow creating new handles
  efi_selftest: enable CONFIG_CMD_BOOTEFI_SELFTEST
  efi_selftest: use efi_st_error for all error messages
  efi_loader: use type bool for event states
  efi_selftest: make tests easier to read
  efi_loader: provide function comments for boot services
  efi_loader: replace efi_div10 by do_div
  efi_loader: call EFI_EXIT in efi_copy_mem, efi_set_mem
  efi_loader: parameters of CopyMem and SetMem
  efi_loader: pass GUIDs as const efi_guid_t *
  efi_loader: wrong type in wait_for_event
  efi_loader: incorrect definition of EFI_SIMPLE_NETWORK_PROTOCOL
  efi_loader: correct bits of receive_filters bit mask
  efi_loader: fill simple network protocol revision
  efi_loader: efi_net: hwaddr_size = 6
  efi_net: return EFI_UNSUPPORTED where appropriate
  efi_loader: use events for efi_net_receive
  efi_loader: implement WaitForPacket event
  efi_loader: fix efi_net_get_status
  efi_loader: size fields in SimpleNetworkProtocol
  efi_loader: fill return values in SimpleNetworkProtocol
  efi_selftest: correct definition of efi_st_error
  efi_selftest: allow printing MAC addresses
  efi_loader: supply EFI network test
  efi_selftest: efi_st_memcmp return difference of bytes
  efi_selftest: avoid dereferencing NULL in tpl test
  efi_loader: avoid NULL dereference in efi_dp_match
  efi_loader: comments for functions add missing @return
  efi_selftest: error handling in SNP test
  efi_loader: MAX_UTF8_PER_UTF16 = 3
  efi_selftest: correctly check return values

Jonathan Gray (2):
  efi_loader: search all possible disk partitions
  efi_loader: don't increment part twice per loop

Rob Clark (3):
  efi_loader: Fix disk dp's for pre-DM/legacy devices
  efi_loader: Add mem-mapped for fallback
  efi_loader: console support for color attributes

 cmd/bootefi.c|  23 +
 configs/qemu-x86_64_defconfig|   1 +
 configs/qemu-x86_defconfig   |   1 +
 include/charset.h|   4 +-
 include/efi_api.h| 103 ++-
 include/efi_loader.h |  15 +-
 include/efi_selftest.h   |  18 +-
 lib/efi_loader/efi_boottime.c| 788 ---
 lib/efi_loader/efi_console.c |  29 +-
 lib/efi_loader/efi_device_path.c |  24 +
 lib/efi_loader/efi_device_path_to_text.c |   9 +
 lib/efi_loader/efi_disk.c|  26 +-
 lib/efi_loader/efi_net.c | 143 +++-
 lib/efi_selftest/Makefile|   8 +-
 lib/efi_selftest/efi_selftest.c  |  37 +-
 lib/efi_selftest/efi_selftest_console.c  |  41 +-
 lib/efi_selftest/efi_selftest_events.c   |  84 +--
 lib/efi_selftest/efi_selftest_exitbootservices.c |  46 +-
 lib/efi_selftest/efi_selftest_snp.c  | 431 +
 lib/efi_selftest/efi_selftest_tpl.c  |  90 +--
 lib/efi_selftest/efi_selftest_util.c |  25 +
 21 files changed, 1688 insertions(+), 258 deletions(-)
 create mode 100644 lib/efi_selftest/efi_selftest_snp.c
 create mode 100644 lib/efi_selftest/efi_selftest_util.c
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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Michal Simek]

On 13.10.2017 10:33, Marc Zyngier wrote:
> On 13/10/17 08:26, Michal Simek wrote:
>> On 13.10.2017 09:19, Alexander Graf wrote:
>>>
>>>
>>> On 13.10.17 09:08, Michal Simek wrote:
 AArch32 Linux should start in EL1 instead of EL2.
>>>
>>> Why? There is KVM on AArch32 as well.
>>
>> Is AArch32 without KVM able to start from EL2?
>> At least based on my tests this is not working.
> 
> Then someone broke it. Please report the bug on LAKML.

Do you have any kernel version which you are sure it should work?
Or any kernel version which you know that it started to work?

Thanks,
Michal

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Re: [U-Boot] [PATCH] arm: Start AArch32 Linux in EL1 instead of EL2 on AArch64

[Marc Zyngier]

On 13/10/17 09:37, Michal Simek wrote:
> On 13.10.2017 10:33, Marc Zyngier wrote:
>> On 13/10/17 08:26, Michal Simek wrote:
>>> On 13.10.2017 09:19, Alexander Graf wrote:


 On 13.10.17 09:08, Michal Simek wrote:
> AArch32 Linux should start in EL1 instead of EL2.

 Why? There is KVM on AArch32 as well.
>>>
>>> Is AArch32 without KVM able to start from EL2?
>>> At least based on my tests this is not working.
>>
>> Then someone broke it. Please report the bug on LAKML.
> 
> Do you have any kernel version which you are sure it should work?
> Or any kernel version which you know that it started to work?
It should have worked from the day 32bit KVM was merged (3.9), and still
does as of 4.13.

M.
-- 
Jazz is not dead. It just smells funny...
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[U-Boot] [PATCH 1/3] kbuild: Get rid of KBUILD_STR

[Masahiro Yamada]

From: Michal Marek 

The compiler can accept -DKBUILD_MODNAME="foo", it's just a matter of
quoting. That way, we reduce the gcc command line a bit.

Signed-off-by: Michal Marek 
Signed-off-by: Masahiro Yamada 

[ Linux commit: b42841b7bb6286da56b4fa79835c27166b7e228b ]
---

 scripts/Makefile.lib | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 0d5c529..8934b2f 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -99,10 +99,10 @@ obj-dirs:= $(addprefix $(obj)/,$(obj-dirs))
 # Note: Files that end up in two or more modules are compiled without the
 #   KBUILD_MODNAME definition. The reason is that any made-up name would
 #   differ in different configs.
-name-fix = $(subst $(comma),_,$(subst -,_,$1))
-basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))"
+name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst 
-,_,$1))$(quote)$(squote)
+basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
 modname_flags  = $(if $(filter 1,$(words $(modname))),\
- -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
+ -DKBUILD_MODNAME=$(call name-fix,$(modname)))
 
 orig_c_flags   = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
  $(ccflags-y) $(CFLAGS_$(basetarget).o)
@@ -154,7 +154,7 @@ endif
 # Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE
 c_flags= -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
 $(__c_flags) $(modkern_cflags)   \
--D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
+$(basename_flags) $(modname_flags)
 
 a_flags= -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
 $(__a_flags) $(modkern_aflags)
-- 
2.7.4

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[U-Boot] [PATCH 3/3] kbuild: redefine __FILE__ as relative path from $(srctree) if possible

[Masahiro Yamada]

Since Kbuild runs in the objtree, __FILE__ can be a very long path
depending of $(srctree).

If objtree is a child of srctree, the situation is a bit better.
($(srctree) is "..")

For other cases of out-of-tree build, filenames in WARN_ON() etc. are
still an absolute path.  It also means the U-Boot image depends on
where it was built.

Here, the idea is to redefine __FILE__ as the relative path from
$(srctree), but doing so causes a compiler warning:
  warning: "__FILE__" redefined [-Wbuiltin-macro-redefined]

The option -Wno-builtin-macro-redefined can suppress it, but it is
only recognized by GCC 4.4 or newer.  Redefine __FILE__ only when
possible.

Signed-off-by: Masahiro Yamada 
---

 Makefile | 9 +
 1 file changed, 9 insertions(+)

diff --git a/Makefile b/Makefile
index 888486b..ab7775d 100644
--- a/Makefile
+++ b/Makefile
@@ -1334,6 +1334,15 @@ prepare0: archprepare FORCE
 # All the preparing..
 prepare: prepare0
 
+# If possible, redefne __FILE__ as relative path from $(srctree).
+# $$ is needed to expand the following in submake
+ifeq ($(call cc-option-yn,-Wno-builtin-macro-redefined),y)
+KBUILD_CFLAGS   += -Wno-builtin-macro-redefined \
+  -D__FILE__=$$(call stringify,$$(src)/$$(notdir $$<))
+endif
+# CAUTION: Do not add any reference to KBUILD_CFLAGS below this line.
+# Any call of cc-option, etc. will fail.
+
 # Generate some files
 # ---
 
-- 
2.7.4

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[U-Boot] [PATCH 2/3] kbuild: add stringify helper to quote a string passed to C files

[Masahiro Yamada]

I want to reuse $(squote)$(quote)...$(quote)$(squote) in the next
commit.  Move it to a helper.

Signed-off-by: Masahiro Yamada 
---

 scripts/Kbuild.include | 4 
 scripts/Makefile.lib   | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 2c7918a..48a641c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -30,6 +30,10 @@ baseprereq = $(basename $(notdir $<))
 escsq = $(subst $(squote),'\$(squote)',$1)
 
 ###
+# Quote a string to pass it to C files. foo => '"foo"'
+stringify = $(squote)$(quote)$1$(quote)$(squote)
+
+###
 # Easy method for doing a status message
kecho := :
  quiet_kecho := echo
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 8934b2f..bd0977e 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -99,7 +99,7 @@ obj-dirs  := $(addprefix $(obj)/,$(obj-dirs))
 # Note: Files that end up in two or more modules are compiled without the
 #   KBUILD_MODNAME definition. The reason is that any made-up name would
 #   differ in different configs.
-name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst 
-,_,$1))$(quote)$(squote)
+name-fix = $(call stringify,$(subst $(comma),_,$(subst -,_,$1)))
 basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
 modname_flags  = $(if $(filter 1,$(words $(modname))),\
  -DKBUILD_MODNAME=$(call name-fix,$(modname)))
-- 
2.7.4

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[U-Boot] [PATCH 0/3] kbuild: always use relative path for __FILE__

[Masahiro Yamada]

We discussed the __FILE__ problem when U-Boot is built out of tree.
https://www.mail-archive.com/u-boot@lists.denx.de/msg242852.html

The deeper your build directory is located, the larger
your U-Boot image becomes.
If your platform has memory footprint limit, this is a problem.

Recently, I submitted the following patches to Kbuild ML.
(no RFC, this time)
https://patchwork.kernel.org/patch/10001419/
https://patchwork.kernel.org/patch/10001409/

I consider them for Linux 4.15 unless there is
a strong objection or a problem report.

This series is a port for U-Boot.

If Tom wants to pick this up earlier, it is OK.
If not in hurry, you can wait for the activity in Linux.
Either will do.



Masahiro Yamada (2):
  kbuild: add stringify helper to quote a string passed to C files
  kbuild: redefine __FILE__ as relative path from $(srctree) if possible

Michal Marek (1):
  kbuild: Get rid of KBUILD_STR

 Makefile   | 9 +
 scripts/Kbuild.include | 4 
 scripts/Makefile.lib   | 8 
 3 files changed, 17 insertions(+), 4 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH v2 3/3] kbuild: redefine __FILE__ as relative path from $(srctree) if possible

[Masahiro Yamada]

Since Kbuild runs in the objtree, __FILE__ can be a very long path
depending of $(srctree).

If objtree is a child of srctree, the situation is a bit better.
($(srctree) is "..")

For other cases of out-of-tree build, filenames in WARN_ON() etc. are
still an absolute path.  It also means the U-Boot image depends on
where it was built.

Here, the idea is to redefine __FILE__ as the relative path from
$(srctree), but doing so causes a compiler warning:
  warning: "__FILE__" redefined [-Wbuiltin-macro-redefined]

The option -Wno-builtin-macro-redefined can suppress it, but it is
only recognized by GCC 4.4 or newer.  Redefine __FILE__ only when
possible.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Rephrase comments for clarification
  - Fix a typo

 Makefile | 9 +
 1 file changed, 9 insertions(+)

diff --git a/Makefile b/Makefile
index 888486b..1ff312a 100644
--- a/Makefile
+++ b/Makefile
@@ -1334,6 +1334,15 @@ prepare0: archprepare FORCE
 # All the preparing..
 prepare: prepare0
 
+# If possible, redefine __FILE__ as relative path from $(srctree).
+# $$ is needed to evaluate the variables in sub-directories.
+ifeq ($(call cc-option-yn,-Wno-builtin-macro-redefined),y)
+KBUILD_CFLAGS   += -Wno-builtin-macro-redefined \
+  -D__FILE__=$$(call stringify,$$(src)/$$(notdir $$<))
+endif
+# CAUTION: Do not add any reference to KBUILD_CFLAGS below this line.
+# $(call cc-option,...) etc. may return wrong result.
+
 # Generate some files
 # ---
 
-- 
2.7.4

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[U-Boot] [PATCH v2 2/3] kbuild: add stringify helper to quote a string passed to C files

[Masahiro Yamada]

I want to reuse $(squote)$(quote)...$(quote)$(squote) in the next
commit.  Move it to a helper.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 scripts/Kbuild.include | 4 
 scripts/Makefile.lib   | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 2c7918a..48a641c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -30,6 +30,10 @@ baseprereq = $(basename $(notdir $<))
 escsq = $(subst $(squote),'\$(squote)',$1)
 
 ###
+# Quote a string to pass it to C files. foo => '"foo"'
+stringify = $(squote)$(quote)$1$(quote)$(squote)
+
+###
 # Easy method for doing a status message
kecho := :
  quiet_kecho := echo
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 8934b2f..bd0977e 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -99,7 +99,7 @@ obj-dirs  := $(addprefix $(obj)/,$(obj-dirs))
 # Note: Files that end up in two or more modules are compiled without the
 #   KBUILD_MODNAME definition. The reason is that any made-up name would
 #   differ in different configs.
-name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst 
-,_,$1))$(quote)$(squote)
+name-fix = $(call stringify,$(subst $(comma),_,$(subst -,_,$1)))
 basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
 modname_flags  = $(if $(filter 1,$(words $(modname))),\
  -DKBUILD_MODNAME=$(call name-fix,$(modname)))
-- 
2.7.4

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[U-Boot] [PATCH v2 0/3] kbuild: always use relative path for __FILE__

[Masahiro Yamada]

We discussed the __FILE__ problem when U-Boot is built out of tree.
https://www.mail-archive.com/u-boot@lists.denx.de/msg242852.html

The deeper your build directory is located, the larger
your U-Boot image becomes.
If your platform has memory footprint limit, this is a problem.

Recently, I submitted the following patches to Kbuild ML.
(no RFC, this time)
https://patchwork.kernel.org/patch/10001419/
https://patchwork.kernel.org/patch/10001409/

I consider them for Linux 4.15 unless there is
a strong objection or a problem report.

This series is a port for U-Boot.

If Tom wants to pick this up earlier, it is OK.
If not in hurry, you can wait for the activity in Linux.
Either will do.


Changes in v2:
  - Rephrase comments for clarification
  - Fix a typo

Masahiro Yamada (2):
  kbuild: add stringify helper to quote a string passed to C files
  kbuild: redefine __FILE__ as relative path from $(srctree) if possible

Michal Marek (1):
  kbuild: Get rid of KBUILD_STR

 Makefile   | 9 +
 scripts/Kbuild.include | 4 
 scripts/Makefile.lib   | 8 
 3 files changed, 17 insertions(+), 4 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH v2 1/3] kbuild: Get rid of KBUILD_STR

[Masahiro Yamada]

From: Michal Marek 

The compiler can accept -DKBUILD_MODNAME="foo", it's just a matter of
quoting. That way, we reduce the gcc command line a bit.

Signed-off-by: Michal Marek 
Signed-off-by: Masahiro Yamada 

[ Linux commit: b42841b7bb6286da56b4fa79835c27166b7e228b ]
---

Changes in v2: None

 scripts/Makefile.lib | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 0d5c529..8934b2f 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -99,10 +99,10 @@ obj-dirs:= $(addprefix $(obj)/,$(obj-dirs))
 # Note: Files that end up in two or more modules are compiled without the
 #   KBUILD_MODNAME definition. The reason is that any made-up name would
 #   differ in different configs.
-name-fix = $(subst $(comma),_,$(subst -,_,$1))
-basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))"
+name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst 
-,_,$1))$(quote)$(squote)
+basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
 modname_flags  = $(if $(filter 1,$(words $(modname))),\
- -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
+ -DKBUILD_MODNAME=$(call name-fix,$(modname)))
 
 orig_c_flags   = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
  $(ccflags-y) $(CFLAGS_$(basetarget).o)
@@ -154,7 +154,7 @@ endif
 # Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE
 c_flags= -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
 $(__c_flags) $(modkern_cflags)   \
--D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
+$(basename_flags) $(modname_flags)
 
 a_flags= -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
 $(__a_flags) $(modkern_aflags)
-- 
2.7.4

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[U-Boot] [PATCH 15/20] i2c: uniphier-f: use clk for enable and get_rate

[Masahiro Yamada]

Get clock rate from the clock driver instead of hard-coding it.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/i2c-uniphier-f.c | 19 ---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index eb6c9f3..6f45cc5 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -61,8 +62,6 @@ struct uniphier_fi2c_regs {
 #define I2C_BRST_RSCLO (1 << 0)/* release SCL low fixing */
 };
 
-#define FIOCLK 5000
-
 struct uniphier_fi2c_priv {
struct udevice *dev;
struct uniphier_fi2c_regs __iomem *regs;/* register base */
@@ -93,6 +92,8 @@ static int uniphier_fi2c_probe(struct udevice *dev)
 {
fdt_addr_t addr;
struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
+   struct clk clk;
+   int ret;
 
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -102,7 +103,19 @@ static int uniphier_fi2c_probe(struct udevice *dev)
if (!priv->regs)
return -ENOMEM;
 
-   priv->fioclk = FIOCLK;
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (ret < 0) {
+   dev_err(dev, "failed to get clock\n");
+   return ret;
+   }
+
+   ret = clk_enable(&clk);
+   if (ret) {
+   dev_err(dev, "failed to enable clock\n");
+   return ret;
+   }
+
+   priv->fioclk = clk_get_rate(&clk);
 
priv->dev = dev;
 
-- 
2.7.4

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[U-Boot] [PATCH 14/20] i2c: uniphier: use clk for enable and get_rate

[Masahiro Yamada]

Get clock rate from the clock driver instead of hard-coding it.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/i2c-uniphier.c | 19 ---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index 0f2734e..9100129 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,8 +37,6 @@ struct uniphier_i2c_regs {
u32 setup;  /* setup time control */
 };
 
-#define IOBUS_FREQ 1
-
 struct uniphier_i2c_priv {
struct udevice *dev;
struct uniphier_i2c_regs __iomem *regs; /* register base */
@@ -49,6 +48,8 @@ static int uniphier_i2c_probe(struct udevice *dev)
 {
fdt_addr_t addr;
struct uniphier_i2c_priv *priv = dev_get_priv(dev);
+   struct clk clk;
+   int ret;
 
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -58,7 +59,19 @@ static int uniphier_i2c_probe(struct udevice *dev)
if (!priv->regs)
return -ENOMEM;
 
-   priv->input_clk = IOBUS_FREQ;
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (ret < 0) {
+   dev_err(dev, "failed to get clock\n");
+   return ret;
+   }
+
+   ret = clk_enable(&clk);
+   if (ret) {
+   dev_err(dev, "failed to enable clock\n");
+   return ret;
+   }
+
+   priv->input_clk = clk_get_rate(&clk);
 
priv->dev = dev;
 
-- 
2.7.4

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[U-Boot] [PATCH 04/20] pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3

[Masahiro Yamada]

Like other recenct UniPhier SoCs, the pupdctrl number of PXs3
matches to the pin number.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index 423e48b..7c54d37 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -118,7 +118,8 @@ static struct uniphier_pinctrl_socdata 
uniphier_pxs3_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(uniphier_pxs3_groups),
.functions = uniphier_pxs3_functions,
.functions_count = ARRAY_SIZE(uniphier_pxs3_functions),
-   .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+   .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+   UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
 };
 
 static int uniphier_pxs3_pinctrl_probe(struct udevice *dev)
-- 
2.7.4

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[U-Boot] [PATCH 20/20] ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI

[Masahiro Yamada]

ARCH_UNIPHIER_V8_MULTI depends on !SPL, so the default may be hidden.
Use a clearer default.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 6512d42..0d48e04 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -12,7 +12,7 @@ config ARCH_UNIPHIER_32BIT
 
 choice
 prompt "UniPhier SoC select"
-default ARCH_UNIPHIER_V8_MULTI
+default ARCH_UNIPHIER_V7_MULTI
 
 config ARCH_UNIPHIER_LD4_SLD8
bool "UniPhier LD4/sLD8 SoCs"
-- 
2.7.4

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[U-Boot] [PATCH 11/20] clk: uniphier: add PXs3 clock data

[Masahiro Yamada]

Add basic clock data for Socionext's new SoC PXs3.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/uniphier/clk-uniphier-core.c |  8 
 drivers/clk/uniphier/clk-uniphier-sys.c  | 14 ++
 drivers/clk/uniphier/clk-uniphier.h  |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-core.c 
b/drivers/clk/uniphier/clk-uniphier-core.c
index 3d1d411..9a7d03a 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -296,6 +296,10 @@ static const struct udevice_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-ld20-clock",
.data = (ulong)uniphier_ld20_sys_clk_data,
},
+   {
+   .compatible = "socionext,uniphier-pxs3-clock",
+   .data = (ulong)uniphier_pxs3_sys_clk_data,
+   },
/* Media I/O clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
@@ -325,6 +329,10 @@ static const struct udevice_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-ld20-sd-clock",
.data = (ulong)uniphier_mio_clk_data,
},
+   {
+   .compatible = "socionext,uniphier-pxs3-sd-clock",
+   .data = (ulong)uniphier_mio_clk_data,
+   },
{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c 
b/drivers/clk/uniphier/clk-uniphier-sys.c
index e9df885..f8cf6da 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -30,3 +30,17 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] 
= {
{ /* sentinel */ }
 #endif
 };
+
+const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
+   UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),/* usb30 (gio0) */
+   UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5),/* usb31-0 (gio1) */
+   UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6),/* usb31-1 (gio1-1) */
+   UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16),   /* usb30-phy0 */
+   UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18),   /* usb30-phy1 */
+   UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20),   /* usb30-phy2 */
+   UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17),   /* usb31-phy0 */
+   UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19),   /* usb31-phy1 */
+   { /* sentinel */ }
+#endif
+};
diff --git a/drivers/clk/uniphier/clk-uniphier.h 
b/drivers/clk/uniphier/clk-uniphier.h
index 9b6c94f..77ebae1 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -73,6 +73,7 @@ struct uniphier_clk_data {
 
 extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_mio_clk_data[];
 
 #endif /* __CLK_UNIPHIER_H__ */
-- 
2.7.4

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[U-Boot] [PATCH 19/20] ARM: dts: uniphier: sync DT with Linux 4.14-rc4

[Masahiro Yamada]

Sync with Linux 4.14-rc4.  (Include some DT updates queued up
for Linux 4.15.)

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld11.dtsi| 15 --
 arch/arm/dts/uniphier-ld20.dtsi| 97 --
 arch/arm/dts/uniphier-ld4-ref.dts  |  4 ++
 arch/arm/dts/uniphier-ld4.dtsi |  4 --
 arch/arm/dts/uniphier-ld6b-ref.dts |  4 ++
 arch/arm/dts/uniphier-pinctrl.dtsi | 15 ++
 arch/arm/dts/uniphier-pro4.dtsi|  4 --
 arch/arm/dts/uniphier-pro5.dtsi|  4 --
 arch/arm/dts/uniphier-pxs2.dtsi| 51 
 arch/arm/dts/uniphier-pxs3.dtsi|  4 --
 arch/arm/dts/uniphier-sld8-ref.dts |  4 ++
 arch/arm/dts/uniphier-sld8.dtsi|  4 --
 12 files changed, 174 insertions(+), 36 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 0cc6fd7..2ac1bfc 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -118,7 +118,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
-   clock-frequency = <5882>;
};
 
serial1: serial@54006900 {
@@ -129,7 +128,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
-   clock-frequency = <5882>;
};
 
serial2: serial@54006a00 {
@@ -140,7 +138,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
-   clock-frequency = <5882>;
};
 
serial3: serial@54006b00 {
@@ -151,7 +148,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
-   clock-frequency = <5882>;
+   };
+
+   adamv@5792 {
+   compatible = "socionext,uniphier-ld11-adamv",
+"simple-mfd", "syscon";
+   reg = <0x5792 0x1000>;
+
+   adamv_rst: reset {
+   compatible = 
"socionext,uniphier-ld11-adamv-reset";
+   #reset-cells = <1>;
+   };
};
 
gpio: gpio@5500 {
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index a7fdaa7..b74efb9 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -7,6 +7,8 @@
  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
+#include 
+
 /memreserve/ 0x8000 0x0200;
 
 / {
@@ -46,6 +48,7 @@
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
+   #cooling-cells = <2>;
};
 
cpu1: cpu@1 {
@@ -64,6 +67,7 @@
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
+   #cooling-cells = <2>;
};
 
cpu3: cpu@101 {
@@ -173,6 +177,40 @@
 <1 10 4>;
};
 
+   thermal-zones {
+   cpu_thermal {
+   polling-delay-passive = <250>;  /* 250ms */
+   polling-delay = <1000>; /* 1000ms */
+   thermal-sensors = <&pvtctl>;
+
+   trips {
+   cpu_crit: cpu_crit {
+   temperature = <11>; /* 110C */
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   cpu_alert: cpu_alert {
+   temperature = <10>; /* 100C */
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <&cpu_alert>;
+   cooling-device = <&cpu0
+   THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   map1 {
+   trip = <&cpu_alert>;
+   cooling-device = <&cpu2
+   THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   };
+ 

[U-Boot] [PATCH 01/20] ARM: uniphier: switch to CONFIG_ENV_IS_NOWHERE

[Masahiro Yamada]

The non-volatile storage varies board by board.  The default should
be NOWHERE.  Please choose a proper device via Kconfig.

Signed-off-by: Masahiro Yamada 
---

 env/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/env/Kconfig b/env/Kconfig
index 024d4d7..20516a5 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -3,7 +3,6 @@ menu "Environment"
 choice
prompt "Select the location of the environment"
default ENV_IS_IN_MMC if ARCH_SUNXI
-   default ENV_IS_IN_MMC if ARCH_UNIPHIER
default ENV_IS_IN_MMC if ARCH_EXYNOS4
default ENV_IS_IN_MMC if MX6SX || MX7D
default ENV_IS_IN_MMC if TEGRA30 || TEGRA124
-- 
2.7.4

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[U-Boot] [PATCH 13/20] reset: uniphier: fix the first argument passed to dev_err()

[Masahiro Yamada]

priv->dev does not exist.  Pass the correct pointer to udevice.

Signed-off-by: Masahiro Yamada 
---

 drivers/reset/reset-uniphier.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index c74d16f..a40cea5 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -210,7 +210,8 @@ static int uniphier_reset_update(struct reset_ctl 
*reset_ctl, int assert)
return 0;
}
 
-   dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
+   dev_err(reset_ctl->dev, "reset_id=%lu was not handled\n", id);
+
return -EINVAL;
 }
 
-- 
2.7.4

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[U-Boot] [PATCH 08/20] i2c: uniphier: replace debug() with dev_dbg()

[Masahiro Yamada]

Use dev_dbg() functions.  It will be helpful to prefix log messages
with the corresponding device name when the core framework is ready.

While I am here, I renamed "dev", which was actually private data,
into "priv" because dev->dev looks confusing.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/i2c-uniphier.c | 63 --
 1 file changed, 33 insertions(+), 30 deletions(-)

diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index 3412e2a..0f2734e 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -6,14 +6,14 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
-#include 
+#include 
+#include 
 #include 
+#include 
 
 struct uniphier_i2c_regs {
u32 dtrm;   /* data transmission */
@@ -38,7 +38,8 @@ struct uniphier_i2c_regs {
 
 #define IOBUS_FREQ 1
 
-struct uniphier_i2c_dev {
+struct uniphier_i2c_priv {
+   struct udevice *dev;
struct uniphier_i2c_regs __iomem *regs; /* register base */
unsigned long input_clk;/* master clock (Hz) */
unsigned long wait_us;  /* wait for every byte transfer (us) */
@@ -47,7 +48,7 @@ struct uniphier_i2c_dev {
 static int uniphier_i2c_probe(struct udevice *dev)
 {
fdt_addr_t addr;
-   struct uniphier_i2c_dev *priv = dev_get_priv(dev);
+   struct uniphier_i2c_priv *priv = dev_get_priv(dev);
 
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -59,15 +60,17 @@ static int uniphier_i2c_probe(struct udevice *dev)
 
priv->input_clk = IOBUS_FREQ;
 
+   priv->dev = dev;
+
/* deassert reset */
writel(0x3, &priv->regs->brst);
 
return 0;
 }
 
-static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm)
+static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm)
 {
-   writel(dtrm, &dev->regs->dtrm);
+   writel(dtrm, &priv->regs->dtrm);
 
/*
 * This controller only provides interruption to inform the completion
@@ -75,72 +78,72 @@ static int send_and_recv_byte(struct uniphier_i2c_dev *dev, 
u32 dtrm)
 * Unfortunately, U-Boot does not have a good support of interrupt.
 * Wait for a while.
 */
-   udelay(dev->wait_us);
+   udelay(priv->wait_us);
 
-   return readl(&dev->regs->drec);
+   return readl(&priv->regs->drec);
 }
 
-static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop)
+static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop)
 {
int ret = 0;
u32 drec;
 
-   drec = send_and_recv_byte(dev, dtrm);
+   drec = send_and_recv_byte(priv, dtrm);
 
if (drec & I2C_DREC_LAB) {
-   debug("uniphier_i2c: bus arbitration failed\n");
+   dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n");
*stop = false;
ret = -EREMOTEIO;
}
if (drec & I2C_DREC_LRB) {
-   debug("uniphier_i2c: slave did not return ACK\n");
+   dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n");
ret = -EREMOTEIO;
}
return ret;
 }
 
-static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr,
+static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr,
 uint len, const u8 *buf, bool *stop)
 {
int ret;
 
-   debug("%s: addr = %x, len = %d\n", __func__, addr, len);
+   dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
 
-   ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
+   ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
if (ret < 0)
goto fail;
 
while (len--) {
-   ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop);
+   ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop);
if (ret < 0)
goto fail;
}
 
 fail:
if (*stop)
-   writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm);
+   writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
 
return ret;
 }
 
-static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr,
+static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr,
uint len, u8 *buf, bool *stop)
 {
int ret;
 
-   debug("%s: addr = %x, len = %d\n", __func__, addr, len);
+   dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
 
-   ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK |
+   ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK |
I2C_DTRM_RD | addr << 1, stop);
if (ret < 0)
goto fail;
 
while (len--)
-   *buf++ = send_and_recv_byte(dev,

[U-Boot] [PATCH 06/20] ARM: uniphier: use pr_() instead of printf() where appropriate

[Masahiro Yamada]

Replace printf() with pr_() to specify proper loglevel.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/arm32/psci.c  |  4 +++-
 arch/arm/mach-uniphier/board_late_init.c |  4 +++-
 arch/arm/mach-uniphier/boot-device/boot-device.c |  1 +
 arch/arm/mach-uniphier/cpu-info.c|  7 ---
 arch/arm/mach-uniphier/dram/cmd_ddrmphy.c|  4 +++-
 arch/arm/mach-uniphier/dram/cmd_ddrphy.c |  4 +++-
 arch/arm/mach-uniphier/dram/ddrphy-ld4.c |  5 +++--
 arch/arm/mach-uniphier/dram/umc-pxs2.c   | 18 ++
 arch/arm/mach-uniphier/dram_init.c   |  7 +--
 9 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-uniphier/arm32/psci.c 
b/arch/arm/mach-uniphier/arm32/psci.c
index 3ab101a..efe7419 100644
--- a/arch/arm/mach-uniphier/arm32/psci.c
+++ b/arch/arm/mach-uniphier/arm32/psci.c
@@ -7,8 +7,10 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -91,7 +93,7 @@ static void uniphier_smp_kick_all_cpus(void)
}
 
if (!timeout)
-   printf("warning: some of secondary CPUs may not boot\n");
+   pr_warn("warning: some of secondary CPUs may not boot\n");
 
uniphier_cache_disable();
 }
diff --git a/arch/arm/mach-uniphier/board_late_init.c 
b/arch/arm/mach-uniphier/board_late_init.c
index b9a2cbe..6849b3d 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -10,7 +10,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include <../drivers/mtd/nand/denali.h>
 
 #include "init.h"
@@ -92,7 +94,7 @@ int board_late_init(void)
printf("\n");
 
if (uniphier_set_fdt_file())
-   printf("fdt_file environment was not set correctly\n");
+   pr_warn("fdt_file environment was not set correctly\n");
 
return 0;
 }
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c 
b/arch/arm/mach-uniphier/boot-device/boot-device.c
index 0f93926..2818b50 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include "../init.h"
diff --git a/arch/arm/mach-uniphier/cpu-info.c 
b/arch/arm/mach-uniphier/cpu-info.c
index 90ef411..bf41d05 100644
--- a/arch/arm/mach-uniphier/cpu-info.c
+++ b/arch/arm/mach-uniphier/cpu-info.c
@@ -6,9 +6,10 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
+#include 
 #include 
 #include 
+#include 
 
 #include "soc-info.h"
 
@@ -59,11 +60,11 @@ int print_cpuinfo(void)
printf(" (model %d, revision %d)\n", model, rev);
 
if (model < required_model) {
-   printf("Only model %d or newer is supported.\n",
+   pr_err("Only model %d or newer is supported.\n",
   required_model);
return -ENOTSUPP;
} else if (rev < required_rev) {
-   printf("Only revision %d or newer is supported.\n",
+   pr_err("Only revision %d or newer is supported.\n",
   required_rev);
return -ENOTSUPP;
}
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c 
b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
index 873dad2..50f0dde 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
@@ -6,7 +6,9 @@
  */
 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 #include "../soc-info.h"
@@ -297,7 +299,7 @@ static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
param = uniphier_get_ddrmphy_param();
if (!param) {
-   printf("unsupported SoC\n");
+   pr_err("unsupported SoC\n");
return CMD_RET_FAILURE;
}
 
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c 
b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index a71f704..0283eda 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -7,7 +7,9 @@
  */
 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 #include "../soc-info.h"
@@ -267,7 +269,7 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
param = uniphier_get_ddrphy_param();
if (!param) {
-   printf("unsupported SoC\n");
+   pr_err("unsupported SoC\n");
return CMD_RET_FAILURE;
}
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c 
b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
index c20730d..ba3d314 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
@@ -5,9 +5,10 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
+#include 
 #include 
 #include 
+#include 
 
 #include "ddrphy-init.h"
 #include "ddrphy-regs.h"
@@ -41,7 +42,7 @@ int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int 
freq, bool

[U-Boot] [PATCH 00/20] ARM: uniphier: various refactoring for v2017.11-rc2

[Masahiro Yamada]

 - Reactor of GPIO, clk, reset drivers.
 - Clean up SOC code
 - Sync DT
 - Use more clock drivers
 - Split U-Boot specific DT property


Masahiro Yamada (20):
  ARM: uniphier: switch to CONFIG_ENV_IS_NOWHERE
  gpio: uniphier: rework single device node model
  ARM: dts: uniphier: update GPIO nodes
  pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3
  pinctrl: uniphier: simplify input enable and delete pin arrays
  ARM: uniphier: use pr_() instead of printf() where appropriate
  usb: dwc3-uniphier: replace  with 
  i2c: uniphier: replace debug() with dev_dbg()
  i2c: uniphier-f: replace debug() with dev_dbg()
  clk: uniphier: rework for better clock tree structure
  clk: uniphier: add PXs3 clock data
  clk: uniphier: add peripheral clock data
  reset: uniphier: fix the first argument passed to dev_err()
  i2c: uniphier: use clk for enable and get_rate
  i2c: uniphier-f: use clk for enable and get_rate
  ARM: uniphier: split u-boot,dm-pre-reloc out to
uniphier-v7-u-boot.dtsi
  ARM: dts: uniphier: prepare to use clock for serial
  serial: uniphier: use clk for enable and get_rate
  ARM: dts: uniphier: sync DT with Linux 4.14-rc4
  ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI

 arch/arm/dts/uniphier-ld11.dtsi  |  38 ++-
 arch/arm/dts/uniphier-ld20.dtsi  |  97 ++-
 arch/arm/dts/uniphier-ld4-ref.dts|   9 +-
 arch/arm/dts/uniphier-ld4.dtsi   | 122 +
 arch/arm/dts/uniphier-ld6b-ref.dts   |   9 +-
 arch/arm/dts/uniphier-pinctrl.dtsi   |  15 ++
 arch/arm/dts/uniphier-pro4-ace.dts   |   9 -
 arch/arm/dts/uniphier-pro4-ref.dts   |   9 -
 arch/arm/dts/uniphier-pro4-sanji.dts |  21 --
 arch/arm/dts/uniphier-pro4.dtsi  | 214 +---
 arch/arm/dts/uniphier-pro5-4kbox.dts |   9 -
 arch/arm/dts/uniphier-pro5.dtsi  | 214 +---
 arch/arm/dts/uniphier-pxs2-gentil.dts|  21 --
 arch/arm/dts/uniphier-pxs2-vodka.dts |  21 --
 arch/arm/dts/uniphier-pxs2.dtsi  | 256 ---
 arch/arm/dts/uniphier-pxs3.dtsi  |   7 +-
 arch/arm/dts/uniphier-sld8-ref.dts   |   9 +-
 arch/arm/dts/uniphier-sld8.dtsi  | 126 +-
 arch/arm/dts/uniphier-v7-u-boot.dtsi |  69 +
 arch/arm/dts/uniphier-v8-u-boot.dtsi |  13 +
 arch/arm/mach-uniphier/Kconfig   |   5 +-
 arch/arm/mach-uniphier/arm32/psci.c  |   4 +-
 arch/arm/mach-uniphier/board_late_init.c |   4 +-
 arch/arm/mach-uniphier/boot-device/boot-device.c |   1 +
 arch/arm/mach-uniphier/cpu-info.c|   7 +-
 arch/arm/mach-uniphier/dram/cmd_ddrmphy.c|   4 +-
 arch/arm/mach-uniphier/dram/cmd_ddrphy.c |   4 +-
 arch/arm/mach-uniphier/dram/ddrphy-ld4.c |   5 +-
 arch/arm/mach-uniphier/dram/umc-pxs2.c   |  18 +-
 arch/arm/mach-uniphier/dram_init.c   |   7 +-
 drivers/clk/uniphier/Makefile|   2 +
 drivers/clk/uniphier/clk-uniphier-core.c | 308 +--
 drivers/clk/uniphier/clk-uniphier-mio.c  | 118 -
 drivers/clk/uniphier/clk-uniphier-peri.c | 113 +
 drivers/clk/uniphier/clk-uniphier-sys.c  |  52 ++--
 drivers/clk/uniphier/clk-uniphier.h  |  85 ---
 drivers/gpio/gpio-uniphier.c | 140 +++
 drivers/i2c/i2c-uniphier-f.c | 131 +-
 drivers/i2c/i2c-uniphier.c   |  82 +++---
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c |  17 +-
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c  |  16 --
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c |   5 -
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c |  15 --
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c |   9 -
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c |   3 +-
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c |  30 ---
 drivers/reset/reset-uniphier.c   |   3 +-
 drivers/serial/serial_uniphier.c |  16 +-
 drivers/usb/dwc3/dwc3-uniphier.c |   2 +-
 env/Kconfig  |   1 -
 50 files changed, 1082 insertions(+), 1413 deletions(-)
 create mode 100644 arch/arm/dts/uniphier-v7-u-boot.dtsi
 create mode 100644 arch/arm/dts/uniphier-v8-u-boot.dtsi
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c

-- 
2.7.4

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[U-Boot] [PATCH 03/20] ARM: dts: uniphier: update GPIO nodes

[Masahiro Yamada]

Switch to the single node design.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld11.dtsi |  23 +
 arch/arm/dts/uniphier-ld4.dtsi  | 115 ++
 arch/arm/dts/uniphier-pro4.dtsi | 206 ++--
 arch/arm/dts/uniphier-pro5.dtsi | 206 ++--
 arch/arm/dts/uniphier-pxs2.dtsi | 201 ++-
 arch/arm/dts/uniphier-pxs3.dtsi |   3 +-
 arch/arm/dts/uniphier-sld8.dtsi | 119 +++
 7 files changed, 71 insertions(+), 802 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 0f172c3..0cc6fd7 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -154,6 +154,29 @@
clock-frequency = <5882>;
};
 
+   gpio: gpio@5500 {
+   compatible = "socionext,uniphier-gpio";
+   reg = <0x5500 0x200>;
+   interrupt-parent = <&aidet>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <&pinctrl 0 0 0>,
+ <&pinctrl 43 0 0>,
+ <&pinctrl 51 0 0>,
+ <&pinctrl 96 0 0>,
+ <&pinctrl 160 0 0>,
+ <&pinctrl 184 0 0>;
+   gpio-ranges-group-names = "gpio_range0",
+ "gpio_range1",
+ "gpio_range2",
+ "gpio_range3",
+ "gpio_range4",
+ "gpio_range5";
+   ngpios = <200>;
+   };
+
i2c0: i2c@5878 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index a3bcf22..b816038 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -108,116 +108,17 @@
clock-frequency = <36864000>;
};
 
-   port0x: gpio@5508 {
+   gpio: gpio@5500 {
compatible = "socionext,uniphier-gpio";
-   reg = <0x5508 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port1x: gpio@5510 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5510 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port2x: gpio@5518 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5518 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port3x: gpio@5520 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5520 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port4: gpio@5528 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5528 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port5x: gpio@5530 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5530 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port6x: gpio@5538 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5538 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port7x: gpio@5540 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5540 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port8x: gpio@5548 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5548 0x8>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
-   port9x: gpio@5550 {
-   compatible = "socionext,uniphier-gpio";
-   reg = <0x5550 0x8>;
-   gpio-controll

[U-Boot] [PATCH 10/20] clk: uniphier: rework for better clock tree structure

[Masahiro Yamada]

U-Boot does not support fancy clock tree structures like the Linux
common clock framework.  Implement a simple clock tree model at the
driver level.  With this, the clock data will be simplified.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/uniphier/clk-uniphier-core.c | 267 ++-
 drivers/clk/uniphier/clk-uniphier-mio.c  | 118 +++---
 drivers/clk/uniphier/clk-uniphier-sys.c  |  42 +++--
 drivers/clk/uniphier/clk-uniphier.h  |  79 +
 4 files changed, 323 insertions(+), 183 deletions(-)

diff --git a/drivers/clk/uniphier/clk-uniphier-core.c 
b/drivers/clk/uniphier/clk-uniphier-core.c
index 722cd6b..3d1d411 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
  *   Author: Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -21,104 +21,224 @@
  * @data: SoC specific data
  */
 struct uniphier_clk_priv {
+   struct udevice *dev;
void __iomem *base;
const struct uniphier_clk_data *data;
 };
 
-static int uniphier_clk_enable(struct clk *clk)
+static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
+const struct uniphier_clk_gate_data *gate)
 {
-   struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
-   unsigned long id = clk->id;
-   const struct uniphier_clk_gate_data *p;
+   u32 val;
 
-   for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
-   u32 val;
+   val = readl(priv->base + gate->reg);
+   val |= BIT(gate->bit);
+   writel(val, priv->base + gate->reg);
+}
 
-   if (p->id != id)
-   continue;
+static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
+   const struct uniphier_clk_mux_data *mux,
+   u8 id)
+{
+   u32 val;
+   int i;
 
-   val = readl(priv->base + p->reg);
-   val |= BIT(p->bit);
-   writel(val, priv->base + p->reg);
+   for (i = 0; i < mux->num_parents; i++) {
+   if (mux->parent_ids[i] != id)
+   continue;
 
-   return 0;
+   val = readl(priv->base + mux->reg);
+   val &= ~mux->masks[i];
+   val |= mux->vals[i];
+   writel(val, priv->base + mux->reg);
+   return;
}
 
-   dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
-   return -EINVAL;
+   WARN_ON(1);
 }
 
-static const struct uniphier_clk_mux_data *
-uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
+static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
+ const struct uniphier_clk_mux_data *mux)
 {
-   const struct uniphier_clk_mux_data *p;
+   u32 val;
+   int i;
 
-   for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
-   if (p->id == id)
-   return p;
-   }
+   val = readl(priv->base + mux->reg);
+
+   for (i = 0; i < mux->num_parents; i++)
+   if ((mux->masks[i] & val) == mux->vals[i])
+   return mux->parent_ids[i];
+
+   dev_err(priv->dev, "invalid mux setting\n");
+
+   return UNIPHIER_CLK_ID_INVALID;
+}
+
+static const struct uniphier_clk_data *uniphier_clk_get_data(
+   struct uniphier_clk_priv *priv, u8 id)
+{
+   const struct uniphier_clk_data *data;
+
+   for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
+   if (data->id == id)
+   return data;
+
+   dev_err(priv->dev, "id=%u not found\n", id);
 
return NULL;
 }
 
-static ulong uniphier_clk_get_rate(struct clk *clk)
+static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
+   struct uniphier_clk_priv *priv,
+   const struct uniphier_clk_data *data)
 {
-   struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
-   const struct uniphier_clk_mux_data *mux;
-   u32 val;
-   int i;
+   const struct uniphier_clk_data *parent_data;
+   u8 parent_id = UNIPHIER_CLK_ID_INVALID;
+
+   switch (data->type) {
+   case UNIPHIER_CLK_TYPE_GATE:
+   parent_id = data->data.gate.parent_id;
+   break;
+   case UNIPHIER_CLK_TYPE_MUX:
+   parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
+   break;
+   default:
+   break;
+   }
 
-   mux = uniphier_clk_get_mux_data(priv, clk->id);
-   if (!mux)
-   return 0;
+   if (parent_id == UNIPHIER_CLK_ID_INVALID)
+   return NULL;
 
-   if (!mux->nr_muxs)  /* fixed-rate */
-

[U-Boot] [PATCH 02/20] gpio: uniphier: rework single device node model

[Masahiro Yamada]

First, I implemented this driver as per-bank model, but it was
a design mistake.

  - There are 31 banks in the maximum case.  It is painful to add
so many nodes to DT.

  - The IRQ control registers are shared between banks.  Per-bank
design is a problem for Linux.  The counterpart for Linux turned
around to the single node model.

Rework based on the driver for Linux.

Signed-off-by: Masahiro Yamada 
---

 drivers/gpio/gpio-uniphier.c | 140 +++
 1 file changed, 89 insertions(+), 51 deletions(-)

diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c
index c11e953..107c3fc 100644
--- a/drivers/gpio/gpio-uniphier.c
+++ b/drivers/gpio/gpio-uniphier.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
  *   Author: Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -11,73 +11,123 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
-#define UNIPHIER_GPIO_PORTS_PER_BANK   8
+#define UNIPHIER_GPIO_LINES_PER_BANK   8
 
-#define UNIPHIER_GPIO_REG_DATA 0   /* data */
-#define UNIPHIER_GPIO_REG_DIR  4   /* direction (1:in, 0:out) */
+#define UNIPHIER_GPIO_PORT_DATA0x0 /* data */
+#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
+#define UNIPHIER_GPIO_IRQ_EN   0x90/* irq enable */
 
 struct uniphier_gpio_priv {
-   void __iomem *base;
-   char bank_name[16];
+   void __iomem *regs;
 };
 
-static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset,
-  unsigned reg, int value)
+static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
+{
+   unsigned int reg;
+
+   reg = (bank + 1) * 8;
+
+   /*
+* Unfortunately, the GPIO port registers are not contiguous because
+* offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
+*/
+   if (reg >= UNIPHIER_GPIO_IRQ_EN)
+   reg += 0x10;
+
+   return reg;
+}
+
+static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
+   unsigned int *bank, u32 *mask)
+{
+   *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
+   *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
+}
+
+static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
+unsigned int reg, u32 mask, u32 val)
 {
-   struct uniphier_gpio_priv *priv = dev_get_priv(dev);
u32 tmp;
 
-   tmp = readl(priv->base + reg);
-   if (value)
-   tmp |= BIT(offset);
-   else
-   tmp &= ~BIT(offset);
-   writel(tmp, priv->base + reg);
+   tmp = readl(priv->regs + reg);
+   tmp &= ~mask;
+   tmp |= mask & val;
+   writel(tmp, priv->regs + reg);
 }
 
-static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset,
-unsigned reg)
+static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
+unsigned int reg, u32 mask, u32 val)
 {
struct uniphier_gpio_priv *priv = dev_get_priv(dev);
 
-   return !!(readl(priv->base + reg) & BIT(offset));
+   if (!mask)
+   return;
+
+   uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
+mask, val);
 }
 
-static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset)
+static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int 
offset,
+  unsigned int reg, int val)
 {
-   uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1);
+   unsigned int bank;
+   u32 mask;
 
-   return 0;
+   uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
+
+   uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
 }
 
-static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset,
- int value)
+static int uniphier_gpio_offset_read(struct udevice *dev,
+unsigned int offset, unsigned int reg)
 {
-   uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
-   uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0);
+   struct uniphier_gpio_priv *priv = dev_get_priv(dev);
+   unsigned int bank, reg_offset;
+   u32 mask;
 
-   return 0;
+   uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
+   reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
+
+   return !!(readl(priv->regs + reg_offset) & mask);
 }
 
-static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset)
+static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
 {
-   return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA);
+   return uniphier_gp

[U-Boot] [PATCH 07/20] usb: dwc3-uniphier: replace with

[Masahiro Yamada]

Including  pulls in a lot of bloat.  What this driver needs
is BIT(), so replace it with 

Signed-off-by: Masahiro Yamada 
---

 drivers/usb/dwc3/dwc3-uniphier.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/dwc3-uniphier.c b/drivers/usb/dwc3/dwc3-uniphier.c
index 0d13770..25b17a8 100644
--- a/drivers/usb/dwc3/dwc3-uniphier.c
+++ b/drivers/usb/dwc3/dwc3-uniphier.c
@@ -7,8 +7,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.7.4

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[U-Boot] [PATCH 16/20] ARM: uniphier: split u-boot, dm-pre-reloc out to uniphier-v7-u-boot.dtsi

[Masahiro Yamada]

UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL.  So, many nodes must
be marked as dm-pre-reloc to prevent fdtgrep from stripping them off.

Sprinkling U-Boot specific properties all over the place is painful
because DT files are synced with Linux from time to time.

Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is
appended to UniPhier V7 DTS before the build.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld4-ref.dts |  9 --
 arch/arm/dts/uniphier-ld4.dtsi|  3 --
 arch/arm/dts/uniphier-ld6b-ref.dts|  9 --
 arch/arm/dts/uniphier-pro4-ace.dts|  9 --
 arch/arm/dts/uniphier-pro4-ref.dts|  9 --
 arch/arm/dts/uniphier-pro4-sanji.dts  | 21 
 arch/arm/dts/uniphier-pro4.dtsi   |  4 ---
 arch/arm/dts/uniphier-pro5-4kbox.dts  |  9 --
 arch/arm/dts/uniphier-pro5.dtsi   |  4 ---
 arch/arm/dts/uniphier-pxs2-gentil.dts | 21 
 arch/arm/dts/uniphier-pxs2-vodka.dts  | 21 
 arch/arm/dts/uniphier-pxs2.dtsi   |  4 ---
 arch/arm/dts/uniphier-sld8-ref.dts|  9 --
 arch/arm/dts/uniphier-sld8.dtsi   |  3 --
 arch/arm/dts/uniphier-v7-u-boot.dtsi  | 61 +++
 arch/arm/mach-uniphier/Kconfig|  3 ++
 16 files changed, 64 insertions(+), 135 deletions(-)
 create mode 100644 arch/arm/dts/uniphier-v7-u-boot.dtsi

diff --git a/arch/arm/dts/uniphier-ld4-ref.dts 
b/arch/arm/dts/uniphier-ld4-ref.dts
index 0f50acb..0fd66e7 100644
--- a/arch/arm/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -68,12 +68,3 @@
 &usb1 {
status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-   u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index b816038..158beae 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -50,7 +50,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
-   u-boot,dm-pre-reloc;
 
l2: l2-cache@500c {
compatible = "socionext,uniphier-system-cache";
@@ -295,11 +294,9 @@
compatible = "socionext,uniphier-ld4-soc-glue",
 "simple-mfd", "syscon";
reg = <0x5f80 0x2000>;
-   u-boot,dm-pre-reloc;
 
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
-   u-boot,dm-pre-reloc;
};
};
 
diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts 
b/arch/arm/dts/uniphier-ld6b-ref.dts
index bdb7f50..926d37e 100644
--- a/arch/arm/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ld6b-ref.dts
@@ -70,12 +70,3 @@
 &usb1 {
status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-   u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts 
b/arch/arm/dts/uniphier-pro4-ace.dts
index 8161ba8..60a8c33 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -90,12 +90,3 @@
 &usb3 {
status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-   u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts 
b/arch/arm/dts/uniphier-pro4-ref.dts
index 360b31d..1b22f80 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -83,12 +83,3 @@
 &usb1 {
status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-   u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts 
b/arch/arm/dts/uniphier-pro4-sanji.dts
index 778e2bb..950f47a 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -85,24 +85,3 @@
 &usb3 {
status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-   u-boot,dm-pre-reloc;
-};
-
-&mio_clk {
-   u-boot,dm-pre-reloc;
-};
-
-&emmc {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-   u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
-   u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 5f39972..ea97e26 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -58,7 +58,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
-   u-boot,dm-pre-reloc;
 
l2: l2-cache@500c {
compatible = "socionext,uniphier-system-cache";
@@ -224,7 +223,6 @@
compatible = "socionext,uniphier-pro4-mioctrl",
 "simple-mfd", "syscon";
reg = <0x5981 0x800>;
- 

[U-Boot] [PATCH 12/20] clk: uniphier: add peripheral clock data

[Masahiro Yamada]

Add peripheral clock data for all SoCs.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/uniphier/Makefile|   2 +
 drivers/clk/uniphier/clk-uniphier-core.c |  33 +
 drivers/clk/uniphier/clk-uniphier-peri.c | 113 +++
 drivers/clk/uniphier/clk-uniphier.h  |   5 ++
 4 files changed, 153 insertions(+)
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c

diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 54c7e09..d132cf7 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -1,3 +1,5 @@
 obj-y  += clk-uniphier-core.o
+
 obj-y  += clk-uniphier-sys.o
 obj-y  += clk-uniphier-mio.o
+obj-y  += clk-uniphier-peri.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c 
b/drivers/clk/uniphier/clk-uniphier-core.c
index 9a7d03a..ed5acbd 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -333,6 +333,39 @@ static const struct udevice_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-pxs3-sd-clock",
.data = (ulong)uniphier_mio_clk_data,
},
+   /* Peripheral clock */
+   {
+   .compatible = "socionext,uniphier-ld4-peri-clock",
+   .data = (ulong)uniphier_ld4_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-pro4-peri-clock",
+   .data = (ulong)uniphier_pro4_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-sld8-peri-clock",
+   .data = (ulong)uniphier_sld8_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-pro5-peri-clock",
+   .data = (ulong)uniphier_pro4_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-pxs2-peri-clock",
+   .data = (ulong)uniphier_pxs2_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-ld11-peri-clock",
+   .data = (ulong)uniphier_ld11_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-ld20-peri-clock",
+   .data = (ulong)uniphier_ld11_peri_clk_data,
+   },
+   {
+   .compatible = "socionext,uniphier-pxs3-peri-clock",
+   .data = (ulong)uniphier_ld11_peri_clk_data,
+   },
{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c 
b/drivers/clk/uniphier/clk-uniphier-peri.c
new file mode 100644
index 000..51edcab
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-peri.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_PERI_CLK_UART(id, ch) \
+   UNIPHIER_CLK_GATE(id, 128, 0x24, 19 + (ch))
+
+#define UNIPHIER_PERI_CLK_I2C(id, ch)  \
+   UNIPHIER_CLK_GATE(id, 129, 0x24, 5 + (ch))
+
+#define UNIPHIER_PERI_CLK_FI2C(id, ch) \
+   UNIPHIER_CLK_GATE(id, 129, 0x24, 24 + (ch))
+
+const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
+#ifdef CONFIG_ARCH_UNIPHIER_LD4
+   UNIPHIER_CLK_RATE(128, 36864000),
+   UNIPHIER_CLK_RATE(129, 9984),
+   UNIPHIER_PERI_CLK_UART(0, 0),
+   UNIPHIER_PERI_CLK_UART(1, 1),
+   UNIPHIER_PERI_CLK_UART(2, 2),
+   UNIPHIER_PERI_CLK_UART(3, 3),
+   UNIPHIER_PERI_CLK_I2C(4, 0),
+   UNIPHIER_PERI_CLK_I2C(5, 1),
+   UNIPHIER_PERI_CLK_I2C(6, 2),
+   UNIPHIER_PERI_CLK_I2C(7, 3),
+   UNIPHIER_PERI_CLK_I2C(8, 4),
+   UNIPHIER_PERI_CLK_I2C(9, 5),
+   UNIPHIER_PERI_CLK_I2C(10, 6),
+   { /* sentinel */ }
+#endif
+};
+
+const struct uniphier_clk_data uniphier_sld8_peri_clk_data[] = {
+#ifdef CONFIG_ARCH_UNIPHIER_SLD8
+   UNIPHIER_CLK_RATE(128, 8000),
+   UNIPHIER_CLK_RATE(129, 1),
+   UNIPHIER_PERI_CLK_UART(0, 0),
+   UNIPHIER_PERI_CLK_UART(1, 1),
+   UNIPHIER_PERI_CLK_UART(2, 2),
+   UNIPHIER_PERI_CLK_UART(3, 3),
+   UNIPHIER_PERI_CLK_I2C(4, 0),
+   UNIPHIER_PERI_CLK_I2C(5, 1),
+   UNIPHIER_PERI_CLK_I2C(6, 2),
+   UNIPHIER_PERI_CLK_I2C(7, 3),
+   UNIPHIER_PERI_CLK_I2C(8, 4),
+   UNIPHIER_PERI_CLK_I2C(9, 5),
+   UNIPHIER_PERI_CLK_I2C(10, 6),
+   { /* sentinel */ }
+#endif
+};
+
+const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5)
+   UNIPHIER_CLK_RATE(128, 73728000),
+   UNIPHIER_CLK_RATE(129, 5000),
+   UNIPHIER_PERI_CLK_UART(0, 0),
+   UNIPHIER_PERI_CLK_UART(1, 1),
+   UNIPHIER_PERI_CLK_UART(2, 2),
+   UNIPHIER_PERI_CLK_UART(3, 3),
+   UNIPHIER_PERI_CLK_FI2C(4, 0),
+   UNIPHIER_PERI_CLK_FI2C(5, 1),
+   UNIPHIER_PERI_CLK_FI2C(6, 2),
+   UNIPHIER_PERI_CLK_FI2C(7, 3),
+   UNIPHIE

[U-Boot] [PATCH] simple-bus: remove DECLARE_GLOBAL_DATA_PTR and

[Masahiro Yamada]

Both are unneeded in this file.

Signed-off-by: Masahiro Yamada 
---

 drivers/core/simple-bus.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
index 14803e3..cc48c8b 100644
--- a/drivers/core/simple-bus.c
+++ b/drivers/core/simple-bus.c
@@ -4,11 +4,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
 #include 
 
-DECLARE_GLOBAL_DATA_PTR;
-
 struct simple_bus_plat {
u32 base;
u32 size;
-- 
2.7.4

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[U-Boot] [PATCH 18/20] serial: uniphier: use clk for enable and get_rate

[Masahiro Yamada]

Get clock rate from the clock driver to drop U-Boot specific
property "clock-frequency".

Signed-off-by: Masahiro Yamada 
---

 drivers/serial/serial_uniphier.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 68895bd..a9d8b5c 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -90,11 +90,12 @@ static int uniphier_serial_pending(struct udevice *dev, 
bool input)
 
 static int uniphier_serial_probe(struct udevice *dev)
 {
-   DECLARE_GLOBAL_DATA_PTR;
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial __iomem *port;
+   struct clk clk;
fdt_addr_t base;
u32 tmp;
+   int ret;
 
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
@@ -106,8 +107,15 @@ static int uniphier_serial_probe(struct udevice *dev)
 
priv->membase = port;
 
-   priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-  "clock-frequency", 0);
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (ret)
+   return ret;
+
+   ret = clk_enable(&clk);
+   if (ret)
+   return ret;
+
+   priv->uartclk = clk_get_rate(&clk);
 
tmp = readl(&port->lcr_mcr);
tmp &= ~LCR_MASK;
-- 
2.7.4

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[U-Boot] [PATCH 05/20] pinctrl: uniphier: simplify input enable and delete pin arrays

[Masahiro Yamada]

The pin data are implemented for old SoCs to specify the bit shift of
the IECTRL register.  They are not wortwhile given the required memory
footprint.  Delete all the pin data and enable all bits of the IECTRL
register.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 17 +++---
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c  | 16 -
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c |  5 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 15 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c |  9 ---
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 30 
 6 files changed, 3 insertions(+), 89 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index d314482..215b19e 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -81,9 +82,6 @@ static int uniphier_pinconf_input_enable_legacy(struct 
udevice *dev,
unsigned int pin, int enable)
 {
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
-   int pins_count = priv->socdata->pins_count;
-   const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
-   int i;
 
/*
 * Multiple pins share one input enable, per-pin disabling is
@@ -92,17 +90,8 @@ static int uniphier_pinconf_input_enable_legacy(struct 
udevice *dev,
if (!enable)
return -EINVAL;
 
-   for (i = 0; i < pins_count; i++) {
-   if (pins[i].number == pin) {
-   unsigned int iectrl;
-   u32 tmp;
-
-   iectrl = uniphier_pin_get_iectrl(pins[i].data);
-   tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL);
-   tmp |= 1 << iectrl;
-   writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL);
-   }
-   }
+   /* Set all bits instead of having a bunch of pin data */
+   writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
 
return 0;
 }
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 709b005..7eb693d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -11,20 +11,6 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin uniphier_ld4_pins[] = {
-   UNIPHIER_PINCTRL_PIN(53, 0),
-   UNIPHIER_PINCTRL_PIN(54, 0),
-   UNIPHIER_PINCTRL_PIN(55, 0),
-   UNIPHIER_PINCTRL_PIN(56, 0),
-   UNIPHIER_PINCTRL_PIN(67, 0),
-   UNIPHIER_PINCTRL_PIN(68, 0),
-   UNIPHIER_PINCTRL_PIN(69, 0),
-   UNIPHIER_PINCTRL_PIN(70, 0),
-   UNIPHIER_PINCTRL_PIN(85, 0),
-   UNIPHIER_PINCTRL_PIN(88, 0),
-   UNIPHIER_PINCTRL_PIN(156, 0),
-};
-
 static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
 static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
@@ -132,8 +118,6 @@ static const char * const uniphier_ld4_functions[] = {
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = {
-   .pins = uniphier_ld4_pins,
-   .pins_count = ARRAY_SIZE(uniphier_ld4_pins),
.groups = uniphier_ld4_groups,
.groups_count = ARRAY_SIZE(uniphier_ld4_groups),
.functions = uniphier_ld4_functions,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index df5f2d8..0695e07 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -11,9 +11,6 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin uniphier_pro4_pins[] = {
-};
-
 static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
 static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
@@ -151,8 +148,6 @@ static const char * const uniphier_pro4_functions[] = {
 };
 
 static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = {
-   .pins = uniphier_pro4_pins,
-   .pins_count = ARRAY_SIZE(uniphier_pro4_pins),
.groups = uniphier_pro4_groups,
.groups_count = ARRAY_SIZE(uniphier_pro4_groups),
.functions = uniphier_pro4_functions,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 7b14662..39cdd95 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -11,19 +11,6 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin uniphier_pro5_pins[] = {
-   UNIPHIER_PINCTRL_PIN(47, 0),
-   UN

[U-Boot] [PATCH 17/20] ARM: dts: uniphier: prepare to use clock for serial

[Masahiro Yamada]

The serial driver is probed by SPL and/or board_init_f.  To get the
clock from the serial driver, the clock node must be marked as
u-boot,dm-pre-reloc.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-v7-u-boot.dtsi |  8 
 arch/arm/dts/uniphier-v8-u-boot.dtsi | 13 +
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/dts/uniphier-v8-u-boot.dtsi

diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi 
b/arch/arm/dts/uniphier-v7-u-boot.dtsi
index 4a0c9c0..e3854fa 100644
--- a/arch/arm/dts/uniphier-v7-u-boot.dtsi
+++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi
@@ -30,6 +30,14 @@
};
};
 
+   perictrl@5982 {
+   u-boot,dm-pre-reloc;
+
+   clock {
+   u-boot,dm-pre-reloc;
+   };
+   };
+
soc-glue@5f80 {
u-boot,dm-pre-reloc;
 
diff --git a/arch/arm/dts/uniphier-v8-u-boot.dtsi 
b/arch/arm/dts/uniphier-v8-u-boot.dtsi
new file mode 100644
index 000..3d83e62
--- /dev/null
+++ b/arch/arm/dts/uniphier-v8-u-boot.dtsi
@@ -0,0 +1,13 @@
+/ {
+   soc@0 {
+   u-boot,dm-pre-reloc;
+
+   perictrl@5982 {
+   u-boot,dm-pre-reloc;
+
+   clock {
+   u-boot,dm-pre-reloc;
+   };
+   };
+   };
+};
-- 
2.7.4

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[U-Boot] [PATCH] i2c: remove DECLARE_GLOBAL_DATA_PTR from i2c-uclass

[Masahiro Yamada]

No global pointer is used in this file.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/i2c-uclass.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 1397f34..920811a 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -12,8 +12,6 @@
 #include 
 #include 
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define I2C_MAX_OFFSET_LEN 4
 
 /* Useful debugging function */
-- 
2.7.4

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[U-Boot] [PATCH 09/20] i2c: uniphier-f: replace debug() with dev_dbg()

[Masahiro Yamada]

Use dev_dbg() functions.  It will be helpful to prefix log messages
with the corresponding device name when the core framework is ready.

While I am here, I renamed "dev", which was actually private data,
into "priv" because dev->dev looks confusing.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/i2c-uniphier-f.c | 114 ---
 1 file changed, 52 insertions(+), 62 deletions(-)

diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index e51537b..eb6c9f3 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -6,13 +6,12 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
-#include 
-#include 
+#include 
 #include 
 #include 
 #include 
-#include 
+#include 
+#include 
 #include 
 #include 
 
@@ -64,35 +63,27 @@ struct uniphier_fi2c_regs {
 
 #define FIOCLK 5000
 
-struct uniphier_fi2c_dev {
+struct uniphier_fi2c_priv {
+   struct udevice *dev;
struct uniphier_fi2c_regs __iomem *regs;/* register base */
unsigned long fioclk;   /* internal operation clock */
unsigned long timeout;  /* time out (us) */
 };
 
-static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
+static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
 {
-   u32 val;
-   int ret;
-
-   /* bus forcible reset */
-   writel(I2C_RST_RST, ®s->rst);
-   ret = readl_poll_timeout(®s->rst, val, !(val & I2C_RST_RST), 1);
-   if (ret < 0)
-   debug("error: fail to reset I2C controller\n");
-
-   return ret;
+   writel(I2C_RST_RST, &priv->regs->rst);
 }
 
-static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
+static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv)
 {
u32 val;
int ret;
 
-   ret = readl_poll_timeout(®s->sr, val, !(val & I2C_SR_DB), 100);
+   ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100);
if (ret < 0) {
-   debug("error: device busy too long. reset...\n");
-   ret = reset_bus(regs);
+   dev_dbg(priv->dev, "error: device busy too long. reset...\n");
+   uniphier_fi2c_reset(priv);
}
 
return ret;
@@ -101,8 +92,7 @@ static int check_device_busy(struct uniphier_fi2c_regs 
__iomem *regs)
 static int uniphier_fi2c_probe(struct udevice *dev)
 {
fdt_addr_t addr;
-   struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
-   int ret;
+   struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
 
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -114,85 +104,85 @@ static int uniphier_fi2c_probe(struct udevice *dev)
 
priv->fioclk = FIOCLK;
 
+   priv->dev = dev;
+
/* bus forcible reset */
-   ret = reset_bus(priv->regs);
-   if (ret < 0)
-   return ret;
+   uniphier_fi2c_reset(priv);
 
writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
 
return 0;
 }
 
-static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
+static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags,
bool *stop)
 {
u32 irq;
int ret;
 
-   ret = readl_poll_timeout(&dev->regs->intr, irq, irq & flags,
-dev->timeout);
+   ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
+priv->timeout);
if (ret < 0) {
-   debug("error: time out\n");
+   dev_dbg(priv->dev, "error: time out\n");
return ret;
}
 
if (irq & I2C_INT_AL) {
-   debug("error: arbitration lost\n");
+   dev_dbg(priv->dev, "error: arbitration lost\n");
*stop = false;
return ret;
}
 
if (irq & I2C_INT_NA) {
-   debug("error: no answer\n");
+   dev_dbg(priv->dev, "error: no answer\n");
return ret;
}
 
return 0;
 }
 
-static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
+static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret)
 {
int ret;
 
-   debug("stop condition\n");
-   writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
+   dev_dbg(priv->dev, "stop condition\n");
+   writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr);
 
-   ret = check_device_busy(dev->regs);
+   ret = uniphier_fi2c_check_bus_busy(priv);
if (ret < 0)
-   debug("error: device busy after operation\n");
+   dev_dbg(priv->dev, "error: device busy after operation\n");
 
return old_ret ? old_ret : ret;
 }
 
-static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
+static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr,
  uint len, const u8 *buf, bool *stop)
 {
int ret;
const u32 i

Re: [U-Boot] [PATCH 07/20] usb: dwc3-uniphier: replace with

[Marek Vasut]

On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
> Including  pulls in a lot of bloat.  What this driver needs
> is BIT(), so replace it with 
> 
> Signed-off-by: Masahiro Yamada 

Doesn't common.h also pull in the config macros ? Maybe they are not
needed here though ...

> ---
> 
>  drivers/usb/dwc3/dwc3-uniphier.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/dwc3-uniphier.c 
> b/drivers/usb/dwc3/dwc3-uniphier.c
> index 0d13770..25b17a8 100644
> --- a/drivers/usb/dwc3/dwc3-uniphier.c
> +++ b/drivers/usb/dwc3/dwc3-uniphier.c
> @@ -7,8 +7,8 @@
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
>  
> -#include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> 


-- 
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Re: [U-Boot] [PATCH v2 0/2] Support for TI bandgap temperature sensor

[Faiz Abbas]

Hi,

On Monday 09 October 2017 05:47 PM, Faiz Abbas wrote:
> Adding support for TI bandgap temperature sensor.
> Also add dt support for bandgap sensor in spl.
> 
> Faiz Abbas (2):
>   thermal: ti-bandgap: Add support for temperature sensor
>   ARM: dts: OMAP5+: Add support for bandgap sensor in SPL
> 
>  arch/arm/dts/omap5-u-boot.dtsi |   4 +
>  common/spl/Kconfig |   8 +
>  configs/dra7xx_evm_defconfig   |   3 +
>  .../thermal/ti_soc_thermal.txt |  35 
>  drivers/Makefile   |   2 +-
>  drivers/thermal/Kconfig|   6 +
>  drivers/thermal/Makefile   |   1 +
>  drivers/thermal/ti-bandgap.c   | 197 
> +
>  8 files changed, 255 insertions(+), 1 deletion(-)
>  create mode 100644 doc/device-tree-bindings/thermal/ti_soc_thermal.txt
>  create mode 100644 drivers/thermal/ti-bandgap.c
> 

Gentle ping.

Thanks,
Faiz
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Re: [U-Boot] [PATCH 07/20] usb: dwc3-uniphier: replace with

[Masahiro Yamada]

Hi Marek,


2017-10-13 19:40 GMT+09:00 Marek Vasut :
> On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
>> Including  pulls in a lot of bloat.  What this driver needs
>> is BIT(), so replace it with 
>>
>> Signed-off-by: Masahiro Yamada 
>
> Doesn't common.h also pull in the config macros ? Maybe they are not
> needed here though ...


If you need legacy CONFIG from include/configs/.h,
yes, you need to include 
(or  at least)


Recent CONFIG options from Kconfig are automatically provided
via  -include $(srctree)/include/linux/kconfig.h




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Re: [U-Boot] [PATCH 2/2] x86: Turn off running VGA ROM during S3 resume

[Stefan Roese]

On 12.10.2017 14:07, Bin Meng wrote:

This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.

Change this option's default to n in the Kconfig.

Signed-off-by: Bin Meng 
---

  arch/x86/Kconfig | 1 -
  1 file changed, 1 deletion(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 38a6187..c869ae2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -677,7 +677,6 @@ config HAVE_ACPI_RESUME
  config S3_VGA_ROM_RUN
bool "Re-run VGA option ROMs on S3 resume"
depends on HAVE_ACPI_RESUME
-   default y if HAVE_ACPI_RESUME
help
  Execute VGA option ROMs in U-Boot when resuming from S3. Normally
  this is needed when graphics console is being used in the kernel.



Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/2] x86: baytrail: Fix unstable ACPI S3 resume

[Stefan Roese]

On 12.10.2017 14:07, Bin Meng wrote:

It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.

The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.

Clear the mysterious interrupt bits for this pin.


Thanks for working on this. This must have been very tough to debug
and fix.


Reported-by: Stefan Roese 
Signed-off-by: Bin Meng 


Tested-by: Stefan Roese 
Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 07/20] usb: dwc3-uniphier: replace with

[Marek Vasut]

On 10/13/2017 01:01 PM, Masahiro Yamada wrote:
> Hi Marek,
> 
> 
> 2017-10-13 19:40 GMT+09:00 Marek Vasut :
>> On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
>>> Including  pulls in a lot of bloat.  What this driver needs
>>> is BIT(), so replace it with 
>>>
>>> Signed-off-by: Masahiro Yamada 
>>
>> Doesn't common.h also pull in the config macros ? Maybe they are not
>> needed here though ...
> 
> 
> If you need legacy CONFIG from include/configs/.h,
> yes, you need to include 
> (or  at least)
> 
> 
> Recent CONFIG options from Kconfig are automatically provided
> via  -include $(srctree)/include/linux/kconfig.h

OK, so not needed , perfect, thanks.

Acked-by: Marek Vasut 

-- 
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Re: [U-Boot] [PATCH 2/3] x86: baytrail: fsp: Use a function to update the Azalia config pointer

[Stefan Roese]

On 13.10.2017 10:30, Bin Meng wrote:

At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng 
---

  arch/x86/cpu/baytrail/fsp_configs.c  | 15 +--
  arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h |  2 +-
  2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 926f26b..3052fb6 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -120,6 +120,17 @@ const struct azalia_config azalia_config = {
  };
  
  /**

+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia:pointer to be updated to point to a ROM address where Azalia
+ * configuration data is stored
+ */
+static void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+   *azalia = (struct azalia_config *)&azalia_config;
+}
+
+/**
   * Override the FSP's configuration data.
   * If the device tree does not specify an integer setting, use the default
   * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf 
file.
@@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config,
rt_buf->common.boot_mode = config->common.boot_mode;
rt_buf->common.upd_data = &config->fsp_upd;
  
-	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;

-
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
if (node < 0) {
debug("%s: Cannot find FSP node\n", __func__);
@@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config,
SATA_MODE_AHCI);
fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
 "fsp,enable-azalia");
+   if (fsp_upd->enable_azalia)
+   update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr);
fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
   LPE_MODE_PCI);
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h 
b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
index 8c07b37..e2f0e39 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -45,7 +45,7 @@ struct __packed upd_region {
uint8_t enable_sata;/* Offset 0x002d */
uint8_t sata_mode;  /* Offset 0x002e */
uint8_t enable_azalia;  /* Offset 0x002f */
-   uint32_t azalia_config_ptr; /* Offset 0x0030 */
+   struct azalia_config *azalia_cfg_ptr;   /* Offset 0x0030 */
uint8_t enable_xhci;/* Offset 0x0034 */
uint8_t lpe_mode;   /* Offset 0x0035 */
uint8_t lpss_sio_mode;  /* Offset 0x0036 */



Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/3] x86: fsp: Consolidate Azalia header file

[Stefan Roese]

On 13.10.2017 10:30, Bin Meng wrote:

So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng 
---

  arch/x86/cpu/baytrail/fsp_configs.c  | 13 
  arch/x86/include/asm/arch-baytrail/fsp/azalia.h  | 39 
  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 26 
  arch/x86/include/asm/fsp/fsp_azalia.h| 39 
  arch/x86/include/asm/fsp/fsp_support.h   |  1 +
  5 files changed, 46 insertions(+), 72 deletions(-)
  delete mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
  create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 45f9bf9..926f26b 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -8,13 +8,12 @@
  
  #include 

  #include 
-#include 
  #include 
  
  DECLARE_GLOBAL_DATA_PTR;
  
  /* ALC262 Verb Table - 10EC0262 */

-static const uint32_t verb_table_data13[] = {
+static const u32 verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
0x01171cf0,
0x01171d11,
@@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = {
   * Codec Address: CAd value (0/1/2)
   * Codec Vendor: 0x10EC0262
   */
-static const struct pch_azalia_verb_table azalia_verb_table[] = {
+static const struct azalia_verb_table azalia_verb_table[] = {
{
{
0x10ec0262,
@@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table 
azalia_verb_table[] = {
}
  };
  
-const struct pch_azalia_config azalia_config = {

+const struct azalia_config azalia_config = {
.pme_enable = 1,
.docking_supported = 1,
.docking_attached = 0,
.hdmi_codec_enable = 1,
.azalia_v_ci_enable = 1,
.rsvdbits = 0,
-   .azalia_verb_table_num = 1,
-   .azalia_verb_table = azalia_verb_table,
-   .reset_wait_timer_us = 300
+   .verb_table_num = 1,
+   .verb_table = azalia_verb_table,
+   .reset_wait_timer_ms = 300
  };
  
  /**

diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h 
b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
deleted file mode 100644
index d96a20f..000
--- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier:Intel
- */
-
-#ifndef _FSP_AZALIA_H_
-#define _FSP_AZALIA_H_
-
-struct __packed pch_azalia_verb_table_header {
-   uint32_t vendor_device_id;
-   uint16_t sub_system_id;
-   uint8_t revision_id;/* 0xff applies to all steppings */
-   uint8_t front_panel_support;
-   uint16_t number_of_rear_jacks;
-   uint16_t number_of_front_jacks;
-};
-
-struct __packed pch_azalia_verb_table {
-   struct pch_azalia_verb_table_header verb_table_header;
-   const uint32_t *verb_table_data;
-};
-
-struct __packed pch_azalia_config {
-   uint8_t pme_enable:1;
-   uint8_t docking_supported:1;
-   uint8_t docking_attached:1;
-   uint8_t hdmi_codec_enable:1;
-   uint8_t azalia_v_ci_enable:1;
-   uint8_t rsvdbits:3;
-   /* number of verb tables provided by platform */
-   uint8_t azalia_verb_table_num;
-   const struct pch_azalia_verb_table *azalia_verb_table;
-   /* delay timer after azalia reset */
-   uint16_t reset_wait_timer_us;
-};
-
-#endif
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h 
b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
index ecb01fa..99c4c0a 100644
--- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
@@ -29,32 +29,6 @@ struct __packed memory_upd {
u8 reserved[189];   /* Offset 0x0043 */
  };
  
-struct __packed azalia_verb_table_header {

-   u32 vendor_device_id;
-   u16 sub_system_id;
-   u8 revision_id;
-   u8 front_panel_support;
-   u16 number_of_rear_jacks;
-   u16 number_of_front_jacks;
-};
-
-struct __packed azalia_verb_table {
-   struct azalia_verb_table_header header;
-   u32 *data;
-};
-
-struct __packed azalia_config {
-   u8 pme_enable:1;
-   u8 docking_supported:1;
-   u8 docking_attached:1;
-   u8 hdmi_codec_enable:1;
-   u8 azalia_v_ci_enable:1;
-   u8 reserved:3;
-   u8 verb_table_num;
-   struct azalia_verb_table *verb_table;
-   u16 reset_wait_timer_ms;
-};
-
  struct gpio_family {
u32 confg;
u32 confg_changes;
diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h 
b/arch/x86/include/asm/fsp/fsp_azalia.h
new file mode 100644
index 000..a1

Re: [U-Boot] [PATCH 3/3] x86: baytrail: fsp: Move Azalia update codes to board

[Stefan Roese]

On 13.10.2017 10:30, Bin Meng wrote:

Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng 
---

  arch/x86/cpu/baytrail/fsp_configs.c| 111 +
  .../som-db5800-som-6867/som-db5800-som-6867.c  | 111 +
  2 files changed, 113 insertions(+), 109 deletions(-)

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c 
b/arch/x86/cpu/baytrail/fsp_configs.c
index 3052fb6..6b762e5 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -12,122 +12,15 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
-/* ALC262 Verb Table - 10EC0262 */

-static const u32 verb_table_data13[] = {
-   /* Pin Complex (NID 0x11) */
-   0x01171cf0,
-   0x01171d11,
-   0x01171e11,
-   0x01171f41,
-   /* Pin Complex (NID 0x12) */
-   0x01271cf0,
-   0x01271d11,
-   0x01271e11,
-   0x01271f41,
-   /* Pin Complex (NID 0x14) */
-   0x01471c10,
-   0x01471d40,
-   0x01471e01,
-   0x01471f01,
-   /* Pin Complex (NID 0x15) */
-   0x01571cf0,
-   0x01571d11,
-   0x01571e11,
-   0x01571f41,
-   /* Pin Complex (NID 0x16) */
-   0x01671cf0,
-   0x01671d11,
-   0x01671e11,
-   0x01671f41,
-   /* Pin Complex (NID 0x18) */
-   0x01871c20,
-   0x01871d98,
-   0x01871ea1,
-   0x01871f01,
-   /* Pin Complex (NID 0x19) */
-   0x01971c21,
-   0x01971d98,
-   0x01971ea1,
-   0x01971f02,
-   /* Pin Complex (NID 0x1A) */
-   0x01a71c2f,
-   0x01a71d30,
-   0x01a71e81,
-   0x01a71f01,
-   /* Pin Complex */
-   0x01b71c1f,
-   0x01b71d40,
-   0x01b71e21,
-   0x01b71f02,
-   /* Pin Complex */
-   0x01c71cf0,
-   0x01c71d11,
-   0x01c71e11,
-   0x01c71f41,
-   /* Pin Complex */
-   0x01d71c01,
-   0x01d71dc6,
-   0x01d71e14,
-   0x01d71f40,
-   /* Pin Complex */
-   0x01e71cf0,
-   0x01e71d11,
-   0x01e71e11,
-   0x01e71f41,
-   /* Pin Complex */
-   0x01f71cf0,
-   0x01f71d11,
-   0x01f71e11,
-   0x01f71f41,
-};
-
-/*
- * This needs to be in ROM since if we put it in CAR, FSP init loses it when
- * it drops CAR.
- *
- * TODO(s...@chromium.org): Move to device tree when FSP allows it
- *
- * VerbTable: (RealTek ALC262)
- * Revision ID = 0xFF, support all steps
- * Codec Verb Table For AZALIA
- * Codec Address: CAd value (0/1/2)
- * Codec Vendor: 0x10EC0262
- */
-static const struct azalia_verb_table azalia_verb_table[] = {
-   {
-   {
-   0x10ec0262,
-   0x,
-   0xff,
-   0x01,
-   0x000b,
-   0x0002,
-   },
-   verb_table_data13
-   }
-};
-
-const struct azalia_config azalia_config = {
-   .pme_enable = 1,
-   .docking_supported = 1,
-   .docking_attached = 0,
-   .hdmi_codec_enable = 1,
-   .azalia_v_ci_enable = 1,
-   .rsvdbits = 0,
-   .verb_table_num = 1,
-   .verb_table = azalia_verb_table,
-   .reset_wait_timer_ms = 300
-};
-
  /**
   * Override the FSP's Azalia configuration data
   *
   * @azalia:   pointer to be updated to point to a ROM address where Azalia
   *configuration data is stored
   */
-static void update_fsp_azalia_configs(struct azalia_config **azalia)
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
  {
-   *azalia = (struct azalia_config *)&azalia_config;
+   *azalia = NULL;
  }
  
  /**

diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c 
b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
index 6158795..202e9875 100644
--- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -6,6 +6,117 @@
   */
  
  #include 

+#include 
+
+/* ALC262 Verb Table - 10EC0262 */
+static const u32 verb_table_data13[] = {
+   /* Pin Complex (NID 0x11) */
+   0x01171cf0,
+   0x01171d11,
+   0x01171e11,
+   0x01171f41,
+   /* Pin Complex (NID 0x12) */
+   0x01271cf0,
+   0x01271d11,
+   0x01271e11,
+   0x01271f41,
+   /* Pin Complex (NID 0x14) */
+   0x01471c10,
+   0x01471d40,
+   0x01471e01,
+   0x01471f01,
+   /* Pin Complex (NID 0x15) */
+   0x01571cf0,
+   0x01571d11,
+   0x01571e11,
+   0x01571f41,
+   /* Pin Complex (NID 0x16) */
+   0x01671cf0,
+   0x01671d11,
+   0x01671e11,
+   0x01671f41,
+   /* Pin Complex (NID 0x18) */
+   0x01871c20,
+   0x01871d98

[U-Boot] [PATCH] drivers: core: Add translation in live tree case

[Mario Six]

The function dev_read_addr calls ofnode_get_addr_index in the live tree
case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.

Fix this situation by applying bus translations in the live tree case as
well.

Signed-off-by: Mario Six 
---
 drivers/core/ofnode.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 9123e88425..d7d8f039b9 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -215,13 +215,15 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
uint flags;
u64 size;
int na;
+   __be32 addr;
 
prop_val = of_get_address(ofnode_to_np(node), index, &size,
  &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
na = of_n_addr_cells(ofnode_to_np(node));
-   return of_read_number(prop_val, na);
+   addr = of_read_number(prop_val, na);
+   return of_translate_address(ofnode_to_np(node), &addr);
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
-- 
2.11.0

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[U-Boot] [PATCH] [RFC] imx: dek_blob: Fix lock-up on dek_blob command

[Henri Roosen]

The function blob_encap_dek accesses a CAAM register
 CONFIG_SYS_FSL_JR0_ADDR + 0x102c, before the CAAM clock has been enabled,
which causes the system to lock-up at the dek_blob command.

This patch enables and disables the CAAM clock, because this is also done in
arch/arm/imx-common/hab.c:authenticate_image(). However in my opinion
controlling the clock should be done in one of the underlaying layers, so
this needs further cleanup.

Please comment on a clean implementation of controlling of the CAAM clock.

Signed-off-by: Henri Roosen 
---
 arch/arm/imx-common/cmd_dek.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c
index ada8adf..72a7d49 100644
--- a/arch/arm/imx-common/cmd_dek.c
+++ b/arch/arm/imx-common/cmd_dek.c
@@ -30,20 +30,22 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
 {
int ret = 0;
u32 jr_size = 4;
-
-   u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
-   if (out_jr_size != jr_size) {
-   hab_caam_clock_enable(1);
-   sec_init();
-   }
+   u32 out_jr_size;
 
if (!((len == 128) | (len == 192) | (len == 256))) {
debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
return -1;
}
 
+   hab_caam_clock_enable(1);
+   out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+   if (out_jr_size != jr_size) {
+   sec_init();
+   }
+
len /= 8;
ret = blob_dek(src, dst, len);
+   hab_caam_clock_enable(0);
 
return ret;
 }
-- 
2.1.4

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Re: [U-Boot] [PATCH 2/6] mmc: uniphier-sd: Use mmc_of_parse()

[Masahiro Yamada]

Hi Marek,

2017-10-06 21:07 GMT+09:00 Marek Vasut :
> Drop the ad-hoc DT caps parsing in favor of common framework function.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 


"git grep" could not find mmc_of_parse.


Are you waiting for this one?

http://patchwork.ozlabs.org/patch/816911/


>  drivers/mmc/uniphier-sd.c | 23 +++
>  1 file changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index 784bb883ce..cf85ec23c7 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -799,24 +799,15 @@ static int uniphier_sd_probe(struct udevice *dev)
> return ret;
> }
>
> -   plat->cfg.name = dev->name;
> -   plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
> -
> -   switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
> -  1)) {
> -   case 8:
> -   plat->cfg.host_caps |= MMC_MODE_8BIT;
> -   break;
> -   case 4:
> -   plat->cfg.host_caps |= MMC_MODE_4BIT;
> -   break;
> -   case 1:
> -   break;
> -   default:
> -   dev_err(dev, "Invalid \"bus-width\" value\n");
> -   return -EINVAL;
> +   ret = mmc_of_parse(gd->fdt_blob, dev_of_offset(dev), &plat->cfg);
> +   if (ret < 0) {
> +   dev_err(dev, "failed to parse host caps\n");
> +   return ret;
> }
>
> +   plat->cfg.name = dev->name;
> +   plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
> +
> if (quirks)
> priv->caps = quirks;
>
> --
> 2.11.0
>
> ___
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Re: [U-Boot] [PATCH 2/6] mmc: uniphier-sd: Use mmc_of_parse()

[Marek Vasut]

On 10/13/2017 01:36 PM, Masahiro Yamada wrote:
> Hi Marek,
> 
> 2017-10-06 21:07 GMT+09:00 Marek Vasut :
>> Drop the ad-hoc DT caps parsing in favor of common framework function.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Jaehoon Chung 
>> Cc: Masahiro Yamada 
> 
> 
> "git grep" could not find mmc_of_parse.
> 
> 
> Are you waiting for this one?
> 
> http://patchwork.ozlabs.org/patch/816911/

Yeah, I think Jaehoon is testing the patchset again . Hopefully this
time there will be some result from the testing ...

>>  drivers/mmc/uniphier-sd.c | 23 +++
>>  1 file changed, 7 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
>> index 784bb883ce..cf85ec23c7 100644
>> --- a/drivers/mmc/uniphier-sd.c
>> +++ b/drivers/mmc/uniphier-sd.c
>> @@ -799,24 +799,15 @@ static int uniphier_sd_probe(struct udevice *dev)
>> return ret;
>> }
>>
>> -   plat->cfg.name = dev->name;
>> -   plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
>> -
>> -   switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
>> -  1)) {
>> -   case 8:
>> -   plat->cfg.host_caps |= MMC_MODE_8BIT;
>> -   break;
>> -   case 4:
>> -   plat->cfg.host_caps |= MMC_MODE_4BIT;
>> -   break;
>> -   case 1:
>> -   break;
>> -   default:
>> -   dev_err(dev, "Invalid \"bus-width\" value\n");
>> -   return -EINVAL;
>> +   ret = mmc_of_parse(gd->fdt_blob, dev_of_offset(dev), &plat->cfg);
>> +   if (ret < 0) {
>> +   dev_err(dev, "failed to parse host caps\n");
>> +   return ret;
>> }
>>
>> +   plat->cfg.name = dev->name;
>> +   plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
>> +
>> if (quirks)
>> priv->caps = quirks;
>>
>> --
>> 2.11.0
>>
>> ___
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> 
> 
> 


-- 
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Re: [U-Boot] [PATCH v2 0/3] kbuild: always use relative path for __FILE__

[Tom Rini]

On Fri, Oct 13, 2017 at 06:51:42PM +0900, Masahiro Yamada wrote:

> We discussed the __FILE__ problem when U-Boot is built out of tree.
> https://www.mail-archive.com/u-boot@lists.denx.de/msg242852.html
> 
> The deeper your build directory is located, the larger
> your U-Boot image becomes.
> If your platform has memory footprint limit, this is a problem.
> 
> Recently, I submitted the following patches to Kbuild ML.
> (no RFC, this time)
> https://patchwork.kernel.org/patch/10001419/
> https://patchwork.kernel.org/patch/10001409/
> 
> I consider them for Linux 4.15 unless there is
> a strong objection or a problem report.
> 
> This series is a port for U-Boot.
> 
> If Tom wants to pick this up earlier, it is OK.
> If not in hurry, you can wait for the activity in Linux.
> Either will do.

Yay.  I plan to pick these up after v2017.11 has been released, so no
need to re-spin this if it stops applying cleanly until we're closer to
release.  Thanks!

-- 
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Re: [U-Boot] [PATCH v2 0/3] kbuild: always use relative path for __FILE__

[Masahiro Yamada]

2017-10-13 21:11 GMT+09:00 Tom Rini :
> On Fri, Oct 13, 2017 at 06:51:42PM +0900, Masahiro Yamada wrote:
>
>> We discussed the __FILE__ problem when U-Boot is built out of tree.
>> https://www.mail-archive.com/u-boot@lists.denx.de/msg242852.html
>>
>> The deeper your build directory is located, the larger
>> your U-Boot image becomes.
>> If your platform has memory footprint limit, this is a problem.
>>
>> Recently, I submitted the following patches to Kbuild ML.
>> (no RFC, this time)
>> https://patchwork.kernel.org/patch/10001419/
>> https://patchwork.kernel.org/patch/10001409/
>>
>> I consider them for Linux 4.15 unless there is
>> a strong objection or a problem report.
>>
>> This series is a port for U-Boot.
>>
>> If Tom wants to pick this up earlier, it is OK.
>> If not in hurry, you can wait for the activity in Linux.
>> Either will do.
>
> Yay.  I plan to pick these up after v2017.11 has been released, so no
> need to re-spin this if it stops applying cleanly until we're closer to
> release.  Thanks!
>

Good.

According to this:
http://phb-crystal-ball.org/

The MW for v4.15 will open 2017-11-12.

So, the next MW for U-Boot and Linux will be almost lined up.

You will be able to apply it more confidently
if Linus pulls the Linux counterpart.

Until then, I will test it in linux-next.



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[U-Boot] U-Boot download link broken

[Guillaume Gardet]

Hi,

On this page: http://www.denx.de/wiki/U-Boot/SourceCode

there is a link to Amazon Cloud Drive to download U-Boot, but this link is not 
working anymore.

Another problem: on the FTP, there is no tarball for v2017.11-rc1.


Guillaume


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[U-Boot] [PATCH] ARC: HSDK: introduce CREG GPIO driver

[Eugeniy Paltsev]

The HSDK can manage some pins via CREG registers block.

Signed-off-by: Eugeniy Paltsev 
---
 MAINTAINERS   |   6 +++
 drivers/gpio/Kconfig  |   7 +++
 drivers/gpio/Makefile |   1 +
 drivers/gpio/hsdk-creg-gpio.c | 109 ++
 4 files changed, 123 insertions(+)
 create mode 100644 drivers/gpio/hsdk-creg-gpio.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 04acf2b..df662aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -59,6 +59,12 @@ S:   Maintained
 T: git git://git.denx.de/u-boot-arc.git
 F: arch/arc/
 
+ARC HSDK CREG GPIO
+M: Eugeniy Paltsev 
+S: Maintained
+L: uboot-snps-...@synopsys.com
+F: drivers/gpio/hsdk-creg-gpio.c
+
 ARM
 M: Albert Aribaud 
 S: Maintained
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ffeda94..9928911 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -80,6 +80,13 @@ config IMX_RGPIO2P
help
  This driver supports i.MX7ULP Rapid GPIO2P controller.
 
+config HSDK_CREG_GPIO
+   bool "HSDK CREG GPIO griver"
+   depends on DM
+   default n
+   help
+ This driver supports CREG GPIOs on Synopsys HSDK SOC.
+
 config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1396467..c7efc4c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_GPIO_UNIPHIER)   += gpio-uniphier.o
 obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)  += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
+obj-$(CONFIG_HSDK_CREG_GPIO)   += hsdk-creg-gpio.o
 obj-$(CONFIG_IMX_RGPIO2P)  += imx_rgpio2p.o
 obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
 obj-$(CONFIG_MVEBU_GPIO)   += mvebu_gpio.o
diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c
new file mode 100644
index 000..bfbfe5b
--- /dev/null
+++ b/drivers/gpio/hsdk-creg-gpio.c
@@ -0,0 +1,109 @@
+/*
+ * Synopsys HSDK SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HSDK_CREG_MAX_GPIO 8
+
+#define GPIO_ACTIVATE  0x2
+#define GPIO_DEACTIVATE0x3
+#define GPIO_PIN_MASK  0x3
+#define BIT_PER_GPIO   2
+
+struct hsdk_creg_gpio {
+   uint32_t *regs;
+};
+
+static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
+{
+   struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+   uint32_t reg = readl(hcg->regs);
+   uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+
+   reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
+   reg |=  (cmd << (oft * BIT_PER_GPIO));
+
+   writel(reg, hcg->regs);
+
+   return 0;
+}
+
+static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
+  int val)
+{
+   hsdk_creg_gpio_set_value(dev, oft, val);
+
+   return 0;
+}
+
+static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+   error("hsdk-creg-gpio can't be used as input!\n");
+
+   return -ENOTSUPP;
+}
+
+static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
+{
+   struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+   uint32_t val = readl(hcg->regs);
+
+   val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
+   return (val == GPIO_DEACTIVATE) ? 1 : 0;
+}
+
+static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
+   .direction_output   = hsdk_creg_gpio_direction_output,
+   .direction_input= hsdk_creg_gpio_direction_input,
+   .set_value  = hsdk_creg_gpio_set_value,
+   .get_value  = hsdk_creg_gpio_get_value,
+};
+
+static int hsdk_creg_gpio_probe(struct udevice *dev)
+{
+   struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+
+   hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
+
+   uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
+   if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
+   uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+
+   uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+   if (!uc_priv->bank_name)
+   uc_priv->bank_name = dev_read_name(dev);
+
+   debug("%s GPIO [0x%p] controller with %d gpios probed\n",
+ uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
+
+   return 0;
+}
+
+static const struct udevice_id hsdk_creg_gpio_ids[] = {
+   { .compatible = "snps,hsdk-creg-gpio" },
+   { }
+};
+
+U_BOOT_DRIVER(gpio_hsdk_creg) = {
+   .na

[U-Boot] [PATCH v2] mx6slevk: Fix MMC breakage for the SPL target

[Fabio Estevam]

From: Fabio Estevam 

Commit 001cdbbb32ef1f6 ("imx: mx6slevk: enable more DM drivers") breaks
MMC support in U-Boot proper on the mx6slevk_spl_defconfig target:

U-Boot SPL 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18)
Trying to boot from MMC1

U-Boot 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18 -0300)

CPU:   Freescale i.MX6SL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 33C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

As mx6slevk_spl_defconfig does not use CONFIG_DM_MMC and its
board file does not register the mmc controller for U-Boot proper,
let's fix this by adding CONFIG_DM_MMC=y and device tree support.

While at it, add more DM drivers, so that it becomes closer to 
mx6slevk_defconfig.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Fix the breakage by adding CONFIG_DM_MMC=y

 configs/mx6slevk_spl_defconfig | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 689fe79..05a5c9e 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -9,7 +9,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL,SYS_I2C"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
@@ -32,13 +33,26 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-- 
2.7.4

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Re: [U-Boot] fsl_esdhc driver is broken with DM

[Fabio Estevam]

Hi Lukasz,

On Fri, Oct 13, 2017 at 5:16 AM, Lukasz Majewski  wrote:

> There is some ongoing work to provide such facility. for imx6
> boards. I will keep you informed.

That's good news! Please keep me in the loop as well.

Thanks
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Re: [U-Boot] [PATCH] ARC: HSDK: introduce CREG GPIO driver

[Alexey Brodkin]

Hi Tom,

On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> The HSDK can manage some pins via CREG registers block.
> 
> Signed-off-by: Eugeniy Paltsev 
> ---
>  MAINTAINERS   |   6 +++
>  drivers/gpio/Kconfig  |   7 +++
>  drivers/gpio/Makefile |   1 +
>  drivers/gpio/hsdk-creg-gpio.c | 109 
> ++
>  4 files changed, 123 insertions(+)
>  create mode 100644 drivers/gpio/hsdk-creg-gpio.c

I'm wondering if this one should go through my tree as this
is for one of our Synopsys ARC devboards or GPIO stuff usually
goes through some other tree?

-Alexey
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Re: [U-Boot] [PATCH] ARC: HSDK: introduce CREG GPIO driver

[Tom Rini]

On Fri, Oct 13, 2017 at 01:33:22PM +, Alexey Brodkin wrote:
> Hi Tom,
> 
> On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> > The HSDK can manage some pins via CREG registers block.
> > 
> > Signed-off-by: Eugeniy Paltsev 
> > ---
> >  MAINTAINERS   |   6 +++
> >  drivers/gpio/Kconfig  |   7 +++
> >  drivers/gpio/Makefile |   1 +
> >  drivers/gpio/hsdk-creg-gpio.c | 109 
> > ++
> >  4 files changed, 123 insertions(+)
> >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c
> 
> I'm wondering if this one should go through my tree as this
> is for one of our Synopsys ARC devboards or GPIO stuff usually
> goes through some other tree?

The ARC tree is fine, but it's a bit late posting for this release.
Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH v2 0/3] kbuild: always use relative path for __FILE__

[Tom Rini]

On Fri, Oct 13, 2017 at 09:21:19PM +0900, Masahiro Yamada wrote:
> 2017-10-13 21:11 GMT+09:00 Tom Rini :
> > On Fri, Oct 13, 2017 at 06:51:42PM +0900, Masahiro Yamada wrote:
> >
> >> We discussed the __FILE__ problem when U-Boot is built out of tree.
> >> https://www.mail-archive.com/u-boot@lists.denx.de/msg242852.html
> >>
> >> The deeper your build directory is located, the larger
> >> your U-Boot image becomes.
> >> If your platform has memory footprint limit, this is a problem.
> >>
> >> Recently, I submitted the following patches to Kbuild ML.
> >> (no RFC, this time)
> >> https://patchwork.kernel.org/patch/10001419/
> >> https://patchwork.kernel.org/patch/10001409/
> >>
> >> I consider them for Linux 4.15 unless there is
> >> a strong objection or a problem report.
> >>
> >> This series is a port for U-Boot.
> >>
> >> If Tom wants to pick this up earlier, it is OK.
> >> If not in hurry, you can wait for the activity in Linux.
> >> Either will do.
> >
> > Yay.  I plan to pick these up after v2017.11 has been released, so no
> > need to re-spin this if it stops applying cleanly until we're closer to
> > release.  Thanks!
> >
> 
> Good.
> 
> According to this:
> http://phb-crystal-ball.org/
> 
> The MW for v4.15 will open 2017-11-12.
> 
> So, the next MW for U-Boot and Linux will be almost lined up.
> 
> You will be able to apply it more confidently
> if Linus pulls the Linux counterpart.
> 
> Until then, I will test it in linux-next.

FWIW, a world build is:
https://gist.github.com/trini/ad0f55b9f46997fd11801aac48bf0c10

I wonder why we see size increase in a few cases?  In both cases, the
obj directory is /tmp/something/01_of_.. (or 04_of_..)/current/..

-- 
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Re: [U-Boot] [PATCH] ARC: HSDK: introduce CREG GPIO driver

[Alexey Brodkin]

Hi Tom,

On Fri, 2017-10-13 at 09:46 -0400, Tom Rini wrote:
> On Fri, Oct 13, 2017 at 01:33:22PM +, Alexey Brodkin wrote:
> > 
> > Hi Tom,
> > 
> > On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> > > 
> > > The HSDK can manage some pins via CREG registers block.
> > > 
> > > Signed-off-by: Eugeniy Paltsev 
> > > ---
> > >  MAINTAINERS   |   6 +++
> > >  drivers/gpio/Kconfig  |   7 +++
> > >  drivers/gpio/Makefile |   1 +
> > >  drivers/gpio/hsdk-creg-gpio.c | 109 
> > > ++
> > >  4 files changed, 123 insertions(+)
> > >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c
> > 
> > I'm wondering if this one should go through my tree as this
> > is for one of our Synopsys ARC devboards or GPIO stuff usually
> > goes through some other tree?
> 
> The ARC tree is fine, but it's a bit late posting for this release.

So should I keep this one in "next" branch of my tree before v2017.11
gets cut?

-Alexey
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Re: [U-Boot] [PATCH] ARC: HSDK: introduce CREG GPIO driver

[Tom Rini]

On Fri, Oct 13, 2017 at 01:55:28PM +, Alexey Brodkin wrote:
> Hi Tom,
> 
> On Fri, 2017-10-13 at 09:46 -0400, Tom Rini wrote:
> > On Fri, Oct 13, 2017 at 01:33:22PM +, Alexey Brodkin wrote:
> > > 
> > > Hi Tom,
> > > 
> > > On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> > > > 
> > > > The HSDK can manage some pins via CREG registers block.
> > > > 
> > > > Signed-off-by: Eugeniy Paltsev 
> > > > ---
> > > >  MAINTAINERS   |   6 +++
> > > >  drivers/gpio/Kconfig  |   7 +++
> > > >  drivers/gpio/Makefile |   1 +
> > > >  drivers/gpio/hsdk-creg-gpio.c | 109 
> > > > ++
> > > >  4 files changed, 123 insertions(+)
> > > >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c
> > > 
> > > I'm wondering if this one should go through my tree as this
> > > is for one of our Synopsys ARC devboards or GPIO stuff usually
> > > goes through some other tree?
> > 
> > The ARC tree is fine, but it's a bit late posting for this release.
> 
> So should I keep this one in "next" branch of my tree before v2017.11
> gets cut?

Yes, thanks.

-- 
Tom


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Re: [U-Boot] [PATCH 07/11] efi_loader: fix events

[Rob Clark]

On Fri, Oct 13, 2017 at 1:24 AM, Heinrich Schuchardt  wrote:
>
>
> On 10/10/2017 02:23 PM, Rob Clark wrote:
>>
>> An event can be created with type==0, Shell.efi does this for an event
>> that is set when Ctrl-C is typed.  So our current approach of having a
>> fixed set of timer slots, and determining which slots are unused by
>> type==0 doesn't work so well.  But we don't have any particularly good
>> reason to have a fixed table of events, so just dynamically allocate
>> them and keep a list.
>>
>> Also fixes an incorrect implementation of CheckEvent() which was (a)
>> incorrectly returning an error if type==0, and (b) didn't handle the
>> case of an unsignaled event with a notify callback.
>>
>> With these fixes (plus implementation of SIMPLE_TEXT_INPUT_EX protocol),
>> Ctrl-C works in Shell.efi.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>   include/efi_loader.h  |   1 +
>>   lib/efi_loader/efi_boottime.c | 217
>> +-
>>   2 files changed, 111 insertions(+), 107 deletions(-)
>>
>> diff --git a/include/efi_loader.h b/include/efi_loader.h
>> index e6e55d2cb4..2232caca44 100644
>> --- a/include/efi_loader.h
>> +++ b/include/efi_loader.h
>> @@ -154,6 +154,7 @@ struct efi_event {
>> enum efi_timer_delay trigger_type;
>> bool is_queued;
>> bool is_signaled;
>> +   struct list_head link;
>>   };
>> diff --git a/lib/efi_loader/efi_boottime.c
>> b/lib/efi_loader/efi_boottime.c
>> index 39dcc72648..19fafe546c 100644
>> --- a/lib/efi_loader/efi_boottime.c
>> +++ b/lib/efi_loader/efi_boottime.c
>> @@ -350,11 +350,26 @@ static efi_status_t efi_create_handle(void **handle)
>> return r;
>>   }
>>   +static LIST_HEAD(efi_events);
>> +
>>   /*
>> - * Our event capabilities are very limited. Only a small limited
>> - * number of events is allowed to coexist.
>> + * Check if a pointer is a valid event.
>> + *
>> + * It might be nice at some point to extend this to a more general
>> + * mechanism to check if pointers passed from the EFI world are
>> + * valid objects of a particular type.
>>*/
>> -static struct efi_event efi_events[16];
>> +static bool efi_is_event(const void *obj)
>> +{
>> +   struct efi_event *evt;
>> +
>> +   list_for_each_entry(evt, &efi_events, link) {
>> +   if (evt == obj)
>> +   return true;
>> +   }
>> +
>> +   return false;
>> +}
>> /*
>>* Create an event.
>> @@ -377,7 +392,7 @@ efi_status_t efi_create_event(uint32_t type, UINTN
>> notify_tpl,
>> void *context),
>>   void *notify_context, struct efi_event
>> **event)
>>   {
>> -   int i;
>> +   struct efi_event *evt;
>> if (event == NULL)
>> return EFI_INVALID_PARAMETER;
>> @@ -389,21 +404,24 @@ efi_status_t efi_create_event(uint32_t type, UINTN
>> notify_tpl,
>> notify_function == NULL)
>> return EFI_INVALID_PARAMETER;
>>   - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
>> -   if (efi_events[i].type)
>> -   continue;
>> -   efi_events[i].type = type;
>> -   efi_events[i].notify_tpl = notify_tpl;
>> -   efi_events[i].notify_function = notify_function;
>> -   efi_events[i].notify_context = notify_context;
>> -   /* Disable timers on bootup */
>> -   efi_events[i].trigger_next = -1ULL;
>> -   efi_events[i].is_queued = false;
>> -   efi_events[i].is_signaled = false;
>> -   *event = &efi_events[i];
>> -   return EFI_SUCCESS;
>> -   }
>> -   return EFI_OUT_OF_RESOURCES;
>> +   evt = calloc(1, sizeof(*evt));
>> +   if (!evt)
>> +   return EFI_OUT_OF_RESOURCES;
>> +
>> +   evt->type = type;
>> +   evt->notify_tpl = notify_tpl;
>> +   evt->notify_function = notify_function;
>> +   evt->notify_context = notify_context;
>> +   /* Disable timers on bootup */
>> +   evt->trigger_next = -1ULL;
>> +   evt->is_queued = false;
>> +   evt->is_signaled = false;
>> +
>> +   list_add_tail(&evt->link, &efi_events);
>> +
>> +   *event = evt;
>> +
>> +   return EFI_SUCCESS;
>>   }
>> /*
>> @@ -443,30 +461,31 @@ static efi_status_t EFIAPI efi_create_event_ext(
>>*/
>>   void efi_timer_check(void)
>>   {
>> -   int i;
>> +   struct efi_event *evt;
>> u64 now = timer_get_us();
>>   - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
>> -   if (!efi_events[i].type)
>> -   continue;
>> -   if (efi_events[i].is_queued)
>> -   efi_signal_event(&efi_events[i]);
>> -   if (!(efi_events[i].type & EVT_TIMER) ||
>> -   now < efi_events[i].trigger_next)
>> +   /*
>> +* TODO perhaps optimize a bit and track the time of next
>> +* timer to expire?
>> +  

Re: [U-Boot] [PATCH] power: extend prefix match to regulator-name property

[Felix Brack]

Hello Simon,

On 12.10.2017 04:07, Simon Glass wrote:
> Hi Felix,
> 
> On 9 October 2017 at 03:04, Felix Brack  wrote:
>>
>> This patch extends pmic_bind_children prefix matching. In addition to
>> the node name the property regulator-name is used while trying to match
>> prefixes. This allows assigning different drivers to regulator nodes
>> named regulator@1 and regulator@10 for example.
>> Signed-off-by: Felix Brack 
>> ---
>>
>>  drivers/power/pmic/pmic-uclass.c | 15 +--
>>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> Can you please add a sandbox test and documentation for this?
> 
I just forgot to extend the documentation. I will do so of course as
soon as the node property for matching has been fixed.

I think the test itself does already exist (test/dm/regulator.c). I will
have to add a regulator to arch/sandbox/dts/sandbox_pmic.dtsi. This
regulator will have a node name prefix other then 'buck' or 'ldo' for my
code to do the matching. Some other files will also need modifications
for the test to work correctly.

> See:
> 
> test/dm/pmic.c
> doc/driver-model/pmic-framework.txt
> 
>>
>> diff --git a/drivers/power/pmic/pmic-uclass.c 
>> b/drivers/power/pmic/pmic-uclass.c
>> index 64964e4..5a034f0 100644
>> --- a/drivers/power/pmic/pmic-uclass.c
>> +++ b/drivers/power/pmic/pmic-uclass.c
>> @@ -26,6 +26,7 @@ int pmic_bind_children(struct udevice *pmic, ofnode parent,
>> struct driver *drv;
>> struct udevice *child;
>> const char *node_name;
>> +   const char *reg_name;
>> int bind_count = 0;
>> ofnode node;
>> int prefix_len;
>> @@ -44,8 +45,18 @@ int pmic_bind_children(struct udevice *pmic, ofnode 
>> parent,
>> debug("  - compatible prefix: '%s'\n", info->prefix);
>>
>> prefix_len = strlen(info->prefix);
>> -   if (strncmp(info->prefix, node_name, prefix_len))
>> -   continue;
>> +   if (strncmp(info->prefix, node_name, prefix_len)) {
>> +   reg_name = ofnode_read_string(node,
>> + 
>> "regulator-name");
>> +   if (reg_name) {
>> +   if (strncmp(info->prefix, reg_name,
>> +   prefix_len)) {
>> +   continue;
>> +   }
>> +   } else {
>> +   continue;
>> +   }
>> +   }
>>
>> drv = lists_driver_lookup_name(info->driver);
>> if (!drv) {
>> --
>> 2.7.4
>>
> 
> Regards,
> Simon
> 

regards, Felix
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[U-Boot] [PATCH v2] DW SPI: Get clock value from Device Tree

[Eugeniy Paltsev]

Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Old way of setting spi controller clock frequency (via implementation
of 'cm_get_spi_controller_clk_hz' function in platform specific code)
remains supported for backward compatibility.

Signed-off-by: Eugeniy Paltsev 
---
Changes v1->v2:
  * disable clock if we can't get the rate.
  * get rid of cm_get_spi_controller_clk_hz weak declaration.

 drivers/spi/designware_spi.c | 65 +++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5aa507b..9eb5b1c 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -18,7 +19,10 @@
 #include 
 #include 
 #include 
+/* Only SOCFPGA_GEN5 and SOCFPGA_ARRIA10 uses their clock_manager functions */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || 
defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -94,6 +98,7 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq;  /* Default frequency */
unsigned int mode;
+   unsigned long bus_clk_rate;
 
int bits_per_word;
u8 cs;  /* chip select pin */
@@ -176,14 +181,72 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 }
 
+static int dw_spi_of_get_clk(struct udevice *bus)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
+   struct dw_spi_priv *priv = dev_get_priv(bus);
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(bus, 0, &clk);
+   if (ret)
+   return -EINVAL;
+
+   ret = clk_enable(&clk);
+   if (ret && ret != -ENOSYS)
+   return ret;
+
+   priv->bus_clk_rate = clk_get_rate(&clk);
+   if (!priv->bus_clk_rate) {
+   clk_disable(&clk);
+   return -EINVAL;
+   }
+
+   clk_free(&clk);
+
+   return 0;
+#else
+   return -ENOSYS;
+#endif
+}
+
+static int dw_spi_get_clk(struct udevice *bus)
+{
+   struct dw_spi_priv *priv = dev_get_priv(bus);
+
+   /* Firstly try to get clock frequency from device tree */
+   if (!dw_spi_of_get_clk(bus))
+   return 0;
+
+   /*
+* SOCFPGA_GEN5 and SOCFPGA_ARRIA10 uses cm_get_spi_controller_clk_hz
+* function (defined in asm/arch/clock_manager.h) to get spi controller
+* clock frequency. So in case of get clock frequency from device
+* tree failure rollback to cm_get_spi_controller_clk_hz
+*/
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || 
defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   priv->bus_clk_rate = cm_get_spi_controller_clk_hz();
+#endif
+
+   if (!priv->bus_clk_rate)
+   return -EINVAL;
+
+   return 0;
+}
+
 static int dw_spi_probe(struct udevice *bus)
 {
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+   int ret;
 
priv->regs = plat->regs;
priv->freq = plat->frequency;
 
+   ret = dw_spi_get_clk(bus);
+   if (ret)
+   return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
 
@@ -369,7 +432,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
 
/* clk_div doesn't support odd number */
-   clk_div = cm_get_spi_controller_clk_hz() / speed;
+   clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
 
-- 
2.9.3

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[U-Boot] [PATCH 1/4] ARM: uniphier: enable DWC3 xHCI driver

[Masahiro Yamada]

Enable CONFIGs for the DWC3 core and the UniPhier specific glue layer.

Signed-off-by: Masahiro Yamada 
---

 configs/uniphier_v7_defconfig | 2 ++
 configs/uniphier_v8_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 12b24bc..96e962d 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -48,4 +48,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_UNIPHIER=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 796839b..31dd9b3 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -45,4 +45,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_UNIPHIER=y
 CONFIG_USB_STORAGE=y
-- 
2.7.4

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[U-Boot] [PATCH 4/4] clk: uniphier: add NAND controller clock

[Masahiro Yamada]

This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/uniphier/clk-uniphier-sys.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c 
b/drivers/clk/uniphier/clk-uniphier-sys.c
index f8cf6da..c852c78 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -7,10 +7,20 @@
 
 #include "clk-uniphier.h"
 
+/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
+#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
+   UNIPHIER_CLK_RATE(128, 2),  \
+   UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
+
+#define UNIPHIER_LD11_SYS_CLK_NAND(_id)
\
+   UNIPHIER_CLK_RATE(128, 2),  \
+   UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
+
 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) 
||\
 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+   UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10),/* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6),/* gio (Pro4, Pro5) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16),   /* usb30 (Pro4, Pro5, 
PXs2) */
@@ -23,6 +33,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = 
{
 
 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+   UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),   /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),   /* usb30-phy0 (LD20) */
@@ -33,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = 
{
 
 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
+   UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),/* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5),/* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6),/* usb31-1 (gio1-1) */
-- 
2.7.4

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[U-Boot] [PATCH 2/4] ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG

[Masahiro Yamada]

Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/clk/clk-pro4.c | 6 +++---
 arch/arm/mach-uniphier/clk/clk-pro5.c | 6 +++---
 arch/arm/mach-uniphier/clk/clk-pxs2.c | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c 
b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 19be4f3..8a978d2 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -17,7 +17,7 @@ void uniphier_pro4_clk_init(void)
 
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
 #endif
@@ -30,7 +30,7 @@ void uniphier_pro4_clk_init(void)
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
writel(tmp, SC_RSTCTRL2);
@@ -39,7 +39,7 @@ void uniphier_pro4_clk_init(void)
 
/* provide clocks */
tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
 #endif
diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c 
b/arch/arm/mach-uniphier/clk/clk-pro5.c
index 823bb06..dd86cad 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro5.c
@@ -15,7 +15,7 @@ void uniphier_pro5_clk_init(void)
 
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
 #ifdef CONFIG_NAND_DENALI
@@ -24,7 +24,7 @@ void uniphier_pro5_clk_init(void)
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, SC_RSTCTRL2);
@@ -33,7 +33,7 @@ void uniphier_pro5_clk_init(void)
 
/* provide clocks */
tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
 #endif
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c 
b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index 0d92405..9775127 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -16,7 +16,7 @@ void uniphier_pxs2_clk_init(void)
 
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH
@@ -28,7 +28,7 @@ void uniphier_pxs2_clk_init(void)
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, SC_RSTCTRL2);
@@ -41,7 +41,7 @@ void uniphier_pxs2_clk_init(void)
 
/* provide clocks */
tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 3/4] mtd: nand: denali_dt: add clock support

[Masahiro Yamada]

Enable clock in the probe hook.  The clock rate will be necessary
when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada 
---

 drivers/mtd/nand/denali.h|  1 +
 drivers/mtd/nand/denali_dt.c | 12 
 2 files changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 08db488..f796f0d 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -435,6 +435,7 @@ struct nand_buf {
 
 struct denali_nand_info {
struct nand_chip nand;
+   unsigned long clk_x_rate;   /* bus interface clock rate */
int flash_bank; /* currently selected chip */
int status;
int platform;
diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c
index 4afd679..805c066 100644
--- a/drivers/mtd/nand/denali_dt.c
+++ b/drivers/mtd/nand/denali_dt.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -52,6 +53,7 @@ static int denali_dt_probe(struct udevice *dev)
 {
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
+   struct clk clk;
struct resource res;
int ret;
 
@@ -73,6 +75,16 @@ static int denali_dt_probe(struct udevice *dev)
 
denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));
 
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (ret)
+   return ret;
+
+   ret = clk_enable(&clk);
+   if (ret)
+   return ret;
+
+   denali->clk_x_rate = clk_get_rate(&clk);
+
return denali_init(denali);
 }
 
-- 
2.7.4

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[U-Boot] [PATCH 1/1] scripts/get_maintainer.pl: update to current version

[Heinrich Schuchardt]

Update the script to version 0.26 (as of Linux v4.14-rc1)
Keep our "penguin_chief".
Keep our top_of_kernel_tree.

The negative forms of the command line parameters are described
when using --help.

New options are

 --git-blame-signatures => when used with --git-blame,
   also include all commit signers
 --r => include reviewer(s) if any
 --letters => print all matching 'letter' types
  from all matching sections

File .get_maintainer.ignore can be used to specify
email addressees that shall be ignored.

Signed-off-by: Heinrich Schuchardt 
---
 scripts/get_maintainer.pl | 202 +++---
 1 file changed, 156 insertions(+), 46 deletions(-)

diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 83a4e5bad2..8b6037b73f 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -1,4 +1,4 @@
-#!/usr/bin/perl -w
+#!/usr/bin/env perl
 # (c) 2007, Joe Perches 
 #   created from checkpatch.pl
 #
@@ -10,18 +10,22 @@
 #
 # Licensed under the terms of the GNU GPL License version 2
 
+use warnings;
 use strict;
 
 my $P = $0;
 my $V = '0.26';
 
 use Getopt::Long qw(:config no_auto_abbrev);
+use Cwd;
 use File::Find;
 
+my $cur_path = fastgetcwd() . '/';
 my $lk_path = "./";
 my $email = 1;
 my $email_usename = 1;
 my $email_maintainer = 1;
+my $email_reviewer = 1;
 my $email_list = 1;
 my $email_subscriber_list = 0;
 my $email_git_penguin_chiefs = 0;
@@ -42,10 +46,12 @@ my $output_multiline = 1;
 my $output_separator = ", ";
 my $output_roles = 0;
 my $output_rolestats = 1;
+my $output_section_maxlen = 50;
 my $scm = 0;
 my $web = 0;
 my $subsystem = 0;
 my $status = 0;
+my $letters = "";
 my $keywords = 1;
 my $sections = 0;
 my $file_emails = 0;
@@ -53,6 +59,7 @@ my $from_filename = 0;
 my $pattern_depth = 0;
 my $version = 0;
 my $help = 0;
+my $find_maintainer_files = 0;
 
 my $vcs_used = 0;
 
@@ -128,6 +135,7 @@ my %VCS_cmds_git = (
 "author_pattern" => "^GitAuthor: (.*)",
 "subject_pattern" => "^GitSubject: (.*)",
 "stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$",
+"file_exists_cmd" => "git ls-files \$file",
 );
 
 my %VCS_cmds_hg = (
@@ -156,6 +164,7 @@ my %VCS_cmds_hg = (
 "author_pattern" => "^HgAuthor: (.*)",
 "subject_pattern" => "^HgSubject: (.*)",
 "stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$",
+"file_exists_cmd" => "hg files \$file",
 );
 
 my $conf = which_conf(".get_maintainer.conf");
@@ -184,6 +193,27 @@ if (-f $conf) {
 unshift(@ARGV, @conf_args) if @conf_args;
 }
 
+my @ignore_emails = ();
+my $ignore_file = which_conf(".get_maintainer.ignore");
+if (-f $ignore_file) {
+open(my $ignore, '<', "$ignore_file")
+   or warn "$P: Can't find a readable .get_maintainer.ignore file $!\n";
+while (<$ignore>) {
+   my $line = $_;
+
+   $line =~ s/\s*\n?$//;
+   $line =~ s/^\s*//;
+   $line =~ s/\s+$//;
+   $line =~ s/#.*$//;
+
+   next if ($line =~ m/^\s*$/);
+   if (rfc822_valid($line)) {
+   push(@ignore_emails, $line);
+   }
+}
+close($ignore);
+}
+
 if (!GetOptions(
'email!' => \$email,
'git!' => \$email_git,
@@ -201,6 +231,7 @@ if (!GetOptions(
'remove-duplicates!' => \$email_remove_duplicates,
'mailmap!' => \$email_use_mailmap,
'm!' => \$email_maintainer,
+   'r!' => \$email_reviewer,
'n!' => \$email_usename,
'l!' => \$email_list,
's!' => \$email_subscriber_list,
@@ -212,11 +243,13 @@ if (!GetOptions(
'status!' => \$status,
'scm!' => \$scm,
'web!' => \$web,
+   'letters=s' => \$letters,
'pattern-depth=i' => \$pattern_depth,
'k|keywords!' => \$keywords,
'sections!' => \$sections,
'fe|file-emails!' => \$file_emails,
'f|file' => \$from_filename,
+   'find-maintainer-files' => \$find_maintainer_files,
'v|version' => \$version,
'h|help|usage' => \$help,
)) {
@@ -242,7 +275,8 @@ $output_multiline = 0 if ($output_separator ne ", ");
 $output_rolestats = 1 if ($interactive);
 $output_roles = 1 if ($output_rolestats);
 
-if ($sections) {
+if ($sections || $letters ne "") {
+$sections = 1;
 $email = 0;
 $email_list = 0;
 $scm = 0;
@@ -259,42 +293,28 @@ if ($sections) {
 }
 
 if ($email &&
-($email_maintainer + $email_list + $email_subscriber_list +
+($email_maintainer + $email_reviewer +
+ $email_list + $email_subscriber_list +
  $email_git + $email_git_penguin_chiefs + $email_git_blame) == 0) {
 die "$P: Please select at least 1 email option\n";
 }
 
 if (!top_of_kernel_tree($lk_path)) {
 die "$P: The current directory does not appear to be "
-   . "a linux kernel source tree.\n";
+   . "a U-Boot source tree.\n";
 }
 
 ## Read MAI

[U-Boot] [PATCH v2 2/9] efi_loader: implement SetWatchdogTimer

[Heinrich Schuchardt]

The watchdog is initialized with a 5 minute timeout period.
It can be reset by SetWatchdogTimer.
It is stopped by ExitBoottimeServices.

Signed-off-by: Heinrich Schuchardt 
---
v2
code comments updated
---
 cmd/bootefi.c |  1 +
 include/efi_loader.h  |  4 ++
 lib/efi_loader/Makefile   |  2 +-
 lib/efi_loader/efi_boottime.c | 17 ++---
 lib/efi_loader/efi_watchdog.c | 86 +++
 5 files changed, 95 insertions(+), 15 deletions(-)
 create mode 100644 lib/efi_loader/efi_watchdog.c

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 478bc116e2..18176a1266 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -43,6 +43,7 @@ static void efi_init_obj_list(void)
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
efi_smbios_register();
 #endif
+   efi_watchdog_register();
 
/* Initialize EFI runtime services */
efi_reset_system_init();
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 1b92edbd77..af64b11cee 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -163,6 +163,8 @@ int efi_disk_register(void);
 int efi_gop_register(void);
 /* Called by bootefi to make the network interface available */
 int efi_net_register(void);
+/* Called by bootefi to make the watchdog available */
+int efi_watchdog_register(void);
 /* Called by bootefi to make SMBIOS tables available */
 void efi_smbios_register(void);
 
@@ -171,6 +173,8 @@ efi_fs_from_path(struct efi_device_path *fp);
 
 /* Called by networking code to memorize the dhcp ack package */
 void efi_net_set_dhcp_ack(void *pkt, int len);
+/* Called by efi_set_watchdog_timer to reset the timer */
+efi_status_t efi_set_watchdog(unsigned long timeout);
 
 /* Called from places to check whether a timer expired */
 void efi_timer_check(void);
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index ddb978f650..83d879b686 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -17,7 +17,7 @@ endif
 obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
 obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
 obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o
-obj-y += efi_file.o efi_variable.o efi_bootmgr.o
+obj-y += efi_file.o efi_variable.o efi_bootmgr.o efi_watchdog.o
 obj-$(CONFIG_LCD) += efi_gop.o
 obj-$(CONFIG_DM_VIDEO) += efi_gop.o
 obj-$(CONFIG_PARTITIONS) += efi_disk.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 30577f717e..fd8d15655b 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -155,18 +155,6 @@ void efi_signal_event(struct efi_event *event)
event->is_queued = false;
 }
 
-/*
- * Write a debug message for an EPI API service that is not implemented yet.
- *
- * @funcname   function that is not yet implemented
- * @return EFI_UNSUPPORTED
- */
-static efi_status_t efi_unsupported(const char *funcname)
-{
-   debug("EFI: App called into unimplemented function %s\n", funcname);
-   return EFI_EXIT(EFI_UNSUPPORTED);
-}
-
 /*
  * Raise the task priority level.
  *
@@ -1454,6 +1442,7 @@ static efi_status_t EFIAPI efi_exit_boot_services(void 
*image_handle,
bootm_disable_interrupts();
 
/* Give the payload some time to boot */
+   efi_set_watchdog(0);
WATCHDOG_RESET();
 
return EFI_EXIT(EFI_SUCCESS);
@@ -1497,7 +1486,7 @@ static efi_status_t EFIAPI efi_stall(unsigned long 
microseconds)
 /*
  * Reset the watchdog timer.
  *
- * This function implements the WatchdogTimer service.
+ * This function implements the SetWatchdogTimer service.
  * See the Unified Extensible Firmware Interface (UEFI) specification
  * for details.
  *
@@ -1514,7 +1503,7 @@ static efi_status_t EFIAPI 
efi_set_watchdog_timer(unsigned long timeout,
 {
EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code,
  data_size, watchdog_data);
-   return efi_unsupported(__func__);
+   return EFI_EXIT(efi_set_watchdog(timeout));
 }
 
 /*
diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c
new file mode 100644
index 00..eb437faf4b
--- /dev/null
+++ b/lib/efi_loader/efi_watchdog.c
@@ -0,0 +1,86 @@
+/*
+ *  EFI watchdog
+ *
+ *  Copyright (c) 2017 Heinrich Schuchardt
+ *
+ *  SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+static struct efi_event *watchdog_timer_event;
+
+/*
+ * Reset the system when the watchdog event is notified.
+ *
+ * @event: the watchdog event
+ * @context:   not used
+ */
+static void EFIAPI efi_watchdog_timer_notify(struct efi_event *event,
+void *context)
+{
+   EFI_ENTRY("%p, %p", event, context);
+
+   printf("\nEFI: Watchdog timeout\n");
+   EFI_CALL_VOID(efi_runtime_services.reset_system(EFI_RESET_COLD,
+   EFI_SUCCESS, 0, NULL));
+
+   EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+/*
+ * Reset the watchdog ti

[U-Boot] [PATCH v2 1/9] efi_loader: move efi_search_obj up in code

[Heinrich Schuchardt]

To avoid a forward declaration move efi_search_obj before
all protocol services functions.

Signed-off-by: Heinrich Schuchardt 
---
v2
no change
---
 lib/efi_loader/efi_boottime.c | 41 +
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index f627340de4..30577f717e 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -690,6 +690,27 @@ static efi_status_t EFIAPI efi_check_event(struct 
efi_event *event)
return EFI_EXIT(EFI_INVALID_PARAMETER);
 }
 
+/*
+ * Find the internal EFI object for a handle.
+ *
+ * @handle handle to find
+ * @return EFI object
+ */
+static struct efi_object *efi_search_obj(void *handle)
+{
+   struct list_head *lhandle;
+
+   list_for_each(lhandle, &efi_obj_list) {
+   struct efi_object *efiobj;
+
+   efiobj = list_entry(lhandle, struct efi_object, link);
+   if (efiobj->handle == handle)
+   return efiobj;
+   }
+
+   return NULL;
+}
+
 /*
  * Install protocol interface.
  *
@@ -1355,26 +1376,6 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t 
image_handle,
panic("EFI application exited");
 }
 
-/*
- * Find the internal EFI object for a handle.
- *
- * @handle handle to find
- * @return EFI object
- */
-static struct efi_object *efi_search_obj(void *handle)
-{
-   struct list_head *lhandle;
-
-   list_for_each(lhandle, &efi_obj_list) {
-   struct efi_object *efiobj;
-   efiobj = list_entry(lhandle, struct efi_object, link);
-   if (efiobj->handle == handle)
-   return efiobj;
-   }
-
-   return NULL;
-}
-
 /*
  * Unload an EFI image.
  *
-- 
2.14.1

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