Re: [U-Boot] [PATCH] spl: dfu: compilation fixes for spl-dfu

[B, Ravi]

Hi Lukasz

>> diff --git a/common/cli.c b/common/cli.c index a433ef2..5e0869b 100644
>> --- a/common/cli.c
>> +++ b/common/cli.c
>> @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
>>   */
>>  int run_command(const char *cmd, int flag)  { -#ifndef 
>> CONFIG_HUSH_PARSER
>> +#if defined(CONFIG_SPL_DFU_SUPPORT) || !defined(CONFIG_HUSH_PARSER)

>I must admit that this seems odd to mesince we should avoided adding
> (SPL DFU) dependency to common parser code.

Yes, I agree, or use CONFIG_SPL_BUILD.

>Maybe some kconfig tweaks would help?

You Mean, unselect CONFIG_HUSH_PARSER when SPL_DFU_SUPPORT enabled?

Regards
Ravi


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[U-Boot] [PATCH v2] rockchip: rk3399: use actual dram size

[Kever Yang]

Since our sdram driver is ready, we can use the actual size
instead of hard code.

Signed-off-by: Kever Yang 
Acked-by: Simon Glass 
---

Changes in v2:
- fix compile warning of print type not match

 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c |  8 
 board/rockchip/evb_rk3399/evb-rk3399.c   | 19 ++-
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c 
b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
index 749b52c..536879d 100644
--- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
@@ -1280,6 +1280,8 @@ static int rk3399_dmc_probe(struct udevice *dev)
 
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+   priv->info.base = 0;
+   priv->info.size = sdram_size_mb(priv) << 20;
 #endif
return 0;
 }
@@ -1288,9 +1290,7 @@ static int rk3399_dmc_get_info(struct udevice *dev, 
struct ram_info *info)
 {
struct dram_info *priv = dev_get_priv(dev);
 
-   info = &priv->info;
-   priv->info.base = 0;
-   priv->info.size = sdram_size_mb(priv) << 20;
+   *info = priv->info;
 
return 0;
 }
@@ -1314,8 +1314,8 @@ U_BOOT_DRIVER(dmc_rk3399) = {
.ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
 #endif
.probe = rk3399_dmc_probe,
-#ifdef CONFIG_SPL_BUILD
.priv_auto_alloc_size = sizeof(struct dram_info),
+#ifdef CONFIG_SPL_BUILD
.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
 #endif
 };
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c 
b/board/rockchip/evb_rk3399/evb-rk3399.c
index e3ba020..9b98388 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -64,7 +65,23 @@ out:
 
 int dram_init(void)
 {
-   gd->ram_size = 0x8000;
+   struct ram_info ram;
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+   if (ret) {
+   debug("DRAM init failed: %d\n", ret);
+   return ret;
+   }
+   ret = ram_get_info(dev, &ram);
+   if (ret) {
+   debug("Cannot get DRAM size: %d\n", ret);
+   return ret;
+   }
+   debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size);
+   gd->ram_size = ram.size;
+
return 0;
 }
 
-- 
1.9.1

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Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Marek Vasut]

On 04/19/2017 05:32 AM, Ley Foon Tan wrote:
> On Tue, Apr 18, 2017 at 6:58 PM, Marek Vasut  wrote:
>> On 04/18/2017 05:12 AM, Ley Foon Tan wrote:
>>> On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut  wrote:
 On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut  wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Add config and defconfig for the Arria10 and update socfpga_common.h.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Signed-off-by: Ley Foon Tan 
>>
>> [...]
>>
>>> @@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>>   */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
>>> -#define CONFIG_SPL_MAX_SIZE  (64 * 1024)
>>> +#define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SPL_BOARD_INIT
>>
>> This should be in Kconfig and selected by arch/arm/mach-socfpga/Kconfig
>> entry for A10
> We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a
> Kconfig parameter now.

 OK. You can turn it into one, although that is out of the scope of this
 patchset.
>>> Okay, I will add SPL_BOARD_INIT to  arch/arm/mach-socfpga/Kconfig and
>>> select it for Arria 10.
>>
>> Do it in a separate patch please . Also, there's a script for turning
>> symbols into Kconfig symbols in u-boot.
> I think we don't need script if just add Kconfig to
> arch/arm/mach-socfpga/Kconfig, unless
> you want me add to common/spl/Kconfig and move this option to kconfig
> for all architectures.

That's what I had in mind, but please do it outside of this patchset, so
this one can go in.

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Re: [U-Boot] [PATCH 0/6] Android A/B Bootloader support

[Kever Yang]

Hi Alex,


It's great for this patch set which able to support full android 
boot flow,

there was no support for parse misc and enter recovery in U-Boot mainline.

Do you have a public tree or more detail step by step document, I want
to test this patch set on my board.

Thanks,
- Kever
On 04/02/2017 04:49 PM, Alex Deymo wrote:

An "Android Bootloader" has a lot of requirements about how it should
behave which Android partners must implement. In particular, the new
A/B updates [1] added more requirements and flows to the bootloader
which are not common, on top of the existing flows.

For example, a few uncommon requirements include:
* Lookup in the BCB (boot control block) whether a "recovery" message
   is stored. This is used by the recovery environment when applying a
   multi-stage update in the legacy update model (recovery reboots to
   recovery again) and for interrumpted factory-reset (a reboot during
   the factory reset should continue to reboot into factory reset until
   it is done).
* A new "repair" mode. In the A/B model, when none of the slots is
   bootable, the device would boot into repair mode, which is often the
   same as "bootloader" mode (fastboot).
* Recovery as root: In newer version of AOSP, it is possible to mount
   the system image as / without an initramfs, which then frees up the
   initramfs in the "boot" partition to hold the "recovery" initramfs.
   This is the default for new devices and required for the A/B setup.

This patchset updates the Android-related headers and introduces new
commands to boot a recent Android build. This work is based on the
bootloader used in the Raspberry Pi in Android Things and extensively
tested there.

[1] https://source.android.com/devices/tech/ota/ab_updates.html


Alex Deymo (6):
   image: Update include/android_image.h
   image: Implement a function to load Android Images.
   cmd: Add 'load_android' command to load Android images.
   disk: Return the partition number in part_get_info_by_name()
   Initial support for the Android Bootloader flow
   cmd: Add "boot_android" command.

  README   |  25 ++-
  cmd/Kconfig  |  19 ++
  cmd/Makefile |   2 +
  cmd/boot_android.c   | 126 +
  cmd/load_android.c   |  56 ++
  common/Kconfig   |  19 ++
  common/Makefile  |   1 +
  common/android_bootloader.c  | 350 +++
  common/fb_mmc.c  |   6 +-
  common/image-android.c   |  60 ++
  disk/part.c  |   2 +-
  include/android_bootloader.h |  48 +
  include/android_bootloader_message.h | 174 +
  include/android_image.h  |  24 ++-
  include/image.h  |  19 ++
  include/part.h   |   3 +-
  16 files changed, 920 insertions(+), 14 deletions(-)
  create mode 100644 cmd/boot_android.c
  create mode 100644 cmd/load_android.c
  create mode 100644 common/android_bootloader.c
  create mode 100644 include/android_bootloader.h
  create mode 100644 include/android_bootloader_message.h




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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Marek Vasut]

On 04/19/2017 07:29 AM, Heiko Schocher wrote:
> Hello Tom,
> 
> added Lukasz, Marek and Felipe,
> 
> Am 18.04.2017 um 00:22 schrieb Tom Rini:
>> Hey all,
>>
>> It's release day and v2017.05-rc2 is out.  I think my patchwork queue is
>> looking good currently.  I have some outstanding removal patches to take
>> from Masahiro related to architectures that I removed as promised.  The
>> release is bigger than I really wanted, but since I was on vacation for
>> most of the normal -rc1 window, stuff came in that would have come in
>> then now, instead.  Things are on track for -rc3 on the 1st.
> 
> My weekly dfu test on the siemens smartweb board failed with
> current HEAD.
> 
> I started an automated git bisect with tbot, and found:
> 
> 2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect visualize
> 2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
> 842778a091047b0c868efa12229633959f711152
> Author: Felipe Balbi 
> Date:   Wed Feb 22 17:12:40 2017 +0200
> usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
> 
> We don't want to claim that we support a serial number string and
> later return nothing. Because of that, if g_dnl_serial is an empty
> string, let's skip setting iSerialNumber to a valid number.
> 
> Signed-off-by: Felipe Balbi 
> hs@pollux [ 7:24:30] ttbott>
> 2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
> 2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start
> # bad: [f6c1df44b815a08585e7fd3805a1db51a5955d09] Prepare v2017.05-rc2
> git bisect bad f6c1df44b815a08585e7fd3805a1db51a5955d09
> # good: [9963890b8be1d208035945abc5ba9f77637b6542] libfdt: fix build
> with Python 3
> git bisect good 9963890b8be1d208035945abc5ba9f77637b6542
> # good: [af1b7286d8b2712cff5779d8a1565afed9d9d8e6] Merge branch 'master'
> of git://git.denx.de/u-boot-mmc
> git bisect good af1b7286d8b2712cff5779d8a1565afed9d9d8e6
> # bad: [3fea95369850987de15a2a0ac009d05e13b90246] Merge branch 'master'
> of git://git.denx.de/u-boot-video
> git bisect bad 3fea95369850987de15a2a0ac009d05e13b90246
> # good: [c1a16c3ab541c014b029b42cc27cae496107e170] Merge branch 'master'
> of git://git.denx.de/u-boot-socfpga
> git bisect good c1a16c3ab541c014b029b42cc27cae496107e170
> # bad: [fbeb33752999e7317113199ef89873d6b6916814] buildman: Translate
> more strings to latin-1
> git bisect bad fbeb33752999e7317113199ef89873d6b6916814
> # bad: [b7bf4a95922c3e1a4974aa34ebb714ac2eb89937] usb: dwc3: ensure
> consistent types for dwc3_flush_cache
> git bisect bad b7bf4a95922c3e1a4974aa34ebb714ac2eb89937
> # good: [12d0b8f5f07b76d7447d60f7528d578233553909] usb: gadget: g_dnl:
> hold maximum string descriptor
> git bisect good 12d0b8f5f07b76d7447d60f7528d578233553909
> # bad: [207835b13feeae15db074d89352a4e5379a4] usb: gadget: g_dnl:
> don't set iProduct nor iSerialNumber
> git bisect bad 207835b13feeae15db074d89352a4e5379a4
> # bad: [842778a091047b0c868efa12229633959f711152] usb: gadget: g_dnl:
> only set iSerialNumber if we have a serial#
> git bisect bad 842778a091047b0c868efa12229633959f711152
> # first bad commit: [842778a091047b0c868efa12229633959f711152] usb:
> gadget: g_dnl: only set iSerialNumber if we have a serial#
> hs@pollux [ 7:24:31] ttbott>
> 
> Any ideas?

Is your board setting up the serial number with g_dnl_set_serialnumber()
correctly ?

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Stefan Roese]

Hi Kosta,

On 28.03.2017 17:16, kos...@marvell.com wrote:
> From: Konstantin Porotchkin 
> 
> Add NAND configuration parameters to A8K shared config file.
> Add defconfig for db-88f7040 board with boot from NAND setup.
> 
> Signed-off-by: Konstantin Porotchkin 
> Cc: Stefan Roese 
> Cc: Igal Liberman 
> Cc: Nadav Haklai 
> ---
>  configs/mvebu_db-88f7040-nand_defconfig | 72 
> +
>  include/configs/mvebu_armada-8k.h   | 11 +
>  2 files changed, 83 insertions(+)
>  create mode 100644 configs/mvebu_db-88f7040-nand_defconfig

I'm currently testing this patchset and get this compilation error
via Travis:

   aarch64:  +   mvebu_db-88f7040-nand
+drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
+drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE undeclared 
(first use in this function)
+  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;

Did I miss a patch that adds this macro for A7/8k?

Thanks,
Stefan
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Re: [U-Boot] [PATCH v2] rockchip: reserve memory for rk3399 ATF data

[Dr. Philipp Tomsich]

Reviewed-by: Philipp Tomsich mailto:philipp.toms...@theobroma-systems.com>>

> On 19 Apr 2017, at 08:42, Kever Yang  wrote:
> 
> There are 3 region used by rk3399 ATF:
> - bl31 code, locate at 0x1;
> - cortex-m0 code and data, locate at 0xff8c;
> - bl31 data, locate at 0xff8c1000 ~ 0xff8c4000;
> 
> SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
> for ATF data, or else there will have memory corrupt after SPL
> load ATF image.
> 
> More detail about cortex-M0 code in ATF:
> https://github.com/ARM-software/arm-trusted-firmware/commit/
> 8382e17c4c6bffd15119dfce1ee4372e3c1a7890
> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v2:
> - use Kconfig for the reserved memory size
> 
> arch/arm/include/asm/arch-rockchip/boot0.h | 4 
> arch/arm/mach-rockchip/Kconfig | 8 
> 2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h 
> b/arch/arm/include/asm/arch-rockchip/boot0.h
> index 8d7bc9a..7346876 100644
> --- a/arch/arm/include/asm/arch-rockchip/boot0.h
> +++ b/arch/arm/include/asm/arch-rockchip/boot0.h
> @@ -16,3 +16,7 @@
>   .space 0x4 /* space for the 'RK33' */
> #endif
>   b reset
> +
> +#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
> + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
> +#endif
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index af0796d..979b48e 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -72,6 +72,14 @@ config ROCKCHIP_SPL_BACK_TO_BROM
>   SPL will return to the boot rom, which will then load the U-Boot
>   binary to keep going on.
> 
> +config ROCKCHIP_SPL_RESERVE_IRAM
> + hex "Size of IRAM reserved in SPL"
> + default 0x4000
> + help
> +   SPL may need reserve memory for firmware load by SPL, which load
> +   address is in IRAM and may overlay with SPL text area if not
> +   reserved.
> +
> config ROCKCHIP_BROM_HELPER
>   bool
> 
> -- 
> 1.9.1
> 

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Re: [U-Boot] [PATCH] at91_udc.c: Fix unused variable warning

[Marek Vasut]

On 04/19/2017 04:23 AM, Tom Rini wrote:
> With gcc-6 and later we see warnings that at91sam9263_udc_caps and
> at91rm9200_udc_caps are unused.
> 
> Fixes: 620197670a69 ("usb: gadget: at91_udc: add at91_udc into U-Boot")
> Cc: Lukasz Majewski 
> Cc: Marek Vasut 
> Signed-off-by: Tom Rini 

I'd like Heiko's ACK on this one, since it's his patch which dropped the
references. IMO looks OK tho.

> ---
>  drivers/usb/gadget/at91_udc.c | 10 --
>  1 file changed, 10 deletions(-)
> 
> diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
> index f5bc277fa6e0..01a59078b84a 100644
> --- a/drivers/usb/gadget/at91_udc.c
> +++ b/drivers/usb/gadget/at91_udc.c
> @@ -1386,11 +1386,6 @@ static void at91rm9200_udc_pullup(struct at91_udc 
> *udc, int is_on)
>   gpio_set_value(udc->board.pullup_pin, !active);
>  }
>  
> -static const struct at91_udc_caps at91rm9200_udc_caps = {
> - .init = at91rm9200_udc_init,
> - .pullup = at91rm9200_udc_pullup,
> -};
> -
>  static int at91sam9260_udc_init(struct at91_udc *udc)
>  {
>   struct at91_ep *ep;
> @@ -1503,11 +1498,6 @@ static int at91sam9263_udc_init(struct at91_udc *udc)
>   return 0;
>  }
>  
> -static const struct at91_udc_caps at91sam9263_udc_caps = {
> - .init = at91sam9263_udc_init,
> - .pullup = at91sam9260_udc_pullup,
> -};
> -
>  int usb_gadget_handle_interrupts(int index)
>  {
>   struct at91_udc *udc = controller;
> 


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Ley Foon Tan]

On Wed, Apr 19, 2017 at 4:38 PM, Marek Vasut  wrote:
> On 04/19/2017 05:32 AM, Ley Foon Tan wrote:
>> On Tue, Apr 18, 2017 at 6:58 PM, Marek Vasut  wrote:
>>> On 04/18/2017 05:12 AM, Ley Foon Tan wrote:
 On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut  wrote:
> On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
>> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut  wrote:
>>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
 Add config and defconfig for the Arria10 and update socfpga_common.h.

 Signed-off-by: Tien Fong Chee 
 Signed-off-by: Ley Foon Tan 
>>>
>>> [...]
>>>
 @@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
   */
  #define CONFIG_SPL_FRAMEWORK
  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
 -#define CONFIG_SPL_MAX_SIZE  (64 * 1024)
 +#define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
 +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 +#define CONFIG_SPL_BOARD_INIT
>>>
>>> This should be in Kconfig and selected by arch/arm/mach-socfpga/Kconfig
>>> entry for A10
>> We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a
>> Kconfig parameter now.
>
> OK. You can turn it into one, although that is out of the scope of this
> patchset.
 Okay, I will add SPL_BOARD_INIT to  arch/arm/mach-socfpga/Kconfig and
 select it for Arria 10.
>>>
>>> Do it in a separate patch please . Also, there's a script for turning
>>> symbols into Kconfig symbols in u-boot.
>> I think we don't need script if just add Kconfig to
>> arch/arm/mach-socfpga/Kconfig, unless
>> you want me add to common/spl/Kconfig and move this option to kconfig
>> for all architectures.
>
> That's what I had in mind, but please do it outside of this patchset, so
> this one can go in.
For this A10 patchset, I will add it to  arch/arm/mach-socfpga/Kconfig
first and I will send another patchset to add SPL_BOARD_INIT to
common/spl/Kconfig on top of this patchset.
So, we can get this patchset to get in first because move
SPL_BOARD_INIT to kconfig for all architectures might take longer time
to review . What do you think?

Regards
Ley Foon
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Re: [U-Boot] [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Kostya Porotchkin]

Hi, Stefan,

> -Original Message-
> From: Stefan Roese [mailto:s...@denx.de]
> Sent: Wednesday, April 19, 2017 11:45
> To: Kostya Porotchkin; u-boot@lists.denx.de
> Cc: Igal Liberman; Nadav Haklai
> Subject: [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration
> parameters
> 
> External Email
> 
> --
> Hi Kosta,
> 
> On 28.03.2017 17:16, kos...@marvell.com wrote:
> > From: Konstantin Porotchkin 
> >
> > Add NAND configuration parameters to A8K shared config file.
> > Add defconfig for db-88f7040 board with boot from NAND setup.
> >
> > Signed-off-by: Konstantin Porotchkin 
> > Cc: Stefan Roese 
> > Cc: Igal Liberman 
> > Cc: Nadav Haklai 
> > ---
> >  configs/mvebu_db-88f7040-nand_defconfig | 72
> +
> >  include/configs/mvebu_armada-8k.h   | 11 +
> >  2 files changed, 83 insertions(+)
> >  create mode 100644 configs/mvebu_db-88f7040-nand_defconfig
> 
> I'm currently testing this patchset and get this compilation error via
> Travis:
> 
>aarch64:  +   mvebu_db-88f7040-nand
> +drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
> +drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE
> +undeclared (first use in this function)
> +  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
> 
> Did I miss a patch that adds this macro for A7/8k?
[Konstantin Porotchkin] 
The hardcoded values should be changed in the following patch:
[PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver
However I do not see it on patchworks site.
Should I re-send it?

Thanks
Kosta
> 
> Thanks,
> Stefan
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Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Marek Vasut]

On 04/19/2017 10:49 AM, Ley Foon Tan wrote:
> On Wed, Apr 19, 2017 at 4:38 PM, Marek Vasut  wrote:
>> On 04/19/2017 05:32 AM, Ley Foon Tan wrote:
>>> On Tue, Apr 18, 2017 at 6:58 PM, Marek Vasut  wrote:
 On 04/18/2017 05:12 AM, Ley Foon Tan wrote:
> On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut  wrote:
>> On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
>>> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut  wrote:
 On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
> Add config and defconfig for the Arria10 and update socfpga_common.h.
>
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 

 [...]

> @@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   */
>  #define CONFIG_SPL_FRAMEWORK
>  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
> -#define CONFIG_SPL_MAX_SIZE  (64 * 1024)
> +#define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SPL_BOARD_INIT

 This should be in Kconfig and selected by arch/arm/mach-socfpga/Kconfig
 entry for A10
>>> We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a
>>> Kconfig parameter now.
>>
>> OK. You can turn it into one, although that is out of the scope of this
>> patchset.
> Okay, I will add SPL_BOARD_INIT to  arch/arm/mach-socfpga/Kconfig and
> select it for Arria 10.

 Do it in a separate patch please . Also, there's a script for turning
 symbols into Kconfig symbols in u-boot.
>>> I think we don't need script if just add Kconfig to
>>> arch/arm/mach-socfpga/Kconfig, unless
>>> you want me add to common/spl/Kconfig and move this option to kconfig
>>> for all architectures.
>>
>> That's what I had in mind, but please do it outside of this patchset, so
>> this one can go in.
> For this A10 patchset, I will add it to  arch/arm/mach-socfpga/Kconfig
> first and I will send another patchset to add SPL_BOARD_INIT to
> common/spl/Kconfig on top of this patchset.

No, please don't, this will only introduce inconsistency.

> So, we can get this patchset to get in first because move
> SPL_BOARD_INIT to kconfig for all architectures might take longer time
> to review . What do you think?

Just keep it as is now and ev. submit a separate patch which converts
that to Kconfig later.

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Re: [U-Boot] [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Stefan Roese]

Hi Kosta,

On 19.04.2017 10:50, Kostya Porotchkin wrote:

Hi, Stefan,


-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Wednesday, April 19, 2017 11:45
To: Kostya Porotchkin; u-boot@lists.denx.de
Cc: Igal Liberman; Nadav Haklai
Subject: [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration
parameters

External Email

--
Hi Kosta,

On 28.03.2017 17:16, kos...@marvell.com wrote:

From: Konstantin Porotchkin 

Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.

Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Igal Liberman 
Cc: Nadav Haklai 
---
 configs/mvebu_db-88f7040-nand_defconfig | 72

+

 include/configs/mvebu_armada-8k.h   | 11 +
 2 files changed, 83 insertions(+)
 create mode 100644 configs/mvebu_db-88f7040-nand_defconfig


I'm currently testing this patchset and get this compilation error via
Travis:

   aarch64:  +   mvebu_db-88f7040-nand
+drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
+drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE
+undeclared (first use in this function)
+  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;

Did I miss a patch that adds this macro for A7/8k?

[Konstantin Porotchkin]
The hardcoded values should be changed in the following patch:
[PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver
However I do not see it on patchworks site.
Should I re-send it?


No need. I've found it in my inbox. Travis build is already restarted...

Thanks,
Stefan
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Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Ley Foon Tan]

On Wed, Apr 19, 2017 at 4:53 PM, Marek Vasut  wrote:
> On 04/19/2017 10:49 AM, Ley Foon Tan wrote:
>> On Wed, Apr 19, 2017 at 4:38 PM, Marek Vasut  wrote:
>>> On 04/19/2017 05:32 AM, Ley Foon Tan wrote:
 On Tue, Apr 18, 2017 at 6:58 PM, Marek Vasut  wrote:
> On 04/18/2017 05:12 AM, Ley Foon Tan wrote:
>> On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut  wrote:
>>> On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
 On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut  wrote:
> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>> Add config and defconfig for the Arria10 and update socfpga_common.h.
>>
>> Signed-off-by: Tien Fong Chee 
>> Signed-off-by: Ley Foon Tan 
>
> [...]
>
>> @@ -298,7 +306,10 @@ unsigned int 
>> cm_get_qspi_controller_clk_hz(void);
>>   */
>>  #define CONFIG_SPL_FRAMEWORK
>>  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
>> -#define CONFIG_SPL_MAX_SIZE  (64 * 1024)
>> +#define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#define CONFIG_SPL_BOARD_INIT
>
> This should be in Kconfig and selected by 
> arch/arm/mach-socfpga/Kconfig
> entry for A10
 We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a
 Kconfig parameter now.
>>>
>>> OK. You can turn it into one, although that is out of the scope of this
>>> patchset.
>> Okay, I will add SPL_BOARD_INIT to  arch/arm/mach-socfpga/Kconfig and
>> select it for Arria 10.
>
> Do it in a separate patch please . Also, there's a script for turning
> symbols into Kconfig symbols in u-boot.
 I think we don't need script if just add Kconfig to
 arch/arm/mach-socfpga/Kconfig, unless
 you want me add to common/spl/Kconfig and move this option to kconfig
 for all architectures.
>>>
>>> That's what I had in mind, but please do it outside of this patchset, so
>>> this one can go in.
>> For this A10 patchset, I will add it to  arch/arm/mach-socfpga/Kconfig
>> first and I will send another patchset to add SPL_BOARD_INIT to
>> common/spl/Kconfig on top of this patchset.
>
> No, please don't, this will only introduce inconsistency.
>
>> So, we can get this patchset to get in first because move
>> SPL_BOARD_INIT to kconfig for all architectures might take longer time
>> to review . What do you think?
>
> Just keep it as is now and ev. submit a separate patch which converts
> that to Kconfig later.
Okay, will keep SPL_BOARD_INIT in include/configs/socfpga_common.h as
now first and send separate patchset to convert it to kconfig later.

Thanks.

Regards
Ley Foon
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[U-Boot] [PATCH] imx-common: timer: clean up

[Peng Fan]

Drop the unneeded code. lib/time.c use timebase_l/h.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/timer.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index ee6eff2..9b01114 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -105,9 +105,6 @@ int timer_init(void)
 #endif
__raw_writel(i, &cur_gpt->control);
 
-   gd->arch.tbl = __raw_readl(&cur_gpt->counter);
-   gd->arch.tbu = 0;
-
return 0;
 }
 
-- 
2.6.2

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Re: [U-Boot] [PATCH] imx-common: timer: clean up

[Stefano Babic]

On 19/04/2017 11:05, Peng Fan wrote:
> Drop the unneeded code. lib/time.c use timebase_l/h.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> ---
>  arch/arm/imx-common/timer.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
> index ee6eff2..9b01114 100644
> --- a/arch/arm/imx-common/timer.c
> +++ b/arch/arm/imx-common/timer.c
> @@ -105,9 +105,6 @@ int timer_init(void)
>  #endif
>   __raw_writel(i, &cur_gpt->control);
>  
> - gd->arch.tbl = __raw_readl(&cur_gpt->counter);
> - gd->arch.tbu = 0;
> -
>   return 0;
>  }
>  
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH v3 02/15] sysreset-uclass: ensure udevice is probed before requesting reset

[Álvaro Fernández Rojas]

This is what I think it's going on:
sysreset_walk():
- calls uclass_first_device():
- Calls uclass_find_first_device():
- device is found.
- ret is set to 0.
- Calls uclass_get_device_tail():
- ret == 0 -> doesn't return.
- dev != null -> assert is true.
- Calls device_probe():
- It fails *somewhere* and goes to fail WITHOUT setting 
dev to NULL.
- ret != 0 -> returns without setting devp = dev.
- dev is NOT NULL but device is not probed.
- Tries to get ops from a not probed device -> Exception.
So basically it's a bug related to device_probe not nulling dev when failing 
and sysreset_walk() checking only if the device is not null and not the actual 
return of uclass_first_device() and uclass_next_device()...







On Wed, Apr 19, 2017 at 7:28 AM +0200, "Álvaro Fernández Rojas" 
 wrote:










Hi Simon,

El 19/04/2017 a las 2:13, Simon Glass escribió:
> Hi Alvaro,
> 
> On 18 April 2017 at 14:38, Álvaro Fernández Rojas  wrote:
>> This causes exceptions for drivers that aren't probed when reboot is
>> requested.
>>
>> Signed-off-by: Álvaro Fernández Rojas 
>> ---
>>  v3: add new patch to ensure that the device is probed
>>
>>  drivers/sysreset/sysreset-uclass.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/sysreset/sysreset-uclass.c 
>> b/drivers/sysreset/sysreset-uclass.c
>> index 3566d17..329dc2e 100644
>> --- a/drivers/sysreset/sysreset-uclass.c
>> +++ b/drivers/sysreset/sysreset-uclass.c
>> @@ -34,6 +34,9 @@ int sysreset_walk(enum sysreset_t type)
>> for (uclass_first_device(UCLASS_SYSRESET, &dev);
>>  dev;
>>  uclass_next_device(&dev)) {
>> +   if (!device_active(dev) && device_probe(dev))
>> +   continue;
> 
> uclass_first_device() should activate the device. Can you please dig
> into what is going on here?
I'll try to investigate it later today or tomorrow...
Could this be related to core/uclass: uclass_get_device_tail: always set devp?
http://patchwork.ozlabs.org/patch/751929/

> 
>> +
>> ret = sysreset_request(dev, type);
>> if (ret == -EINPROGRESS)
>> break;
>> --
>> 2.1.4
>>
> 
> Regards,
> Simon
> 
Regards,
Álvaro.





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Re: [U-Boot] [PATCH 1/4] dm: device_remove: Don't return in device_chld_remove() upon error

[Stefan Roese]

Hi Simon,

sorry for the late replay - just back from vacation

On 09.04.2017 21:28, Simon Glass wrote:

Hi Stefan,

On 6 April 2017 at 07:29, Stefan Roese  wrote:

On my x86 platform I've noticed, that calling dm_uninit() or the new
function dm_remove_devices_flags() does not remove the desired device at
all. Debugging showed, that the serial uclass returns -EPERM in
serial_pre_remove() and this leads to a complete stop of the device
removal pretty early, as the serial device is one of the first ones in
the DM. Here the dm tree output:

=> dm tree
 Class   Probed   Name

 root[ + ]root_driver
 rsa_mod_exp [   ]|-- mod_exp_sw
 serial  [ + ]|-- serial
 rtc [   ]|-- rtc
 timer   [ + ]|-- tsc-timer
 syscon  [ + ]|-- pch_pinctrl
 ...

In this example, device_remove(root) will stop directly after trying to
remove the "serial" device.

To solve this problem, this patch removes the return upon error check in
the device_remove() call in device_chld_remove(). This leads to
device_chld_remove() continuing with the device_remove() call to the
following child devices.


I think the right solution is to find out why stdio_deregister_dev()
fails. It is probably because the device is in use within the stdio
variables.


This is most likely the case, yes.


Perhaps you need to remove it first?


Not sure if this should / could be done in this general case of
removal of all devices (or all devices matching a remove-flag)?
Please think of dm_uninit() being called. This functions should
have no internal knowledge of usage of devices. One thing I could
do, probably best in a separate patch, is to use the force flag
of stdio_deregister_dev() in serial_pre_remove() to force the
serial device(s) to be removed in this case. What do you think?



Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 drivers/core/device-remove.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index cc0043b990..8b46f3343e 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -52,15 +52,11 @@ static int device_chld_unbind(struct udevice *dev)
 static int device_chld_remove(struct udevice *dev, uint flags)
 {
struct udevice *pos, *n;
-   int ret;

assert(dev);

-   list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
-   ret = device_remove(pos, flags);
-   if (ret)
-   return ret;
-   }
+   list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node)
+   device_remove(pos, flags);


I think we should keep the error checking here.


The main fix with this patch is, that removing of child devices does
not stop once an error is encountered. Even if an error occurs with
one child-device of a parent, all other child-devices of this
parent should still be removed - or at least tried to.

So what does this error code buy us here? Should I print a log message
here in this error case?

Thanks,
Stefan
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[U-Boot] [PATCH v6 00/16] Add Intel Arria 10 SoC support

[Ley Foon Tan]

This is the 6th version of patchset to adds support for Intel Arria 10 SoC.
This is initial patchset enables the basic support for Arria 10 and other
features will come after this.

There is only one minor change in patch #5.

This series is rebased on top of 
http://git.denx.de/?p=u-boot/u-boot-socfpga.git.

v5 -> v6 changes:
-
-  macros sorted by address

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240052.html
[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg241249.html
[v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg243107.html
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg243815.html
[v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg244930.html

Ley Foon Tan (16):
  arm: socfpga: Restructure clock manager driver
  arm: socfpga: Restructure reset manager driver
  arm: socfpga: Restructure system manager
  arm: socfpga: Restructure misc driver
  arm: socfpga: Add A10 macros
  arm: socfpga: Add reset driver support for Arria 10
  arm: socfpga: Add clock driver for Arria 10
  arm: socfpga: Add system manager for Arria 10
  arm: socfpga: Add sdram header file for Arria 10
  arm: socfpga: Add pinmux for Arria 10
  arm: socfpga: Add misc support for Arria 10
  arm: dts: Add dts and dtsi for Arria 10
  arm: socfpga: Add SPL support for Arria 10
  arm: socfpga: Add config and defconfig for Arria 10
  arm: socfpga: Add board files for the Arria10
  arm: socfpga: Enable build for Arria 10

 arch/arm/dts/Makefile  |1 +
 arch/arm/dts/socfpga_arria10.dtsi  |  869 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   38 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  481 +
 arch/arm/mach-socfpga/Kconfig  |   10 +
 arch/arm/mach-socfpga/Makefile |   41 +-
 arch/arm/mach-socfpga/clock_manager.c  |  525 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1096 
 .../{clock_manager.c => clock_manager_gen5.c}  |  137 +--
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |8 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  317 +-
 .../include/mach/clock_manager_arria10.h   |  224 
 .../mach/{clock_manager.h => clock_manager_gen5.h} |  151 +--
 arch/arm/mach-socfpga/include/mach/misc.h  |   31 +
 arch/arm/mach-socfpga/include/mach/pinmux.h|   17 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   50 +-
 .../include/mach/reset_manager_arria10.h   |  146 +++
 .../mach-socfpga/include/mach/reset_manager_gen5.h |   49 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |  380 +++
 .../arm/mach-socfpga/include/mach/system_manager.h |  202 ++--
 .../include/mach/system_manager_arria10.h  |   81 ++
 .../{system_manager.h => system_manager_gen5.h}|   39 +-
 arch/arm/mach-socfpga/misc.c   |  363 +--
 arch/arm/mach-socfpga/misc_arria10.c   |  259 +
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  |  157 +--
 arch/arm/mach-socfpga/pinmux_arria10.c |   96 ++
 arch/arm/mach-socfpga/reset_manager.c  |   93 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  383 +++
 .../{reset_manager.c => reset_manager_gen5.c}  |   51 +-
 arch/arm/mach-socfpga/spl.c|   75 +-
 .../{system_manager.c => system_manager_gen5.c}|6 +-
 board/altera/arria10-socdk/Kconfig |   18 +
 board/altera/arria10-socdk/Makefile|7 +
 board/altera/arria10-socdk/socfpga.c   |7 +
 configs/socfpga_arria10_defconfig  |   29 +
 include/configs/socfpga_arria10_socdk.h|   66 ++
 include/configs/socfpga_common.h   |   21 +-
 include/dt-bindings/reset/altr,rst-mgr-a10.h   |  110 ++
 38 files changed, 4837 insertions(+), 1797 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (85%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{clock_manager.h => 
clock_manager_gen5.h} (79%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{system_manager.h => 
system

[U-Boot] [PATCH v6 02/16] arm: socfpga: Restructure reset manager driver

[Ley Foon Tan]

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files. Change socfpga_per_reset() return 
type to int.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |  2 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 48 ++-
 .../mach-socfpga/include/mach/reset_manager_gen5.h | 49 
 arch/arm/mach-socfpga/reset_manager.c  | 93 +-
 .../{reset_manager.c => reset_manager_gen5.c}  | 51 ++--
 5 files changed, 83 insertions(+), 160 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (75%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b76de4c..97819ac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..c99efa7 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,34 +1,19 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef_RESET_MANAGER_H_
-#define_RESET_MANAGER_H_
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
 
-void socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-   u32 status;
-   u32 ctrl;
-   u32 counts;
-   u32 padding1;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;
-   u32 per2_mod_reset;
-   u32 brg_mod_reset;
-   u32 misc_mod_reset;
-   u32 padding2[12];
-   u32 tstscratch;
-};
-
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
@@ -55,28 +40,11 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
-#define RSTMGR_NANDRSTMGR_DEFINE(1, 4)
-#define RSTMGR_QSPIRSTMGR_DEFINE(1, 5)
-#define RSTMGR_L4WD0   RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0  RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0   RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 19)
-#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
-#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
-#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 000..39529fa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,49 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _RESET_MANAGER_GEN5_H_
+#define _RESET_MANAGER_GEN5_H_
+
+#include 
+
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 ctrl;
+   u32 counts;
+   u32 padding1;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;
+   u32 per2_mod_reset;
+   u32 brg_mod_reset;
+   u32 misc_mod_reset;
+   u32 padding2[12];
+   u32 tstscratch;
+};
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1,

[U-Boot] [PATCH v6 01/16] arm: socfpga: Restructure clock manager driver

[Ley Foon Tan]

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   3 +-
 arch/arm/mach-socfpga/clock_manager.c  | 515 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 137 ++
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 316 +
 .../mach/{clock_manager.h => clock_manager_gen5.h} | 151 +++---
 arch/arm/mach-socfpga/spl.c|   3 +-
 6 files changed, 149 insertions(+), 976 deletions(-)
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (85%)
 copy arch/arm/mach-socfpga/include/mach/{clock_manager.h => 
clock_manager_gen5.h} (79%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b76de4c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -13,7 +13,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o 
clock_manager.o \
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
+  clock_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 29e18f8..8051995 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,10 +1,11 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -13,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+void cm_wait_for_lock(u32 mask)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
+   u32 inter_val;
+   u32 retry = 0;
do {
inter_val = readl(&clock_manager_base->inter) & mask;
if (inter_val == mask)
@@ -29,510 +30,10 @@ static void cm_wait_for_lock(uint32_t mask)
 }
 
 /* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
+int cm_wait_for_fsm(void)
 {
-   while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
-
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, &clock_manager_base->bypass);
-   cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, &clock_manager_base->ctrl);
-   cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
-{
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
-
-   writel(value, reg_address);
-
-   while (readl(reg_address) & mask)
-   ;
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-void cm_basic_init(const struct cm_config * const cfg)
-{
-   unsigned long end;
-
-   /* Start by being paranoid and gate all sw managed clocks */
-
-   /*
-* We need to disable nandclk
-* and then do another apb access before disabling
-* gatting off the rest of the periperal clocks.
-*/
-   writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-   readl(&clock_manager_base->per_pll.en),
-   &clock_manager_base->per_pll.en);
-
-   /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE

[U-Boot] [PATCH v6 03/16] arm: socfpga: Restructure system manager

[Ley Foon Tan]

Restructure system manager in the preparation to support A10.
No functional change.

Change uint32_t to u32.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   5 +-
 .../arm/mach-socfpga/include/mach/system_manager.h | 128 ++---
 .../{system_manager.h => system_manager_gen5.h}|  39 +--
 .../{system_manager.c => system_manager_gen5.c}|   6 +-
 4 files changed, 22 insertions(+), 156 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{system_manager.h => 
system_manager_gen5.h} (73%)
 rename arch/arm/mach-socfpga/{system_manager.c => system_manager_gen5.c} (94%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 97819ac..4980e51 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -7,14 +7,15 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o \
+  system_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..30f0bbe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -1,120 +1,11 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef_SYSTEM_MANAGER_H_
-#define_SYSTEM_MANAGER_H_
-
-#ifndef __ASSEMBLY__
-
-void sysmgr_pinmux_init(void);
-void sysmgr_config_warmrstcfgio(int enable);
-
-void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-#endif
-
-struct socfpga_system_manager {
-   /* System Manager Module */
-   u32 siliconid1; /* 0x00 */
-   u32 siliconid2;
-   u32 _pad_0x8_0xf[2];
-   u32 wddbg;  /* 0x10 */
-   u32 bootinfo;
-   u32 hpsinfo;
-   u32 parityinj;
-   /* FPGA Interface Group */
-   u32 fpgaintfgrp_gbl;/* 0x20 */
-   u32 fpgaintfgrp_indiv;
-   u32 fpgaintfgrp_module;
-   u32 _pad_0x2c_0x2f;
-   /* Scan Manager Group */
-   u32 scanmgrgrp_ctrl;/* 0x30 */
-   u32 _pad_0x34_0x3f[3];
-   /* Freeze Control Group */
-   u32 frzctrl_vioctrl;/* 0x40 */
-   u32 _pad_0x44_0x4f[3];
-   u32 frzctrl_hioctrl;/* 0x50 */
-   u32 frzctrl_src;
-   u32 frzctrl_hwctrl;
-   u32 _pad_0x5c_0x5f;
-   /* EMAC Group */
-   u32 emacgrp_ctrl;   /* 0x60 */
-   u32 emacgrp_l3master;
-   u32 _pad_0x68_0x6f[2];
-   /* DMA Controller Group */
-   u32 dmagrp_ctrl;/* 0x70 */
-   u32 dmagrp_persecurity;
-   u32 _pad_0x78_0x7f[2];
-   /* Preloader (initial software) Group */
-   u32 iswgrp_handoff[8];  /* 0x80 */
-   u32 _pad_0xa0_0xbf[8];  /* 0xa0 */
-   /* Boot ROM Code Register Group */
-   u32 romcodegrp_ctrl;/* 0xc0 */
-   u32 romcodegrp_cpu1startaddr;
-   u32 romcodegrp_initswstate;
-   u32 romcodegrp_initswlastld;
-   u32 romcodegrp_bootromswstate;  /* 0xd0 */
-   u32 __pad_0xd4_0xdf[3];
-   /* Warm Boot from On-Chip RAM Group */
-   u32 romcodegrp_warmramgrp_enable;   /* 0xe0 */
-   u32 romcodegrp_warmramgrp_datastart;
-   u32 romcodegrp_warmramgrp_length;
-   u32 romcodegrp_warmramgrp_execution;
-   u32 romcodegrp_warmramgrp_crc;  /* 0xf0 */
-   u32 __pad_0xf4_0xff[3];
-   /* Boot ROM Hardware Register Group */
-   u32 romhwgrp_ctrl;  /* 0x100 */
-   u32 _pad_0x104_0x107;
-   /* SDMMC Controller Group */
-   u32 sdmmcgrp_ctrl;
-   u32 sdmmcgrp_l3master;
-   /* NAND Flash Controller Register Group */
-   u32 nandgrp_bootstrap;  /* 0x110 */
-   u32 nandgrp_l3master;
-   /* USB Controller Group */
-   u32 usbgrp_l3master;
-   u32 _pad_0x11c_0x13f[9];
-   /* ECC Management Register Group */
-   u32 eccgrp_l2; 

[U-Boot] [PATCH v6 04/16] arm: socfpga: Restructure misc driver

[Ley Foon Tan]

Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.

Change all uint32_t_to u32 and check return value from
socfpga_bridges_reset.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   2 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  25 ++
 arch/arm/mach-socfpga/misc.c  | 363 ++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 157 ++-
 4 files changed, 65 insertions(+), 482 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (71%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4980e51..e83da2e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
   clock_manager_gen5.o 
reset_manager_gen5.o \
-  system_manager_gen5.o
+  misc_gen5.o system_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..f344749
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+
+struct bsel {
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..00eff90 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -20,20 +21,21 @@
 #include 
 #include 
 
-#include 
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bsel bsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -72,207 +74,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   u32 physhift, reset;
-
-   if (of_reset_id == EMAC0_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-   reset = SOCFPGA_RESET(EMAC0);
-   } else if (of_reset_id == EMAC1_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-   reset = SOCFPGA_RESET(EMAC1);
-   } else {
-   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-   return;
-   }
-
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
-   /* configure to PHY interface select choosed */
-   setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-phymode << physhift);
-
-   /* Release the EMAC controller from reset */
-   socfpga_per_reset(reset, 0);
-}
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-   if (!phymode)
-   return -EINVAL;
-
-   if (!strcmp(phymode, "

[U-Boot] [PATCH v6 08/16] arm: socfpga: Add system manager for Arria 10

[Ley Foon Tan]

Add system manager register struct and macros for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 74 +---
 .../include/mach/system_manager_arria10.h  | 81 ++
 2 files changed, 144 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 30f0bbe..e6d4280 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,18 +7,18 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
-#define SYSMGR_ECC_OCRAM_EN(1 << 0)
-#define SYSMGR_ECC_OCRAM_SERR  (1 << 3)
-#define SYSMGR_ECC_OCRAM_DERR  (1 << 4)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
+#define SYSMGR_ECC_OCRAM_ENBIT(0)
+#define SYSMGR_ECC_OCRAM_SERR  BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR  BIT(4)
 #define SYSMGR_FPGAINTF_USEFPGA0x1
-#define SYSMGR_FPGAINTF_SPIM0  (1 << 0)
-#define SYSMGR_FPGAINTF_SPIM1  (1 << 1)
-#define SYSMGR_FPGAINTF_EMAC0  (1 << 2)
-#define SYSMGR_FPGAINTF_EMAC1  (1 << 3)
-#define SYSMGR_FPGAINTF_NAND   (1 << 4)
-#define SYSMGR_FPGAINTF_SDMMC  (1 << 5)
+#define SYSMGR_FPGAINTF_SPIM0  BIT(0)
+#define SYSMGR_FPGAINTF_SPIM1  BIT(1)
+#define SYSMGR_FPGAINTF_EMAC0  BIT(2)
+#define SYSMGR_FPGAINTF_EMAC1  BIT(3)
+#define SYSMGR_FPGAINTF_NAND   BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC  BIT(5)
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
 
@@ -31,8 +31,60 @@
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   BIT(4)
+#define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  BIT(16)
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  BIT(20)
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  BIT(24)
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK  BIT(0)
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK  BIT(1)
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK  BIT(1)
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
new file mode 100644
index 000..f235aba
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SYSTEM_MANAGER_ARRIA10_H_
+#define _SYSTEM_MANAGER_ARRIA10_H_
+
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac[3];
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_va

[U-Boot] [PATCH v6 06/16] arm: socfpga: Add reset driver support for Arria 10

[Ley Foon Tan]

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   2 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   | 146 
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 383 +
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 110 ++
 5 files changed, 643 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e83da2e..d81f003 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,6 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index c99efa7..a0d611b 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100644
index 000..e2b490d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _RESET_MANAGER_ARRIA10_H_
+#define _RESET_MANAGER_ARRIA10_H_
+
+#include 
+
+void socfpga_watchdog_disable(void);
+void socfpga_reset_deassert_noc_ddr_scheduler(void);
+int socfpga_is_wdt_in_reset(void);
+void socfpga_emac_manage_reset(ulong emacbase, u32 state);
+int socfpga_reset_deassert_bridges_handoff(void);
+void socfpga_reset_assert_fpga_connected_peripherals(void);
+void socfpga_reset_deassert_osc1wd0(void);
+void socfpga_reset_uart(int assert);
+
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpumodrst;
+   u32 per0modrst;
+   u32 per1modrst;
+   u32 brgmodrst;
+   u32 sysmodrst;
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSKBIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSKBIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSKBIT(7)
+#define ALT_RSTMGR_PER0MODR

[U-Boot] [PATCH v6 05/16] arm: socfpga: Add A10 macros

[Ley Foon Tan]

Add i2c, timer and other A10 macros.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..7818aa5 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -29,17 +29,23 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
-- 
1.8.2.3

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[U-Boot] [PATCH v6 11/16] arm: socfpga: Add misc support for Arria 10

[Ley Foon Tan]

Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/misc.h |   6 +
 arch/arm/mach-socfpga/misc_arria10.c  | 259 ++
 3 files changed, 266 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 503b79f..4ce8eac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -12,6 +12,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
pinmux_arria10.o\
+   misc_arria10.o  \
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index f344749..0b65783 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -22,4 +22,10 @@ void socfpga_fpga_add(void);
 static inline void socfpga_fpga_add(void) {}
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
new file mode 100644
index 000..9d751f6
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3  0x08
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3  0x68
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7  0x18
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7  0x78
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3  0x98
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+#endif
+
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode)
+{
+   u32 reset;
+
+   if (of_reset_id == EMAC0_RESET) {
+   reset = SOCFPGA_RESET(EMAC0);
+   } else if (of_reset_id == EMAC1_RESET) {
+   reset = SOCFPGA_RESET(EMAC1);
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+   } else {
+   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+   return;
+   }
+
+   clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+
+   /* Release the EMAC controller from reset */
+   socfpga_per_reset(reset, 0);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, &noc_fw_ocram_base->region0);
+   writel(0x1, &noc_fw_ocram_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, &pl310->pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#else
+int arch_early_init_r(void)
+{
+   return 0;
+}
+#endif
+
+/*
+ * This function looking the 1st encounter UART peripheral,
+ * and then return its offset of the dedicated/shared IO pin
+ * mux. offset value (zero and above).
+ */
+static int find_peripheral_uart(const void *blob,
+   int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr = 0;
+   fdt_size_t size;
+   const u32 *cell;
+   u3

[U-Boot] [PATCH v6 07/16] arm: socfpga: Add clock driver for Arria 10

[Ley Foon Tan]

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |3 +-
 arch/arm/mach-socfpga/clock_manager.c  |   10 +
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1096 
 arch/arm/mach-socfpga/include/mach/clock_manager.h |3 +
 .../include/mach/clock_manager_arria10.h   |  224 
 5 files changed, 1335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d81f003..c494930 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,7 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 8051995..cb6ae03 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -19,7 +19,12 @@ void cm_wait_for_lock(u32 mask)
u32 inter_val;
u32 retry = 0;
do {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(&clock_manager_base->inter) & mask;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   inter_val = readl(&clock_manager_base->stat) & mask;
+#endif
+   /* Wait for stable lock */
if (inter_val == mask)
retry++;
else
@@ -44,7 +49,12 @@ int set_cpu_clk_info(void)
 
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
gd->bd->bi_dsp_freq = 0;
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
return 0;
 }
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
new file mode 100644
index 000..482b854
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -0,0 +1,1096 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 eosc1_hz;
+static u32 cb_intosc_hz;
+static u32 f2s_free_hz;
+static u32 cm_l4_main_clk_hz;
+static u32 cm_l4_sp_clk_hz;
+static u32 cm_l4_mp_clk_hz;
+static u32 cm_l4_sys_free_clk_hz;
+
+struct mainpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 mpuclk;
+   u32 mpuclk_cnt;
+   u32 mpuclk_src;
+   u32 nocclk;
+   u32 nocclk_cnt;
+   u32 nocclk_src;
+   u32 cntr2clk_cnt;
+   u32 cntr3clk_cnt;
+   u32 cntr4clk_cnt;
+   u32 cntr5clk_cnt;
+   u32 cntr6clk_cnt;
+   u32 cntr7clk_cnt;
+   u32 cntr7clk_src;
+   u32 cntr8clk_cnt;
+   u32 cntr9clk_cnt;
+   u32 cntr9clk_src;
+   u32 cntr15clk_cnt;
+   u32 nocdiv_l4mainclk;
+   u32 nocdiv_l4mpclk;
+   u32 nocdiv_l4spclk;
+   u32 nocdiv_csatclk;
+   u32 nocdiv_cstraceclk;
+   u32 nocdiv_cspdbclk;
+};
+
+struct perpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 cntr2clk_cnt;
+   u32 cntr2clk_src;
+   u32 cntr3clk_cnt;
+   u32 cntr3clk_src;
+   u32 cntr4clk_cnt;
+   u32 cntr4clk_src;
+   u32 cntr5clk_cnt;
+   u32 cntr5clk_src;
+   u32 cntr6clk_cnt;
+   u32 cntr6clk_src;
+   u32 cntr7clk_cnt;
+   u32 cntr8clk_cnt;
+   u32 cntr8clk_src;
+   u32 cntr9clk_cnt;
+   u32 emacctl_emac0sel;
+   u32 emacctl_emac1sel;
+   u32 emacctl_emac2sel;
+   u32 gpiodiv_gpiodbclk;
+};
+
+struct alteragrp_cfg {
+   u32 nocclk;
+   u32 mpuclk;
+};
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
+{
+   if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
+(u32 *)cfg, cfg_len)) {
+   /* could not find required property */
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int of_get_input_clks(const void *blob, int node, u32 *val)
+{
+   *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
+   if (!*val)
+   return -EINVAL;
+
+   return 0;
+}
+
+static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
+ struct perpll_cfg *per_cfg,
+ 

[U-Boot] [PATCH v6 10/16] arm: socfpga: Add pinmux for Arria 10

[Ley Foon Tan]

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile  |  1 +
 arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +
 arch/arm/mach-socfpga/pinmux_arria10.c  | 96 +
 3 files changed, 114 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c494930..503b79f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -11,6 +11,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   pinmux_arria10.o\
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..563a3db
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#define PINMUX_UART0xD
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c 
b/arch/arm/mach-socfpga/pinmux_arria10.c
new file mode 100644
index 000..69d6a92
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux_arria10.c
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int do_pinctr_pin(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
+   if (!cell || len <= 0)
+   return -EFAULT;
+
+   debug("%p %d\n", cell, len);
+   for (; len > 0; len -= (2 * sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   return -EFAULT;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return -EINVAL;
+
+   node_name = fdt_get_name(blob, child, &len);
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name))
+   return do_pinctr_pin(blob, child, node_name);
+
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, &len);
+   }
+
+   return -EFAULT;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return -EFAULT;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return -EFAULT;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return -EFAULT;
+
+   return 0;
+}
-- 
1.8.2.3

___
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[U-Boot] [PATCH v6 12/16] arm: dts: Add dts and dtsi for Arria 10

[Ley Foon Tan]

Device tree files for Arria 10

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/socfpga_arria10.dtsi  | 869 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  38 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 481 
 4 files changed, 1389 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 68d2791..cc31ae9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb 
\
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb\
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..377700d
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,869 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   ethernet2 = &gmac2;
+   serial0 = &uart0;
+   serial1 = &uart1;
+   timer0 = &timer0;
+   timer1 = &timer1;
+   timer2 = &timer2;
+   timer3 = &timer3;
+   spi0 = &spi0;
+   spi1 = &spi1;
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <&L2>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <&L2>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <&intc>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clock

[U-Boot] [PATCH v6 09/16] arm: socfpga: Add sdram header file for Arria 10

[Ley Foon Tan]

Add sdram header file for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
new file mode 100644
index 000..1d7b7c1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
+#define _SOCFPGA_SDRAM_ARRIA10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   u32 caltiming5;
+   u32 caltiming6;
+   u32 caltiming7;
+   u32 caltiming8;
+   u32 caltiming9;
+   u32 caltiming10;
+   u32 dramaddrw;
+   u32 sideband0;
+   u32 sideband1;
+   u32 sideband2;
+   u32 sideband3;
+   u32 si

[U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Ley Foon Tan]

Add SPL support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/spl.c | 72 +
 1 file changed, 67 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 0064fc8..f4a3cdd 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -19,23 +19,32 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
unsigned long sdram_size;
unsigned long reg;
+   int ret;
 
/*
 * First C code to run. Clear fake OCRAM ECC first as SBE
@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
/* Put everything into reset but L4WD0. */
socfpga_per_reset_all();
/* Put FPGA bridges into reset too. */
-   socfpga_bridges_reset(1);
+   ret = socfpga_bridges_reset(1);
+   if (ret) {
+   printf("socfpga_bridges_reset() failed: %d\n", ret);
+   hang();
+   }
 
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 
/* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
-   socfpga_bridges_reset(0);
+   ret = socfpga_bridges_reset(0);
+   if (ret) {
+   printf("socfpga_bridges_reset() failed: %d\n", ret);
+   hang();
+   }
 
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
@@ -178,8 +197,51 @@ void board_init_f(ulong dummy)
hang();
}
 
-   socfpga_bridges_reset(1);
+   ret = socfpga_bridges_reset(1);
+   if (ret) {
+   printf("socfpga_bridges_reset() failed: %d\n", ret);
+   hang();
+   }
 
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   socfpga_reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   socfpga_watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   socfpga_reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
+#endif
-- 
1.8.2.3

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[U-Boot] [PATCH v6 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Ley Foon Tan]

Add config and defconfig for the Arria10 and update socfpga_common.h.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 configs/socfpga_arria10_defconfig   | 29 +++
 include/configs/socfpga_arria10_socdk.h | 66 +
 include/configs/socfpga_common.h| 21 ---
 3 files changed, 111 insertions(+), 5 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..46bda47
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..7ea780b
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,66 @@
+/*
+ *  Copyright (C) 2015-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Booting Linux */
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x4000
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* The rest of the configuration is shared */
+#include 
+
+#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 107c6d5..da7e4ad 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -32,9 +32,13 @@
 #define CONFIG_SYS_MALLOC_LEN  (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR   0x
 #define CONFIG_SYS_INIT_RAM_SIZE   0x1
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET  \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR\
@@ -101,13 +105,14 @@
 /*
  * FPGA Driver
  */
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT  1
 #endif
-
+#endif
 /*
  * L4 OSC1 Timer 0
  */
@@ -207,11 +212,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE-4
-#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK 100
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_CLK 1
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK 5000
 #endif
 #define CONFIG_CONS_INDEX

[U-Boot] [PATCH v3 2/3] doc: dtbinding: add pwm binding file

[Kever Yang]

This is a copy from kernel.

Signed-off-by: Kever Yang 
---

Changes in v3: None
Changes in v2: None

 doc/device-tree-bindings/pwm/pwm.txt | 69 
 1 file changed, 69 insertions(+)
 create mode 100644 doc/device-tree-bindings/pwm/pwm.txt

diff --git a/doc/device-tree-bindings/pwm/pwm.txt 
b/doc/device-tree-bindings/pwm/pwm.txt
new file mode 100644
index 000..8556263
--- /dev/null
+++ b/doc/device-tree-bindings/pwm/pwm.txt
@@ -0,0 +1,69 @@
+Specifying PWM information for devices
+==
+
+1) PWM user nodes
+-
+
+PWM users should specify a list of PWM devices that they want to use
+with a property containing a 'pwm-list':
+
+   pwm-list ::=  [pwm-list]
+   single-pwm ::=  
+   pwm-phandle : phandle to PWM controller node
+   pwm-specifier : array of #pwm-cells specifying the given PWM
+   (controller specific)
+
+PWM properties should be named "pwms". The exact meaning of each pwms
+property must be documented in the device tree binding for each device.
+An optional property "pwm-names" may contain a list of strings to label
+each of the PWM devices listed in the "pwms" property. If no "pwm-names"
+property is given, the name of the user node will be used as fallback.
+
+Drivers for devices that use more than a single PWM device can use the
+"pwm-names" property to map the name of the PWM device requested by the
+pwm_get() call to an index into the list given by the "pwms" property.
+
+The following example could be used to describe a PWM-based backlight
+device:
+
+   pwm: pwm {
+   #pwm-cells = <2>;
+   };
+
+   [...]
+
+   bl: backlight {
+   pwms = <&pwm 0 500>;
+   pwm-names = "backlight";
+   };
+
+Note that in the example above, specifying the "pwm-names" is redundant
+because the name "backlight" would be used as fallback anyway.
+
+pwm-specifier typically encodes the chip-relative PWM number and the PWM
+period in nanoseconds.
+
+Optionally, the pwm-specifier can encode a number of flags (defined in
+) in a third cell:
+- PWM_POLARITY_INVERTED: invert the PWM signal polarity
+
+Example with optional PWM specifier for inverse polarity
+
+   bl: backlight {
+   pwms = <&pwm 0 500 PWM_POLARITY_INVERTED>;
+   pwm-names = "backlight";
+   };
+
+2) PWM controller nodes
+---
+
+PWM controller nodes must specify the number of cells used for the
+specifier using the '#pwm-cells' property.
+
+An example PWM controller might look like this:
+
+   pwm: pwm@7000a000 {
+   compatible = "nvidia,tegra20-pwm";
+   reg = <0x7000a000 0x100>;
+   #pwm-cells = <2>;
+   };
-- 
1.9.1

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[U-Boot] [PATCH v3 3/3] dm: sanbox: pwm: add test for pwm_set_invert()

[Kever Yang]

Add test case for new interface set_invert().

Signed-off-by: Kever Yang 
---

Changes in v3: None
Changes in v2: None

 drivers/pwm/sandbox_pwm.c | 16 
 test/dm/pwm.c |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/pwm/sandbox_pwm.c b/drivers/pwm/sandbox_pwm.c
index c2ce974..50a35d9 100644
--- a/drivers/pwm/sandbox_pwm.c
+++ b/drivers/pwm/sandbox_pwm.c
@@ -21,6 +21,7 @@ struct sandbox_pwm_chan {
uint period_ns;
uint duty_ns;
bool enable;
+   bool polarity;
 };
 
 struct sandbox_pwm_priv {
@@ -56,9 +57,24 @@ static int sandbox_pwm_set_enable(struct udevice *dev, uint 
channel,
return 0;
 }
 
+static int sandbox_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity);
+{
+   struct sandbox_pwm_priv *priv = dev_get_priv(dev);
+   struct sandbox_pwm_chan *chan;
+
+   if (channel >= NUM_CHANNELS)
+   return -ENOSPC;
+   chan = &priv->chan[channel];
+   chan->polarity = polarity;
+
+   return 0;
+}
+
 static const struct pwm_ops sandbox_pwm_ops = {
.set_config = sandbox_pwm_set_config,
.set_enable = sandbox_pwm_set_enable,
+   .set_invert = sandbox_pwm_set_invert,
 };
 
 static const struct udevice_id sandbox_pwm_ids[] = {
diff --git a/test/dm/pwm.c b/test/dm/pwm.c
index 7bdc75a..f1e38c7 100644
--- a/test/dm/pwm.c
+++ b/test/dm/pwm.c
@@ -23,6 +23,7 @@ static int dm_test_pwm_base(struct unit_test_state *uts)
ut_assertok(pwm_set_enable(dev, 1, true));
ut_assertok(pwm_set_enable(dev, 2, true));
ut_asserteq(-ENOSPC, pwm_set_enable(dev, 3, true));
+   ut_assertok(pwm_set_invert(dev, 0, true));
 
ut_assertok(uclass_get_device(UCLASS_PWM, 1, &dev));
ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PWM, 2, &dev));
-- 
1.9.1

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[U-Boot] [PATCH v6 15/16] arm: socfpga: Add board files for the Arria10

[Ley Foon Tan]

Add support for the Arria10 SoCDK.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c |  7 +++
 3 files changed, 32 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..8516633
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
1.8.2.3

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[U-Boot] [PATCH v6 16/16] arm: socfpga: Enable build for Arria 10

[Ley Foon Tan]

Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Kconfig  | 10 +
 arch/arm/mach-socfpga/Makefile | 46 ++
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9bfee04..b36ffb1 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -37,6 +37,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -49,6 +52,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -94,6 +101,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -106,6 +114,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -119,6 +128,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4ce8eac..41b779c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,28 +2,48 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2017 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
-  fpga_manager.o board.o
+obj-y  += board.o
+obj-y  += clock_manager.o
+obj-y  += fpga_manager.o
+obj-y  += misc.o
+obj-y  += reset_manager.o
+obj-y  += timer.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
-   pinmux_arria10.o\
-   misc_arria10.o  \
-   reset_manager_arria10.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += clock_manager_gen5.o
+obj-y  += misc_gen5.o
+obj-y  += reset_manager_gen5.o
+obj-y  += scan_manager.o
+obj-y  += system_manager_gen5.o
+obj-y  += wrap_pll_config.o
+endif
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += clock_manager_arria10.o
+obj-y  += misc_arria10.o
+obj-y  += pinmux_arria10.o
+obj-y  += reset_manager_arria10.o
+endif
 
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += freeze_controller.o
+obj-y  += wrap_iocsr_config.o
+obj-y  += wrap_pinmux_config.o
+obj-y  += wrap_sdram_config.o
+endif
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o \
-  misc_gen5.o system_manager_gen5.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
-- 
1.8.2.3

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Re: [U-Boot] [PATCH v5 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Marek Vasut]

On 04/19/2017 10:58 AM, Ley Foon Tan wrote:
> On Wed, Apr 19, 2017 at 4:53 PM, Marek Vasut  wrote:
>> On 04/19/2017 10:49 AM, Ley Foon Tan wrote:
>>> On Wed, Apr 19, 2017 at 4:38 PM, Marek Vasut  wrote:
 On 04/19/2017 05:32 AM, Ley Foon Tan wrote:
> On Tue, Apr 18, 2017 at 6:58 PM, Marek Vasut  wrote:
>> On 04/18/2017 05:12 AM, Ley Foon Tan wrote:
>>> On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut  wrote:
 On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut  wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Add config and defconfig for the Arria10 and update 
>>> socfpga_common.h.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Signed-off-by: Ley Foon Tan 
>>
>> [...]
>>
>>> @@ -298,7 +306,10 @@ unsigned int 
>>> cm_get_qspi_controller_clk_hz(void);
>>>   */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
>>> -#define CONFIG_SPL_MAX_SIZE  (64 * 1024)
>>> +#define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SPL_BOARD_INIT
>>
>> This should be in Kconfig and selected by 
>> arch/arm/mach-socfpga/Kconfig
>> entry for A10
> We can't use Kconfig method for CONFIG_SPL_BOARD_INIT, it is not a
> Kconfig parameter now.

 OK. You can turn it into one, although that is out of the scope of this
 patchset.
>>> Okay, I will add SPL_BOARD_INIT to  arch/arm/mach-socfpga/Kconfig and
>>> select it for Arria 10.
>>
>> Do it in a separate patch please . Also, there's a script for turning
>> symbols into Kconfig symbols in u-boot.
> I think we don't need script if just add Kconfig to
> arch/arm/mach-socfpga/Kconfig, unless
> you want me add to common/spl/Kconfig and move this option to kconfig
> for all architectures.

 That's what I had in mind, but please do it outside of this patchset, so
 this one can go in.
>>> For this A10 patchset, I will add it to  arch/arm/mach-socfpga/Kconfig
>>> first and I will send another patchset to add SPL_BOARD_INIT to
>>> common/spl/Kconfig on top of this patchset.
>>
>> No, please don't, this will only introduce inconsistency.
>>
>>> So, we can get this patchset to get in first because move
>>> SPL_BOARD_INIT to kconfig for all architectures might take longer time
>>> to review . What do you think?
>>
>> Just keep it as is now and ev. submit a separate patch which converts
>> that to Kconfig later.
> Okay, will keep SPL_BOARD_INIT in include/configs/socfpga_common.h as
> now first and send separate patchset to convert it to kconfig later.

Super, thanks

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v3 1/3] power: regulator: pwm: support pwm polarity setting

[Kever Yang]

The latest kernel PWM drivers enable the polarity settings. When system
run from U-Boot to kerenl, if there are differences in polarity set or
duty cycle, the PMW will re-init:
  close -> set polarity and duty cycle -> enable the PWM.
The power supply controled by pwm regulator may have voltage shaking,
which lead to the system not stable.

Signed-off-by: Elaine Zhang 
Signed-off-by: Kever Yang 
---

Changes in v3:
- use bool type for polarity
- add sambox test

Changes in v2:
- use pwm_set_invert() instead of pwm_set_init()
- add comment for polarity

 drivers/power/regulator/pwm_regulator.c | 16 ++--
 drivers/pwm/pwm-uclass.c| 10 ++
 drivers/pwm/rk_pwm.c| 17 -
 include/pwm.h   | 19 +++
 4 files changed, 59 insertions(+), 3 deletions(-)

diff --git a/drivers/power/regulator/pwm_regulator.c 
b/drivers/power/regulator/pwm_regulator.c
index 4875238..a6c9fcc 100644
--- a/drivers/power/regulator/pwm_regulator.c
+++ b/drivers/power/regulator/pwm_regulator.c
@@ -24,6 +24,12 @@ struct pwm_regulator_info {
int pwm_id;
/* the period of one PWM cycle */
int period_ns;
+   /*
+* the polarity of one PWM
+* 0: normal polarity
+* 1: inverted polarity
+*/
+   bool polarity;
struct udevice *pwm;
/* initialize voltage of regulator */
unsigned int init_voltage;
@@ -49,7 +55,7 @@ static int pwm_voltage_to_duty_cycle_percentage(struct 
udevice *dev, int req_uV)
int max_uV = priv->max_voltage;
int diff = max_uV - min_uV;
 
-   return 100 - (((req_uV * 100) - (min_uV * 100)) / diff);
+   return ((req_uV * 100) - (min_uV * 100)) / diff;
 }
 
 static int pwm_regulator_get_voltage(struct udevice *dev)
@@ -67,6 +73,12 @@ static int pwm_regulator_set_voltage(struct udevice *dev, 
int uvolt)
 
duty_cycle = pwm_voltage_to_duty_cycle_percentage(dev, uvolt);
 
+   ret = pwm_set_invert(priv->pwm, priv->pwm_id, priv->polarity);
+   if (ret) {
+   dev_err(dev, "Failed to init PWM\n");
+   return ret;
+   }
+
ret = pwm_set_config(priv->pwm, priv->pwm_id,
(priv->period_ns / 100) * duty_cycle, priv->period_ns);
if (ret) {
@@ -97,9 +109,9 @@ static int pwm_regulator_ofdata_to_platdata(struct udevice 
*dev)
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
-   /* TODO: pwm_id here from device tree if needed */
 
priv->period_ns = args.args[1];
+   priv->polarity = args.args[2];
 
priv->init_voltage = fdtdec_get_int(blob, node,
"regulator-init-microvolt", -1);
diff --git a/drivers/pwm/pwm-uclass.c b/drivers/pwm/pwm-uclass.c
index c2200af..69051fe 100644
--- a/drivers/pwm/pwm-uclass.c
+++ b/drivers/pwm/pwm-uclass.c
@@ -9,6 +9,16 @@
 #include 
 #include 
 
+int pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
+{
+   struct pwm_ops *ops = pwm_get_ops(dev);
+
+   if (!ops->set_invert)
+   return -ENOSYS;
+
+   return ops->set_invert(dev, channel, polarity);
+}
+
 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
   uint duty_ns)
 {
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 9254f5b..f3b2f76 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -21,8 +21,22 @@ DECLARE_GLOBAL_DATA_PTR;
 struct rk_pwm_priv {
struct rk3288_pwm *regs;
ulong freq;
+   uint enable_conf;
 };
 
+static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
+{
+   struct rk_pwm_priv *priv = dev_get_priv(dev);
+
+   debug("%s: polarity=%u\n", __func__, polarity);
+   if (polarity)
+   priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
+   else
+   priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
+
+   return 0;
+}
+
 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
 uint duty_ns)
 {
@@ -32,7 +46,7 @@ static int rk_pwm_set_config(struct udevice *dev, uint 
channel, uint period_ns,
 
debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
-   PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
+   PWM_CONTINUOUS | priv->enable_conf |
RK_PWM_DISABLE,
®s->ctrl);
 
@@ -83,6 +97,7 @@ static int rk_pwm_probe(struct udevice *dev)
 }
 
 static const struct pwm_ops rk_pwm_ops = {
+   .set_invert = rk_pwm_set_invert,
.set_config = rk_pwm_set_config,
.set_enable = rk_pwm_set_enable,
 };
diff --git a/include/pwm.h b/include/pwm.h
index 851915e..ebee227 100644
--- a/include/pwm.h
+++ b/include/pwm.h
@@ -34,6 +34,15 @@ struct pw

Re: [U-Boot] [PATCH v6 00/16] Add Intel Arria 10 SoC support

[Marek Vasut]

On 04/19/2017 11:29 AM, Ley Foon Tan wrote:
> This is the 6th version of patchset to adds support for Intel Arria 10 SoC.
> This is initial patchset enables the basic support for Arria 10 and other
> features will come after this.
> 
> There is only one minor change in patch #5.
> 
> This series is rebased on top of 
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git.
> 
> v5 -> v6 changes:
> -
> -  macros sorted by address
> 

OK, waiting for final review by Dinh ...

-- 
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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Heiko Schocher]

Hello Marek,

Am 19.04.2017 um 10:43 schrieb Marek Vasut:

On 04/19/2017 07:29 AM, Heiko Schocher wrote:

Hello Tom,

added Lukasz, Marek and Felipe,

Am 18.04.2017 um 00:22 schrieb Tom Rini:

Hey all,

It's release day and v2017.05-rc2 is out.  I think my patchwork queue is
looking good currently.  I have some outstanding removal patches to take
from Masahiro related to architectures that I removed as promised.  The
release is bigger than I really wanted, but since I was on vacation for
most of the normal -rc1 window, stuff came in that would have come in
then now, instead.  Things are on track for -rc3 on the 1st.


My weekly dfu test on the siemens smartweb board failed with
current HEAD.

I started an automated git bisect with tbot, and found:

2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect visualize
2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
842778a091047b0c868efa12229633959f711152
Author: Felipe Balbi 
Date:   Wed Feb 22 17:12:40 2017 +0200
 usb: gadget: g_dnl: only set iSerialNumber if we have a serial#

 We don't want to claim that we support a serial number string and
 later return nothing. Because of that, if g_dnl_serial is an empty
 string, let's skip setting iSerialNumber to a valid number.

 Signed-off-by: Felipe Balbi 
hs@pollux [ 7:24:30] ttbott>
2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start

[...]


Any ideas?


Is your board setting up the serial number with g_dnl_set_serialnumber()
correctly ?


Hmm.. good question ... its done here:

http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/common/factoryset.c;h=6c869ed2b035a0e9f840e1f6f960fe0e6ac824e5;hb=f6c1df44b815a08585e7fd3805a1db51a5955d09#l313

but may this does not work correct and now pops up.

I try to find out more, thanks for the hint!

bye,
Heiko
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH 2/4] dm: core: Add DM_FLAG_PRE_OS_FINALIZE flag

[Stefan Roese]

Hi Simon,

On 09.04.2017 21:28, Simon Glass wrote:

Hi Stefan,

On 6 April 2017 at 07:29, Stefan Roese  wrote:

This new flag can be added to DM device drivers, which need to do some
final configuration before U-Boot exits and the OS (e.g. Linux) is
started. The remove functions of those drivers will get called at
this stage to do these last-stage configuration steps.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 drivers/core/device-remove.c | 17 -
 include/dm/device.h  | 11 ++-
 2 files changed, 22 insertions(+), 6 deletions(-)


Reviewed-by: Simon Glass 

You could perhaps have a separate patch to move the code into
flags_remove(), but I suppose it isn't important.

nit below.



diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 8b46f3343e..390be5a0d8 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -148,6 +148,16 @@ void device_free(struct udevice *dev)
devres_release_probe(dev);
 }

+static int flags_remove(uint flags, uint drv_flags)


Can this be bool, and return true/false?


I'm not a big fan of bool but I've no hard feelings here. I'll change
this if you prefer it this way in v2.


+{
+   if ((flags & DM_REMOVE_NORMAL) ||
+   (flags & (drv_flags &
+ (DM_FLAG_ACTIVE_DMA | DM_FLAG_PRE_OS_FINALIZE


What do you think about OS_PREPARE instead? It doesn't really finalize
the OS...


Much better, thanks. Will change in v2.

Thanks,
Stefan
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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Marek Vasut]

On 04/19/2017 11:46 AM, Heiko Schocher wrote:
> Hello Marek,
> 
> Am 19.04.2017 um 10:43 schrieb Marek Vasut:
>> On 04/19/2017 07:29 AM, Heiko Schocher wrote:
>>> Hello Tom,
>>>
>>> added Lukasz, Marek and Felipe,
>>>
>>> Am 18.04.2017 um 00:22 schrieb Tom Rini:
 Hey all,

 It's release day and v2017.05-rc2 is out.  I think my patchwork
 queue is
 looking good currently.  I have some outstanding removal patches to
 take
 from Masahiro related to architectures that I removed as promised.  The
 release is bigger than I really wanted, but since I was on vacation for
 most of the normal -rc1 window, stuff came in that would have come in
 then now, instead.  Things are on track for -rc3 on the 1st.
>>>
>>> My weekly dfu test on the siemens smartweb board failed with
>>> current HEAD.
>>>
>>> I started an automated git bisect with tbot, and found:
>>>
>>> 2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect
>>> visualize
>>> 2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
>>> 842778a091047b0c868efa12229633959f711152
>>> Author: Felipe Balbi 
>>> Date:   Wed Feb 22 17:12:40 2017 +0200
>>>  usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
>>>
>>>  We don't want to claim that we support a serial number string and
>>>  later return nothing. Because of that, if g_dnl_serial is an empty
>>>  string, let's skip setting iSerialNumber to a valid number.
>>>
>>>  Signed-off-by: Felipe Balbi 
>>> hs@pollux [ 7:24:30] ttbott>
>>> 2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
>>> 2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start
> [...]
>>>
>>> Any ideas?
>>
>> Is your board setting up the serial number with g_dnl_set_serialnumber()
>> correctly ?
> 
> Hmm.. good question ... its done here:
> 
> http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/common/factoryset.c;h=6c869ed2b035a0e9f840e1f6f960fe0e6ac824e5;hb=f6c1df44b815a08585e7fd3805a1db51a5955d09#l313
> 
> 
> but may this does not work correct and now pops up.
> 
> I try to find out more, thanks for the hint!

Just check if you're not passing in NULL or empty string, that might be
it. Otherwise the USB code is botched.

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH] ehci-ppc4xx: Prepare for usage of readl()/writel() accessors

[Stefan Roese]

On 17.04.2017 18:13, Alexey Brodkin wrote:

We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.

Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
>8---
  CC  drivers/usb/host/ehci-ppc4xx.o
drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 
'readl' [-Wimplicit-function-declaration]
   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
   ^
>8---

Signed-off-by: Alexey Brodkin 
Cc: Tom Rini 
Cc: Marek Vasut 
Cc: Stefan Roese 
---
 drivers/usb/host/ehci-ppc4xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 9aee3ff786cb..9d235776428e 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -8,6 +8,7 @@
  */
 #include 
 #include 
+#include 

 #include "ehci.h"




Alexey, thanks for looking into this:

Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/2] rockchip: dts: rk3399: sync with kernel dts

[Kever Yang]

Hi Simon,

Some change of the patch is on list and I will update the firefly dts

for there are some dts properties order change. I will send out version 2.

Thanks,

- Kever
On 04/17/2017 03:31 AM, Simon Glass wrote:

On 12 April 2017 at 03:49, Kever Yang  wrote:

The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.


Could you also include which kernel version or commit?


Signed-off-by: Kever Yang 
---

  arch/arm/dts/rk3399.dtsi | 1288 +-
  include/dt-bindings/pinctrl/rockchip.h   |   35 +-
  include/dt-bindings/power/rk3399-power.h |   53 ++
  3 files changed, 1172 insertions(+), 204 deletions(-)
  create mode 100644 include/dt-bindings/power/rk3399-power.h

Acked-by: Simon Glass 




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[U-Boot] [PATCH v2 1/2] rockchip: dts: rk3399: sync with kernel dts

[Kever Yang]

The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.

Signed-off-by: Kever Yang 
Acked-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3399.dtsi | 1274 +-
 include/dt-bindings/pinctrl/rockchip.h   |   35 +-
 include/dt-bindings/power/rk3399-power.h |   53 ++
 3 files changed, 1157 insertions(+), 205 deletions(-)
 create mode 100644 include/dt-bindings/power/rk3399-power.h

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index a51015f..5d37a1e 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -9,6 +9,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #define USB_CLASS_HUB  9
 
 / {
@@ -19,6 +21,15 @@
#size-cells = <2>;
 
aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &i2c7;
+   i2c8 = &i2c8;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -26,7 +37,6 @@
serial4 = &uart4;
mmc0 = &sdhci;
mmc1 = &sdmmc;
-   i2c0 = &i2c0;
};
 
cpus {
@@ -110,6 +120,16 @@
};
};
 
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts = ;
+   };
+
+   pmu_a72 {
+   compatible = "arm,cortex-a72-pmu";
+   interrupts = ;
+   };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -117,10 +137,11 @@
 
timer {
compatible = "arm,armv8-timer";
-   interrupts = ,
-,
-,
-;
+   interrupts = ,
+,
+,
+;
+   arm,no-tick-in-suspend;
};
 
xin24m: xin24m {
@@ -139,8 +160,8 @@
dmac_bus: dma-controller@ff6d {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6d 0x0 0x4000>;
-   interrupts = ,
-;
+   interrupts = ,
+;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC0_PERILP>;
clock-names = "apb_pclk";
@@ -149,24 +170,92 @@
dmac_peri: dma-controller@ff6e {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6e 0x0 0x4000>;
-   interrupts = ,
-;
+   interrupts = ,
+;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1_PERILP>;
clock-names = "apb_pclk";
};
};
 
+   pcie0: pcie@f800 {
+   compatible = "rockchip,rk3399-pcie";
+   reg = <0x0 0xf800 0x0 0x200>,
+ <0x0 0xfd00 0x0 0x100>;
+   reg-names = "axi-base", "apb-base";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   aspm-no-l0s;
+   bus-range = <0x0 0x1>;
+   clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+   clock-names = "aclk", "aclk-perf",
+ "hclk", "pm";
+   interrupts = ,
+,
+;
+   interrupt-names = "sys", "legacy", "client";
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+   <0 0 0 2 &pcie0_intc 1>,
+   <0 0 0 3 &pcie0_intc 2>,
+   <0 0 0 4 &pcie0_intc 3>;
+   linux,pci-domain = <0>;
+   max-link-speed = <1>;
+   msi-map = <0x0 &its 0x0 0x1000>;
+   phys = <&pcie_phy>;
+   phy-names = "pcie-phy";
+   ranges = <0x8300 0x0 0xfa00 0x0 0xfa00 0x0 0x60
+ 0x8100 0x0 0xfa60 0x0 0xfa60 0x0 
0x10>;
+   resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
+ 

[U-Boot] [PATCH v2 2/2] rockchip: dts: add rk3399-firefly dts

[Kever Yang]

Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/

This patch add basic node for the board and make it able to bring
up.

Peripheral/interfaces on board:
- usb hub which connect to ehci controller;
- UART2 debug
- eMMC
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP

Signed-off-by: Kever Yang 
---

Changes in v2:
- dts properity order update

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/rk3399-firefly.dts | 660 
 2 files changed, 661 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-firefly.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7378c88..2dfe85f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3399-evb.dtb \
+   rk3399-firefly.dtb \
rk3399-puma.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
new file mode 100644
index 000..edf48fb
--- /dev/null
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-sdram-ddr3-1333.dtsi"
+
+/ {
+   model = "Firefly-RK3399 Board";
+   compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+   pwms = <&pwm0 0 25000 0>;
+   brightness-levels = <
+ 0   1   2   3   4   5   6   7
+ 8   9  10  11  12  13  14  15
+16  17  18  19  20  21  22  23
+24  25  26  27  28  29  30  31
+32  33  34  35  36  37  38  39
+40  41  42  43  44  45  46  47
+48  49  50  51  52  53  54  55
+56  57  58  59  60  61  62  63
+64  65  66  67  68  69  70  71
+72  73  74  75  76  77  78  79
+80  81  82  83  84  85  86  87
+88  89  90  91  92  93  94  95
+96  97  98  99 100 101 102 103
+   104 105 106 107 108 109 110 111
+   112 113 114 115 116 117 118 119
+   120 121 122 123 124 125 126 127
+   128 129 130 131 132 133 134 135
+   136 137 138 139 140 141 142 143
+   144 145 146 147 148 149 150 151
+   152 153 154 155 156 157 158 159
+   160 161 162 163 164 165 166 167
+   168 169 170 171 172 173 174 175
+   176 177 178 179 180 181 182 183
+   184 185 186 187 188 189 190 191
+   192 193 194 195 196 197 198 199
+   200 201 202 203 204 205 206 207
+   208 209 210 211 212 213 214 215
+   216 217 218 219 220 221 222 223
+   224 225 226 227 228 229 230 231
+   232 233 234 235 236 237 238 239
+   240 241 242 243 244 245 246 247
+   248 249 250 251 252 253 254 255>;
+   default-brightness-level = <200>;
+   };
+
+   clkin_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "clkin_gmac";
+   #clock-cells = <0>;
+   };
+
+   rt5640-sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,name = "rockchip,rt5640-codec";
+   simple-audio-card,format = "i2s";
+   simple-audio-card,mclk-fs = <256>;
+   simple-audio-card,widgets =
+   "Microphone", "Mic Jack",
+   "Headphone", "Headphone Jack";
+   simple-audio-card,routing =
+   "Mic Jack", "MICBIAS1",
+   "IN1P", "Mic Jack",
+   "Headphone Jack", "HPOL",
+   "Headphone Jack", "HPOR";
+
+   simple-audio-card,cpu {
+   sound-dai = <&i2s1>;
+   };
+
+   simple-audio-card,codec {
+   sound-dai = <&rt5640>;
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <&rk808 1>;
+   clock

[U-Boot] [PATCH] fix: mvebu_ comphy: Update COMPHY sequence number

[kostap]

From: Konstantin Porotchkin 

Use local static counter for maintaining the COMPHY chip-ID
upon its initialization.
The dev->seq originally used as the COMPHY chip-ID depends
on the device tree scan order and produces wrong results
that breaks the deficated PHYs init flow, which in turn
breaks the USB support.

Change-Id: I4e3f7ec36590a7f95dc94d9269a3c47fb708c4a9
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Igal Liberman 
Cc: Stefan Chulski 
Cc: Nadav Haklai 
---
 drivers/phy/marvell/comphy_core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/marvell/comphy_core.c 
b/drivers/phy/marvell/comphy_core.c
index caa1928..7729e4b 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -113,6 +113,7 @@ static int comphy_probe(struct udevice *dev)
int subnode;
int lane;
int last_idx = 0;
+   static int current_idx;
 
/* Save base addresses for later use */
chip_cfg->comphy_base_addr = (void *)dev_get_addr_index(dev, 0);
@@ -175,7 +176,7 @@ static int comphy_probe(struct udevice *dev)
}
 
/* Save comphy index for MultiCP devices (A8K) */
-   chip_cfg->comphy_index = dev->seq;
+   chip_cfg->comphy_index = current_idx++;
/* PHY power UP sequence */
chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
/* PHY print SerDes status */
-- 
2.7.4

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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Heiko Schocher]

Hello Marek,

Am 19.04.2017 um 11:51 schrieb Marek Vasut:

On 04/19/2017 11:46 AM, Heiko Schocher wrote:

Hello Marek,

Am 19.04.2017 um 10:43 schrieb Marek Vasut:

On 04/19/2017 07:29 AM, Heiko Schocher wrote:

Hello Tom,

added Lukasz, Marek and Felipe,

Am 18.04.2017 um 00:22 schrieb Tom Rini:

Hey all,

It's release day and v2017.05-rc2 is out.  I think my patchwork
queue is
looking good currently.  I have some outstanding removal patches to
take
from Masahiro related to architectures that I removed as promised.  The
release is bigger than I really wanted, but since I was on vacation for
most of the normal -rc1 window, stuff came in that would have come in
then now, instead.  Things are on track for -rc3 on the 1st.


My weekly dfu test on the siemens smartweb board failed with
current HEAD.

I started an automated git bisect with tbot, and found:

2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect
visualize
2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
842778a091047b0c868efa12229633959f711152
Author: Felipe Balbi 
Date:   Wed Feb 22 17:12:40 2017 +0200
  usb: gadget: g_dnl: only set iSerialNumber if we have a serial#

  We don't want to claim that we support a serial number string and
  later return nothing. Because of that, if g_dnl_serial is an empty
  string, let's skip setting iSerialNumber to a valid number.

  Signed-off-by: Felipe Balbi 
hs@pollux [ 7:24:30] ttbott>
2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start

[...]


Any ideas?


Is your board setting up the serial number with g_dnl_set_serialnumber()
correctly ?


Hmm.. good question ... its done here:

http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/common/factoryset.c;h=6c869ed2b035a0e9f840e1f6f960fe0e6ac824e5;hb=f6c1df44b815a08585e7fd3805a1db51a5955d09#l313


but may this does not work correct and now pops up.

I try to find out more, thanks for the hint!


Just check if you're not passing in NULL or empty string, that might be
it. Otherwise the USB code is botched.


Hmm... OK, on the smartweb board there is no factory set, so never
calling g_dnl_set_serialnumber()

:-(

why did this worked before commit 842778a091?

So, I added for a fast dirty test:

diff --git a/board/siemens/smartweb/smartweb.c 
b/board/siemens/smartweb/smartweb.c
index 78a7946..01a3dd2 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -34,6 +34,7 @@
 #ifndef CONFIG_DM_ETH
 # include 
 #endif
+#include 

 DECLARE_GLOBAL_DATA_PTR;

@@ -265,3 +266,17 @@ U_BOOT_DEVICE(at91sam9260_serial) = {
.name   = "serial_atmel",
.platdata = &at91sam9260_serial_plat,
 };
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+   printf("%s: *\n", __func__);
+   g_dnl_set_serialnumber("0123456789");
+
+   return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+   return 0;
+}

Now I see this printf:
(also enabled debug in ./drivers/usb/gadget/g_dnl.c)

dfu 0 nand 0
using id 'nand0,4'
g_dnl_register: g_dnl_driver.name = usb_dnl_dfu
g_dnl_bind: gadget: 0x23adf6c0 cdev: 0x23b262d0
g_dnl_bind_fixup: *
g_dnl_do_config: configuration: 0x23b263c0 composite dev: 0x23b262d0
g_dnl_bind: calling usb_gadget_connect for controller 'at91_udc'

but result is the same:
# ./src/dfu-util -l
dfu-util 0.7

Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2012 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-u...@lists.gnumonks.org
tb_ctrl: Found DFU: [0908:02d2] ver=, devnum=0, cfg=1, intf=0, alt=0,
name="Linux", serial="UNDEFINED"

reverting commit 842778a091 and it works as before ... console
output for this case:

./src/dfu-util -l
dfu-util 0.7

Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2012 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-u...@lists.gnumonks.org
tb_ctrl: Found DFU: [0908:02d2] ver=, devnum=0, cfg=1, intf=0, alt=0,
name="Linux", serial="0123456789"

Ok, before commit 842778a091 is in mainline I had the follwoing output:

# tb_ctrl: ./src/dfu-util -l
# tb_ctrl: dfu-util 0.7

Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2012 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-u...@lists.gnumonks.org

Found DFU: [0908:02d2] ver=0212, devnum=0, cfg=1, intf=0, alt=0,
name="Linux", serial=""

serial is an empty string ... It seems to me, that commit 842778a091
broke here something fundamental ...

Hmm ... looking into drivers/usb/gadget/g_dnl.c g_dnl_bind()

if (strlen(g_dnl_serial)) {

is *before* g_dnl_bind_fixup() is called ... ?

Yup, with patch:

diff --git a/drivers/us

Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Lukasz Majewski]

Hi Heiko,

> Hello Tom,
> 
> added Lukasz, Marek and Felipe,
> 
> Am 18.04.2017 um 00:22 schrieb Tom Rini:
> > Hey all,
> >
> > It's release day and v2017.05-rc2 is out.  I think my patchwork
> > queue is looking good currently.  I have some outstanding removal
> > patches to take from Masahiro related to architectures that I
> > removed as promised.  The release is bigger than I really wanted,
> > but since I was on vacation for most of the normal -rc1 window,
> > stuff came in that would have come in then now, instead.  Things
> > are on track for -rc3 on the 1st.
> 
> My weekly dfu test on the siemens smartweb board failed with
> current HEAD.
> 
> I started an automated git bisect with tbot, and found:
> 
> 2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect
> visualize 2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
> 842778a091047b0c868efa12229633959f711152 Author: Felipe Balbi
>  Date:   Wed Feb 22 17:12:40 2017 +0200
>  usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
> 
>  We don't want to claim that we support a serial number string and
>  later return nothing. Because of that, if g_dnl_serial is an
> empty string, let's skip setting iSerialNumber to a valid number.

This change was added recently to DFU tree. It seemed like the one,
which clean up things.

Moreover, I tested it on the "old" set of DFU tests (however, those
tests are not the USB compliance test suite).

Heiko, could you paste the error output? (from the host PC and the
board)?

> 
>  Signed-off-by: Felipe Balbi 
> hs@pollux [ 7:24:30] ttbott>
> 2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
> 2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start
> # bad: [f6c1df44b815a08585e7fd3805a1db51a5955d09] Prepare v2017.05-rc2
> git bisect bad f6c1df44b815a08585e7fd3805a1db51a5955d09
> # good: [9963890b8be1d208035945abc5ba9f77637b6542] libfdt: fix build
> with Python 3 git bisect good 9963890b8be1d208035945abc5ba9f77637b6542
> # good: [af1b7286d8b2712cff5779d8a1565afed9d9d8e6] Merge branch
> 'master' of git://git.denx.de/u-boot-mmc git bisect good
> af1b7286d8b2712cff5779d8a1565afed9d9d8e6 # bad:
> [3fea95369850987de15a2a0ac009d05e13b90246] Merge branch 'master' of
> git://git.denx.de/u-boot-video git bisect bad
> 3fea95369850987de15a2a0ac009d05e13b90246 # good:
> [c1a16c3ab541c014b029b42cc27cae496107e170] Merge branch 'master' of
> git://git.denx.de/u-boot-socfpga git bisect good
> c1a16c3ab541c014b029b42cc27cae496107e170 # bad:
> [fbeb33752999e7317113199ef89873d6b6916814] buildman: Translate more
> strings to latin-1 git bisect bad
> fbeb33752999e7317113199ef89873d6b6916814 # bad:
> [b7bf4a95922c3e1a4974aa34ebb714ac2eb89937] usb: dwc3: ensure
> consistent types for dwc3_flush_cache git bisect bad
> b7bf4a95922c3e1a4974aa34ebb714ac2eb89937 # good:
> [12d0b8f5f07b76d7447d60f7528d578233553909] usb: gadget: g_dnl: hold
> maximum string descriptor git bisect good
> 12d0b8f5f07b76d7447d60f7528d578233553909 # bad:
> [207835b13feeae15db074d89352a4e5379a4] usb: gadget: g_dnl: don't
> set iProduct nor iSerialNumber git bisect bad
> 207835b13feeae15db074d89352a4e5379a4 # bad:
> [842778a091047b0c868efa12229633959f711152] usb: gadget: g_dnl: only
> set iSerialNumber if we have a serial# git bisect bad
> 842778a091047b0c868efa12229633959f711152 # first bad commit:
> [842778a091047b0c868efa12229633959f711152] usb: gadget: g_dnl: only
> set iSerialNumber if we have a serial# hs@pollux [ 7:24:31] ttbott>
> 
> Any ideas?
> 
> bye,
> Heiko




Best regards,

Lukasz Majewski

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH] spl: dfu: compilation fixes for spl-dfu

[Lukasz Majewski]

Hi Ravi,

Please add u-boot mailing list to CC, when sending patches.

> This patch fixes the compilation error
> common/cli_hush.c:3349: undefined reference to 'realloc_simple'
> 
> The dfu does not depend on HUSH_PARSER.
> The dfu, fastboot uses run_command(), it is
> part of cli.c and use cli_simple_run_command().
> 
> Signed-off-by: Ravi Babu 
> ---
>  common/Makefile | 1 -
>  common/cli.c| 2 +-
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/common/Makefile b/common/Makefile
> index bcd2486..dc5cb1d 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -90,7 +90,6 @@ endif # !CONFIG_SPL_BUILD
>  
>  ifdef CONFIG_SPL_BUILD
>  obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o
> -obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
>  obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
>  obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
>  obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
> diff --git a/common/cli.c b/common/cli.c
> index a433ef2..3dd4c2b 100644
> --- a/common/cli.c
> +++ b/common/cli.c
> @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  int run_command(const char *cmd, int flag)
>  {
> -#ifndef CONFIG_HUSH_PARSER
> +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_HUSH_PARSER)
>   /*
>* cli_run_command can return 0 or 1 for success, so clean up
>* its result.

So for the initial support of the DFU in SPL you did not needed the
HUSH parser.

What is the motivation to enable it now? Enabling the HUSH in SPL
should make the binary even bigger - hence it is counterintuitive. 


Best regards,

Lukasz Majewski

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH] spl: dfu: compilation fixes for spl-dfu

[B, Ravi]

Hi Lukasz

>> 
>> diff --git a/common/Makefile b/common/Makefile index bcd2486..dc5cb1d 
>> 100644
>> --- a/common/Makefile
>> +++ b/common/Makefile
>> @@ -90,7 +90,6 @@ endif # !CONFIG_SPL_BUILD
>>  
>>  ifdef CONFIG_SPL_BUILD
>>  obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o
>> -obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
>>  obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
>>  obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
>>  obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o diff --git 
>> a/common/cli.c b/common/cli.c index a433ef2..3dd4c2b 100644
>> --- a/common/cli.c
>> +++ b/common/cli.c
>> @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
>>   */
>>  int run_command(const char *cmd, int flag)  { -#ifndef 
>> CONFIG_HUSH_PARSER
>> +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_HUSH_PARSER)
>>  /*
>>   * cli_run_command can return 0 or 1 for success, so clean up
>>   * its result.

>So for the initial support of the DFU in SPL you did not needed the HUSH 
>parser.

>What is the motivation to enable it now? Enabling the HUSH in SPL should make 
>the binary even bigger - hence it is counterintuitive. 

The CONFIG_HUSH_PARSER is enabled in dra7xx_evm_defconfig by commit: adad96e: 
configs: Re-sync HUSH options
Hence CONFIG_HUSH_PARSER included for both SPL and u-boot as well. 
The cli.c is common for both SPL & u-boot.

Regards
Ravi

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Re: [U-Boot] [PATCH v1] cpu: Add Intel Tangier support

[Andy Shevchenko]

On Tue, 2017-04-18 at 18:12 -0600, Simon Glass wrote:
> On 18 April 2017 at 08:21, Andy Shevchenko
>  wrote:
> > From: Felipe Balbi 
> > 
> > Add Intel Tangier SoC support.
> > 
> > Intel Tangier SoC is a core part of Intel Merrifield platform. For
> > example, Intel Edison board is based on such platform.
> > 
> > The patch is based on work done by the following people (in
> > alphabetical
> > order):
> > Aiden Park 
> > Dukjoon Jeon 
> > eric.park 
> > Fabien Chereau 
> > Scott D Phillips 
> > Sebastien Colleur 
> > Steve Sakoman 
> > Vincent Tinelli 
> > 
> > Signed-off-by: Vincent Tinelli 
> > Signed-off-by: Felipe Balbi 
> > Signed-off-by: Andy Shevchenko 

> Reviewed-by: Simon Glass 

Thanks for review.

> Please check the chromium copyright though.

Actually if you can give an advice what better to do here.

The code is based somehow on some code (origin of which I have never saw
since I have no clue what was the tree and version of it) from coreboot,
but Felipe and me rewrote a major part of it (I can evaluate that about
90% is rewritten / refactored).

So, would it be better to update copyrights, if yes, what could they
look like?

-- 
Andy Shevchenko 
Intel Finland Oy
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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Marek Vasut]

On 04/19/2017 12:39 PM, Heiko Schocher wrote:
> Hello Marek,
> 
> Am 19.04.2017 um 11:51 schrieb Marek Vasut:
>> On 04/19/2017 11:46 AM, Heiko Schocher wrote:
>>> Hello Marek,
>>>
>>> Am 19.04.2017 um 10:43 schrieb Marek Vasut:
 On 04/19/2017 07:29 AM, Heiko Schocher wrote:
> Hello Tom,
>
> added Lukasz, Marek and Felipe,
>
> Am 18.04.2017 um 00:22 schrieb Tom Rini:
>> Hey all,
>>
>> It's release day and v2017.05-rc2 is out.  I think my patchwork
>> queue is
>> looking good currently.  I have some outstanding removal patches to
>> take
>> from Masahiro related to architectures that I removed as
>> promised.  The
>> release is bigger than I really wanted, but since I was on
>> vacation for
>> most of the normal -rc1 window, stuff came in that would have come in
>> then now, instead.  Things are on track for -rc3 on the 1st.
>
> My weekly dfu test on the siemens smartweb board failed with
> current HEAD.
>
> I started an automated git bisect with tbot, and found:
>
> 2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect
> visualize
> 2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
> 842778a091047b0c868efa12229633959f711152
> Author: Felipe Balbi 
> Date:   Wed Feb 22 17:12:40 2017 +0200
>   usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
>
>   We don't want to claim that we support a serial number string
> and
>   later return nothing. Because of that, if g_dnl_serial is an
> empty
>   string, let's skip setting iSerialNumber to a valid number.
>
>   Signed-off-by: Felipe Balbi 
> hs@pollux [ 7:24:30] ttbott>
> 2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect log
> 2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git bisect start
>>> [...]
>
> Any ideas?

 Is your board setting up the serial number with
 g_dnl_set_serialnumber()
 correctly ?
>>>
>>> Hmm.. good question ... its done here:
>>>
>>> http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/common/factoryset.c;h=6c869ed2b035a0e9f840e1f6f960fe0e6ac824e5;hb=f6c1df44b815a08585e7fd3805a1db51a5955d09#l313
>>>
>>>
>>>
>>> but may this does not work correct and now pops up.
>>>
>>> I try to find out more, thanks for the hint!
>>
>> Just check if you're not passing in NULL or empty string, that might be
>> it. Otherwise the USB code is botched.
> 
> Hmm... OK, on the smartweb board there is no factory set, so never
> calling g_dnl_set_serialnumber()
> 
> :-(
> 
> why did this worked before commit 842778a091?
> 
> So, I added for a fast dirty test:
> 
> diff --git a/board/siemens/smartweb/smartweb.c
> b/board/siemens/smartweb/smartweb.c
> index 78a7946..01a3dd2 100644
> --- a/board/siemens/smartweb/smartweb.c
> +++ b/board/siemens/smartweb/smartweb.c
> @@ -34,6 +34,7 @@
>  #ifndef CONFIG_DM_ETH
>  # include 
>  #endif
> +#include 
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -265,3 +266,17 @@ U_BOOT_DEVICE(at91sam9260_serial) = {
> .name   = "serial_atmel",
> .platdata = &at91sam9260_serial_plat,
>  };
> +
> +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
> +{
> +   printf("%s: *\n", __func__);
> +   g_dnl_set_serialnumber("0123456789");
> +
> +   return 0;
> +}
> +
> +int g_dnl_get_board_bcd_device_number(int gcnum)
> +{
> +   return 0;
> +}
> 
> Now I see this printf:
> (also enabled debug in ./drivers/usb/gadget/g_dnl.c)
> 
> dfu 0 nand 0
> using id 'nand0,4'
> g_dnl_register: g_dnl_driver.name = usb_dnl_dfu
> g_dnl_bind: gadget: 0x23adf6c0 cdev: 0x23b262d0
> g_dnl_bind_fixup: *
> g_dnl_do_config: configuration: 0x23b263c0 composite dev: 0x23b262d0
> g_dnl_bind: calling usb_gadget_connect for controller 'at91_udc'
> 
> but result is the same:
> # ./src/dfu-util -l
> dfu-util 0.7
> 
> Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
> Copyright 2010-2012 Tormod Volden and Stefan Schmidt
> This program is Free Software and has ABSOLUTELY NO WARRANTY
> Please report bugs to dfu-u...@lists.gnumonks.org
> tb_ctrl: Found DFU: [0908:02d2] ver=, devnum=0, cfg=1, intf=0, alt=0,
> name="Linux", serial="UNDEFINED"
> 
> reverting commit 842778a091 and it works as before ... console
> output for this case:
> 
> ./src/dfu-util -l
> dfu-util 0.7
> 
> Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
> Copyright 2010-2012 Tormod Volden and Stefan Schmidt
> This program is Free Software and has ABSOLUTELY NO WARRANTY
> Please report bugs to dfu-u...@lists.gnumonks.org
> tb_ctrl: Found DFU: [0908:02d2] ver=, devnum=0, cfg=1, intf=0, alt=0,
> name="Linux", serial="0123456789"
> 
> Ok, before commit 842778a091 is in mainline I had the follwoing output:
> 
> # tb_ctrl: ./src/dfu-util -l
> # tb_ctrl: dfu-util 0.7
> 
> Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
> 

[U-Boot] [PATCH v2 1/1] core/uclass: iterate over all devices of a uclass

[Heinrich Schuchardt]

When iterating over the devices of an uclass the iteration stops
at the first device that cannot be probed.
When calling booefi this will result in no block device being
passed to the EFI executable if the first device cannot be probed.

The problem was reported by Andreas Färber in
https://lists.denx.de/pipermail/u-boot/2017-April/287432.html

For testing I used an odroid-c2 with a dts including
&sd_emmc_a {
status = "okay";
}
This device does not exist on the board and cannot be initialized.

With the patch uclass_first_device and uclass_next_device
iterate internally until they find the first device that can be
probed or the end of the device list is reached.

Debug output is provided for the two functions.

Reported-by: Andreas Färber 
Cc: Simon Glass 
Signed-off-by: Heinrich Schuchardt 
---
v2:
  As suggested by Simon Glass correct uclass_first_device() and
  uclass_next_device() instead of uclass_get_device_tail() to
  avoid side effects.
v1:
  The original patch was posted as
  core/uclass: uclass_get_device_tail: always set devp
  https://lists.denx.de/pipermail/u-boot/2017-April/288068.html
---
 drivers/core/uclass.c | 44 +---
 1 file changed, 33 insertions(+), 11 deletions(-)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 04fb45b..cff3a3f 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -420,16 +420,30 @@ int uclass_get_device_by_phandle(enum uclass_id id, 
struct udevice *parent,
 }
 #endif
 
+/**
+ * uclass_first_device() - Finds first device of an uclass that can be probed
+ * @id: uclass id
+ * @devp: device found or NULL
+ * @return always 0
+ *
+ * For iterating over all devices of an uclass use
+ * for(uclass_first_device(id, &dev); dev; uclass_next_device(&dev)).
+ */
 int uclass_first_device(enum uclass_id id, struct udevice **devp)
 {
struct udevice *dev;
-   int ret;
 
*devp = NULL;
-   ret = uclass_find_first_device(id, &dev);
-   if (!dev)
-   return 0;
-   return uclass_get_device_tail(dev, ret, devp);
+   for (uclass_find_first_device(id, &dev); dev;
+uclass_find_next_device(&dev)) {
+
+   uclass_get_device_tail(dev, 0, devp);
+   if (*devp)
+   break;
+   }
+   debug("%s(%d): %s\n", __func__, id, dev ? dev->name : "(EOL)");
+
+   return 0;
 }
 
 int uclass_first_device_err(enum uclass_id id, struct udevice **devp)
@@ -445,16 +459,24 @@ int uclass_first_device_err(enum uclass_id id, struct 
udevice **devp)
return 0;
 }
 
+/**
+ * uclass_next_device() - Find next device of an uclass that can be probed
+ * @devp: device found or NULL
+ * @return always 0
+ */
 int uclass_next_device(struct udevice **devp)
 {
struct udevice *dev = *devp;
-   int ret;
 
-   *devp = NULL;
-   ret = uclass_find_next_device(&dev);
-   if (!dev)
-   return 0;
-   return uclass_get_device_tail(dev, ret, devp);
+   for (*devp = NULL; !*devp; ) {
+   uclass_find_next_device(&dev);
+   if (!dev)
+   break;
+   uclass_get_device_tail(dev, 0, devp);
+   }
+   debug("%s: %s\n", __func__, dev ? dev->name : "(EOL)");
+
+   return 0;
 }
 
 int uclass_bind_device(struct udevice *dev)
-- 
2.1.4

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Re: [U-Boot] [PATCH v1] mmc: sdhci: SDHCI controllers also need power

[Andy Shevchenko]

On Tue, 2017-04-18 at 18:12 -0600, Simon Glass wrote:
> Hi Andy,
> 
> On 18 April 2017 at 08:45, Andy Shevchenko
>  wrote:
> > On Tue, 2017-04-18 at 08:33 -0600, Simon Glass wrote:
> > > Hi Andy,
> > > 
> > > On 18 April 2017 at 08:29, Andy Shevchenko
> > >  wrote:
> > > > On Fri, 2017-04-07 at 19:05 +0900, Jaehoon Chung wrote:
> > > > > Hi Andy,
> > > > > 
> > > > > On 04/06/2017 07:58 PM, Andy Shevchenko wrote:
> > > > > > On Thu, Apr 6, 2017 at 1:50 PM, Jaehoon Chung  > > > > > msun
> > > > > > g.co
> > > > > > m> wrote:
> > > > > > > On 04/06/2017 06:46 PM, Andy Shevchenko wrote:
> > > > > > > > On Thu, 2017-04-06 at 18:24 +0900, Jaehoon Chung wrote:
> > > > > > > > > On 04/06/2017 05:51 PM, Andy Shevchenko wrote:
> > > > > > > > > > On Thu, Apr 6, 2017 at 6:44 AM, Simon Glass  > > > > > > > > > omiu
> > > > > > > > > > m.or
> > > > > > > > > > g>
> > > > > > > > > > wrote:
> > > > > > > > > > > On 1 April 2017 at 07:11, Andy Shevchenko
> > > > > > > > > > >  wrote:
> > > > > > > > > 
> > > > > > > > > how about mmc_power_init() is called in mmc_probe()?
> > > > > > > > Yes, that's what I'm referring to. But the driver is
> > > > > > > > pure
> > > > > > > > SDHCI,
> > > > > > > > it
> > > > > > > > doesn't call mmc_probe() IIRC.
> > > > > > > 
> > > > > > > After converting to DM, it might have the dependent to
> > > > > > > probing
> > > > > > > sequence.
> > > > > > > I'm not sure that u-boot has the priority for probing.
> > > > > > > maybe
> > > > > > > not...
> > > > > > > 
> > > > > > > hmm..need to consider this patch..but i will think about
> > > > > > > more
> > > > > > > generic solution..
> > > > > > 
> > > > > > It would be nice to have a generic solution indeed.
> > > > > 
> > > > > Just thinking about below..?
> > > > > 
> > > > > vcc_sd: sdmmc-regulator {
> > > > >   ...
> > > > >   regulator-boot-on;
> > > > > or
> > > > >   regulator-always-on;
> > > > >   ...
> > > > > 
> > > > > };
> > > > > 
> > > > > It should be always enabled..
> > > > 
> > > > Sorry, but no. It's not a regulator.
> > > > 
> > > > If you would like to know details, the 2 bits in PMU registers
> > > > basically
> > > > represent clock gate and reset signal per IP which PMU controls.
> > > > 
> > > > P.S. Hardware might have a common regulator per power island
> > > > which
> > > > is
> > > > automatically latches the power down if all devices on the
> > > > island
> > > > are on
> > > > D3hot. But it's not controlled by software.
> > > 
> > > You have a few options:
> > > 
> > > - Add a regulator/pmic driver for the PMU
> > 
> > I dunno how many times should I repeat that it is *not* a PMIC at
> > all!
> > 
> > PMIC is a separate *external* IC which is connected to Atom SoC. And
> > it
> > has nothing to do with PMU (on software level).
> 
> That doesn't really matter though. The point is how it is modeled in
> U-Boot.

Hardware matters. Software (drivers) represents whatever hardware design
is underneath. This is how Linux kernel at least being designed. Does U-
Boot follow the same paradigm?

> > 
> > > - Add a reset driver to handle the reset and perhaps a clock
> > > driver to
> > > handle the clock gate, then handle this in your driver
> > 
> > No, I disclosed details just for your understanding that it's not a
> > regulator. On the other hand it's 1:1 mapping to D0/D3hot in PCI,
> > and
> > bits can't be switched separately by specification.
> > 
> > TBH I even don't know which one is which.
> > 
> > > You can subclass sdhci.c and adjust it as you need it.
> > > 
> > > > 
> > > > So, please consider my initial approach.
> > > 
> > > We should use DM rather than custom hooks.
> > 
> > Can anyone answer to a simple question why MMC code *has* been
> > calling
> > such hook and you strongly object to do the same / similar for
> > SDHCI?
> 
> Can you point me to the mmc function you are referring to?

drivers/mmc/mmc.c:

-> (mmc-uclass.c) mmc_blk_probe()
  -> mmc_init()
-> mmc_start_init()
  -> mmc_power_init()
   -> board_mmc_power_init()

> > >  If this doesn't make sense
> > 
> > It does not.
> > 
> > > please let me know how I can help expound on it.
> > 
> > Please, elaborate how pure SDHCI drivers are so different to MMC in
> > init
> > stage and why, but please don't offer regulators.
> 
> It's just that we cannot call a board hook function from DM.

World is not ideal, and for me is clear that DM is not ideal either.

>  That's
> the way things used to work, but with DM we need to have things in the
> driver.
> 
> I'm sorry if you're finding this frustrating, but I do want to
> understand this. While it seems like a minor point it actually is a
> key design feature of DM.

I understand your point. And I am all ears to implement the best of
possible solutions (with current U-Boot design), OTOH I don't like any
idea of faking in software something that is not present on real
platform (like doing weird PMIC or regulators for PMU which is not
either of them).

Please, understand 

Re: [U-Boot] [PATCH] ehci-ppc4xx: Prepare for usage of readl()/writel() accessors

[Marek Vasut]

On 04/19/2017 12:05 PM, Stefan Roese wrote:
> On 17.04.2017 18:13, Alexey Brodkin wrote:
>> We used to have opencoded ehci_readl()/writel() which required no
>> external functions to be called.
>>
>> Now with attempt to switch to generic readl()/writel() accessors
>> we see a missing declaration of those accessors in ehci-ppc4xx.
>> Something like that happens if applied
>> http://patchwork.ozlabs.org/patch/726714/:
>> >8---
>>   CC  drivers/usb/host/ehci-ppc4xx.o
>> drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
>> drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of
>> function 'readl' [-Wimplicit-function-declaration]
>>HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
>>^
>> >8---
>>
>> Signed-off-by: Alexey Brodkin 
>> Cc: Tom Rini 
>> Cc: Marek Vasut 
>> Cc: Stefan Roese 
>> ---
>>  drivers/usb/host/ehci-ppc4xx.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/usb/host/ehci-ppc4xx.c
>> b/drivers/usb/host/ehci-ppc4xx.c
>> index 9aee3ff786cb..9d235776428e 100644
>> --- a/drivers/usb/host/ehci-ppc4xx.c
>> +++ b/drivers/usb/host/ehci-ppc4xx.c
>> @@ -8,6 +8,7 @@
>>   */
>>  #include 
>>  #include 
>> +#include 
>>
>>  #include "ehci.h"
>>
>>
> 
> Alexey, thanks for looking into this:
> 
> Reviewed-by: Stefan Roese 

Applied, thanks.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v1 11/15] aspeed: Add I2C Driver

[Heiko Schocher]

Hello Maxim,

Am 17.04.2017 um 21:00 schrieb Maxim Sloyko:

Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.

Signed-off-by: Maxim Sloyko 

---

Changes in v1:
- Style fixes


---
  drivers/i2c/Kconfig   |   9 ++
  drivers/i2c/Makefile  |   1 +
  drivers/i2c/ast_i2c.c | 357 ++
  drivers/i2c/ast_i2c.h | 132 +++
  4 files changed, 499 insertions(+)
  create mode 100644 drivers/i2c/ast_i2c.c
  create mode 100644 drivers/i2c/ast_i2c.h


Is this "version 2" from the patch you posted in march?

Acked-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  enable status register. This config option can be enabled in such
  cases.

+config SYS_I2C_ASPEED
+   bool "Aspeed I2C Controller"
+   depends on DM_I2C && ARCH_ASPEED
+   help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
  config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
  obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
  obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
  obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
  obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
  obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
  obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..16dfb57066
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2012-2020  ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+   /* This device's clock */
+   struct clk clk;
+   /* Device registers */
+   struct ast_i2c_regs *regs;
+   /* I2C speed in Hz */
+   int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+   ulong inc = 0, div;
+   ulong scl_low, scl_high, data;
+
+   for (div = 0; divider_ratio >= 16; div++) {
+   inc |= (divider_ratio & 1);
+   divider_ratio >>= 1;
+   }
+   divider_ratio += inc;
+   scl_low = (divider_ratio >> 1) - 1;
+   scl_high = divider_ratio - scl_low - 2;
+   data = I2CD_CACTC_BASE
+   | (scl_high << I2CD_TCKHIGH_SHIFT)
+   | (scl_low << I2CD_TCKLOW_SHIFT)
+   | (div << I2CD_BASE_DIV_SHIFT);
+
+   return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+   struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+   writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+   struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+   /* Reset device */
+   writel(0, &priv->regs->fcr);
+   /* Enable Master Mode. Assuming single-master */
+   writel(I2CD_MASTER_EN
+  | I2CD_M_SDA_LOCK_EN
+  | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+  &priv->regs->fcr);
+   /* Enable Interrupts */
+   writel(I2CD_INTR_TX_ACK
+  | I2CD_INTR_TX_NAK
+  | I2CD_INTR_RX_DONE
+  | I2CD_INTR_BUS_RECOVER_DONE
+  | I2CD_INTR_NORMAL_STOP
+  | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ast_i2c_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   priv->regs = dev_get_addr_ptr(dev);
+   if (IS_ERR(priv->regs))
+   return PTR_ERR(priv->regs);
+
+   ret = clk_get_by_index(dev, 0, &priv->clk);
+   if (ret < 0) {
+   debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static int ast_i2c_probe(struct udevice *d

Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released

[Lukasz Majewski]

Dear All,

> On 04/19/2017 12:39 PM, Heiko Schocher wrote:
> > Hello Marek,
> > 
> > Am 19.04.2017 um 11:51 schrieb Marek Vasut:
> >> On 04/19/2017 11:46 AM, Heiko Schocher wrote:
> >>> Hello Marek,
> >>>
> >>> Am 19.04.2017 um 10:43 schrieb Marek Vasut:
>  On 04/19/2017 07:29 AM, Heiko Schocher wrote:
> > Hello Tom,
> >
> > added Lukasz, Marek and Felipe,
> >
> > Am 18.04.2017 um 00:22 schrieb Tom Rini:
> >> Hey all,
> >>
> >> It's release day and v2017.05-rc2 is out.  I think my patchwork
> >> queue is
> >> looking good currently.  I have some outstanding removal
> >> patches to take
> >> from Masahiro related to architectures that I removed as
> >> promised.  The
> >> release is bigger than I really wanted, but since I was on
> >> vacation for
> >> most of the normal -rc1 window, stuff came in that would have
> >> come in then now, instead.  Things are on track for -rc3 on
> >> the 1st.
> >
> > My weekly dfu test on the siemens smartweb board failed with
> > current HEAD.
> >
> > I started an automated git bisect with tbot, and found:
> >
> > 2017-04-19 07:24:30,717:CON:tbotlib   # tb_ctrl: git bisect
> > visualize
> > 2017-04-19 07:24:30,783:CON:tbotlib   # tb_ctrl: commit
> > 842778a091047b0c868efa12229633959f711152
> > Author: Felipe Balbi 
> > Date:   Wed Feb 22 17:12:40 2017 +0200
> >   usb: gadget: g_dnl: only set iSerialNumber if we have a
> > serial#
> >
> >   We don't want to claim that we support a serial number
> > string and
> >   later return nothing. Because of that, if g_dnl_serial is
> > an empty
> >   string, let's skip setting iSerialNumber to a valid
> > number.
> >
> >   Signed-off-by: Felipe Balbi 
> > hs@pollux [ 7:24:30] ttbott>
> > 2017-04-19 07:24:31,769:CON:tbotlib   # tb_ctrl: git bisect
> > log 2017-04-19 07:24:31,836:CON:tbotlib   # tb_ctrl: git
> > bisect start
> >>> [...]
> >
> > Any ideas?
> 
>  Is your board setting up the serial number with
>  g_dnl_set_serialnumber()
>  correctly ?
> >>>
> >>> Hmm.. good question ... its done here:
> >>>
> >>> http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/common/factoryset.c;h=6c869ed2b035a0e9f840e1f6f960fe0e6ac824e5;hb=f6c1df44b815a08585e7fd3805a1db51a5955d09#l313
> >>>
> >>>
> >>>
> >>> but may this does not work correct and now pops up.
> >>>
> >>> I try to find out more, thanks for the hint!
> >>
> >> Just check if you're not passing in NULL or empty string, that
> >> might be it. Otherwise the USB code is botched.
> > 
> > Hmm... OK, on the smartweb board there is no factory set, so never
> > calling g_dnl_set_serialnumber()
> > 
> > :-(
> > 
> > why did this worked before commit 842778a091?
> > 
> > So, I added for a fast dirty test:
> > 
> > diff --git a/board/siemens/smartweb/smartweb.c
> > b/board/siemens/smartweb/smartweb.c
> > index 78a7946..01a3dd2 100644
> > --- a/board/siemens/smartweb/smartweb.c
> > +++ b/board/siemens/smartweb/smartweb.c
> > @@ -34,6 +34,7 @@
> >  #ifndef CONFIG_DM_ETH
> >  # include 
> >  #endif
> > +#include 
> > 
> >  DECLARE_GLOBAL_DATA_PTR;
> > 
> > @@ -265,3 +266,17 @@ U_BOOT_DEVICE(at91sam9260_serial) = {
> > .name   = "serial_atmel",
> > .platdata = &at91sam9260_serial_plat,
> >  };
> > +
> > +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char
> > *name) +{
> > +   printf("%s: *\n", __func__);
> > +   g_dnl_set_serialnumber("0123456789");
> > +
> > +   return 0;
> > +}
> > +
> > +int g_dnl_get_board_bcd_device_number(int gcnum)
> > +{
> > +   return 0;
> > +}
> > 
> > Now I see this printf:
> > (also enabled debug in ./drivers/usb/gadget/g_dnl.c)
> > 
> > dfu 0 nand 0
> > using id 'nand0,4'
> > g_dnl_register: g_dnl_driver.name = usb_dnl_dfu
> > g_dnl_bind: gadget: 0x23adf6c0 cdev: 0x23b262d0
> > g_dnl_bind_fixup: *
> > g_dnl_do_config: configuration: 0x23b263c0 composite dev: 0x23b262d0
> > g_dnl_bind: calling usb_gadget_connect for controller 'at91_udc'
> > 
> > but result is the same:
> > # ./src/dfu-util -l
> > dfu-util 0.7
> > 
> > Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
> > Copyright 2010-2012 Tormod Volden and Stefan Schmidt
> > This program is Free Software and has ABSOLUTELY NO WARRANTY
> > Please report bugs to dfu-u...@lists.gnumonks.org
> > tb_ctrl: Found DFU: [0908:02d2] ver=, devnum=0, cfg=1, intf=0,
> > alt=0, name="Linux", serial="UNDEFINED"
> > 
> > reverting commit 842778a091 and it works as before ... console
> > output for this case:
> > 
> > ./src/dfu-util -l
> > dfu-util 0.7
> > 
> > Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc.
> > Copyright 2010-2012 Tormod Volden and Stefan Schmidt
> > This program is Free Software and has ABSOLUTELY NO WARRANTY
> > Please report bugs to dfu-u...@lists.gnumonks.org
> > tb_ct

[U-Boot] [PATCH v2 1/3] fsl-ppa: Kconfig: Support to load PPA hdr from eMMC/SD and NAND Flash

[Sumit Garg]

Add support to load PPA hdr from eMMC/SD and NAND Flash in Kconfig

Signed-off-by: Sumit Garg 
Signed-off-by: Udit Agarwal 
Tested-by: Vinitha Pillai 
---

Changes in v2:
Changed order of patch 1 & 2. Also moved assignment of ppa_esbc_hdr to
CONFIG_SYS_LS_PPA_ESBC_ADDR in XIP space as it's not required in case of
SD/NAND.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9fb76f0..4c9b6ce 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -179,12 +179,22 @@ config SYS_LS_PPA_ESBC_ADDR
default 0x4074 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x4048 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x580c4 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+   default 0x70 if SYS_LS_PPA_FW_IN_MMC
+   default 0x70 if SYS_LS_PPA_FW_IN_NAND
help
  If the PPA header firmware locate at XIP flash, such as NOR or
  QSPI flash, this address is a directly memory-mapped.
  If it is in a serial accessed flash, such as NAND and SD
  card, it is a byte offset.
 
+config LS_PPA_ESBC_HDR_SIZE
+   hex "Length of PPA ESBC header"
+   depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
+   default 0x2000
+   help
+ Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
+ NAND to memory to validate PPA image.
+
 endmenu
 
 config SYS_FSL_ERRATUM_A010315
-- 
1.9.1

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[U-Boot] [PATCH v2 3/3] ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND boot

[Sumit Garg]

Signed-off-by: Sumit Garg 
Signed-off-by: Udit Agarwal 
Tested-by: Vinitha Pillai 
---

Changes in v2:
Changed order of patch 1 & 2. Also moved assignment of ppa_esbc_hdr to
CONFIG_SYS_LS_PPA_ESBC_ADDR in XIP space as it's not required in case of
SD/NAND.

 configs/ls1043ardb_nand_SECURE_BOOT_defconfig   | 1 +
 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 +
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 66c89fa..70f28d8 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_NAND_BOOT=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 3f35d64..5f9b21d 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SECURE_BOOT=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index a41ec80..1e32023 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
 CONFIG_SECURE_BOOT=y
-- 
1.9.1

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[U-Boot] [PATCH v2 2/3] fsl: PPA: add support PPA image validation from NAND and SD

[Sumit Garg]

Signed-off-by: Sumit Garg 
Signed-off-by: Udit Agarwal 
Tested-by: Vinitha Pillai 
---

Changes in v2:
Changed order of patch 1 & 2. Also moved assignment of ppa_esbc_hdr to
CONFIG_SYS_LS_PPA_ESBC_ADDR in XIP space as it's not required in case of
SD/NAND.

 arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 72 -
 1 file changed, 70 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index 7f87bb8..26c47a1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -37,13 +37,20 @@ int ppa_init(void)
int ret;
 
 #ifdef CONFIG_CHAIN_OF_TRUST
-   uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+   uintptr_t ppa_esbc_hdr = 0;
uintptr_t ppa_img_addr = 0;
+#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
+   defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+   void *ppa_hdr_ddr;
+#endif
 #endif
 
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
debug("%s: PPA image load from XIP\n", __func__);
+#ifdef CONFIG_CHAIN_OF_TRUST
+   ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+#endif
 #else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
 
@@ -53,7 +60,7 @@ int ppa_init(void)
int dev = CONFIG_SYS_MMC_ENV_DEV;
struct fdt_header *fitp;
u32 cnt;
-   u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
+   u32 blk;
 
debug("%s: PPA image load from eMMC/SD\n", __func__);
 
@@ -81,6 +88,7 @@ int ppa_init(void)
return -ENOMEM;
}
 
+   blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
cnt = DIV_ROUND_UP(fdt_header_len, 512);
debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
  __func__, dev, blk, cnt);
@@ -102,6 +110,29 @@ int ppa_init(void)
return ret;
}
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+   ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
+   if (!ppa_hdr_ddr) {
+   printf("PPA: malloc failed for PPA header\n");
+   return -ENOMEM;
+   }
+
+   blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9;
+   cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512);
+   ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr);
+   if (ret != cnt) {
+   free(ppa_hdr_ddr);
+   printf("MMC/SD read of PPA header failed\n");
+   return -EIO;
+   }
+   debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
+
+   /* flush cache after read */
+   flush_cache((ulong)ppa_hdr_ddr, cnt * 512);
+
+   ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
+#endif
+
fw_length = fdt_totalsize(fitp);
free(fitp);
 
@@ -113,6 +144,7 @@ int ppa_init(void)
return -ENOMEM;
}
 
+   blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
cnt = DIV_ROUND_UP(fw_length, 512);
debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
  __func__, dev, blk, cnt);
@@ -148,6 +180,31 @@ int ppa_init(void)
return ret;
}
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+   ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
+   if (!ppa_hdr_ddr) {
+   printf("PPA: malloc failed for PPA header\n");
+   return -ENOMEM;
+   }
+
+   fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
+
+   ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
+  &fw_length, (u_char *)ppa_hdr_ddr);
+   if (ret == -EUCLEAN) {
+   free(ppa_hdr_ddr);
+   printf("NAND read of PPA firmware at offset 0x%x failed\n",
+  CONFIG_SYS_LS_PPA_FW_ADDR);
+   return -EIO;
+   }
+   debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
+
+   /* flush cache after read */
+   flush_cache((ulong)ppa_hdr_ddr, fw_length);
+
+   ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
+#endif
+
fw_length = fdt_totalsize(&fit);
 
ppa_fit_addr = malloc(fw_length);
@@ -177,6 +234,13 @@ int ppa_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
ppa_img_addr = (uintptr_t)ppa_fit_addr;
if (fsl_check_boot_mode_secure() != 0) {
+   /*
+* In case of failure in validation, fsl_secboot_validate
+* would not return back in case of Production environment
+* with ITS=1. In Development environment (ITS=0 and
+* SB_EN=1), the function may return back in case of
+* non-fatal failures.
+*/
ret = fsl_secboot_validate(ppa_esbc_hdr,
   PPA_KEY_HASH,
   &ppa_img_addr);
@@ -185,6 +249,10 @@ int ppa_init(void)
else
printf("PPA validation Successful\n");
}
+#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \

Re: [U-Boot] [PATCH] usb: lpc32xx: Add i2c DM support

[Sylvain Lemieux]

On Fri, 2017-04-14 at 16:01 +0200, Marek Vasut wrote:
> On 03/14/2017 04:28 PM, Sylvain Lemieux wrote:
> > From: Liam Beguin 
> > 
> > Add DM support for i2c functions.
> > 
> > Signed-off-by: Liam Beguin 
> > Signed-off-by: Sylvain Lemieux 
> > ---
> > Note:
> > * This patch is require as part of the DM support of the LPC32xx I2C driver.
> >   All I2C drivers should be converted, to DM, by the end of June 2017.
> > 
> > * The USB driver is supporting the DM and non-DM API.
> > 
> > * This patch depend on the following patchset:
> >   https://lists.denx.de/pipermail/u-boot/2017-March/283672.html
> > 
> >  drivers/usb/host/ohci-lpc32xx.c | 33 +++--
> >  1 file changed, 31 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/usb/host/ohci-lpc32xx.c 
> > b/drivers/usb/host/ohci-lpc32xx.c
> > index 9245126ed6..51be4c90c7 100644
> > --- a/drivers/usb/host/ohci-lpc32xx.c
> > +++ b/drivers/usb/host/ohci-lpc32xx.c
> > @@ -14,8 +14,10 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  /* OTG I2C controller module register structures */
> >  struct otgi2c_regs {
> > @@ -83,12 +85,35 @@ static struct clk_pm_regs *clk_pwr = (struct 
> > clk_pm_regs *)CLK_PM_BASE;
> >  
> >  static int isp1301_set_value(int reg, u8 value)
> >  {
> > +#ifndef CONFIG_DM_I2C
> > return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
> > +#else
> > +   struct udevice *dev;
> > +   int ret;
> > +
> > +   ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR,
> > + 1, &dev);
> 
> I'd rather see you passing udevice around than requesting it on each
> single i2c write.
> 
Will do the change and submit a version 2.

> > +   if (ret)
> > +   return ret;
> > +
> > +   return dm_i2c_write(dev, reg, &value, 1);
> > +#endif
> >  }
> >  
> > -static void isp1301_configure(void)
> > +static int isp1301_configure(void)
> >  {
> > +#ifndef CONFIG_DM_I2C
> > i2c_set_bus_num(I2C_2);
> > +#else
> > +   int ret;
> > +   struct udevice *bus;
> > +
> > +   ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_2, &bus);
> > +   if (ret) {
> > +   debug("%s: No bus %d\n", __func__, I2C_2);
> > +   return ret;
> > +   }
> > +#endif
> >  
> > /*
> >  * LPC32XX only supports DAT_SE0 USB mode
> > @@ -116,6 +141,8 @@ static void isp1301_configure(void)
> >  
> > /* Enable usb_need_clk clock after transceiver is initialized */
> > setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
> > +
> > +   return 0;
> >  }
> >  
> >  static int usbpll_setup(void)
> > @@ -167,7 +194,9 @@ int usb_cpu_init(void)
> > return ret;
> >  
> > /* Configure ISP1301 */
> > -   isp1301_configure();
> > +   ret = isp1301_configure();
> > +   if (ret)
> > +   return ret;
> 
> Don't we need some sort of failpath now, to undo the changes ?
> 
With the rework of the patch, this change is no longer needed.

> > /* setup USB clocks and PLL */
> > ret = usbpll_setup();
> > 
> 
> 
Sylvain


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[U-Boot] [PATCH v3 02/11] rockchip: video: Add mipi driver for rockchip soc

[Eric Gao]

Signed-off-by: Eric Gao 

---

Changes in v3:
-Split mipi dsi driver file and header as a single patch.

Changes in v2: None

 .../include/asm/arch-rockchip/rockchip_mipi_dsi.h  | 195 
 drivers/video/rockchip/rk_mipi.c   | 491 +
 2 files changed, 686 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
 create mode 100644 drivers/video/rockchip/rk_mipi.c

diff --git a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h 
b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
new file mode 100644
index 000..d7f79c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * author: Eric Gao 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef ROCKCHIP_MIPI_DSI_H
+#define ROCKCHIP_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide reg address offset,
+ * bits width, bit offset for a specified register bits. With these message, we
+ * can set or clear every bits individually for a 32bit widthregister. We use
+ * DSI_HOST_BITS macro definition to combinat these message using the following
+ * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * For example:
+ *#define SHUTDOWNZ   DSI_HOST_BITS(0x004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
+ * offset is 0x004.The conbinat result  = (0x004 << 16) | (1 << 8) | 0
+ */
+#define ADDR_SHIFT 16
+#define BITS_SHIFT 8
+#define OFFSET_SHIFT 0
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
+
+/* DWC_DSI_VERSION_0x3133302A */
+#define VERSIONDSI_HOST_BITS(0x000, 32, 0)
+#define SHUTDOWNZ  DSI_HOST_BITS(0x004, 1, 0)
+#define TO_CLK_DIVISIONDSI_HOST_BITS(0x008, 8, 8)
+#define TX_ESC_CLK_DIVISIONDSI_HOST_BITS(0x008, 8, 0)
+#define DPI_VCID   DSI_HOST_BITS(0x00c, 2, 0)
+#define EN18_LOOSELY   DSI_HOST_BITS(0x010, 1, 8)
+#define DPI_COLOR_CODING   DSI_HOST_BITS(0x010, 4, 0)
+#define COLORM_ACTIVE_LOW  DSI_HOST_BITS(0x014, 1, 4)
+#define SHUTD_ACTIVE_LOW   DSI_HOST_BITS(0x014, 1, 3)
+#define HSYNC_ACTIVE_LOW   DSI_HOST_BITS(0x014, 1, 2)
+#define VSYNC_ACTIVE_LOW   DSI_HOST_BITS(0x014, 1, 1)
+#define DATAEN_ACTIVE_LOW  DSI_HOST_BITS(0x014, 1, 0)
+#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16)
+#define INVACT_LPCMD_TIME  DSI_HOST_BITS(0x018, 8, 0)
+#define CRC_RX_EN  DSI_HOST_BITS(0x02c, 1, 4)
+#define ECC_RX_EN  DSI_HOST_BITS(0x02c, 1, 3)
+#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2)
+#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1)
+#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0)
+#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0)
+#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0)
+#define VPG_ORIENTATIONDSI_HOST_BITS(0x038, 1, 24)
+#define VPG_MODE   DSI_HOST_BITS(0x038, 1, 20)
+#define VPG_EN DSI_HOST_BITS(0x038, 1, 16)
+#define LP_CMD_EN  DSI_HOST_BITS(0x038, 1, 15)
+#define FRAME_BTA_ACK_EN   DSI_HOST_BITS(0x038, 1, 14)
+#define LP_HFP_EN  DSI_HOST_BITS(0x038, 1, 13)
+#define LP_HBP_EN  DSI_HOST_BITS(0x038, 1, 12)
+#define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11)
+#define LP_VFP_EN  DSI_HOST_BITS(0x038, 1, 10)
+#define LP_VBP_EN  DSI_HOST_BITS(0x038, 1, 9)
+#define LP_VSA_EN  DSI_HOST_BITS(0x038, 1, 8)
+#define VID_MODE_TYPE  DSI_HOST_BITS(0x038, 2, 0)
+#define VID_PKT_SIZE   DSI_HOST_BITS(0x03c, 14, 0)
+#define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0)
+#define NULL_PKT_SIZE  DSI_HOST_BITS(0x044, 13, 0)
+#define VID_HSA_TIME   DSI_HOST_BITS(0x048, 12, 0)
+#define VID_HBP_TIME   DSI_HOST_BITS(0x04c, 12, 0)
+#define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0)
+#define VID_VSA_LINES  DSI_HOST_BITS(0x054, 10, 0)
+#define VID_VBP_LINES  DSI_HOST_BITS(0x058, 10, 0)
+#define VID_VFP_LINES  DSI_HOST_BITS(0x05c, 10, 0)
+#define VID_ACTIVE_LINES   DSI_HOST_BITS(0x060, 14, 0)
+#define EDPI_CMD_SIZE  DSI_HOST_BITS(0x064, 16, 0)
+#define MAX_RD_PKT_SIZEDSI_HOST_BITS(0x068, 1, 24)
+#define DCS_LW_TX  DSI_HOST_BITS(0x068, 1, 19)
+#define DCS_SR_0P_TX   DSI_HOST_BITS(0x068, 1, 18)
+#define DCS_SW_1P_TX   DSI_HOST_BITS(0x068, 1, 17)
+#define DCS_SW_0P_TX   DSI_HOST_BITS(0x068, 1, 16)
+#define GEN_LW_TX  DSI_HOST_BITS(0x068, 1, 14)
+#define GEN_SR_2P_TX   DSI_HOST_BITS(0x068, 1, 13)
+#d

[U-Boot] [PATCH v3 01/11] rockchip: include: grf: Add GRF register declaration for mipi dsi

[Eric Gao]

Signed-off-by: Eric Gao 

---

Changes in v3:
-Split GRF changes as a single patch

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b340b05..63b3b94 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -440,6 +440,29 @@ enum {
GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
GRF_UART_DBG_SEL_C  = 2,
 
+   /* GRF_SOC_CON20 */
+   GRF_DSI0_VOP_SEL_SHIFT  = 0,
+   GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+   GRF_DSI0_VOP_SEL_B  = 0,
+   GRF_DSI0_VOP_SEL_L,
+
+   /* GRF_SOC_CON22 */
+   GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+   GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+   GRF_DPHY_TX0_RXMODE_EN = 0xb,
+   GRF_DPHY_TX0_RXMODE_DIS = 0,
+
+   GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+   GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+   GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
+   GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+   GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+   GRF_DPHY_TX0_TURNREQUEST_MASK = 0xf000
+   << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+   GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
+   GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
+
/*  PMUGRF_GPIO0A_IOMUX */
PMUGRF_GPIO0A6_SEL_SHIFT= 12,
PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
-- 
1.9.1


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[U-Boot] [PATCH v3 00/11] Add mipi dsi display support for rockchip soc.

[Eric Gao]

Changes in v3:
-Split GRF changes as a single patch
-Split mipi dsi driver file and header as a single patch.
-Split Makefile changes to a single patch.
-Split Kconfig changes to a single patch.
-Add more description in the commit message
-Add ret value in debug message.
-Improve indentation relationship

Changes in v2:
-Add mipi display mode for vop.
-Add compatible items for rk3399 vop.
-Change the bitwidth for different display mode.
-Extend frame buffer size for mipi display
-Add pwm0 pinctrl init for lcd backlight.
-Add dts config for mipi display.
-Add defconfigs for mipi display, so that it can be enabled by default.

Eric Gao (11):
  rockchip: include: grf: Add GRF register declaration for mipi dsi
  rockchip: video: Add mipi driver for rockchip soc
  rockchip: video: Makefile: Add mipi driver addition.
  rockchip: video: Kconfig: Add mipi driver addition.
  rockchip: video: vop: Add mipi display mode for rk3399
  rockchip: video: vop: Set different bitwidth for different display
mode
  rockchip: video: vop: Reserve enough space for mipi dispaly
  rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight
  rockchip: dts: Add mipi dsi support for rk3399
  rockchip: configs: Enable mipi dsi for rk3399
  rockchip: video: vop: Fix rk_display_init() return error

 arch/arm/dts/rk3399-evb.dts|  84 
 arch/arm/dts/rk3399.dtsi   |  72 +++
 arch/arm/include/asm/arch-rockchip/grf_rk3399.h|  23 +
 .../include/asm/arch-rockchip/rockchip_mipi_dsi.h  | 195 
 arch/arm/include/asm/arch-rockchip/vop_rk3288.h|   1 +
 board/rockchip/evb_rk3399/evb-rk3399.c |   7 +
 configs/evb-rk3399_defconfig   |   6 +
 drivers/video/rockchip/Kconfig |  11 +-
 drivers/video/rockchip/Makefile|   5 +-
 drivers/video/rockchip/rk_mipi.c   | 491 +
 drivers/video/rockchip/rk_vop.c|  38 +-
 11 files changed, 919 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
 create mode 100644 drivers/video/rockchip/rk_mipi.c

-- 
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[U-Boot] [PATCH v3 04/11] rockchip: video: Kconfig: Add mipi driver addition.

[Eric Gao]

Signed-off-by: Eric Gao 

---

Changes in v3:
-Split Kconfig changes to a single patch.

Changes in v2: None

 drivers/video/rockchip/Kconfig | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index 09c4ea2..1383efa 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -37,7 +37,14 @@ if VIDEO_ROCKCHIP
bool "HDMI port"
depends on VIDEO_ROCKCHIP
help
-   This enable High-Definition Multimedia Interface 
display support.
+   This enable High-Definition Multimedia Interface(HDMI) 
display
+   support.
 
+   config DISPLAY_ROCKCHIP_MIPI
+   bool "MIPI Port"
+   depends on VIDEO_ROCKCHIP
+   help
+   This enables Mobile Industry Processor Interface(MIPI) 
display
+   support. The mipi controller and dphy on rk3288& rk3399 
support
+   16,18, 24 bits per pixel with upto 2k resolution ratio.
 endif
-
-- 
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[U-Boot] [PATCH v3 08/11] rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight

[Eric Gao]

Signed-off-by: Eric Gao 

---

Changes in v3:
-Add ret value in debug message.

Changes in v2:
-Add pwm0 pinctrl init for lcd backlight.

 board/rockchip/evb_rk3399/evb-rk3399.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c 
b/board/rockchip/evb_rk3399/evb-rk3399.c
index 362fa0b..4753a76 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -28,6 +28,13 @@ int board_init(void)
goto out;
}
 
+   /* Enable pwm0 for panel backlight */
+   ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
+   if (ret) {
+   debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret);
+   goto out;
+   }
+
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
if (ret) {
debug("%s PWM2 pinctrl init fail!\n", __func__);
-- 
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[U-Boot] [PATCH v3 06/11] rockchip: video: vop: Set different bitwidth for different display mode

[Eric Gao]

Because the bitwidth is different for different display mode, so we need
to set them according to demand.

Signed-off-by: Eric Gao 

---

Changes in v3: None
Changes in v2:
-Change the bitwidth for different display mode.

 drivers/video/rockchip/rk_vop.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 84d6627..a637f7d 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -181,13 +181,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
  *
  * @dev:   VOP device that we want to connect to the display
  * @fbbase:Frame buffer address
- * @l2bpp  Log2 of bits-per-pixels for the display
  * @ep_node:   Device tree node to process - this is the offset of an endpoint
  * node within the VOP's 'port' list.
  * @return 0 if OK, -ve if something went wrong
  */
-int rk_display_init(struct udevice *dev, ulong fbbase,
-   enum video_log2_bpp l2bpp, int ep_node)
+int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
 {
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
@@ -199,6 +197,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
struct clk clk;
+   enum video_log2_bpp l2bpp;
 
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
debug("vop_id=%d\n", vop_id);
@@ -253,6 +252,19 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
return ret;
}
 
+   /* Set bitwidth for vop display according to vop mode */
+   switch (vop_id) {
+   case VOP_MODE_EDP:
+   case VOP_MODE_HDMI:
+   case VOP_MODE_LVDS:
+   l2bpp = VIDEO_BPP16;
+   break;
+   case VOP_MODE_MIPI:
+   l2bpp = VIDEO_BPP32;
+   break;
+   default:
+   l2bpp = VIDEO_BPP16;
+   }
rkvop_mode_set(regs, &timing, vop_id);
 
rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
@@ -330,7 +342,7 @@ static int rk_vop_probe(struct udevice *dev)
for (node = fdt_first_subnode(blob, port);
 node > 0;
 node = fdt_next_subnode(blob, node)) {
-   ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
+   ret = rk_display_init(dev, plat->base, node);
if (ret)
debug("Device failed: ret=%d\n", ret);
if (!ret)
-- 
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[U-Boot] [PATCH v3 10/11] rockchip: configs: Enable mipi dsi for rk3399

[Eric Gao]

Enable mipi dsi by default for rk3399-evb board

Signed-off-by: Eric Gao 

---

Changes in v3: None
Changes in v2:
-Add defconfigs for mipi display, so that it can be enabled by default.

 configs/evb-rk3399_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index cef8506..3405857 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -66,3 +66,9 @@ CONFIG_PMIC_CHILDREN=y
 CONFIG_SPL_PMIC_CHILDREN=y
 CONFIG_PMIC_RK808=y
 CONFIG_REGULATOR_RK808=y
+CONFIG_DM_VIDEO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-- 
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[U-Boot] [PATCH v3 09/11] rockchip: dts: Add mipi dsi support for rk3399

[Eric Gao]

Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.

Signed-off-by: Eric Gao 

---

Changes in v3: None
Changes in v2:
-Add dts config for mipi display.

 arch/arm/dts/rk3399-evb.dts | 84 +
 arch/arm/dts/rk3399.dtsi| 72 ++
 2 files changed, 156 insertions(+)

diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index e1f867b..3d6f3ce 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -59,6 +59,15 @@
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   status = "disabled";
+   };
+
+   panel:panel {
+   compatible = "simple-panel";
+   status = "disabled";
+   };
 };
 
 &emmc_phy {
@@ -141,6 +150,7 @@
status = "okay";
 
vcc12-supply = <&vcc3v3_sys>;
+
regulators {
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
@@ -151,6 +161,80 @@
};
 };
 
+&backlight {
+   power-supply = <&vccsys>;
+   enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+   brightness-levels = <
+ 0   1   2   3   4   5   6   7
+ 8   9  10  11  12  13  14  15
+16  17  18  19  20  21  22  23
+24  25  26  27  28  29  30  31
+32  33  34  35  36  37  38  39
+40  41  42  43  44  45  46  47
+48  49  50  51  52  53  54  55
+56  57  58  59  60  61  62  63
+64  65  66  67  68  69  70  71
+72  73  74  75  76  77  78  79
+80  81  82  83  84  85  86  87
+88  89  90  91  92  93  94  95
+96  97  98  99 100 101 102 103
+   104 105 106 107 108 109 110 111
+   112 113 114 115 116 117 118 119
+   120 121 122 123 124 125 126 127
+   128 129 130 131 132 133 134 135
+   136 137 138 139 140 141 142 143
+   144 145 146 147 148 149 150 151
+   152 153 154 155 156 157 158 159
+   160 161 162 163 164 165 166 167
+   168 169 170 171 172 173 174 175
+   176 177 178 179 180 181 182 183
+   184 185 186 187 188 189 190 191
+   192 193 194 195 196 197 198 199
+   200 201 202 203 204 205 206 207
+   208 209 210 211 212 213 214 215
+   216 217 218 219 220 221 222 223
+   224 225 226 227 228 229 230 231
+   232 233 234 235 236 237 238 239
+   240 241 242 243 244 245 246 247
+   248 249 250 251 252 253 254 255>;
+   default-brightness-level = <200>;
+   pwms = <&pwm0 0 25000 0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm0_pin>;
+   pwm-delay-us = <1>;
+   status = "okay";
+   };
+
+&panel {
+   power-supply = <&vcc33_lcd>;
+   backlight = <&backlight>;
+   /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
+   status = "okay";
+};
+
+&mipi_dsi {
+   status = "okay";
+   rockchip,panel = <&panel>;
+   display-timings {
+   timing0 {
+   bits-per-pixel = <24>;
+   clock-frequency = <16000>;
+   hfront-porch = <120>;
+   hsync-len = <20>;
+   hback-porch = <21>;
+   hactive = <1200>;
+   vfront-porch = <21>;
+   vsync-len = <3>;
+   vback-porch = <18>;
+   vactive = <1920>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <1>;
+   pixelclk-active = <0>;
+   };
+   };
+};
+
 &pinctrl {
pmic {
pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index d94d780..9344a43 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -684,6 +684,78 @@
status = "disabled";
};
 
+   vopl: vop@ff8f {
+   u-boot,dm-pre-reloc;
+   compatible = "rockchip,rk3399-vop-lit";
+   reg = <0x0 0xff8f 0x0 0x3efc>;
+   interrupts = ;
+   clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+   clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+   resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru 
SRST_D_VOP1>;
+  

Re: [U-Boot] [PATCH] usb: lpc32xx: Add i2c DM support

[Marek Vasut]

On 04/19/2017 02:24 PM, Sylvain Lemieux wrote:
> On Fri, 2017-04-14 at 16:01 +0200, Marek Vasut wrote:
>> On 03/14/2017 04:28 PM, Sylvain Lemieux wrote:
>>> From: Liam Beguin 
>>>
>>> Add DM support for i2c functions.
>>>
>>> Signed-off-by: Liam Beguin 
>>> Signed-off-by: Sylvain Lemieux 
>>> ---
>>> Note:
>>> * This patch is require as part of the DM support of the LPC32xx I2C driver.
>>>   All I2C drivers should be converted, to DM, by the end of June 2017.
>>>
>>> * The USB driver is supporting the DM and non-DM API.
>>>
>>> * This patch depend on the following patchset:
>>>   https://lists.denx.de/pipermail/u-boot/2017-March/283672.html
>>>
>>>  drivers/usb/host/ohci-lpc32xx.c | 33 +++--
>>>  1 file changed, 31 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/usb/host/ohci-lpc32xx.c 
>>> b/drivers/usb/host/ohci-lpc32xx.c
>>> index 9245126ed6..51be4c90c7 100644
>>> --- a/drivers/usb/host/ohci-lpc32xx.c
>>> +++ b/drivers/usb/host/ohci-lpc32xx.c
>>> @@ -14,8 +14,10 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  
>>>  /* OTG I2C controller module register structures */
>>>  struct otgi2c_regs {
>>> @@ -83,12 +85,35 @@ static struct clk_pm_regs *clk_pwr = (struct 
>>> clk_pm_regs *)CLK_PM_BASE;
>>>  
>>>  static int isp1301_set_value(int reg, u8 value)
>>>  {
>>> +#ifndef CONFIG_DM_I2C
>>> return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
>>> +#else
>>> +   struct udevice *dev;
>>> +   int ret;
>>> +
>>> +   ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR,
>>> + 1, &dev);
>>
>> I'd rather see you passing udevice around than requesting it on each
>> single i2c write.
>>
> Will do the change and submit a version 2.
> 
>>> +   if (ret)
>>> +   return ret;
>>> +
>>> +   return dm_i2c_write(dev, reg, &value, 1);
>>> +#endif
>>>  }
>>>  
>>> -static void isp1301_configure(void)
>>> +static int isp1301_configure(void)
>>>  {
>>> +#ifndef CONFIG_DM_I2C
>>> i2c_set_bus_num(I2C_2);
>>> +#else
>>> +   int ret;
>>> +   struct udevice *bus;
>>> +
>>> +   ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_2, &bus);
>>> +   if (ret) {
>>> +   debug("%s: No bus %d\n", __func__, I2C_2);
>>> +   return ret;
>>> +   }
>>> +#endif
>>>  
>>> /*
>>>  * LPC32XX only supports DAT_SE0 USB mode
>>> @@ -116,6 +141,8 @@ static void isp1301_configure(void)
>>>  
>>> /* Enable usb_need_clk clock after transceiver is initialized */
>>> setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
>>> +
>>> +   return 0;
>>>  }
>>>  
>>>  static int usbpll_setup(void)
>>> @@ -167,7 +194,9 @@ int usb_cpu_init(void)
>>> return ret;
>>>  
>>> /* Configure ISP1301 */
>>> -   isp1301_configure();
>>> +   ret = isp1301_configure();
>>> +   if (ret)
>>> +   return ret;
>>
>> Don't we need some sort of failpath now, to undo the changes ?
>>
> With the rework of the patch, this change is no longer needed.
> 

OK, super

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v3 05/11] rockchip: video: vop: Add mipi display mode for rk3399

[Eric Gao]

Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.

Signed-off-by: Eric Gao 

---

Changes in v3: None
Changes in v2:
-Add mipi display mode for vop.
-Add compatible items for rk3399 vop.

 arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
 drivers/video/rockchip/rk_vop.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 0ce3d67..d5599ec 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -90,6 +90,7 @@ enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
VOP_MODE_LVDS,
+   VOP_MODE_MIPI,
VOP_MODE_NONE,
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc02f80..84d6627 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -117,6 +117,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
V_RGB_OUT_EN(1));
break;
+   case VOP_MODE_MIPI:
+   clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
+   V_MIPI_OUT_EN(1));
+break;
}
 
if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
@@ -350,6 +354,8 @@ static const struct video_ops rk_vop_ops = {
 };
 
 static const struct udevice_id rk_vop_ids[] = {
+   { .compatible = "rockchip,rk3399-vop-big" },
+   { .compatible = "rockchip,rk3399-vop-lit" },
{ .compatible = "rockchip,rk3288-vop" },
{ }
 };
-- 
1.9.1


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[U-Boot] [PATCH v3 11/11] rockchip: video: vop: Fix rk_display_init() return error

[Eric Gao]

The function clk_set_rate() will return it's input parameter, so it's return
value in normal condition is nonzero. In this case, we should report error
when it return zero rather than return a nonzero value.

Signed-off-by: Eric Gao 
-Fix rk_display_init() function report error(err:-19).
---

Changes in v3:
-Improve indentation relationship

Changes in v2: None

 drivers/video/rockchip/rk_vop.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index ac9e7db..bd80b1b 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -245,13 +245,13 @@ int rk_display_init(struct udevice *dev, ulong fbbase, 
int ep_node)
}
 
ret = clk_get_by_index(dev, 1, &clk);
-   if (!ret)
+   if (!ret) {
ret = clk_set_rate(&clk, timing.pixelclock.typ);
-   if (ret) {
-   debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
-   return ret;
+   if (!ret) {
+   debug("%s: Failed to set pixel clock: ret=%d\n", 
__func__, ret);
+   return ret;
+   }
}
-
/* Set bitwidth for vop display according to vop mode */
switch (vop_id) {
case VOP_MODE_EDP:
-- 
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[U-Boot] [PATCH v3 03/11] rockchip: video: Makefile: Add mipi driver addition.

[Eric Gao]

Signed-off-by: Eric Gao 

---

Changes in v3:
-Split Makefile changes to a single patch.

Changes in v2: None

 drivers/video/rockchip/Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 3bb0519..2937e27 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -1,7 +1,7 @@
 #
-# (C) Copyright 2000-2007
+# (C) Copyright 2017
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
+# Eric Gao 
 # SPDX-License-Identifier: GPL-2.0+
 #
 
@@ -10,4 +10,5 @@ obj-y += rk_vop.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o
 endif
-- 
1.9.1


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[U-Boot] [PATCH v3 07/11] rockchip: video: vop: Reserve enough space for mipi dispaly

[Eric Gao]

plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.

Signed-off-by: Eric Gao 

---

Changes in v3:
-Add more description in the commit message

Changes in v2:
-Extend frame buffer size for mipi display

 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index a637f7d..ac9e7db 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -357,7 +357,7 @@ static int rk_vop_bind(struct udevice *dev)
 {
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 
-   plat->size = 1920 * 1080 * 2;
+   plat->size = 1920 * 1200 * 4;
 
return 0;
 }
-- 
1.9.1


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Re: [U-Boot] [PATCH v2] rockchip: reserve memory for rk3399 ATF data

[Andreas Färber]

Hi Kever,

Some grammar nits below:

Am 19.04.2017 um 08:42 schrieb Kever Yang:
> There are 3 region used by rk3399 ATF:

"regions"

> - bl31 code, locate at 0x1;
> - cortex-m0 code and data, locate at 0xff8c;
> - bl31 data, locate at 0xff8c1000 ~ 0xff8c4000;

3x "located"

> 
> SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
> for ATF data, or else there will have memory corrupt after SPL

"there will be" or "we will have"

> load ATF image.

"loads the" / "loaded the"

> 
> More detail about cortex-M0 code in ATF:
> https://github.com/ARM-software/arm-trusted-firmware/commit/
> 8382e17c4c6bffd15119dfce1ee4372e3c1a7890

Interesting!

> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v2:
> - use Kconfig for the reserved memory size
> 
>  arch/arm/include/asm/arch-rockchip/boot0.h | 4 
>  arch/arm/mach-rockchip/Kconfig | 8 
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h 
> b/arch/arm/include/asm/arch-rockchip/boot0.h
> index 8d7bc9a..7346876 100644
> --- a/arch/arm/include/asm/arch-rockchip/boot0.h
> +++ b/arch/arm/include/asm/arch-rockchip/boot0.h
> @@ -16,3 +16,7 @@
>   .space 0x4 /* space for the 'RK33' */
>  #endif
>   b reset
> +
> +#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
> + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
> +#endif
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index af0796d..979b48e 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -72,6 +72,14 @@ config ROCKCHIP_SPL_BACK_TO_BROM
>SPL will return to the boot rom, which will then load the U-Boot
>binary to keep going on.
>  
> +config ROCKCHIP_SPL_RESERVE_IRAM
> + hex "Size of IRAM reserved in SPL"
> + default 0x4000
> + help
> +   SPL may need reserve memory for firmware load by SPL, which load
> +   address is in IRAM and may overlay with SPL text area if not
> +   reserved.

"SPL may need to reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlap with SPL text area if not reserved."

> +
>  config ROCKCHIP_BROM_HELPER
>   bool
>  

Regards,
Andreas

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Re: [U-Boot] Pull request: u-boot-ubi/master

[Tom Rini]

On Tue, Apr 18, 2017 at 06:18:45AM +0200, Heiko Schocher wrote:

> Hello Tom,
> 
> please pull from u-boot-ubi.git master
> 
> The following changes since commit f6c1df44b815a08585e7fd3805a1db51a5955d09:
> 
>   Prepare v2017.05-rc2 (2017-04-17 18:16:49 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-ubi.git master
> 
> for you to fetch changes up to 18f41f2fa2d021f7baad37ba6fbe01b49309afbb:
> 
>   cmd: ubi: remove unnecessary logical constraint (2017-04-18 06:08:32 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-x86

[Tom Rini]

On Tue, Apr 18, 2017 at 04:12:34PM +0800, Bin Meng wrote:

> Hi Tom,
> 
> The following changes since commit f6c1df44b815a08585e7fd3805a1db51a5955d09:
> 
>   Prepare v2017.05-rc2 (2017-04-17 18:16:49 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git
> 
> for you to fetch changes up to 363f67a96b2b2f6ec5a211eddf349d7b76a09159:
> 
>   x86: config: Enable dhrystone command for link (2017-04-18 15:51:21 +0800)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[Tom Rini]

On Tue, Apr 18, 2017 at 08:32:48AM -0700, York Sun wrote:

> Tom,
> 
> The following changes since commit 3fea95369850987de15a2a0ac009d05e13b90246:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-video
> (2017-04-14 22:05:17 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-fsl-qoriq.git
> 
> for you to fetch changes up to e0dfec863e2ca5088dd797a5b6853d4c0df9002c:
> 
>   powerpc/board/t1024rdb: enable board-level reset when issuing
> reset command (2017-04-17 09:03:30 -0700)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 1/3] cmd: cramfs: use map_sysmem for sandbox support

[Tom Rini]

On Wed, Apr 12, 2017 at 04:29:15PM -0400, Tyler Hall wrote:

> As with most other commands, this needs to factor in the sysmem offset
> in the sandbox or it will try to dereference the simulated physical
> address directly.
> 
> Signed-off-by: Tyler Hall 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2,2/3] cramfs: block pointers are 32 bits

[Tom Rini]

On Wed, Apr 12, 2017 at 04:29:16PM -0400, Tyler Hall wrote:

> Using a variably-sized type is incorrect here since we're reading a
> fixed file format. Fixes cramfs on 64-bit platforms.
> 
> Signed-off-by: Tyler Hall 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v3, 1/3] ARM: import arm-smccc code from Linux 4.11-rc6

[Tom Rini]

On Fri, Apr 14, 2017 at 11:10:22AM +0900, Masahiro Yamada wrote:

> Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
> The files have been copied as follows:
> 
> [Linux]   [U-Boot]
> arch/arm/kernel/smccc-call.S   -> arch/arm/cpu/armv7/smccc-call.S
> arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
> arch/arm/include/asm/opcodes*  -> arch/arm/include/asm/opcodes*
> include/linux/arm-smccc.h  -> include/linux/arm-smccc.h
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] blackfin: ibf-dsp561: remove orphan Blackfin board

[Tom Rini]

On Fri, Apr 14, 2017 at 11:05:48AM +0900, Masahiro Yamada wrote:

> This is a Blackfin board that commit ea3310e8aafa ("Blackfin:
> Remove") missed to remove.
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/1] usbtty: avoid potential NULL pointer dereference

[Tom Rini]

On Sat, Apr 15, 2017 at 03:05:46PM +0200, xypron.g...@gmx.de wrote:

> If current_urb is NULL it should not be dereferenced.
> 
> The problem was indicated by cppcheck.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2,3/3] cramfs: basic symlink support

[Tom Rini]

On Wed, Apr 12, 2017 at 04:29:17PM -0400, Tyler Hall wrote:

> Handle symlinks to files in the current directory. Other cases could be
> handled with additional code, but this is a start.
> 
> Add explicit errors for absolute paths and links found in the middle of
> a path (directories). Other cases like '..' or '.' will result with the
> file not being found as when those path components are explicitly
> provided.
> 
> Add a helper to decompress a null-terminated link name which is shared
> with cramfs_list_inode.
> 
> Signed-off-by: Tyler Hall 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] board: Remove orphan SPARC boards

[Tom Rini]

On Tue, Apr 18, 2017 at 10:31:12AM -0400, Tom Rini wrote:

> Since 936478e797a8 SPARC as been removed as an architecture.  Remove
> these now orphan boards.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] arm: omap-common: add missing va_end()

[Tom Rini]

On Sat, Apr 15, 2017 at 12:29:20PM +0200, xypron.g...@gmx.de wrote:

> Each call of va_start must be matched by a call of va_end.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] tools: moveconfig: remove GCC prefix of obsolete architecture

[Tom Rini]

On Fri, Apr 14, 2017 at 10:53:56AM +0900, Masahiro Yamada wrote:

> Recently, U-Boot removed support for these architectures.
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v3, 3/3] sysreset: psci: support system reset in a generic way with PSCI

[Tom Rini]

On Fri, Apr 14, 2017 at 11:10:24AM +0900, Masahiro Yamada wrote:

> If the system is running PSCI firmware, the System Reset function
> (func ID: 0x8009) is supposed to be handled by PSCI, that is,
> the SoC/board specific reset implementation should be moved to PSCI.
> U-Boot should call the PSCI service according to the arm-smccc
> manner.
> 
> The arm-smccc is supported on ARMv7 or later.  Especially, ARMv8
> generation SoCs are likely to run ARM Trusted Firmware BL31.  In
> this case, U-Boot is a non-secure world boot loader, so it should
> not be able to reset the system directly.
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] FPGA: drivers/fpga/ivm_core.c: incorrect printf

[Tom Rini]

On Sat, Apr 15, 2017 at 03:15:40PM +0200, xypron.g...@gmx.de wrote:

> The number of arguments for printf does not match the
> format string.
> 
> The problem was indicated by cppcheck.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] drivers/crypto/fsl: remove redundant logical contraint

[Tom Rini]

On Sat, Apr 15, 2017 at 04:37:54PM +0200, xypron.g...@gmx.de wrote:

> 'A || (!A && B)' is equivalent to 'A || B'.
> Let's reduce the complexity of the statement in start_jr0().
> 
> The problem was indicated by cppcheck.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: York Sun 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/3] buildman: Allow 'gnueabihf' toolchains for ARM

[Tom Rini]

On Fri, Apr 14, 2017 at 07:47:50PM -0400, Tom Rini wrote:

> Many toolchains for ARM use the 'gnueabihf' suffix rather than just
> 'gnueabi', so allow these to be used, but with a lower priority than
> 'gnueabi' ones.
> 
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> Reviewed-by: Simon Glass 

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Re: [U-Boot] [U-Boot, v3, 2/3] ARM: adjust arm-smccc code for use in U-Boot

[Tom Rini]

On Fri, Apr 14, 2017 at 11:10:23AM +0900, Masahiro Yamada wrote:

> Adjust ARM SMC Calling Convention code for U-Boot:
>   - Replace the license block with SPDX
>   - Change path to asm-offsets.h
>   - Define UNWIND() as no-op
>   - Add Kconfig entry
>   - Add asm-offsets
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 1/1] tools/env: avoid memory leak in fw_setenv

[Tom Rini]

On Sat, Apr 15, 2017 at 01:05:40PM +0200, xypron.g...@gmx.de wrote:

> If realloc fails we should release the old buffer.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 2/2] drivers: remove Blackfin specific drivers

[Tom Rini]

On Fri, Apr 14, 2017 at 10:55:00AM +0900, Masahiro Yamada wrote:

> These drivers have no user since commit ea3310e8aafa ("Blackfin:
> Remove").
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Simon Glass 
> Acked-by: Michal Simek 
> Acked-by: Jaehoon Chung 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,1/2] cmd: remove Blackfin specific commands

[Tom Rini]

On Fri, Apr 14, 2017 at 10:54:59AM +0900, Masahiro Yamada wrote:

> These commands have no user since commit ea3310e8aafa ("Blackfin:
> Remove").
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,1/1] yaffs2: remove redundant condition

[Tom Rini]

On Sat, Apr 15, 2017 at 01:28:13PM +0200, xypron.g...@gmx.de wrote:

> If !parent, the changed line is not reached.
> So there is no need to check the value again.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] ddr: fsl: incorrect logical constraint in populate_memctl_options

[Tom Rini]

On Sat, Apr 15, 2017 at 03:23:49PM +0200, xypron.g...@gmx.de wrote:

> (pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
> is always true.
> 
> We should use && here.
> 
> The problem was indicated by cppcheck.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Tom Rini 
> Reviewed-by: York Sun 

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Re: [U-Boot] [U-Boot, 2/3] travis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARM

[Tom Rini]

On Fri, Apr 14, 2017 at 07:47:51PM -0400, Tom Rini wrote:

> Linaro provides a number of pre-built GCC toolchains for both 32 and
> 64bit ARM.  Switch to their 2017.02 release of gcc-6.3.1 for both.
> 
> Cc: Koen Kooi 
> Signed-off-by: Tom Rini 

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Re: [U-Boot] [U-Boot, v2] rockchip: Print a message when returning to the bootrom

[Tom Rini]

On Sat, Apr 15, 2017 at 01:11:31PM -0600, Simon Glass wrote:

> At present if the return to bootrom fails (e.g. because you are not using
> the Rockchip's bootrom's pointer table in MMC) then the board prints
> SPL message and hangs. Print a message first if we can, to help in
> understanding what happened when it hangs.
> 
> Signed-off-by: Simon Glass 
> Tested-by: Heiko Stuebner 
> Acked-by: Heiko Stuebner 

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