[U-Boot] [PATCH v3 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-18 Thread Nathan Rossi
Currently most boards that have static memory config (which cannot be
detected automatically) use CONFIG_SYS_SDRAM_SIZE to define the size of
memory which is hard coded into U-Boot. With the addition of device tree
support into U-Boot, boards that have device tree data can instead query
the memory bank information from the embedded or appended device tree.
This allows for more dynamic memory configuration and avoids the need to
hard code memory configuration into U-Boot.

The first patch of this series adds two helper functions for handling
the memory bank decoding and initialization of global data which can be
used by boards in their dram_init and dram_init_banksize functions. The
purpose of these helper functions is to provide generic functions that
handle the decoding and setup of memory and memory banks for boards that
intend to use this mechanism.

The series also changes the zynq and zynqmp board implementations to use
these functions to resolve a issue with static variable use.

Changes in v2:
 * Make fdtdec_setup_memory_banksize() return value consistent
 * Add more detail into the function documentation

Changes in v3:
 * Wrap the fdtdec_setup_memory_banksize() function with an #if on
   CONFIG_NR_DRAM_BANKS, so that the function is only available for
   configs that have memory banks available in bd_t.

Nathan Rossi (3):
  fdt: add memory bank decoding functions for board setup
  ARM: zynq: Replace board specific with generic memory bank decoding
  ARM64: zynqmp: Replace board specific with generic memory bank
decoding

 board/xilinx/zynq/board.c| 112 ++-
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 include/fdtdec.h |  34 +
 lib/fdtdec.c |  56 ++
 4 files changed, 96 insertions(+), 218 deletions(-)

-- 
2.11.0
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[U-Boot] [PATCH v3 1/3] fdt: add memory bank decoding functions for board setup

2016-12-18 Thread Nathan Rossi
Add two functions for use by board implementations to decode the memory
banks of the /memory node so as to populate the global data with
ram_size and board info for memory banks.

The fdtdec_setup_memory_size() function decodes the first memory bank
and sets up the gd->ram_size with the size of the memory bank. This
function should be called from the boards dram_init().

The fdtdec_setup_memory_banksize() function decode the memory banks
(up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
into the gd->bd->bi_dram array of banks. This function should be called
from the boards dram_init_banksize().

Signed-off-by: Nathan Rossi 
Cc: Simon Glass 
Cc: Michal Simek 
Reviewed-by: Simon Glass 
---
v2:
 * Make fdtdec_setup_memory_banksize() return value consistent
 * Add more detail into the function documentation
v3:
 * Wrap the fdtdec_setup_memory_banksize() function with an #if on
   CONFIG_NR_DRAM_BANKS, so that the function is only available for
   configs that have memory banks available in bd_t.

This implementation of decoding has been tested on zynq and zynqmp
boards with address/size cells of (1, 1), (1, 2), (2, 1), (2, 2) and
up to 2 memory banks.
---
 include/fdtdec.h | 34 ++
 lib/fdtdec.c | 56 
 2 files changed, 90 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27887c8c21..d074478f14 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -976,6 +976,40 @@ struct display_timing {
  */
 int fdtdec_decode_display_timing(const void *blob, int node, int index,
 struct display_timing *config);
+
+/**
+ * fdtdec_setup_memory_size() - decode and setup gd->ram_size
+ *
+ * Decode the /memory 'reg' property to determine the size of the first memory
+ * bank, populate the global data with the size of the first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size instead of
+ * hard coding the value in the case where the memory size cannot be detected
+ * automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_size(void);
+
+/**
+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks.
+ *
+ * This function should be called from a boards dram_init_banksize(). This
+ * helper function allows for boards to query the device tree for memory bank
+ * information instead of hard coding the information in cases where it cannot
+ * be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_banksize(void);
+
 /**
  * Set up the device tree ready for use
  */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4e619c49a2..81f47ef2c7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1174,6 +1174,62 @@ int fdtdec_decode_display_timing(const void *blob, int 
parent, int index,
return ret;
 }
 
+int fdtdec_setup_memory_size(void)
+{
+   int ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, &res);
+   if (ret != 0) {
+   debug("%s: Unable to decode first memory bank\n", __func__);
+   return -EINVAL;
+   }
+
+   gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+   debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+   return 0;
+}
+
+#if defined(CONFIG_NR_DRAM_BANKS)
+int fdtdec_setup_memory_banksize(void)
+{
+   int bank, ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
+   if (ret == -FDT_ERR_NOTFOUND)
+   break;
+   if (ret != 0)
+   return -EINVAL;
+
+   gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
+   gd->bd->bi_dram[bank].size =
+   (phys_size_t)(res.end - res.start + 1);
+
+   debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
+ __func__, bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start,
+ (unsigned long long)gd->bd->bi_dram[b

[U-Boot] [PATCH v3 3/3] ARM64: zynqmp: Replace board specific with generic memory bank decoding

2016-12-18 Thread Nathan Rossi
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT")
Cc: Michal Simek 
---
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index cef1f6a13a..8a3d0043b9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -180,121 +180,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, &cell[i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, &cell[i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
-   debug("Bank #%d: size %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].size);
-   }
+   fdtdec_setup_memory_banksize();
 }
 
 int dram_init(void)
 {
-   int node, len;
-   const void *blob = gd->fdt_blob;
-   const u32 *cell;
-
-   memset(&tmp, 0, sizeof(tmp));
-
-   /* find or create "/memory" node. */
-   node = fdt_subnode_offset(blob, 0, "memory");
-   if (node < 0) {
-   printf("%s: Can't get memory node\n", __func__);
-   return node;
-   }
-
-   /* Get pointer to cells and lenght of it */
-   cell = fdt_getprop(blob, node, "reg", &len);
-   if (!cell) {
-   printf("%s: Can't get reg property\n", __func__);
-   return -1

[U-Boot] [PATCH v3 2/3] ARM: zynq: Replace board specific with generic memory bank decoding

2016-12-18 Thread Nathan Rossi
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This unsafe use of a static variable was causing a specific bug when
using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the 'image' variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.

   Uncompressing Invalid Image ... Unimplemented compression type 23

It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow. Depending on the
size of various sections, and location of relocations within __rel_dyn
and the compiler/linker the outcome of this bug can differ greatly.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek 
---
 board/xilinx/zynq/board.c | 112 ++
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 2c86940957..5cd9bbf711 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -124,121 +124,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, &cell[i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, &cell[i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
-   

[U-Boot] [PATCH] rockchip: Fix veyron-minnie's Kconfig description

2016-12-18 Thread Martin Michlmayr
The veyron-minnie Kconfig referred to jerry by mistake.

Signed-off-by: Martin Michlmayr 
---
 arch/arm/mach-rockchip/rk3288/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index 223ae41..54545f3 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -61,7 +61,7 @@ config TARGET_CHROMEBIT_MICKEY
 config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
help
- Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0
+ Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
  ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
  HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
  EC (Cortex-M3) to provide access to the keyboard and battery
-- 
2.1.4

-- 
Martin Michlmayr
http://www.cyrius.com/
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Re: [U-Boot] [PATCH 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

2016-12-18 Thread Masahiro Yamada
2016-12-15 15:08 GMT+09:00 Zhiqiang Hou :
> From: Mingkai Hu 
>
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> For A57/A72, SMPEN bit enables the processor to receive instruction
> cache and TLB maintenance operations broadcast from other processors
> in the cluster. This bit should be set before enabling the caches and
> MMU, or performing any cache and TLB maintenance operations.
>
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 
> Signed-off-by: Mateusz Kulikowski 
> Signed-off-by: Hou Zhiqiang 
> ---
>  arch/arm/cpu/armv8/Kconfig | 12 
>  arch/arm/cpu/armv8/start.S | 11 +++
>  2 files changed, 23 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index 965a8d1..ce749f2 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -3,6 +3,18 @@ if ARM64
>  config ARMV8_MULTIENTRY
>  bool "Enable multiple CPUs to enter into U-Boot"
>
> +config ARMV8_SET_SMPEN
> +bool "Enable data coherency with other cores in cluster"
> +help
> +  Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
> +  for single core systems. Unfortunately write access to this
> +  register may be controlled by EL3/EL2 firmware. To be more
> +  precise, by default (if there is EL2/EL3 firmware running)
> +  this register is RO for NS EL1.
> +  This switch can be used to avoid writing to CPUECTLR_EL1,
> +  it can be safely enabled when El2/EL3 initialized SMPEN bit
> +  or when CPU implementation doesn't include that register.
> +


If you run ARM Trusted Firmware, this bit has already been
set correctly. (or if you implement your own trusted firmware,
this bit should be set there.)
In those cases, there is no need to touch it in U-Boot.


The motivation for this commit is
to boot the system without any firmware before U-Boot?




-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PULL] Please pull u-boot-imx

2016-12-18 Thread Stefano Babic
Hi Tom,

please pull from u-boot-imx, thanks !

The following changes since commit 53e8ca22538c2cec691fe74098684a359302688c:

  MAINTAINERS: DFU: Change e-mail address for DFU maintainer (2016-12-12
13:03:15 -0500)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 854bb75be98ad792ff64c26ae38a1392ea185cd6:

  imx6: icorem6_rqs: Add FEC support (2016-12-16 18:39:06 +0100)


Breno Lima (10):
  Revert "ARM: mx6: add MMC2 boot device detection support in SPL"
  udoo_neo: Remove USDHC3 support
  udoo_neo: Move MX6SX configuration to Kconfig
  udoo_neo: Staticize board_string()
  udoo_neo: Remove mmcautodetect option
  udoo_neo: Remove console option
  udoo_neo: Add thermal support
  power: pmic: Add Voltage configuration macro
  udoo_neo: Add PFUZE300 PMIC support
  udoo_neo: Add Ethernet support

Jagan Teki (29):
  net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr
  net: fec_mxc: Convert into driver model
  net: fec_mxc: Driver cleanups
  dm: net: fec: Add .read_rom_hwaddr
  ARM: dts: imx6qdl-icore: Add FEC support
  icorem6: Use CONFIG_DM_ETH support
  video: Kconfig: Add VIDEO_IPV3 entry
  imx6: icorem6: Add framebuffer support
  imx6: icorem6: Add custom splashscreen support
  i2c: Kconfig: Add SYS_I2C_MXC entry
  i2c: mxc: Print hex instead of decimal for bus address
  i2c: mxc: Make 'no gpio pinctrl state' print as debug
  imx6: icorem6: Add I2C support
  arm: dts: Add devicetree for i.MX6UL
  arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support
  arm: dts: imx6ul-geam: Add I2C nodes
  imx6: geam6ul: Add I2C support
  imx6: geam6ul: Add NAND support
  imx6: geam6ul: Enable MTD device support
  imx6: geam6ul: Add default mtd nand partition table
  arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial
support
  arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit
initial support
  imx6: icorem6: Rename engicam icorem6 defconfig files
  arm: dts: imx6qdl-icore-rqs: Add I2C node's
  imx6: icorem6_rqs: Add I2C support
  arm: dts: imx6ul-geam: Add FEC node
  imx6: geam6ul: Add FEC support
  arm: dts: imx6qdl-icore-rqs: Add FEC node
  imx6: icorem6_rqs: Add FEC support

Marcin Niestroj (2):
  ARM: imx6ul: Add support for liteSOM
  board/liteboard: Add support for liteBoard

Max Krummenacher (2):
  arm: imx: initial support for apalis imx6
  arm: imx: initial support for colibri imx6

Patrick Bruenn (1):
  arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC

Peng Fan (19):
  imx: add i.MX 6SLL CPU type
  imx: mx6sll: add pinmux header files
  imx: mx6sll: update register address
  imx-common: timer: add i.MX6SLL support
  imx: mx6sll: add iomux settings
  imx: mx6: fix mmdc ch0 clk for 6SL
  imx: mx6: lcdif: gate clock before changing mux
  imx: mx6sl: add lcdif clock support
  imx: clock: gate clk before changing pix clk mux
  imx: mx6sll: add clock support
  imx-common: cache: configure L2 Cache for i.MX6SLL
  imx: mx6sll: add Kconfig entry for i.MX6SLL
  mx6_common: correct loadaddr and text base for i.MX6SLL
  OCOTP: Update OCOTP driver to support i.MX6SLL
  imx-common: lcdif: update lcdif regs for i.MX6SL/SLL
  pinctrl: imx6: support i.MX6SLL
  arm: dts: add i.MX6SLL device tree
  arm: imx: add i.MX6SLL EVK board support
  imx: mx6sllevk: add plugin support

Sanchayan Maity (1):
  configs: colibri_vf: Add fdt_fixup environment variable

Stefan Agner (6):
  toradex: fix USB Download gadget fixup callback
  toradex: allow custom fdt board setup in board file
  colibri_vf: use device-tree for MTD partitions
  colibri_vf: cleanup USB clock initialization
  colibri_vf: use same NAND clock as Linux uses
  ARM: dts: vf: Fix warning about missing reg property

Stefano Babic (1):
  Merge branch 'master' of git://git.denx.de/u-boot

 arch/arm/Kconfig|2 +
 arch/arm/Makefile   |1 +
 arch/arm/cpu/armv7/mx5/Kconfig  |8 +
 arch/arm/cpu/armv7/mx6/Kconfig  |   63 ++
 arch/arm/cpu/armv7/mx6/clock.c  |  143 ++-
 arch/arm/dts/Makefile   |8 +-
 arch/arm/dts/imx53-cx9020.dts   |  190 
 arch/arm/dts/imx53-pinfunc.h| 1189
+++
 arch/arm/dts/imx53.dtsi |  110 +++
 arch/arm/dts/imx6dl-icore-rqs.dts   |   50 +
 arch/arm/dts/imx6q-icore-rqs.dts|   50 +
 arch/arm/dts/imx6qdl-icore-rqs.dtsi 

[U-Boot] [PATCH v3 00/26] sunxi: Allwinner A64: SPL support

2016-12-18 Thread Andre Przywara
Hi,

another reworked version of the SPL support series for the Allwinner A64
SoC. Again many thanks to the diligent reviewers, I hope I didn't miss any
comments.
As the previous versions this one includes support for both AArch64 and
AArch32 SPL builds. The FIT support is still missing, which means the
functionality is limited. Due to the missing ARM Trusted Firmware (ATF)
in this firmware chain we lose Ethernet and SMP, among other minor things.
A full 64-bit build can be written to an SD card as expected and will
boot the U-Boot proper prompt. However Linux will crash on boot, as
PSCI is missing.
Building the 32-bit version of the SPL and combining this with an ATF
build and the 64-bit U-Boot proper allows to use FEL booting now:
# sunxi-fel spl sunxi-spl.bin write 0x4a00 u-boot-dtb.bin \
  write 0x44000 bl31.bin reset64 0x44000
This way of booting the board gives full functionality.

The first patch is a rather simple fix (with no changes to v2).
Patches 2-8 prepare the SPL code to be compiled for 64-bit in general and
AArch64 in particular.
Patches 9-11 refactor the existing boot0 header functionality to be used
by patch 12, which introduces the 64-bit switch in the first SPL
instructions.
Patches 13-20 then introduce the actual core of the SPL support: the DRAM
initialization, courtesy of Jens. This piggy backs on the existing
H3 DRAM code, deviating where needed. This has been reworked compared to
v2: I added a patch from Philipp to replace the rather uninspired
register writes in the MBUS priority setup function with some meaningful
code, explaining the various bits. Also the actual A64 DRAM code is no
longer #ifdef'ed into the H3 driver, but uses parameters to (static)
functions. The compiler detects this and removes the dead code from
the other variant, resulting in the same binary size for the H3.

Patch 21 finally enables the 64-bit SPL support. So now building the
existing pine64_plus_defconfig will generate a sunxi-spl.bin, which
can be prepended to the U-Boot proper image (not .bin) to boot from
an SD card. Due to the missing ATF support this is of limited usability
at the moment, though. Also FEL support requires more love - to switch
back to AArch32 before returning to FEL (without crashing, that is ;-),
so this is disabled.
On my setup this results in a 26KB SPL binary, which is close to the
28K limit mksunxiboot imposes at the moment. Adding anything (like
FIT support or DEBUG) will exceed this, and although I have patches
to let mksunxiboot get close to 32KB, this is the ulimate frontier.

So patches 22-25 then teach the SPL how to detect an U-Boot image file
of a different bitness and do the RMR switch from AArch32 to AArch64,
if needed.
This is used by the final patch 26, which creates another _defconfig
to let the SPL compile for AArch32 using the Thumb2 encoding. This
results in a binary of less than 17KB in my case, so has plenty of
room for extensions.

Cheers,
Andre.

Changelog v2 .. v3:
- add various Reviewed-by: and Acked-by: tags
- split tiny-printf fix to handle "-" separately
- add various comments and extend commit messages
- add assembly file to re-create the embedded RMR switch code
- add patch 14/26 to explain the MBUS priority setup
- move DRAM r/w delay values into #defines to simplify re-usablity
- replace #ifdef'ed addition of A64 support to the H3 DRAM driver with an
  approach using static parameters

Changelog v1 .. v2:
- drop SPI build fix (already merged)
- confine A31 register init change to H3 and A64
- use IS_ENABLED() instead of #idef to guard MBUS2 clock init
- fix tiny-printf (proper sign extension for 32-bit integers)
- add "size" output in commit msg to document tiny-printf size impact
- fix sdelay(): use only one register, add "cc" clobber
- update RMR switch code to provide easy access to RVBAR register address
- drop redundant DRAM frequency setting from Pine64 defconfig
- minor changes as requested by reviewers

Andre Przywara (21):
  sun6i: Restrict some register initialization to Allwinner A31 SoC
  armv8: prevent using THUMB
  armv8: add lowlevel_init.S
  SPL: tiny-printf: add "l" modifier
  SPL: tiny-printf: ignore "-" modifier
  move UL() macro from armv8/mmu.h into common.h
  SPL: make struct spl_image 64-bit safe
  armv8: add simple sdelay implementation
  armv8: move reset branch into boot hook
  ARM: boot0 hook: remove macro, include whole header file
  sunxi: introduce extra config option for boot0 header
  sunxi: A64: do an RMR switch if started in AArch32 mode
  sunxi: provide default DRAM config for sun50i in Kconfig
  sunxi: H3/A64: fix non-ODT setting
  sunxi: DRAM: fix H3 DRAM size display on aarch64
  sunxi: A64: enable SPL
  SPL: read and store arch property from U-Boot image
  Makefile: use "arm64" architecture for U-Boot image files
  ARM: SPL/FIT: differentiate between arm and arm64 arch properties
  sunxi: introduce RMR switch to enter payloads in 64-bit mode
  sunxi: A64: add 32-bit SPL support

Jens Kuske (3):
  sunxi: H3:

[U-Boot] [PATCH v3 02/26] armv8: prevent using THUMB

2016-12-18 Thread Andre Przywara
The predominantely 32-bit ARM targets try to compile the SPL in Thumb
mode to reduce code size.
The 64-bit AArch64 instruction set does not know an alternative, concise
encoding, so the Thumb build option should only be set for 32-bit
targets.
Likewise -marm machine options are only valid for ARMv7 targets.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Acked-by: Maxime Ripard 
---
 arch/arm/lib/Makefile  | 2 ++
 include/configs/sunxi-common.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0051f76..024139d 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -77,8 +77,10 @@ ifndef CONFIG_HAS_THUMB2
 
 # for C files, just apend -marm, which will override previous -mthumb*
 
+ifndef CONFIG_ARM64
 CFLAGS_cache.o := -marm
 CFLAGS_cache-cp15.o := -marm
+endif
 
 # For .S, drop -mthumb* and other thumb-related options.
 # CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b0bfc0d..e05c318 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -35,7 +35,7 @@
 /*
  * High Level Configuration Options
  */
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
 #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
 #endif
 
-- 
2.8.2

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[U-Boot] [PATCH v3 03/26] armv8: add lowlevel_init.S

2016-12-18 Thread Andre Przywara
For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even with a
64-bit SPL.

Signed-off-by: Andre Przywara 
---
 arch/arm/cpu/armv8/Makefile|  1 +
 arch/arm/cpu/armv8/lowlevel_init.S | 44 ++
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..799a752 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
diff --git a/arch/arm/cpu/armv8/lowlevel_init.S 
b/arch/arm/cpu/armv8/lowlevel_init.S
new file mode 100644
index 000..189e35f
--- /dev/null
+++ b/arch/arm/cpu/armv8/lowlevel_init.S
@@ -0,0 +1,44 @@
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(lowlevel_init)
+   /*
+* Setup a temporary stack. Global data is not available yet.
+*/
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   ldr w0, =CONFIG_SPL_STACK
+#else
+   ldr w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+   bic sp, x0, #0xf/* 16-byte alignment for ABI compliance */
+
+   /*
+* Save the old LR(passed in x29) and the current LR to stack
+*/
+   stp x29, x30, [sp, #-16]!
+
+   /*
+* Call the very early init function. This should do only the
+* absolute bare minimum to get started. It should not:
+*
+* - set up DRAM
+* - use global_data
+* - clear BSS
+* - try to start a console
+*
+* For boards with SPL this should be empty since SPL can do all of
+* this init in the SPL board_init_f() function which is called
+* immediately after this.
+*/
+   bl  s_init
+   ldp x29, x30, [sp]
+   ret
+ENDPROC(lowlevel_init)
-- 
2.8.2

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[U-Boot] [PATCH v3 01/26] sun6i: Restrict some register initialization to Allwinner A31 SoC

2016-12-18 Thread Andre Przywara
These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
the proper voltage seems to be a property of older SoCs only as well.

Restrict the MBUS initialization to this SoC only to avoid writing bogus
values to (undefined) registers in other chips.
I can only verify that the PLL voltage setup is not needed for H3 and
A64, so for now we only spare those two SoCs.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Chen-Yu Tsai 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index ed8cd9b..80cfc0b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -21,6 +21,8 @@ void clock_init_safe(void)
 {
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
@@ -31,6 +33,7 @@ void clock_init_safe(void)
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+#endif
 
clock_set_pll1(40800);
 
@@ -41,7 +44,8 @@ void clock_init_safe(void)
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
 
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
-   writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+   if (IS_ENABLED(CONFIG_MACH_SUN6I))
+   writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
 }
 #endif
 
-- 
2.8.2

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[U-Boot] [PATCH v3 06/26] move UL() macro from armv8/mmu.h into common.h

2016-12-18 Thread Andre Przywara
The UL() macro is pretty useful in sharing constants between assembly
and C files while still being able to specify a type for C.
Move the macro from an armv8 specific header into a common header file
to be able to use it by arm code (for instance) as well.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
---
 arch/arm/include/asm/armv8/mmu.h |  8 
 include/common.h | 13 -
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index aa0f3c4..e9b4cdb 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -8,14 +8,6 @@
 #ifndef _ASM_ARMV8_MMU_H_
 #define _ASM_ARMV8_MMU_H_
 
-#ifdef __ASSEMBLY__
-#define _AC(X, Y)  X
-#else
-#define _AC(X, Y)  (X##Y)
-#endif
-
-#define UL(x)  _AC(x, UL)
-
 /***/
 /*
  * The following definitions are related each other, shoud be
diff --git a/include/common.h b/include/common.h
index a8d833b..ee0436b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -15,6 +15,9 @@ typedef volatile unsigned longvu_long;
 typedef volatile unsigned short vu_short;
 typedef volatile unsigned char vu_char;
 
+/* Allow sharing constants with type modifiers between C and assembly. */
+#define _AC(X, Y)   (X##Y)
+
 #include 
 #include 
 #include 
@@ -936,7 +939,12 @@ int cpu_disable(int nr);
 int cpu_release(int nr, int argc, char * const argv[]);
 #endif
 
-#endif /* __ASSEMBLY__ */
+#else  /* __ASSEMBLY__ */
+
+/* Drop a C type modifier (like in 3UL) for constants used in assembly. */
+#define _AC(X, Y)   X
+
+#endif /* __ASSEMBLY__ */
 
 #ifdef CONFIG_PPC
 /*
@@ -948,6 +956,9 @@ int cpu_release(int nr, int argc, char * const argv[]);
 
 /* Put only stuff here that the assembler can digest */
 
+/* Declare an unsigned long constant digestable both by C and an assembler. */
+#define UL(x)   _AC(x, UL)
+
 #ifdef CONFIG_POST
 #define CONFIG_HAS_POST
 #ifndef CONFIG_POST_ALT_LIST
-- 
2.8.2

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[U-Boot] [PATCH v3 07/26] SPL: make struct spl_image 64-bit safe

2016-12-18 Thread Andre Przywara
Since entry_point and load_addr are addresses, they should be
represented as longs to cover the whole address space and to avoid
warning when compiling the SPL in 64-bit.
Also adjust debug prints to add the 'l' specifier, where needed.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-omap2/boot-common.c | 2 +-
 arch/arm/mach-tegra/spl.c | 2 +-
 common/spl/spl.c  | 8 
 common/spl/spl_mmc.c  | 2 +-
 include/spl.h | 4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/boot-common.c 
b/arch/arm/mach-omap2/boot-common.c
index 385310b..7ae3d80 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -228,7 +228,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
 
u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
 
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
image_entry((u32 *)boot_params);
 }
diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c
index e0f9d5b..41c88cb 100644
--- a/arch/arm/mach-tegra/spl.c
+++ b/arch/arm/mach-tegra/spl.c
@@ -42,7 +42,7 @@ u32 spl_boot_device(void)
 
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
 
start_cpu((u32)spl_image->entry_point);
halt_avp();
diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834..a76ea3a 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -115,7 +115,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
}
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
-   debug("spl: payload image: %.*s load addr: 0x%x size: %d\n",
+   debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
spl_image->load_addr, spl_image->size);
} else {
@@ -140,7 +140,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
spl_image->entry_point = CONFIG_SYS_LOAD_ADDR;
spl_image->size = end - start;
-   debug("spl: payload zImage, load addr: 0x%x size: %d\n",
+   debug("spl: payload zImage, load addr: 0x%lx size: 
%d\n",
  spl_image->load_addr, spl_image->size);
return 0;
}
@@ -164,9 +164,9 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
 
image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+   (image_entry_noargs_t)spl_image->entry_point;
 
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
image_entry();
 }
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 85e3de8..0cd355c 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -36,7 +36,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, 
struct mmc *mmc,
/* Read the header too to avoid extra memcpy */
count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
  (void *)(ulong)spl_image->load_addr);
-   debug("read %x sectors to %x\n", image_size_sectors,
+   debug("read %x sectors to %lx\n", image_size_sectors,
  spl_image->load_addr);
if (count != image_size_sectors)
return -EIO;
diff --git a/include/spl.h b/include/spl.h
index 6e746b2..bde4437 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -23,8 +23,8 @@
 struct spl_image_info {
const char *name;
u8 os;
-   u32 load_addr;
-   u32 entry_point;
+   ulong load_addr;
+   ulong entry_point;
u32 size;
u32 flags;
 };
-- 
2.8.2

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[U-Boot] [PATCH v3 05/26] SPL: tiny-printf: ignore "-" modifier

2016-12-18 Thread Andre Przywara
tiny-printf does not know about the "-" modifier, which aligns numbers.
This is used by some SPL code, but as it's purely cosmetical, we just
ignore this modifier here to avoid changing correct printf strings.

Signed-off-by: Andre Przywara 
---
 lib/tiny-printf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0b8512f..dfa8432 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -69,6 +69,9 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
bool islong = false;
 
ch = *(fmt++);
+   if (ch == '-')
+   ch = *(fmt++);
+
if (ch == '0') {
ch = *(fmt++);
lz = 1;
-- 
2.8.2

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[U-Boot] [PATCH v3 04/26] SPL: tiny-printf: add "l" modifier

2016-12-18 Thread Andre Przywara
tiny-printf does not know about the "l" modifier so far, which breaks
the crash dump on AArch64, because it uses %lx to print the registers.
Add an easy way of handling longs correctly.

Using a relatively decent compiler (GCC 5.3.0) this does _not_ increase
the code size of tiny-printf.o for 32-bit builds (where long and int
are actually the same), actually it looses three (ARM Thumb2) instructions
from the actual SPL (numbers for orangepi_plus_defconfig):
  textdata bss dec hex filename
   758   0   0 758 2f6 spl/lib/tiny-printf.obefore
 18839 488 232   195594c67 spl/u-boot-spl   before
   758   0   0 758 2f6 spl/lib/tiny-printf.oafter
 18833 488 232   195534c61 spl/u-boot-spl   after

This adds some substantial amount of code to a 64-bit build, though:
(taken after a later commit, which enables the ARM64 SPL build for sunxi)
  textdata bss dec hex filename
  1542   0   01542 606 spl/lib/tiny-printf.obefore
 25830 392 360   2658267d6 spl/u-boot-spl   before
  1758   0   01758 6de spl/lib/tiny-printf.oafter
 26040 392 360   2679268a8 spl/u-boot-spl   after

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 lib/tiny-printf.c | 47 ---
 1 file changed, 36 insertions(+), 11 deletions(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 30ac759..0b8512f 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -38,8 +38,8 @@ static void out_dgt(struct printf_info *info, char dgt)
info->zs = 1;
 }
 
-static void div_out(struct printf_info *info, unsigned int *num,
-   unsigned int div)
+static void div_out(struct printf_info *info, unsigned long *num,
+   unsigned long div)
 {
unsigned char dgt = 0;
 
@@ -56,9 +56,9 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
 {
char ch;
char *p;
-   unsigned int num;
+   unsigned long num;
char buf[12];
-   unsigned int div;
+   unsigned long div;
 
while ((ch = *(fmt++))) {
if (ch != '%') {
@@ -66,6 +66,7 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
} else {
bool lz = false;
int width = 0;
+   bool islong = false;
 
ch = *(fmt++);
if (ch == '0') {
@@ -80,6 +81,11 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
ch = *fmt++;
}
}
+   if (ch == 'l') {
+   ch = *(fmt++);
+   islong = true;
+   }
+
info->bf = buf;
p = info->bf;
info->zs = 0;
@@ -89,24 +95,43 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
goto abort;
case 'u':
case 'd':
-   num = va_arg(va, unsigned int);
-   if (ch == 'd' && (int)num < 0) {
-   num = -(int)num;
-   out(info, '-');
+   div = 10;
+   if (islong) {
+   num = va_arg(va, unsigned long);
+   if (sizeof(long) > 4)
+   div *= div * 10;
+   } else {
+   num = va_arg(va, unsigned int);
+   }
+
+   if (ch == 'd') {
+   if (islong && (long)num < 0) {
+   num = -(long)num;
+   out(info, '-');
+   } else if (!islong && (int)num < 0) {
+   num = -(int)num;
+   out(info, '-');
+   }
}
if (!num) {
out_dgt(info, 0);
} else {
-   for (div = 10; div; div /= 10)
+   for (; div; div /= 10)
div_out(info, &num, div);
}
break;
case 'x':
-   num = va_arg(va, unsigned int);

[U-Boot] [PATCH v3 10/26] ARM: boot0 hook: remove macro, include whole header file

2016-12-18 Thread Andre Przywara
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/cpu/armv8/start.S | 1 -
 arch/arm/include/asm/arch-bcm235xx/boot0.h | 8 +---
 arch/arm/include/asm/arch-bcm281xx/boot0.h | 8 +---
 arch/arm/include/asm/arch-sunxi/boot0.h| 8 +---
 arch/arm/lib/vectors.S | 1 -
 5 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index ee393d7..140609d 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -26,7 +26,6 @@ _start:
  * use it here.
  */
 #include 
-ARM_SOC_BOOT0_HOOK
 #else
b   reset
 #endif
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h 
b/arch/arm/include/asm/arch-bcm235xx/boot0.h
index 7e72882..9ff90b8 100644
--- a/arch/arm/include/asm/arch-bcm235xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   .word   0xbabeface; \
+   .word   0xbabeface;
.word   _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h 
b/arch/arm/include/asm/arch-bcm281xx/boot0.h
index 7e72882..9ff90b8 100644
--- a/arch/arm/include/asm/arch-bcm281xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   .word   0xbabeface; \
+   .word   0xbabeface;
.word   _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6f28d63..6a13db5 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* reserve space for BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   b   reset;  \
+   b   reset
.space  1532
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 5cc132b..9fe7415 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -67,7 +67,6 @@ _start:
  * use it here.
  */
 #include 
-ARM_SOC_BOOT0_HOOK
 #endif
 
 /*
-- 
2.8.2

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[U-Boot] [PATCH v3 09/26] armv8: move reset branch into boot hook

2016-12-18 Thread Andre Przywara
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, just refactoring to simplify
upcoming patches.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/cpu/armv8/start.S  | 4 ++--
 arch/arm/include/asm/arch-sunxi/boot0.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4f5f6d8..ee393d7 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,8 +19,6 @@
 
 .globl _start
 _start:
-   b   reset
-
 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
 /*
  * Various SoCs need something special and SoC-specific up front in
@@ -29,6 +27,8 @@ _start:
  */
 #include 
 ARM_SOC_BOOT0_HOOK
+#else
+   b   reset
 #endif
 
.align 3
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index ea5675e..6f28d63 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -9,6 +9,7 @@
 
 /* reserve space for BOOT0 header information */
 #define ARM_SOC_BOOT0_HOOK \
+   b   reset;  \
.space  1532
 
 #endif /* __BOOT0_H */
-- 
2.8.2

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[U-Boot] [PATCH v3 08/26] armv8: add simple sdelay implementation

2016-12-18 Thread Andre Przywara
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.

Signed-off-by: Andre Przywara 
---
 arch/arm/cpu/armv8/cpu.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..c093ae7 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -16,6 +16,20 @@
 #include 
 #include 
 
+/*
+ * sdelay() - simple spin loop.
+ *
+ * Will delay execution by roughly (@loops * 2) cycles.
+ * This is necessary to be used before timers are accessible.
+ *
+ * A value of "0" will results in 2^64 loops.
+ */
+void sdelay(unsigned long loops)
+{
+   __asm__ volatile ("1:\n" "subs %0, %0, #1\n"
+ "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
+}
+
 int cleanup_before_linux(void)
 {
/*
-- 
2.8.2

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[U-Boot] [PATCH v3 11/26] sunxi: introduce extra config option for boot0 header

2016-12-18 Thread Andre Przywara
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
Reviewed-by: Simon Glass 
---
 board/sunxi/Kconfig   | 9 +
 configs/pine64_plus_defconfig | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab1..0cd57a2 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -133,6 +133,15 @@ config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || 
MACH_SUN8I_A83T
 
+config RESERVE_ALLWINNER_BOOT0_HEADER
+   bool "reserve space for Allwinner boot0 header"
+   select ENABLE_ARM_SOC_BOOT0_HOOK
+   ---help---
+   Prepend a 1536 byte (empty) header to the U-Boot image file, to be
+   filled with magic values post build. The Allwinner provided boot0
+   blob relies on this information to load and execute U-Boot.
+   Only needed on 64-bit Allwinner boards so far when using boot0.
+
 config DRAM_TYPE
int "sunxi dram type"
depends on MACH_SUN8I_A83T
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6d0198f..ea53b96 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
-- 
2.8.2

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[U-Boot] [PATCH v3 12/26] sunxi: A64: do an RMR switch if started in AArch32 mode

2016-12-18 Thread Andre Przywara
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.

By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.

We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.

Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.

Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/boot0.h | 30 
 arch/arm/mach-sunxi/rmr_switch.S| 41 +
 board/sunxi/Kconfig | 14 +++
 3 files changed, 85 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/rmr_switch.S

diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6a13db5..9c6d82d 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,6 +4,36 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && 
!defined(CONFIG_SPL_BUILD)
 /* reserve space for BOOT0 header information */
b   reset
.space  1532
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+   tst x0, x0  // this is "b #0x84" in ARM
+   b   reset
+   .space  0x7c
+   .word   0xe59f1024  // ldr r1, [pc, #36] ; 0x17a0
+   .word   0xe59f0024  // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+   .word   0xe581  // str r0, [r1]
+   .word   0xf57ff04f  // dsb sy
+   .word   0xf57ff06f  // isb sy
+   .word   0xee1c0f50  // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
+   .word   0xe383  // orr r0, r0, #3
+   .word   0xee0c0f50  // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
+   .word   0xf57ff06f  // isb sy
+   .word   0xe320f003  // wfi
+   .word   0xeafd  // b   @wfi
+   .word   0x017000a0  // writeable RVBAR mapping address
+#ifdef CONFIG_SPL_BUILD
+   .word   CONFIG_SPL_TEXT_BASE
+#else
+   .word   CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+   b   reset
+#endif
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
new file mode 100644
index 000..cefa930
--- /dev/null
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -0,0 +1,41 @@
+@
+@ ARMv8 RMR reset sequence on Allwinner SoCs.
+@
+@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
+@ exectute the Boot ROM in this state), so we need to switch to AArch64
+@ at some point.
+@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
+@ (RMR), which triggers a warm-reset of a core and can request to switch
+@ into a different execution state (AArch32 or AArch64).
+@ The address at which execution starts after the reset is held in the
+@ RVBAR system register, which is architecturally read-only.
+@ Allwinner provides a writable alias of this register in MMIO space, so
+@ we can easily set the start address of AArch64 code.
+@ This code below switches to AArch64 and starts execution at the specified
+@ start address. It needs to be assembled by an ARM(32) assembler and
+@ the machine code must be inserted as verbatim .word statements into the
+@ beginning of the AArch64 U-Boot code.
+@ To get the encoded bytes, use:
+@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}objdump -d rmr_switch.o
+@
+@ The resulting words should be inserted into the U-Boot file at
+@ arch/arm/include/asm/arch-sunxi/boot0.h.
+@
+@ This file is not build by the U-Boot build system, but provided only as a
+@ reference and to be able to regenerate a (probably fixed) version of this
+@ code found in encoded form in boot0.h.
+
+.text
+
+   ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
+   ldr r0, =0x57aA7add @ start address, to be replaced
+   str r0, [r1]
+   dsb sy
+   isb sy
+   mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
+   orr r0, r0, #3  @ request reset in AArch64
+   mcr 

[U-Boot] [PATCH v3 13/26] sunxi: provide default DRAM config for sun50i in Kconfig

2016-12-18 Thread Andre Przywara
To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 board/sunxi/Kconfig   | 2 ++
 configs/pine64_plus_defconfig | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index f020573..c2eb85e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -168,6 +168,7 @@ config DRAM_CLK
default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+   default 672 if MACH_SUN50I
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
must be a multiple of 24. For the sun9i (A80), the tested values
@@ -187,6 +188,7 @@ config DRAM_ZQ
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 4145117 if MACH_SUN9I
+   default 3881915 if MACH_SUN50I
---help---
Set the dram zq value.
 
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index ea53b96..ebc24b8 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -2,8 +2,6 @@ CONFIG_ARM=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
-CONFIG_DRAM_CLK=672
-CONFIG_DRAM_ZQ=3881915
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
-- 
2.8.2

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[U-Boot] [PATCH v3 14/26] sunxi: H3: Rework MBUS priority setup

2016-12-18 Thread Andre Przywara
From: Philipp Tomsich 

So far the MBUS priority setup was done by writing "magic" values taken
from a DRAM controller register dump after a boot0 run.
By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP
kernel, we learned more about the actual meaning of those bits.
Add macros and refactor the setup function to make the MBUS setup much
more readable and meaningful.
The actual values used now are a transformation of the values used
before, which are assembled by the new code to result in the same register
writes. So this rework does not change any settings, also the code size
stays the same.

The respective source files in the BSP kernel had a proper GPL header,
so lifting this code and information into U-Boot is legal.

[Andre: provide a convenience macro to fit definitions on one line]

[1] 
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c

Signed-off-by: Philipp Tomsich 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 88 +++--
 1 file changed, 64 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index b08b8e6..8925446 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -94,6 +94,58 @@ static void mctl_dq_delay(u32 read, u32 write)
udelay(1);
 }
 
+enum {
+   MBUS_PORT_CPU   = 0,
+   MBUS_PORT_GPU   = 1,
+   MBUS_PORT_UNUSED= 2,
+   MBUS_PORT_DMA   = 3,
+   MBUS_PORT_VE= 4,
+   MBUS_PORT_CSI   = 5,
+   MBUS_PORT_NAND  = 6,
+   MBUS_PORT_SS= 7,
+   MBUS_PORT_TS= 8,
+   MBUS_PORT_DI= 9,
+   MBUS_PORT_DE= 10,
+   MBUS_PORT_DE_CFD= 11,
+};
+
+enum {
+   MBUS_QOS_LOWEST = 0,
+   MBUS_QOS_LOW,
+   MBUS_QOS_HIGH,
+   MBUS_QOS_HIGHEST
+};
+
+inline void mbus_configure_port(u8 port,
+   bool bwlimit,
+   bool priority,
+   u8 qos, /* MBUS_QOS_LOWEST .. 
MBUS_QOS_HIGEST */
+   u8 waittime,/* 0 .. 0xf */
+   u8 acs, /* 0 .. 0xff */
+   u16 bwl0,   /* 0 .. 0x, bandwidth limit 
in MB/s */
+   u16 bwl1,
+   u16 bwl2)
+{
+   struct sunxi_mctl_com_reg * const mctl_com =
+   (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+   const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
+  | (priority ? (1 << 1) : 0)
+  | ((qos & 0x3) << 2)
+  | ((waittime & 0xf) << 4)
+  | ((acs & 0xff) << 8)
+  | (bwl0 << 16) );
+   const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0x);
+
+   debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
+   writel(cfg0, &mctl_com->mcr[port][0]);
+   writel(cfg1, &mctl_com->mcr[port][1]);
+}
+
+#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)   \
+   mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
+   MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
+
 static void mctl_set_master_priority(void)
 {
struct sunxi_mctl_com_reg * const mctl_com =
@@ -105,30 +157,18 @@ static void mctl_set_master_priority(void)
/* set cpu high priority */
writel(0x0001, &mctl_com->mapr);
 
-   writel(0x020d, &mctl_com->mcr[0][0]);
-   writel(0x00800100, &mctl_com->mcr[0][1]);
-   writel(0x0609, &mctl_com->mcr[1][0]);
-   writel(0x01000400, &mctl_com->mcr[1][1]);
-   writel(0x020d, &mctl_com->mcr[2][0]);
-   writel(0x00600100, &mctl_com->mcr[2][1]);
-   writel(0x010d, &mctl_com->mcr[3][0]);
-   writel(0x00200080, &mctl_com->mcr[3][1]);
-   writel(0x0709, &mctl_com->mcr[4][0]);
-   writel(0x01000640, &mctl_com->mcr[4][1]);
-   writel(0x010d, &mctl_com->mcr[5][0]);
-   writel(0x00200080, &mctl_com->mcr[5][1]);
-   writel(0x0109, &mctl_com->mcr[6][0]);
-   writel(0x00400080, &mctl_com->mcr[6][1]);
-   writel(0x010d, &mctl_com->mcr[7][0]);
-   writel(0x00400080, &mctl_com->mcr[7][1]);
-   writel(0x010d, &mctl_com->mcr[8][0]);
-   writel(0x00400080, &mctl_com->mcr[8][1]);
-   writel(0x0409, &mctl_com->mcr[9][0]);
-   writel(0x00400100, &mctl_com->mcr[9][1]);
-   writel(0x230d, &mctl_com->mcr[10][0]);
-   writel(0x04001800, &mctl_com->mcr[10][1]);
-   writel(0x0409, &mctl_com->mcr[11][0]);
-   writel(0x00400120, &mctl_com->mcr[11][1]);
+   MBUS_CONF(   CPU,  true, HIGHEST, 0,  512,  256,  128);
+   MBUS_CONF(   GPU,  true,HIGH, 0, 1536, 1024,  256);
+   MBUS_CONF(UNUSED,  true, HIGH

[U-Boot] [PATCH v3 15/26] sunxi: H3: add and rename some DRAM contoller registers

2016-12-18 Thread Andre Przywara
From: Jens Kuske 

The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 43 ++---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 34 +--
 2 files changed, 41 insertions(+), 36 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h 
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index d0f2b8a..346538c 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -106,20 +106,23 @@ struct sunxi_mctl_ctl_reg {
u32 perfhpr[2]; /* 0x1c4 */
u32 perflpr[2]; /* 0x1cc */
u32 perfwr[2];  /* 0x1d4 */
-   u8 res8[0x2c];  /* 0x1dc */
-   u32 aciocr; /* 0x208 */
-   u8 res9[0xf4];  /* 0x20c */
+   u8 res8[0x24];  /* 0x1dc */
+   u32 acmdlr; /* 0x200 AC master delay line register */
+   u32 aclcdlr;/* 0x204 AC local calibrated delay line 
register */
+   u32 aciocr; /* 0x208 AC I/O configuration register */
+   u8 res9[0x4];   /* 0x20c */
+   u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
+   u8 res10[0x74]; /* 0x28c */
struct {/* 0x300 DATX8 modules*/
-   u32 mdlr;   /* 0x00 */
-   u32 lcdlr[3];   /* 0x04 */
-   u32 iocr[11];   /* 0x10 IO configuration register */
-   u32 bdlr6;  /* 0x3c */
-   u32 gtr;/* 0x40 */
-   u32 gcr;/* 0x44 */
-   u32 gsr[3]; /* 0x48 */
+   u32 mdlr;   /* 0x00 master delay line register */
+   u32 lcdlr[3];   /* 0x04 local calibrated delay line 
registers */
+   u32 bdlr[12];   /* 0x10 bit delay line registers */
+   u32 gtr;/* 0x40 general timing register */
+   u32 gcr;/* 0x44 general configuration register 
*/
+   u32 gsr[3]; /* 0x48 general status registers */
u8 res0[0x2c];  /* 0x54 */
-   } datx[4];
-   u8 res10[0x388];/* 0x500 */
+   } dx[4];
+   u8 res11[0x388];/* 0x500 */
u32 upd2;   /* 0x888 */
 };
 
@@ -172,14 +175,16 @@ struct sunxi_mctl_ctl_reg {
 
 #define PGSR_INIT_DONE (0x1 << 0)  /* PHY init done */
 
-#define ZQCR_PWRDOWN   (0x1 << 31) /* ZQ power down */
+#define ZQCR_PWRDOWN   (1U << 31)  /* ZQ power down */
 
-#define DATX_IOCR_DQ(x)(x) /* DQ0-7 IOCR index */
-#define DATX_IOCR_DM   (8) /* DM IOCR index */
-#define DATX_IOCR_DQS  (9) /* DQS IOCR index */
-#define DATX_IOCR_DQSN (10)/* DQSN IOCR index */
+#define ACBDLR_WRITE_DELAY(x)  ((x) << 8)
 
-#define DATX_IOCR_WRITE_DELAY(x)   ((x) << 8)
-#define DATX_IOCR_READ_DELAY(x)((x) << 0)
+#define DXBDLR_DQ(x)   (x) /* DQ0-7 BDLR index */
+#define DXBDLR_DM  8   /* DM BDLR index */
+#define DXBDLR_DQS 9   /* DQS BDLR index */
+#define DXBDLR_DQSN10  /* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x)  ((x) << 8)
+#define DXBDLR_READ_DELAY(x)   ((x) << 0)
 
 #endif /* _SUNXI_DRAM_SUN8I_H3_H */
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 8925446..539268f 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -72,21 +72,21 @@ static void mctl_dq_delay(u32 read, u32 write)
u32 val;
 
for (i = 0; i < 4; i++) {
-   val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
+   val = DXBDLR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
+ DXBDLR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
 
-   for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
-   writel(val, &mctl_ctl->datx[i].iocr[j]);
+   for (j = DXBDLR_DQ(0); j <= DXBDLR_DM; j++)
+   writel(val, &mctl_ctl->dx[i].bdlr[j]);
}
 
clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
 
for (i = 0; i < 4; i++) {
-   val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+   val = DXBDLR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
+ DXBDLR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
 
-   writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
-   writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
+   writel(val, &mctl_ctl->dx[i].bdlr

[U-Boot] [PATCH v3 17/26] sunxi: clocks: Use the correct pattern register for PLL11

2016-12-18 Thread Andre Przywara
From: Philipp Tomsich 

Signed-off-by: Philipp Tomsich 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 80cfc0b..8e39bbe 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -224,7 +224,7 @@ void clock_set_pll11(unsigned int clk, bool 
sigma_delta_enable)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
if (sigma_delta_enable)
-   writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
+   writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
 
writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
   (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
-- 
2.8.2

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[U-Boot] [PATCH v3 16/26] sunxi: H3: add DRAM controller single bit delay support

2016-12-18 Thread Andre Przywara
From: Jens Kuske 

So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
well) only applied coarse delay line settings, with one delay value for
all the data lines in each byte lane and one value for the control lines.

Instead of setting the delays for whole bytes only allow setting it for
each individual bit. Also add support for address/command lane delays.

For the purpose of this patch the rules for the existing coarse settings
were just applied to the new scheme, so the actual register writes don't
change for the H3. Other SoCs will utilize this feature later properly.

With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from
2296 to 2344 Bytes.

[Andre: move delay parameters into macros to ease later sharing, use
defines for numbers of delay registers, extend commit message]

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 65 ++---
 1 file changed, 38 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 539268f..f89ce5c 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -15,13 +15,19 @@
 #include 
 #include 
 
+#define BITS_PER_BYTE  8
+#define NR_OF_BYTE_LANES   (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
+
 struct dram_para {
-   u32 read_delays;
-   u32 write_delays;
u16 page_size;
u8 bus_width;
u8 dual_rank;
u8 row_bits;
+   const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 ac_delays[31];
 };
 
 static inline int ns_to_t(int nanoseconds)
@@ -64,34 +70,25 @@ static void mctl_phy_init(u32 val)
mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
 }
 
-static void mctl_dq_delay(u32 read, u32 write)
+static void mctl_set_bit_delays(struct dram_para *para)
 {
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
int i, j;
-   u32 val;
-
-   for (i = 0; i < 4; i++) {
-   val = DXBDLR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DXBDLR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
-
-   for (j = DXBDLR_DQ(0); j <= DXBDLR_DM; j++)
-   writel(val, &mctl_ctl->dx[i].bdlr[j]);
-   }
 
clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
 
-   for (i = 0; i < 4; i++) {
-   val = DXBDLR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DXBDLR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+   for (i = 0; i < NR_OF_BYTE_LANES; i++)
+   for (j = 0; j < LINES_PER_BYTE_LANE; j++)
+   writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
+  DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
+  &mctl_ctl->dx[i].bdlr[j]);
 
-   writel(val, &mctl_ctl->dx[i].bdlr[DXBDLR_DQS]);
-   writel(val, &mctl_ctl->dx[i].bdlr[DXBDLR_DQSN]);
-   }
+   for (i = 0; i < 31; i++)
+   writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
+  &mctl_ctl->acbdlr[i]);
 
setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
-
-   udelay(1);
 }
 
 enum {
@@ -412,11 +409,8 @@ static int mctl_channel_init(struct dram_para *para)
clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
(para->dual_rank ? 0x3 : 0x1) << 24);
 
-
-   if (para->read_delays || para->write_delays) {
-   mctl_dq_delay(para->read_delays, para->write_delays);
-   udelay(50);
-   }
+   mctl_set_bit_delays(para);
+   udelay(50);
 
mctl_zq_calibration(para);
 
@@ -490,6 +484,22 @@ static void mctl_auto_detect_dram_size(struct dram_para 
*para)
break;
 }
 
+#define SUN8I_H3_DX_READ_DELAYS\
+   {{ 18, 18, 18, 18, 18, 18, 18, 18, 18,  0,  0 },\
+{ 14, 14, 14, 14, 14, 14, 14, 14, 14,  0,  0 },\
+{ 18, 18, 18, 18, 18, 18, 18, 18, 18,  0,  0 },\
+{ 14, 14, 14, 14, 14, 14, 14, 14, 14,  0,  0 }}
+#define SUN8I_H3_DX_WRITE_DELAYS   \
+   {{  0,  0,  0,  0,  0,  0,  0,  0,  0, 10, 10 },\
+{  0,  0,  0,  0,  0,  0,  0,  0,  0, 10, 10 },\
+{  0,  0,  0,  0,  0,  0,  0,  0,  0, 10, 10 },\
+{  0,  0,  0,  0,  0,  0,  0,  0,  0,  6,  6 }}
+#define SUN8I_H3_AC_DELAYS \
+   {  0,  0,  0,  0,  0,  0,  0,  0,   \
+  0,  0,  0,  0,  0,  0,  0,  0,   \
+  0,  0,  0,  0,  0,  0,  0,  0,   \
+  0,  0

[U-Boot] [PATCH v3 22/26] SPL: read and store arch property from U-Boot image

2016-12-18 Thread Andre Przywara
Read the specified "arch" value from a legacy or FIT U-Boot image and
store it in our SPL data structure.
This allows loaders to take the target architecture in account for
custom loading procedures.
Having the complete string -> arch mapping for FIT based images in the
SPL would be too big, so we leave it up to architectures (or boards) to
overwrite the weak function that does the actual translation, possibly
covering only the required subset there.
Document struct spl_image_info on the way.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 common/spl/spl.c |  1 +
 common/spl/spl_fit.c |  8 
 include/spl.h| 15 ++-
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index a76ea3a..ef195e0 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -114,6 +114,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
header_size;
}
spl_image->os = image_get_os(header);
+   spl_image->arch = image_get_arch(header);
spl_image->name = image_get_name(header);
debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f..a5d903b 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -123,6 +123,11 @@ static int get_aligned_image_size(struct spl_load_info 
*info, int data_size,
return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+__weak u8 spl_genimg_get_arch_id(const char *arch_str)
+{
+   return IH_ARCH_DEFAULT;
+}
+
 int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
 {
@@ -136,6 +141,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int src_sector;
void *dst, *src;
+   const char *arch_str;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -184,10 +190,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
data_offset = fdt_getprop_u32(fit, node, "data-offset");
data_size = fdt_getprop_u32(fit, node, "data-size");
load = fdt_getprop_u32(fit, node, "load");
+   arch_str = fdt_getprop(fit, node, "arch", NULL);
debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
spl_image->load_addr = load;
spl_image->entry_point = load;
spl_image->os = IH_OS_U_BOOT;
+   spl_image->arch = spl_genimg_get_arch_id(arch_str);
 
/*
 * Work out where to place the image. We read it so that the first
diff --git a/include/spl.h b/include/spl.h
index bde4437..8223f4b 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -20,13 +20,26 @@
 #define MMCSD_MODE_FS  2
 #define MMCSD_MODE_EMMCBOOT3
 
+/*
+ * Information about an U-Boot image file as described in include/image.h.
+ * Parsed by the SPL code from a legacy or FIT image file.
+ *
+ * @name: descriptive string (mkimage -n)
+ * @load_addr: address to load the image file to (mkimage -a)
+ * @entry_point: address of first instruction to execute (mkimage -e)
+ * @size: size of image in bytes
+ * @flags: optional, used only for SPL_COPY_PAYLOAD_ONLY so far
+ * @os: target operating system, one of IH_OS_* (mkimage -O)
+ * @arch: target architecture, one of IH_ARCH_* (mkimage -A)
+ */
 struct spl_image_info {
const char *name;
-   u8 os;
ulong load_addr;
ulong entry_point;
u32 size;
u32 flags;
+   u8 os;
+   u8 arch;
 };
 
 /*
-- 
2.8.2

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[U-Boot] [PATCH v3 19/26] sunxi: H3/A64: fix non-ODT setting

2016-12-18 Thread Andre Przywara
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 6ee73ae..1bdd738 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -438,7 +438,7 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
(0x3 << 14),
-   IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+   IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x20);
 
/* AC PDR should always ON */
setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
-- 
2.8.2

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[U-Boot] [PATCH v3 18/26] sunxi: A64: use H3 DRAM initialization code for A64 as well

2016-12-18 Thread Andre Przywara
From: Jens Kuske 

The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
This refactoring does not change the code size for the existing H3 part.

[Andre: rework from #ifdefs to using socid parameters in static
functions, minor fixes, merging in fixes from Jens]

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h   |   1 +
 arch/arm/include/asm/arch-sunxi/cpu.h   |   3 +
 arch/arm/include/asm/arch-sunxi/dram.h  |   2 +-
 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h |  10 +-
 arch/arm/mach-sunxi/Makefile|   1 +
 arch/arm/mach-sunxi/clock_sun6i.c   |   2 +-
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 211 ++--
 7 files changed, 174 insertions(+), 56 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index be9fcfd..3f87672 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -322,6 +322,7 @@ struct sunxi_ccm_reg {
 #define CCM_DRAMCLK_CFG_DIV0_MASK  (0xf << 8)
 #define CCM_DRAMCLK_CFG_SRC_PLL5   (0x0 << 20)
 #define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL11  (0x1 << 20) /* A64 only */
 #define CCM_DRAMCLK_CFG_SRC_MASK   (0x3 << 20)
 #define CCM_DRAMCLK_CFG_UPD(0x1 << 16)
 #define CCM_DRAMCLK_CFG_RST(0x1 << 31)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 73583ed..6f96a97 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -13,4 +13,7 @@
 #include 
 #endif
 
+#define SOCID_A64  0x1689
+#define SOCID_H3   0x1680
+
 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h 
b/arch/arm/include/asm/arch-sunxi/dram.h
index e0be744..53e6d47 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
 #include 
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include 
-#elif defined(CONFIG_MACH_SUN8I_H3)
+#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 #include 
 #elif defined(CONFIG_MACH_SUN9I)
 #include 
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h 
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index 346538c..25d07d9 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -15,7 +15,8 @@
 
 struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
-   u8 res0[0xc];   /* 0x04 */
+   u8 res0[0x8];   /* 0x04 */
+   u32 tmr;/* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr;   /* 0x90 bandwidth control register */
u32 maer;   /* 0x94 master enable register */
@@ -32,7 +33,9 @@ struct sunxi_mctl_com_reg {
u32 swoffr; /* 0xc4 */
u8 res2[0x8];   /* 0xc8 */
u32 cccr;   /* 0xd0 */
-   u8 res3[0x72c]; /* 0xd4 */
+   u8 res3[0x54];  /* 0xd4 */
+   u32 mdfs_bwlr[3];   /* 0x128 (unused on H3) */
+   u8 res4[0x6cc]; /* 0x134 */
u32 protect;/* 0x800 */
 };
 
@@ -81,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
u32 rfshtmg;/* 0x90 refresh timing */
u32 rfshctl1;   /* 0x94 */
u32 pwrtmg; /* 0x98 */
-   u8  res3[0x20]; /* 0x9c */
+   u8 res3[0x1c];  /* 0x9c */
+   u32 vtfcr;  /* 0xb8 (unused on H3) */
u32 dqsgmr; /* 0xbc */
u32 dtcr;   /* 0xc0 */
u32 dtar[4];/* 0xc4 */
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index e73114e..7daba11 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -50,4 +50,5 @@ obj-$(CONFIG_MACH_SUN8I_A33)  += dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
+obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 8e39bbe..d123b3a 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -217,7 +217,7 @@ done:
 }
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 {
struct sunxi_ccm_reg * const ccm =
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index f89ce5c..6ee73ae 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -13,6 +13,7 @@
 #incl

[U-Boot] [PATCH v3 21/26] sunxi: A64: enable SPL

2016-12-18 Thread Andre Przywara
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We disable FEL support for now by making its compilation conditional
and disabling it for ARM64, as the code isn't ready yet.

Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/board.c| 2 +-
 board/sunxi/Kconfig| 2 ++
 configs/pine64_plus_defconfig  | 1 +
 include/configs/sunxi-common.h | 2 ++
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index aa11493..52be5b0 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -133,7 +133,7 @@ static int gpio_init(void)
return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
 static int spl_board_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
 {
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c2eb85e..0001133 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -125,6 +125,7 @@ config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
 
 endchoice
 
@@ -196,6 +197,7 @@ config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
+   default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
 
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index ebc24b8..2374170 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN50I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index e05c318..ab2d33f 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -183,7 +183,9 @@
 
 #define CONFIG_SPL_FRAMEWORK
 
+#ifndef CONFIG_ARM64   /* AArch64 FEL support is not ready yet */
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
+#endif
 
 #if defined(CONFIG_MACH_SUN9I)
 #define CONFIG_SPL_TEXT_BASE   0x10040 /* sram start+header */
-- 
2.8.2

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[U-Boot] [PATCH v3 20/26] sunxi: DRAM: fix H3 DRAM size display on aarch64

2016-12-18 Thread Andre Przywara
Fix the output of the DRAM size on AArch64 SPLs.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 1bdd738..cfc8479 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -646,6 +646,6 @@ unsigned long sunxi_dram_init(void)
mctl_auto_detect_dram_size(¶);
mctl_set_cr(¶);
 
-   return (1 << (para.row_bits + 3)) * para.page_size *
+   return (1UL << (para.row_bits + 3)) * para.page_size *
(para.dual_rank ? 2 : 1);
 }
-- 
2.8.2

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[U-Boot] [PATCH v3 26/26] sunxi: A64: add 32-bit SPL support

2016-12-18 Thread Andre Przywara
When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
use the more compact Thumb2 encoding, which only exists for AArch32
code. This makes the SPL rather big, up to a point where any code
additions or even a different compiler may easily exceed the 32KB limit
that the Allwinner BROM imposes.
Introduce a separate, mostly generic sun50i-a64 configuration, which
defines the CPU_V7 symbol and thus will create a 32-bit binary using
the memory-saving Thumb2 encoding.
This should only be used for the SPL, the U-Boot proper should still be
using the existing 64-bit configuration. The SPL code can switch to
AArch64 if needed, so a 32-bit SPL can be combined with a 64-bit U-Boot
proper to eventually launch arm64 kernels.

Signed-off-by: Andre Przywara 
---
 board/sunxi/Kconfig| 14 --
 configs/pine64_plus_defconfig  |  2 +-
 configs/sun50i_spl32_defconfig | 10 ++
 3 files changed, 23 insertions(+), 3 deletions(-)
 create mode 100644 configs/sun50i_spl32_defconfig

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 0001133..0d77c3a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -43,6 +43,10 @@ config SUNXI_GEN_SUN6I
watchdog, etc.
 
 
+config MACH_SUN50I
+   bool
+   select SUNXI_GEN_SUN6I
+
 choice
prompt "Sunxi SoC Variant"
optional
@@ -121,10 +125,16 @@ config MACH_SUN9I
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
 
-config MACH_SUN50I
+config MACH_SUN50I_64
bool "sun50i (Allwinner A64)"
+   select MACH_SUN50I
select ARM64
-   select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
+
+config MACH_SUN50I_32
+   bool "sun50i (Allwinner A64) SPL-32bit"
+   select MACH_SUN50I
+   select CPU_V7
select SUPPORT_SPL
 
 endchoice
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 2374170..a76f66a 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN50I=y
+CONFIG_MACH_SUN50I_64=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
diff --git a/configs/sun50i_spl32_defconfig b/configs/sun50i_spl32_defconfig
new file mode 100644
index 000..29c6a47
--- /dev/null
+++ b/configs/sun50i_spl32_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_32=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-- 
2.8.2

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[U-Boot] [PATCH v3 25/26] sunxi: introduce RMR switch to enter payloads in 64-bit mode

2016-12-18 Thread Andre Przywara
The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
To run AArch64 code, we have to trigger a warm reset via the RMR register,
which proceeds with code execution at the address stored in the RVBAR
register.
If the bootable payload in the FIT image is using a different
architecture than the SPL has been compiled for, enter it via this said
RMR switch mechanism, by writing the entry point address into the MMIO
mapped, writable version of the RVBAR register.
Then the warm reset is triggered via a system register write.
If the payload architecture is the same as the SPL, we use the normal
branch as usual.

Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/Makefile |  1 +
 arch/arm/mach-sunxi/spl_switch.c | 81 
 2 files changed, 82 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/spl_switch.c

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba11..128091e 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -51,4 +51,5 @@ obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUN50I)  += spl_switch.o
 endif
diff --git a/arch/arm/mach-sunxi/spl_switch.c b/arch/arm/mach-sunxi/spl_switch.c
new file mode 100644
index 000..855379e
--- /dev/null
+++ b/arch/arm/mach-sunxi/spl_switch.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2016 ARM Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+
+static void __noreturn jump_to_image_native(struct spl_image_info *spl_image)
+{
+   typedef void __noreturn (*image_entry_noargs_t)(void);
+
+   image_entry_noargs_t image_entry =
+   (image_entry_noargs_t)spl_image->entry_point;
+
+   image_entry();
+}
+
+/*
+ * Do a warm-reset via the RMR register to enter the processor in a different
+ * execution mode. This allows to switch from AArch32 to AArch64 and vice
+ * versa. Execution starts at the address hold in the RVBAR register, which
+ * needs to be set before.
+ */
+static void __noreturn reset_rmr_switch(void)
+{
+#ifdef CONFIG_ARM64
+   __asm__ volatile ( "mrs  x0, RMR_EL3\n\t"
+  "bic  x0, x0, #1\n\t"   /* Clear enter-in-64 bit */
+  "orr  x0, x0, #2\n\t"   /* set reset request bit */
+  "msr  RMR_EL3, x0\n\t"
+  "isb  sy\n\t"
+  "nop\n\t"
+  "wfi\n\t"
+  "b.\n"
+  ::: "x0");
+#else
+   __asm__ volatile ( "mrc  15, 0, r0, cr12, cr0, 2\n\t"
+  "orr  r0, r0, #3\n\t"   /* request reset in 64 bit */
+  "mcr  15, 0, r0, cr12, cr0, 2\n\t"
+  "isb\n\t"
+  "nop\n\t"
+  "wfi\n\t"
+  "b.\n"
+  ::: "r0");
+#endif
+   while (1);  /* to avoid a compiler warning about __noreturn */
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+   if (spl_image->arch == IH_ARCH_DEFAULT) {
+   /*
+* If the image to be executed is using the same architecture
+* as we are currently running in, just branch to the target
+* address.
+*/
+   debug("entering by branch\n");
+   jump_to_image_native(spl_image);
+   } else {
+   /*
+* If the target architecture and the current one differ, use
+* the RMR routine to change it.
+*/
+   debug("entering by RMR switch\n");
+   /*
+* The start address at which execution continues after the
+* RMR switch is held in the RVBAR system register, which is
+* architecturally read-only.
+* Allwinner provides a writeable alias in MMIO space for it.
+*/
+   writel(spl_image->entry_point, 0x17000a0);
+   DSB;
+   ISB;
+   reset_rmr_switch();
+   }
+}
-- 
2.8.2

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[U-Boot] [PATCH v3 23/26] Makefile: use "arm64" architecture for U-Boot image files

2016-12-18 Thread Andre Przywara
At the moment we use the arch/arm directory for arm64 boards as well,
so the Makefile will pick up the "arm" name for the architecture to use
for tagging binaries in U-Boot image files.
Differentiate between the two by looking at the CPU variable being defined
to "armv8", and use the arm64 architecture name on creating the image
file if that matches.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 Makefile | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index dfed58b..749fc5d 100644
--- a/Makefile
+++ b/Makefile
@@ -923,13 +923,18 @@ quiet_cmd_cpp_cfg = CFG $@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
 
+ifeq ($(CPU),armv8)
+IH_ARCH := arm64
+else
+IH_ARCH := $(ARCH)
+endif
 ifdef CONFIG_SPL_LOAD_FIT
-MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+MKIMAGEFLAGS_u-boot.img = -f auto -A $(IH_ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 else
-MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
+MKIMAGEFLAGS_u-boot.img = -A $(IH_ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 endif
-- 
2.8.2

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[U-Boot] [PATCH v3 24/26] ARM: SPL/FIT: differentiate between arm and arm64 arch properties

2016-12-18 Thread Andre Przywara
Since the SPL FIT loader can now differentiate between different
architectures, teach it how to tell arm and arm64 apart when a FIT
image is used.
We just support those two for now, as these are so far the only sensible
alternatives.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 arch/arm/lib/spl.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index e606d47..45d285c 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -63,3 +63,18 @@ void __noreturn jump_to_image_linux(struct spl_image_info 
*spl_image, void *arg)
image_entry(0, machid, arg);
 }
 #endif
+
+/* This overwrites the weak definition in spl_fit.c */
+u8 spl_genimg_get_arch_id(const char *arch_str)
+{
+   if (!arch_str)
+   return IH_ARCH_DEFAULT;
+
+   if (!strcmp(arch_str, "arm"))
+   return IH_ARCH_ARM;
+
+   if (!strcmp(arch_str, "arm64"))
+   return IH_ARCH_ARM64;
+
+   return IH_ARCH_DEFAULT;
+}
-- 
2.8.2

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Re: [U-Boot] [U-Boot,v6,11/13] sunxi: Use binman for sunxi boards

2016-12-18 Thread Tom Rini
On Fri, Nov 25, 2016 at 08:16:01PM -0700, Simon Glass wrote:

> Move sunxi boards to use binman. This involves adding the image definition
> to the device tree and using it in the Makefile.
> 
> Signed-off-by: Simon Glass 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCHv5 17/17] kconfig: move FSL_PCIE_COMPAT to platform Kconfig

2016-12-18 Thread Z.Q. Hou
Hi Simon,

Thanks a lot for your review!

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年12月18日 6:47
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
> ; Alison Wang ;
> Sumit Garg ; Ruchika Gupta ;
> york sun ; M.H. Lian ; Bin
> Meng ; Mingkai Hu 
> Subject: Re: [PATCHv5 17/17] kconfig: move FSL_PCIE_COMPAT to platform
> Kconfig
> 
> On 12 December 2016 at 23:54, Zhiqiang Hou 
> wrote:
> > From: Hou Zhiqiang 
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V5:
> >  - No change
> >
> >  arch/arm/cpu/armv7/ls102xa/Kconfig|  8 
> >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++
> >  drivers/pci/pcie_layerscape_fixup.c   |  8 
> >  include/configs/ls1012aqds.h  |  1 -
> >  include/configs/ls1012ardb.h  |  1 -
> >  include/configs/ls1021aqds.h  |  1 -
> >  include/configs/ls1021atwr.h  |  1 -
> >  include/configs/ls1043a_common.h  |  1 -
> >  include/configs/ls2080a_common.h  |  3 ---
> >  9 files changed, 23 insertions(+), 12 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 
> I wonder if anyone would really want to change this?

Anyway, better to use Kconfig.

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-18 Thread Chee, Tien Fong
On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > These changes to ensure Arria10 SPL build success.
> > > > > Please reword the commit message, mention you're removing the
> > > > > Arria10
> > > > > bits. Still, this does not even apply on mainline, on top of
> > > > > what
> > > > > does
> > > > > this apply ?
> > > > > 
> > > > I disabled some features temporary, so SPL build can pass and
> > > > print
> > > > out
> > > > working. I will enable these features back in upcoming patches.
> > > > This is
> > > > base on 01-arria10 branch.
> > > But this patch seems to only enable stuff ... ?
> > > 
> > Enable the spl. Disable SPI flash temporary, for preventing build
> > failed, but this will be enabled back with upcoming patches for
> > supporting SPI flash.
> What's the problem with SPI flash ? I thought it's the same block as
> in
> C/A 5 ?
> 
Some compilation error, but i haven't checked it out what errors
causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once
booting from SDMMC working, i will work to boot from QSPI and NAND
too.
> 
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Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

2016-12-18 Thread Chee, Tien Fong
On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > These compat macros would be used by clock manager and pin mux
> > > > drivers
> > > > to look the required HW info from DTS for hardware
> > > > initialization.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> > > > ---
> > > >  include/fdtdec.h |8 
> > > >  lib/fdtdec.c |2 ++
> > > >  2 files changed, 10 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > index 27887c8..68cb199 100644
> > > > --- a/include/fdtdec.h
> > > > +++ b/include/fdtdec.h
> > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > >     COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP
> > > > memory-
> > > > down params */
> > > >     COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge
> > > > FSP
> > > > */
> > > >     COMPAT_SUNXI_NAND,  /* SUNXI NAND
> > > > controller
> > > > */
> > > > +   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock
> > > > initialization */
> > > > +   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /*
> > > > pinctrl-
> > > > single */
> > > > +   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /*
> > > > Arria10
> > > > hps2fpga bridge */
> > > > +   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10
> > > > lwhps2fpga bridge */
> > > > +   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /*
> > > > Arria10
> > > > fpga2hps bridge */
> > > > +   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /*
> > > > Arria10
> > > > fpga2SDRAM0 bridge */
> > > > +   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /*
> > > > Arria10
> > > > fpga2SDRAM1 bridge */
> > > > +   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /*
> > > > Arria10
> > > > fpga2SDRAM2 bridge */
> > > Is all of this needed ? You're only adding two entries in the
> > > FDTDEC
> > > below.
> > > 
> > This is to avoid compilation error, we have some functions ported
> > from
> > our internal branch, which using above COMPAT macro. Soon, in
> > upcoming
> > patches, we will need those functions and more entries will be
> > added
> > into FDTDEC below.
> You can add the compat strings when you really need them. Still, with
> DM, you shouldn't even need them AFAIK.
> 
We have some drivers in these series of patches contain some COMPAT
strings, without these compact strings, the compilation would fail due
to error compact string is not defined. I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
> > 
> > > 
> > > > 
> > > > 
> > > >  
> > > >     COMPAT_COUNT,
> > > >  };
> > > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> > > > index 4defb90..09a1db4 100644
> > > > --- a/lib/fdtdec.c
> > > > +++ b/lib/fdtdec.c
> > > > @@ -66,6 +66,8 @@ static const char * const
> > > > compat_names[COMPAT_COUNT] = {
> > > >     COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-
> > > > mdp"),
> > > >     COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
> > > >     COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
> > > > +   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
> > > > +   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-
> > > > single"),
> > > >  };
> > > >  
> > > >  const char *fdtdec_get_compatible(enum fdt_compat_id id)
> > > > 
> 
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Re: [U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

2016-12-18 Thread Chee, Tien Fong
On Rab, 2016-12-07 at 14:52 +0100, Marek Vasut wrote:
> On 12/07/2016 11:30 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:44 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 08:50 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > This is initial version of device tree for the Intel socfpga
> > > > arria10
> > > > development kit with sdmmc.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> > > > ---
> > > >  arch/arm/dts/Makefile   |3 +-
> > > >  arch/arm/dts/socfpga_arria10.dtsi   |  859
> > > > +++
> > > >  arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi |  473
> > > > +
> > > >  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts|   33 +
> > > >  4 files changed, 1367 insertions(+), 1 deletions(-)
> > > >  create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
> > > >  create mode 100644
> > > > arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi
> > > Isn't the handoff file board-specific ?
> > > 
> > board and flash specific. How bout this name
> > "socfpga_arria10_socdk_sdmmc_handoff"?
> Certainly better
> 
> > 
> > > 
> > > > 
> > > >  create mode 100644
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > Does this patchset somehow supersede the previous one [1] or what
> > > is
> > > the
> > > plan here ?
> > > 
> > Yeah, the series patches here based on 01-arria10.
> Just rebase and repost the whole thing on top of u-boot/master
> 
Okay,noted.
> > 
> > > 
> > > [1]
> > > http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs
> > > /hea
> > > ds/01-arria10
> 
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Re: [U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration

2016-12-18 Thread Chee, Tien Fong
On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/Makefile  |2 +-
>  arch/arm/mach-socfpga/include/mach/pinmux.h |   17 +
>  arch/arm/mach-socfpga/pinmux.c  |  104
> +++
>  3 files changed, 122 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
>  create mode 100644 arch/arm/mach-socfpga/pinmux.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile
> index 71cf31c..1ab68be 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
Any comments on this patch before i start the version 2?

> @@ -10,7 +10,7 @@
>  obj-y+= misc.o timer.o reset_manager.o system_manager.o
> clock_manager.o \
>      fpga_manager.o board.o
>  obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> misc_arria10.o \
> - clock_manager_arria10.o
> + clock_manager_arria10.o pinmux.o
>  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> wrap_pll_config.o \
>   reset_manager_gen5.o misc_gen5.o \
>   clock_manager_gen5.o
> diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h
> b/arch/arm/mach-socfpga/include/mach/pinmux.h
> new file mode 100644
> index 000..e7d831d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright (C) 2016 Intel Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#ifndef  _PINMUX_H_
> +#define  _PINMUX_H_
> +
> +#ifndef __ASSEMBLY__
> +extern int config_dedicated_pins(const void *blob);
> +extern int config_pins(const void *blob, const char *pin_grp);
> +#endif
> +
> +
> +
> +#endif /* _PINMUX_H_ */
> diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-
> socfpga/pinmux.c
> new file mode 100644
> index 000..d45722f
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/pinmux.c
> @@ -0,0 +1,104 @@
> +/*
> + *  Copyright (C) 2016 Intel Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +int config_dedicated_pins(const void *blob);
> +int config_pins(const void *blob, const char *pin_grp);
> +static int __do_pinctr_pins(const void *blob, int child, const char
> *node_name);
> +static int do_pinctrl_pins(const void *blob, int node, const char
> *child_name);
> +
> +static int __do_pinctr_pins(const void *blob, int child, const char
> *node_name)
> +{
> + int len;
> + fdt_addr_t base_addr;
> + fdt_size_t size;
> + const u32 *cell;
> + u32 offset, value;
> +
> + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
> + if (base_addr != FDT_ADDR_T_NONE) {
> + cell = fdt_getprop(blob, child, "pinctrl-
> single,pins",
> + &len);
> + if (cell != NULL) {
> + debug("%p %d\n", cell, len);
> + for (;len > 0; len -= (2*sizeof(u32))) {
> + offset = fdt32_to_cpu(*cell++);
> + value = fdt32_to_cpu(*cell++);
> + debug("<0x%x 0x%x>\n", offset,
> value);
> + writel(value, base_addr + offset);
> + }
> + return 0;
> + }
> + }
> + return 1;
> +}
> +
> +static int do_pinctrl_pins(const void *blob, int node, const char
> *child_name)
> +{
> + int child, len;
> + const char *node_name;
> +
> + child = fdt_first_subnode(blob, node);
> +
> + if (child < 0)
> + return 2;
> +
> + node_name = fdt_get_name(blob, child, &len);
> +
> + while (node_name) {
> + if (!strcmp(child_name, node_name)) {
> + __do_pinctr_pins(blob, child, node_name);
> + return(0);
> + }
> + child = fdt_next_subnode(blob, child);
> +
> + if (child < 0)
> + break;
> +
> + node_name = fdt_get_name(blob, child, &len);
> + }
> +
> + return 1;
> +}
> +
> +int config_dedicated_pins(const void *blob)
> +{
> + int node;
> +
> + node = fdtdec_next_compatible(blob, 0,
> + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> + return 1;
> +
> + if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
> + return 2;
> +
> + if (do_pinctrl_pins(blob, node, "dedicated"))
> + return 3;
> +
> + return 0;
> +}
> +
> +int config_pins(const void *blob, const char *pin_grp)
> +{
> + int node;
> +
> + node = fdtdec_next_compatible(blob, 0,
> + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> +   

Re: [U-Boot] [PATCHv2 1/2] ARMv8/fsl-layerscape: Correct the OCRAM size

2016-12-18 Thread Z.Q. Hou
Hi York,

Thanks a lot for your comments!

> -Original Message-
> From: york sun
> Sent: 2016年12月17日 0:39
> To: Z.Q. Hou ; u-boot@lists.denx.de; Prabhakar
> Kushwaha ; Ruchika Gupta
> ; Mingkai Hu ; Pratiyush
> Srivastava 
> Subject: Re: [PATCHv2 1/2] ARMv8/fsl-layerscape: Correct the OCRAM size
> 
> On 12/16/2016 01:29 AM, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang 
> >
> > The real size of OCRAM is 128KiB, so correct the size of OCRAM.
> > And OCRAM reserved 2MiB space, then add a new macro to describe it,
> > which is used for MMU setup.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V2:
> >  - New patch
> >
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +---
> >  arch/arm/include/asm/arch-fsl-layerscape/cpu.h| 8 
> >  2 files changed, 9 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index c50894a..8e2eea3 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -28,8 +28,9 @@
> >  #define CONFIG_FSL_TZASC_400
> >  #endif
> >
> > -#define CONFIG_SYS_FSL_OCRAM_BASE  0x1800  /* initial RAM */
> > -#define CONFIG_SYS_FSL_OCRAM_SIZE  0x0020  /* 2M */
> > +#define CONFIG_SYS_FSL_OCRAM_BASE  0x1800 /* initial RAM */
> > +#define SYS_FSL_OCRAM_SPACE_SIZE   0x0020 /* 2M space */
> > +#define CONFIG_SYS_FSL_OCRAM_SIZE  0x0002 /* Real size 128K */
> 
> 
> 
> >
> >  /* DDR */
> >  #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
> > @@ -137,7 +138,8 @@
> >  #elif defined(CONFIG_FSL_LSCH2)
> >  #define CONFIG_SYS_FSL_SEC_COMPAT  5
> >  #define CONFIG_SYS_FSL_OCRAM_BASE  0x1000 /* initial
> RAM */
> > -#define CONFIG_SYS_FSL_OCRAM_SIZE  0x0020 /* 2M */
> > +#define SYS_FSL_OCRAM_SPACE_SIZE   0x0020 /* 2M space */
> 
> 
> Zhiqiang,
> 
> The history behind the OCRAM size is page table size. We started from fixed
> table. 2MB was the page granule size to avoid too many tables.
> With now MMU code, we can use 4KB page granule to get rid of this macro,
> but I'd rather not to create a new table just for this purpose.
> 
> I see you want to use the real OCRAM size to initialize it. Why don't you use 
> a
> new macro like SYS_FSL_OCRAM_REAL_SIZE so you don't have to change
> other code. Or better use Kconfig option for the new macro.
> 

The OCRAM_SIZE and OCRAM_REAL_SIZE, I afraid it is confusing.
I think the OCRAM size and OCRAM base are hardware attributes and it's better 
to stay them in the config.h.

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCHv5 09/17] pci: layerscape: move kernel DT fixup to a separate file

2016-12-18 Thread Z.Q. Hou
Hi Simon,

Thanks a lot for your review!

B.R
Zhiqiang

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年12月18日 6:47
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
> ; Alison Wang ;
> Sumit Garg ; Ruchika Gupta ;
> york sun ; M.H. Lian ; Bin
> Meng ; Mingkai Hu 
> Subject: Re: [PATCHv5 09/17] pci: layerscape: move kernel DT fixup to a
> separate file
> 
> On 12 December 2016 at 23:54, Zhiqiang Hou 
> wrote:
> > From: Hou Zhiqiang 
> >
> > To make the layerscape pcie driver clear, move the kernel DT fixup
> > code from pcie_layerscape.c to pcie_layerscape_fixup.c.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V5:
> >  - New patch
> >
> >  drivers/pci/Makefile|   1 +
> >  drivers/pci/pcie_layerscape.c   | 314 
> > +---
> >  drivers/pci/pcie_layerscape.h   | 135 
> >  drivers/pci/pcie_layerscape_fixup.c | 204 +++
> >  4 files changed, 343 insertions(+), 311 deletions(-)  create mode
> > 100644 drivers/pci/pcie_layerscape.h  create mode 100644
> > drivers/pci/pcie_layerscape_fixup.c
> 
> Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

2016-12-18 Thread Chee, Tien Fong
On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> This patch adding the Arria10 critical hardware initialization before
> enabling console print out in spl.
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/spl.c |   86
> +-
>  1 files changed, 83 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> socfpga/spl.c
> index fec4c7a..9375514 100644
> --- a/arch/arm/mach-socfpga/spl.c
> +++ b/arch/arm/mach-socfpga/spl.c
Any comments on this patch before i start the version 2?

> @@ -1,7 +1,7 @@
>  /*
> - *  Copyright (C) 2012 Altera Corporation 
> + *  Copyright (C) 2012-2016 Altera Corporation 
>   *
> - * SPDX-License-Identifier:  GPL-2.0+
> + * SPDX-License-Identifier:  GPL-2.0
>   */
>  
>  #include 
> @@ -19,22 +19,32 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
> +#endif
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static struct pl310_regs *const pl310 =
>   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>  static struct scu_registers *scu_regs =
>   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>  static struct nic301_registers *nic301_regs =
>   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> +#endif
> +
> +static const struct socfpga_system_manager *sysmgr_regs =
>   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  
>  u32 spl_boot_device(void)
>  {
>   const u32 bsel = readl(&sysmgr_regs->bootinfo);
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   switch (bsel & 0x7) {
>   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
>   return BOOT_DEVICE_RAM;
> @@ -55,6 +65,24 @@ u32 spl_boot_device(void)
>   printf("Invalid boot device (bsel=%08x)!\n", bsel);
>   hang();
>   }
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> + switch ((bsel>>12) & 0x7) {
> + case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> + return BOOT_DEVICE_RAM;
> + case 0x2:   /* NAND Flash (1.8V) */
> + case 0x3:   /* NAND Flash (3.0V) */
> + return BOOT_DEVICE_NAND;
> + case 0x4:   /* SD/MMC External Transceiver (1.8V) */
> + case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> + return BOOT_DEVICE_MMC1;
> + case 0x6:   /* QSPI Flash (1.8V) */
> + case 0x7:   /* QSPI Flash (3.0V) */
> + return BOOT_DEVICE_SPI;
> + default:
> + printf("Invalid boot device (bsel=%08x)!\n", bsel);
> + hang();
> + }
> +#endif
>  }
>  
>  #ifdef CONFIG_SPL_MMC_SUPPORT
> @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
>  }
>  #endif
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static void socfpga_nic301_slave_ns(void)
>  {
>   writel(0x1, &nic301_regs->lwhps2fpgaregs);
> @@ -182,3 +211,54 @@ void board_init_f(ulong dummy)
>   /* Configure simple malloc base pointer into RAM. */
>   gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
>  }
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +void board_init_f(ulong dummy)
> +{
> + memset(__bss_start, 0, __bss_end - __bss_start);
> + /*
> +  * Configure Clock Manager to use intosc clock instead
> external osc to
> +  * ensure success watchdog operation. We do it as early as
> possible.
> +  */
> + cm_use_intosc();
> +
> + watchdog_disable();
> +
> + arch_early_init_r();
> +
> +#ifdef CONFIG_HW_WATCHDOG
> + /* release osc1 watchdog timer 0 from reset */
> + reset_deassert_osc1wd0();
> +
> + /* reconfigure and enable the watchdog */
> + hw_watchdog_init();
> + WATCHDOG_RESET();
> +#endif /* CONFIG_HW_WATCHDOG */
> +
> +#ifdef CONFIG_OF_CONTROL
> + /* We need to access to FDT as this stage */
> + /* FDT is at end of image */
> + gd->fdt_blob = (void *)(__bss_end);
> + /* Check whether we have a valid FDT or not. */
> + if (fdtdec_prepare_fdt()) {
> + panic("** CONFIG_OF_CONTROL defined but no FDT -
> please see "
> + "doc/README.fdt-control");
> + }
> +#endif /* CONFIG_OF_CONTROL */
> +
> + /* Initialize the timer */
> + timer_init();
> +
> + /* configuring the clock based on handoff */
> + cm_basic_init(gd->fdt_blob);
> + WATCHDOG_RESET();
> +
> + config_dedicated_pins(gd->fdt_blob);
> + WATCHDOG_RESET();
> +
> + /* configure the Reset Manager */
> + reset_deassert_dedicated_peripherals();
> +
> + /* enable console uart printing */
> + preloader_console_init();
> +}
> +#endif
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Re: [U-Boot] [PATCH 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

2016-12-18 Thread Z.Q. Hou
Hi Masahiro Yamada,

Thanks a lot for your comments!

> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 2016年12月19日 0:49
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Simon Glass ; Mingkai Hu
> ; york sun ; Ashish Kumar
> ; Mateusz Kulikowski
> ; Tom Rini 
> Subject: Re: [U-Boot] [PATCH 1/2] armv8: Enable CPUECTLR.SMPEN for
> coherency
> 
> 2016-12-15 15:08 GMT+09:00 Zhiqiang Hou :
> > From: Mingkai Hu 
> >
> > For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> > set. The SMPEN bit should be set before enabling the data cache.
> > If not enabled, the cache is not coherent with other cores and data
> > corruption could occur.
> >
> > For A57/A72, SMPEN bit enables the processor to receive instruction
> > cache and TLB maintenance operations broadcast from other processors
> > in the cluster. This bit should be set before enabling the caches and
> > MMU, or performing any cache and TLB maintenance operations.
> >
> > Signed-off-by: Mingkai Hu 
> > Signed-off-by: Gong Qianyu 
> > Signed-off-by: Mateusz Kulikowski 
> > Signed-off-by: Hou Zhiqiang 
> > ---
> >  arch/arm/cpu/armv8/Kconfig | 12 
> > arch/arm/cpu/armv8/start.S | 11 +++
> >  2 files changed, 23 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> > index 965a8d1..ce749f2 100644
> > --- a/arch/arm/cpu/armv8/Kconfig
> > +++ b/arch/arm/cpu/armv8/Kconfig
> > @@ -3,6 +3,18 @@ if ARM64
> >  config ARMV8_MULTIENTRY
> >  bool "Enable multiple CPUs to enter into U-Boot"
> >
> > +config ARMV8_SET_SMPEN
> > +bool "Enable data coherency with other cores in cluster"
> > +help
> > +  Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set
> even
> > +  for single core systems. Unfortunately write access to this
> > +  register may be controlled by EL3/EL2 firmware. To be more
> > +  precise, by default (if there is EL2/EL3 firmware running)
> > +  this register is RO for NS EL1.
> > +  This switch can be used to avoid writing to CPUECTLR_EL1,
> > +  it can be safely enabled when El2/EL3 initialized SMPEN bit
> > +  or when CPU implementation doesn't include that register.
> > +
> 
> 
> If you run ARM Trusted Firmware, this bit has already been set correctly. (or 
> if
> you implement your own trusted firmware, this bit should be set there.) In
> those cases, there is no need to touch it in U-Boot.
> 
> 
> The motivation for this commit is
> to boot the system without any firmware before U-Boot?

Yes

Thanks,
Zhiqiang
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[U-Boot] [PATCH] MAINTAINERS, git-mailrc: update the Power maintainer

2016-12-18 Thread Jaehoon Chung
Przemyslaw didn't maintain the PMIC anymore.
Update the pmic maintainer from Przeymyslaw to me.

Signed-off-by: Jaehoon Chung 
---
 MAINTAINERS| 6 ++
 doc/git-mailrc | 3 +--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index c2085ca..793ff49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -366,6 +366,12 @@ S: Maintained
 T: git git://git.denx.de/u-boot-ppc4xx.git
 F: arch/powerpc/cpu/ppc4xx/
 
+POWER
+M: Jaehoon Chung 
+S: Maintained
+T: git git://git.denx.de/u-boot-pmic.git
+F: drivers/power/
+
 NETWORK
 M: Joe Hershberger 
 S: Maintained
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ec6a7db..b9b5929 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -39,7 +39,6 @@ alias mateuszMateusz Kulikowski 

 alias maximeMaxime Ripard 
 alias monstr Michal Simek 
 alias prafulla   Prafulla Wadaskar 
-alias bobenstein Przemyslaw Marczak 
 alias prom   Minkyu Kang 
 alias rbohmerRemy Bohmer 
 alias reinhardm  Reinhard Meyer 
@@ -137,4 +136,4 @@ alias usbuboot, marex
 alias video  uboot, ag
 alias patman uboot, sjg
 alias buildman   uboot, sjg
-alias pmic   uboot, bobenstein
+alias pmic   uboot, jaehoon
-- 
2.10.2

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[U-Boot] [PATCH] driver: net: fsl-mc: Update MC memory allocation code

2016-12-18 Thread Priyanka Jain
Firmware of Management Complex (MC) should be loaded
at 512MB aligned privately allocated memory at DRAM end.
And this memory should be reduced from total memory
available for general purposes.

Update memory allocation code in MC driver to support
above requirements.

Signed-off-by: Priyanka Jain 
---
 drivers/net/fsl-mc/mc.c |   98 +-
 1 files changed, 45 insertions(+), 53 deletions(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 46b8a6b..df3f7fa 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright (C) 2014, 2016 Freescale Semiconductor
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -41,6 +41,7 @@ struct fsl_dpbp_obj *dflt_dpbp = NULL;
 struct fsl_dpio_obj *dflt_dpio = NULL;
 struct fsl_dpni_obj *dflt_dpni = NULL;
 static u64 mc_lazy_dpl_addr;
+static u64 mc_ram_addr;
 
 #ifdef DEBUG
 void dump_ram_words(const char *title, void *addr)
@@ -89,11 +90,11 @@ void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem 
*mc_ccsr_regs)
  * Copying MC firmware or DPL image to DDR
  */
 static int mc_copy_image(const char *title,
-u64 image_addr, u32 image_size, u64 mc_ram_addr)
+u64 image_addr, u32 image_size, u64 mc_addr)
 {
-   debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
-   memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
-   flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
+   debug("%s copied to address %p\n", title, (void *)mc_addr);
+   memcpy((void *)mc_addr, (void *)image_addr, image_size);
+   flush_dcache_range(mc_addr, mc_addr + image_size);
return 0;
 }
 
@@ -156,16 +157,14 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr,
 /*
  * Calculates the values to be used to specify the address range
  * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
- * It returns the highest 512MB-aligned address within the given
- * address range, in '*aligned_base_addr', and the number of 256 MiB
- * blocks in it, in 'num_256mb_blocks'.
+ * It stores the highest 512MB-aligned address within the given
+ * address range, in 'mc_ram_addr', and returns the number of 256 MB
+ * blocks in 'num_256mb_blocks'.
  */
-static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
-  size_t mc_ram_size,
-  u64 *aligned_base_addr,
+static int calculate_mc_private_ram_params(size_t mc_ram_size,
   u8 *num_256mb_blocks)
 {
-   u64 addr;
+   u64 mc_ram_end_addr;
u16 num_blocks;
 
if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
@@ -180,18 +179,39 @@ static int calculate_mc_private_ram_params(u64 
mc_private_ram_start_addr,
   mc_ram_size);
return -EINVAL;
}
+   *num_256mb_blocks = num_blocks;
 
-   addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
+   /*
+* The MC private DRAM block will be carved at the end of DRAM
+*/
+   if (gd->bd->bi_dram[1].start) {
+   mc_ram_end_addr =
+   gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+   } else {
+   mc_ram_end_addr =
+   gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+   }
+
+   mc_ram_addr = (mc_ram_end_addr - mc_ram_size) &
MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
 
-   if (addr < mc_private_ram_start_addr) {
-   printf("fsl-mc: ERROR: bad start address %#llx\n",
-  mc_private_ram_start_addr);
+   if (mc_ram_addr > mc_ram_end_addr) {
+   printf("fsl-mc: ERROR: bad end address %#llx\n",
+  mc_ram_end_addr);
return -EFAULT;
}
 
-   *aligned_base_addr = addr;
-   *num_256mb_blocks = num_blocks;
+   /*
+* Total DRAM available for general purpose will get
+* reduced by the size of private DRAM allocated to MC.
+*/
+   if (gd->bd->bi_dram[1].start) {
+   gd->bd->bi_dram[1].size =
+   mc_ram_addr - gd->bd->bi_dram[1].start;
+   } else {
+   gd->bd->bi_dram[0].size =
+   mc_ram_addr - gd->bd->bi_dram[0].start;
+   }
return 0;
 }
 
@@ -225,7 +245,7 @@ static int mc_fixup_dpc(u64 dpc_addr)
return 0;
 }
 
-static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
+static int load_mc_dpc(size_t mc_ram_size, u64 mc_dpc_addr)
 {
u64 mc_dpc_offset;
 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
@@ -282,7 +302,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, 
u64 mc_dpc_addr)
return 0;
 }
 
-static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
+static int load_mc_dpl

Re: [U-Boot] [PATCH] i2c: mv_i2c.c: Correct address endianness

2016-12-18 Thread Stefan Roese

On 13.12.2016 18:49, Bradley Bolen wrote:

0c0f719ad2f46c8566a56daee37ebdb7c078c3b1 accidentally changed the
endianness of the i2c read and write addresses.  This was noticable when
accessing EEPROMs that use 2 byte addressing as the LSB was being sent
first.

Signed-off-by: Bradley Bolen 
---
 drivers/i2c/mv_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 7f52fa2..c780272 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -270,7 +270,7 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, u8 
*addr, int alen,
msg.condition = I2C_COND_NORMAL;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
-   msg.data  = *(addr++);
+   msg.data  = addr[alen];
if (i2c_transfer(base, &msg))
return -1;
}
@@ -341,7 +341,7 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 
*addr, int alen,
msg.condition = I2C_COND_NORMAL;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
-   msg.data  = *(addr++);
+   msg.data  = addr[alen];
if (i2c_transfer(base, &msg))
return -1;
}



Thanks for spotting:

Rewiewed-by: Stefan Roese 

Thanks,
Stefan


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Re: [U-Boot] [PATCHv5 01/17] configs: ls1021a: enable DT and DM support

2016-12-18 Thread Z.Q. Hou
Hi Simon,

Thanks a lot for your review!

B.R
Zhiqiang

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年12月18日 6:47
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
> ; Alison Wang ;
> Sumit Garg ; Ruchika Gupta ;
> york sun ; M.H. Lian ; Bin
> Meng ; Mingkai Hu 
> Subject: Re: [PATCHv5 01/17] configs: ls1021a: enable DT and DM support
> 
> On 12 December 2016 at 23:54, Zhiqiang Hou 
> wrote:
> > From: Hou Zhiqiang 
> >
> > Enable DT to support Driver Model.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V5:
> >  - No change
> >
> >  configs/ls1021aqds_nand_defconfig   | 3 +++
> >  configs/ls1021aqds_nor_SECURE_BOOT_defconfig| 2 ++
> >  configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 2 ++
> >  configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++
> >  configs/ls1021atwr_sdcard_ifc_defconfig | 3 +++
> >  5 files changed, 12 insertions(+)
> 
> Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] i2c: mv_i2c.c: Correct address endianness

2016-12-18 Thread Heiko Schocher

Hello Stefan,

Am 19.12.2016 um 06:56 schrieb Stefan Roese:

On 13.12.2016 18:49, Bradley Bolen wrote:

0c0f719ad2f46c8566a56daee37ebdb7c078c3b1 accidentally changed the
endianness of the i2c read and write addresses.  This was noticable when
accessing EEPROMs that use 2 byte addressing as the LSB was being sent
first.

Signed-off-by: Bradley Bolen 
---
 drivers/i2c/mv_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 7f52fa2..c780272 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -270,7 +270,7 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, u8 
*addr, int alen,
 msg.condition = I2C_COND_NORMAL;
 msg.acknack   = I2C_ACKNAK_WAITACK;
 msg.direction = I2C_WRITE;
-msg.data  = *(addr++);
+msg.data  = addr[alen];
 if (i2c_transfer(base, &msg))
 return -1;
 }
@@ -341,7 +341,7 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 
*addr, int alen,
 msg.condition = I2C_COND_NORMAL;
 msg.acknack   = I2C_ACKNAK_WAITACK;
 msg.direction = I2C_WRITE;
-msg.data  = *(addr++);
+msg.data  = addr[alen];
 if (i2c_transfer(base, &msg))
 return -1;
 }



Thanks for spotting:

Rewiewed-by: Stefan Roese 


Typo ... I fix this when applying this patch.

Thanks!

bye,
Heiko
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Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

2016-12-18 Thread Chee, Tien Fong
On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:
> On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > Drivers for reset manager is restructured such that common
> > > > > > functions,
> > > > > > gen5 drivers and Arria10 drivers are moved to
> > > > > > reset_manager.c,
> > > > > > reset_manager_gen5.c and reset_manager_arria10.c
> > > > > > respectively.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > > Cc: Marek Vasut 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Chin Liang See 
> > > > > > Cc: Tien Fong 
> > > [...]
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > +void reset_deassert_dedicated_peripherals(void)
> > > > > > +{
> > > > > > +   int i;
> > > > > > +   u32 mask0 = 0;
> > > > > > +   u32 mask1 = 0;
> > > > > > +   u32 pinmux_addr =
> > > > > > SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> > > > > > +   u32 mask = 0;
> > > > > > +#if defined(CONFIG_MMC)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> > > > > > +#elif defined(CONFIG_CADENCE_QSPI)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> > > > > > +#elif defined(CONFIG_NAND_DENALI)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> > > > > > +#else
> > > > > Shouldn't this come from OF instead of being ifdef'd ?
> > > > > 
> > > > What is OF?
> > > Device Tree (Open Firmware).
> > > 
> > > > 
> > > > 
> > > > what is your suggestion to make this function generic for
> > > > all type of flash?
> > > Pull it from OF ?
> > > 
> > Why you prefer device tree implementation over #define in
> > defconfig,
> > because there is performance penalty.
> Because we are moving away from excessive random #defines and toward
> having one single binary where you could exchange just the DT and run
> it on multiple boards, just like Linux, that is the ultimate goal.
> 
> Also, this is not performance critical code, is it.
> 
This code just to release peripherals from reset, not performance
critical codes. However, our defconfigs based on flash type booting, so
this is why i din't use the DT, since we have flash type determined
from defconfig. Since DT is ultimate goal, i can change to DT
implementation.
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Re: [U-Boot] [PATCH v2 01/63] console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable
> for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these
> options will be inactive in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/console.c | 30 +++---
>  1 file changed, 15 insertions(+), 15 deletions(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 02/63] spl: spi: Add a debug message if loading fails

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> This currently fails silently. Add a debug message to aid debugging.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2:
> - Show the error value in spl_spi_load_image()
>
>  common/spl/spl_spi.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 04/63] spl: Allow CPU drivers to be used in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> Add a new Kconfig option to allow CPU drivers to be used in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 10 ++
>  drivers/Makefile   |  1 +
>  2 files changed, 11 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 03/63] spl: Makefile: Define SPL_ earlier

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> This Makefile variable can be used in the architecture's main Makefile but
> at present it is not set up until later. Set it just before this Makefile is
> included.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  scripts/Makefile.spl | 6 ++
>  1 file changed, 6 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 05/63] spl: Allow PCI drivers to be used in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> Add a new Kconfig option to allow PCI drivers to be used in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 07/63] spl: Allow timer drivers to be used in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> Add a new Kconfig option to allow timer drivers to be used in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 06/63] spl: Allow RTC drivers to be used in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> Add a new Kconfig option to allow RTC drivers to be used in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 10 ++
>  drivers/Makefile   |  1 +
>  2 files changed, 11 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 09/63] spl: Don't create a BSS padding when it is separate

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> When BSS does not immediate follow the SPL image we don't need padding
> before the device tree. Remove it in this case.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  scripts/Makefile.spl | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 08/63] spl: Allow PCH drivers to be used in SPL

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass  wrote:
> Add an option for building Platorm Controller Hub drivers in SPL.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

Reviewed-by: Bin Meng 
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[U-Boot] [RESEND PATCH v2] powerpc: Retain compatible property for L2 cache

2016-12-18 Thread Chris Packham
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"-l2-cache-controller" and "cache" as values.

Signed-off-by: Chris Packham 
---

Changes in v2:
- extract a helper function to set the compatible property and use it in
  both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases.

 arch/powerpc/cpu/mpc85xx/fdt.c | 61 +-
 1 file changed, 36 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 12001f85e9fd..67140ba9ee18 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -180,6 +180,39 @@ static inline void ft_fixup_l3cache(void *blob, int off)
 #define ft_fixup_l3cache(x, y)
 #endif
 
+#if defined(CONFIG_L2_CACHE) || \
+   defined(CONFIG_BACKSIDE_L2_CACHE) || \
+   defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+static inline void ft_fixup_l2cache_compatible(void *blob, int off)
+{
+   int len;
+   struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+
+   if (cpu) {
+   char buf[40];
+
+   if (isdigit(cpu->name[0])) {
+   /* MPC, where  == 4-digit number */
+   len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+   cpu->name) + 1;
+   } else {
+   /* P or T, where  == 4-digit number */
+   len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+   tolower(cpu->name[0]), cpu->name + 1) + 1;
+   }
+
+   /*
+* append "cache" after the NULL character that the previous
+* sprintf wrote.  This is how a device tree stores multiple
+* strings in a property.
+*/
+   len += sprintf(buf + len, "cache") + 1;
+
+   fdt_setprop(blob, off, "compatible", buf, len);
+   }
+}
+#endif
+
 #if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
@@ -215,9 +248,8 @@ static inline u32 l2cache_size(void)
 
 static inline void ft_fixup_l2cache(void *blob)
 {
-   int len, off;
+   int off;
u32 *ph;
-   struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 
const u32 line_size = 32;
const u32 num_ways = 8;
@@ -243,28 +275,7 @@ static inline void ft_fixup_l2cache(void *blob)
return ;
}
 
-   if (cpu) {
-   char buf[40];
-
-   if (isdigit(cpu->name[0])) {
-   /* MPC, where  == 4-digit number */
-   len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
-   cpu->name) + 1;
-   } else {
-   /* P or T, where  == 4-digit number */
-   len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
-   tolower(cpu->name[0]), cpu->name + 1) + 1;
-   }
-
-   /*
-* append "cache" after the NULL character that the previous
-* sprintf wrote.  This is how a device tree stores multiple
-* strings in a property.
-*/
-   len += sprintf(buf + len, "cache") + 1;
-
-   fdt_setprop(blob, off, "compatible", buf, len);
-   }
+   ft_fixup_l2cache_compatible(blob, off);
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
@@ -337,7 +348,7 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
-   fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+   ft_fixup_l2cache_compatible(blob, l2_off);
}
 
if (l3_off < 0) {
-- 
2.11.0.24.ge6920cf

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Re: [U-Boot] [PATCH v2 03/63] spl: Makefile: Define SPL_ earlier

2016-12-18 Thread Masahiro Yamada
Hi Simon,


2016-11-20 5:24 GMT+09:00 Simon Glass :
> This Makefile variable can be used in the architecture's main Makefile but
> at present it is not set up until later. Set it just before this Makefile is
> included.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  scripts/Makefile.spl | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> index 03a2f06..f490e29 100644
> --- a/scripts/Makefile.spl
> +++ b/scripts/Makefile.spl
> @@ -35,6 +35,12 @@ else
>  SPL_BIN := u-boot-spl
>  endif
>
> +ifdef CONFIG_SPL_BUILD
> +SPL_ := SPL_
> +else
> +SPL_ :=
> +endif
> +
>  include $(srctree)/config.mk
>  include $(srctree)/arch/$(ARCH)/Makefile
>


In scripts/Makefile.spl, CONFIG_SPL_BUILD is always defined.

So, I think your patch is equivalent to:

>  SPL_BIN := u-boot-spl
>  endif
>
> +SPL_ := SPL_
> +
>  include $(srctree)/config.mk
>  include $(srctree)/arch/$(ARCH)/Makefile





But, more simply, does the following patch work for you?

(just move Kbuild.include below autoconf.mk)



diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index f379713..90fea0a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -19,11 +19,11 @@ src := $(obj)
 # Create output directory if not already present
 _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))

-include $(srctree)/scripts/Kbuild.include
-
 -include include/config/auto.conf
 -include $(obj)/include/autoconf.mk

+include $(srctree)/scripts/Kbuild.include
+
 KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD
 ifeq ($(CONFIG_TPL_BUILD),y)
 KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD




-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] mmc: Extend dependencies for zynq sdhci

2016-12-18 Thread Jaehoon Chung
On 12/15/2016 07:15 PM, Michal Simek wrote:
> There is hard dependency on BLK and DM_MMC which is also used by ATMEL
> and ROCKCHIP.
> 
> Signed-off-by: Michal Simek 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> ---
> 
>  drivers/mmc/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 5e84a4149146..998391328970 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -83,7 +83,7 @@ config PIC32_SDHCI
>  
>  config ZYNQ_SDHCI
>   bool "Arasan SDHCI controller support"
> - depends on DM_MMC && OF_CONTROL
> + depends on DM_MMC && OF_CONTROL && BLK && DM_MMC_OPS
>   help
> Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs 
> platform
>  
> 

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Re: [U-Boot] [RFC PATCH] mmc: spear: remove the entire spear_sdhci.c file

2016-12-18 Thread Jaehoon Chung
On 12/02/2016 11:04 PM, Tom Rini wrote:
> On Fri, Dec 02, 2016 at 05:46:10PM +0900, Jaehoon Chung wrote:
> 
>> Remove the entire spear_sdhci.c file.
>> There is no use case. This is dead codes.
>> Also there is no place to call "spear_sdhci_init()" anywhere.
>>
>> If some people use this file, let me know, plz.
>>
>> Signed-off-by: Jaehoon Chung 
> 
> It looks like it was added as dead code so:
> 
> Reviewed-by: Tom Rini 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> 

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Re: [U-Boot] [PATCH v2 11/63] WIP: x86: Update mpspec to build on 64-bit machines

2016-12-18 Thread Bin Meng
Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> At present this uses u32 to store an address. We should use unsigned long
> and avoid special types in function return values and parameters unless
> necessary. This makes the code more portable.
>
> I believe Alex Graf has a patch to correct all of these, so this is just
> a WIP patch.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/mpspec.h |  8 
>  arch/x86/lib/mpspec.c | 12 ++--
>  2 files changed, 10 insertions(+), 10 deletions(-)
>

Reviewed-by: Bin Meng 

I don't see Alex's patch on this mpspec.c file, but only smbios.c,
guess "WIP" tag is not needed.

Regards,
Bin
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Re: [U-Boot] [PATCH v2 14/63] x86: ivybridge: Add more debugging for failures

2016-12-18 Thread Bin Meng
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Add various debug() messages in places where errors occur. This aids with
> debugging.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2:
> - Output error code values in debug() statements
>
>  arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
>  arch/x86/cpu/ivybridge/sdram.c | 37 -
>  2 files changed, 31 insertions(+), 10 deletions(-)
>

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Re: [U-Boot] [PATCH v2 12/63] x86: Add basic support for U-Boot as a 64-bit EFI application

2016-12-18 Thread Bin Meng
Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Add a link script and relocation code for building 64-bit EFI applications.
> This can be used for the EFI stub.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/lib/elf_x86_64_efi.lds |  3 ++
>  arch/x86/lib/reloc_x86_64.c | 90 
> +
>  2 files changed, 93 insertions(+)
>  create mode 100644 arch/x86/lib/reloc_x86_64.c
>
> diff --git a/arch/x86/lib/elf_x86_64_efi.lds b/arch/x86/lib/elf_x86_64_efi.lds
> index 70c7c52..886ebef 100644
> --- a/arch/x86/lib/elf_x86_64_efi.lds
> +++ b/arch/x86/lib/elf_x86_64_efi.lds
> @@ -54,6 +54,9 @@ SECTIONS
> *(SORT(.u_boot_list*));
> . = ALIGN(8);
> *(.dtb*);
> +   /* Keep U-Boot payload */
> +   . = ALIGN(8);
> +   KEEP(*(.u_boot_bin.*));
> }
>
> . = ALIGN(4096);
> diff --git a/arch/x86/lib/reloc_x86_64.c b/arch/x86/lib/reloc_x86_64.c
> new file mode 100644
> index 000..70a2b2a
> --- /dev/null
> +++ b/arch/x86/lib/reloc_x86_64.c

reloc_x86_64.c is already in the mainline tree.

> @@ -0,0 +1,90 @@

[snip]

Regards,
Bin
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