Re: [U-Boot] Problems with latest U-boot on Mini2440

2014-01-19 Thread Peter Germer
Dear Gerhard,


2014/1/9 Gerhard Sittig 

>
> According to `git log` and `git show b77026225a31` ("ARM : Add
> support for MINI2440 (s3c2440)." as of 2012-05-02) only boot from
> NOR is supported.  Later commit 79a6fcf2573e (2013-06-15) fixed
> GPIO register access, and commit 2108f4c4a302 (2013-10-04)
> adjusted CONFIG_SYS_HZ.
>
> Later I2C and USB got adjusted, but those changes should only
> have an affect after a banner was shown (that's an assumption of
> mine, I2C _may_ be involved in detecting the board before showing
> a banner).  Correct clocks OTOH are a prerequisite for serial
> communication.
>
> You may want to check those exact revisions identified above
> which changed "mini" related code, or their direct predecessors
> in case a change broke a feature for you.  If one of those works
> for you, you may 'git bisect' from there, to help diagnose what
> needs to get improved or added to re-gain support for your board
> in mainline U-Boot.


Thank you for the guidance to the exact revisions where "mini" related
changes were committed. I tried all of them, but I could not run the
binaries on my board. In `git show b77026225a31` it is mentioned, that the
git I used successfully earlier [1] was merged to the mainline U-Boot, but
this one did not work neither (from NAND or RAM). I tried all the revisions
you mentioned, and the direct predecessors as well, and some other I found
could be related to "mini', but so far no joy.


> I understand that you want to keep the current bootloader in NOR,
> which means that lack of support to boot from NAND only leaves
> you with boot from RAM, which the software may not support either
> (it's not as trivial as it may sound, and requires explicit
> support).  So when the software only supports booting from NOR,
> and you don't have the software in NOR, this may be a reason why
> it doesn't work for you.
>
>
Correct. At least since I don't have a JTAG programmer I don't dare to
swipe out the original 'supervivi' boot loader, as with it I can play with
the NAND with no risk. In case the U-Boot I write to NOR would not work, I
will brick my board till I can get a JTAG programmer.
The version from [1] can be started both from RAM and from NAND without any
hassle, but in the mainline log it is clearly mentioned that after
integrating it supports only NOR. So far I could not find any other
revision mentioning that booting from NAND or RAM was solved regarding the
specific board.

I just saw that the board support was removed with the new RC released this
week. So for me it seems the best idea would playing with the source tree
available at [1], as it has more functions supported on my board. Anyway,
thank you for your kind help!


Best regards,
Peter

[1] git://repo.or.cz/u-boot-openmoko/mini2440.git
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Re: [U-Boot] imx6 Solo and LAN8720

2014-01-19 Thread Andy Ng
Dear colleagues,

Thank you very much for all the replies.

Finally, I have found the cause of the problem and there is some joy this
weekend.

The problem was the SION bit. The clock has to loop back.  I think it is a
u-boot bug in the pinmux table for the imx6dl. The mode ALT2
(ENET_REF_CLK/) for the PAD_GPIO16 has to have SION enabled, I suppose.

In the file mx6dl_pins.h

The line:
MX6_PAD_DECL(GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, 0x05E4, 0x0214, 2,
0x080C, 0, 0)

has to become:
MX6_PAD_DECL(GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, 0x05E4, 0x0214, 2 |
IOMUX_CONFIG_SION, 0x080C, 0, 0)

Thank you,
A





On Thu, Jan 16, 2014 at 9:37 PM, Andy Ng  wrote:

> Dear colleagues,
>
> I have setup a LAN8720 phy for my imx6Solo/DL custom board but no packets
> coming out.
> I can see 50MHz going into the phy from the REF_OUT Pin of the SOLO, I can
> read the phy ID using the u-boot MDIO commands
> but  when I do ftp or ping nothing comes out.
>
> mx6s > mdio list
> FEC:
> 0 - SMSC LAN8710/LAN8720 <--> FEC
>
>
> For this design I am using ENET_ANATOP_ETHERNET_REF_OUT.
> Have you used LAN8720 in a similar configuration:
>
> The pinmux i have is the following:
>
> /*
>  * Ethernet PINS for LAN8720
>  */
> static iomux_v3_cfg_t const enet_pads[] = {
> MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_MDC__ENET_MDC| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_CRS_DV__ENET_RX_EN| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_RX_ER__ENET_RX_ER| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_TX_EN__ENET_TX_EN| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_RXD0__ENET_RDATA_0| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_RXD1__ENET_RDATA_1| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_TXD0__ENET_TDATA_0| MUX_PAD_CTRL(ENET_PAD_CTRL),
> MX6_PAD_ENET_TXD1__ENET_TDATA_1| MUX_PAD_CTRL(ENET_PAD_CTRL),
> /* LAN8720 PHY Reset */
> MX6_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
> /* Note: The INT is not handled */
> MX6_PAD_ENET_REF_CLK__GPIO_1_23| MUX_PAD_CTRL(NO_PAD_CTRL),
>
> };
>
> Where ENET_PAT_CTRL is set as:
>
> #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE | \
> PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
> PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
>
> And the Ethernet configuration in the config file as follows:
>
> /* Ethernet Configuration */
> #define CONFIG_CMD_PING
> #define CONFIG_CMD_DHCP
> #define CONFIG_CMD_MII
> #define CONFIG_CMD_NET
> #define CONFIG_FEC_MXC
> #define CONFIG_MII
> #define IMX_FEC_BASEENET_BASE_ADDR
> #define CONFIG_FEC_XCV_TYPERMII
> #define CONFIG_ETHPRIME "FEC"
> #define CONFIG_FEC_MXC_PHYADDR0
>
> #define CONFIG_PHYLIB
> #define CONFIG_PHY_SMSC
>
>
> In the board file:
>
> #ifdef CONFIG_FEC_MXC
>
> /*
>  * Initialise the pins, and reset the PHY
>  */
> static void setup_iomux_enet(void)
> {
> imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
>
> /* Reset LAN8720 PHY */
> gpio_direction_output(ETH_PHY_RESET, 1);
> udelay(150);
> gpio_set_value(ETH_PHY_RESET, 0);
> udelay(150);
> gpio_set_value(ETH_PHY_RESET, 1);
> udelay(200);
> }
>
>
> int enable_fec_anatop_clock(void)
> {
> u32 reg = 0;
> s32 timeout = 10;
>
> struct anatop_regs __iomem *anatop =
> (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
>
> reg = readl(&anatop->pll_enet);
> if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
> (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
> reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
> writel(reg, &anatop->pll_enet);
> while (timeout--) {
> if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
> break;
> }
> if (timeout < 0)
> return -ETIMEDOUT;
> }
>
> /* Enable FEC clock */
> reg |= BM_ANADIG_PLL_ENET_ENABLE;
> reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
> writel(reg, &anatop->pll_enet);
>
> return 0;
> }
>
> int board_eth_init(bd_t *bis)
> {
> int ret;
>
> setup_iomux_enet();
>
> ret = cpu_eth_init(bis);
> if (ret) {
> printf("FEC MXC: %s:failed\n", __func__);
> return ret;
> }
>
> return 0;
> }
>
>
> static int setup_fec(void)
> {
> struct iomuxc_base_regs *iomuxc_regs =
> (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
> int ret;
>
> /* set gpr1[21] to select anatop clock */
> clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK, 1
> << 21);
>
> ret = enable_fec_anatop_clock();
> if (ret)
> return ret;
>
> return 0;
> }
> #endif
>
> int board_late_init(void)
> {
> #ifdef CONFIG_CMD_BMODE
> add_board_boot_modes(board_boot_modes);
> #endif
>
> return 0;
> }
>
> int board_init(void)
> {
>

[U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Andy Ng
The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10


diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 7851eb1..9c18847 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -1047,7 +1047,7 @@ MX6_PAD_DECL(GPIO_1__USDHC1_CD, 0x05E0,
0x0210, 6, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_1__SRC_TESTER_ACK, 0x05E0, 0x0210, 7,
0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__ESAI1_TX3_RX2, 0x05E4, 0x0214, 0,
0x0850, 1, 0)
 MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN  , 0x05E4, 0x0214, 1,
0x, 0, 0)
-MX6_PAD_DECL(GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT , 0x05E4, 0x0214,
2, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT , 0x05E4, 0x0214, 2
| IOMUX_CONFIG_SION, 0x080C, 0, 0)
 MX6_PAD_DECL(GPIO_16__USDHC1_LCTL  , 0x05E4, 0x0214, 3,
0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__SPDIF_IN1, 0x05E4, 0x0214, 4,
0x08F0, 2, 0)
 MX6_PAD_DECL(GPIO_16__GPIO_7_11, 0x05E4, 0x0214, 5,
0x, 0, 0)
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[U-Boot] [PATCH 3/3] PPC 85xx: Add qemu-ppce500 machine

2014-01-19 Thread Alexander Graf
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the current generation ppce500 machine as
it is implemented today.

Signed-off-by: Alexander Graf 
---
 arch/powerpc/cpu/mpc85xx/start.S|7 +
 arch/powerpc/include/asm/config_mpc85xx.h   |4 +
 board/freescale/qemu-ppce500/Makefile   |   10 ++
 board/freescale/qemu-ppce500/qemu-ppce500.c |  260 +++
 board/freescale/qemu-ppce500/tlb.c  |   59 ++
 boards.cfg  |1 +
 include/configs/qemu-ppce500.h  |  235 
 7 files changed, 576 insertions(+)
 create mode 100644 board/freescale/qemu-ppce500/Makefile
 create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c
 create mode 100644 board/freescale/qemu-ppce500/tlb.c
 create mode 100644 include/configs/qemu-ppce500.h

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..ccbcc03 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,6 +80,13 @@ _start_e500:
li  r1,MSR_DE
mtmsr   r1
 
+#ifdef CONFIG_QEMU_E500
+   /* Save our ePAPR device tree off before we clobber it */
+   lis r2, CONFIG_QEMU_DT_ADDR@h
+   ori r2, r2, CONFIG_QEMU_DT_ADDR@l
+   stw r3, 0(r2)
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr   r3,SPRN_SVR
rlwinm  r3,r3,0,0xff
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..a0ab453 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -776,6 +776,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe000
+
 #else
 #error Processor type not defined for this platform
 #endif
diff --git a/board/freescale/qemu-ppce500/Makefile 
b/board/freescale/qemu-ppce500/Makefile
new file mode 100644
index 000..193b160
--- /dev/null
+++ b/board/freescale/qemu-ppce500/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += qemu-ppce500.o
+obj-y  += tlb.o
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c 
b/board/freescale/qemu-ppce500/qemu-ppce500.c
new file mode 100644
index 000..c6c4b4a
--- /dev/null
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int checkboard(void)
+{
+   return 0;
+}
+
+static struct pci_controller pci1_hose;
+
+void pci_init_board(void)
+{
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   struct fsl_pci_info pci_info;
+   u32 devdisr, pordevsr;
+   u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+   int first_free_busno = 0;
+
+   devdisr = in_be32(&gur->devdisr);
+   pordevsr = in_be32(&gur->pordevsr);
+   porpllsr = in_be32(&gur->porpllsr);
+
+   puts("\n");
+
+   pci_speed = 6000;
+   pci_32 = 1;
+   pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+   pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+   if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+   SET_STD_PCI_INFO(pci_info, 1);
+
+   pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+   printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+   (pci_32) ? 32 : 64,
+   (pci_speed == 3000) ? "33" :
+   (pci_speed == 6000) ? "66" : "unknown",
+   pci_clk_sel ? "sync" : "async",
+   pci_agent ? "agent" : "host",
+   pci_arb ? "arbiter" : "external-arbiter",
+   pci_info.regs);
+
+   first_free_busno = fsl_pci_init_port(&pci_info,
+   &pci1_hose, first_free_busno);
+   } else {
+   printf("PCI: disabled\n");
+   }
+
+   puts("\n");
+}
+
+int last_stage_init(void)
+{
+   int ret;
+   int len = 0;
+   const void *prop;
+   int chosen;
+uint32_t *dt_base_ptr = (void*)CONFIG_QEMU_DT_ADDR;
+   uint32_t dt_base = *dt_base_ptr;
+   uint3

[U-Boot] [PATCH 0/3] PPC 85xx: Add support for QEMU's ppce500 PV machine

2014-01-19 Thread Alexander Graf
In QEMU we implement a PV machine type called "ppce500". That board is able
to run any e500+ FSL cores (e500v2, e500mc, e5500, e6500).

It is heavily inspired by the MPC8544DS SoC and board combination, but
implements only the bare minimum to make Linux happy enough to drive a
virtual machine.

This patch set implements support for this PV machine type in U-Boot, enabling
users to run their virtual machines with netboot, u-boot payload binaries or
other fun things they come up with.

Alexander Graf (3):
  PPC 85xx: Detect e500v2 / e500mc during runtime
  PPC 85xx: Add ELF entry point
  PPC 85xx: Add qemu-ppce500 machine

 arch/powerpc/cpu/mpc85xx/fixed_ivor.S   |   21 ++-
 arch/powerpc/cpu/mpc85xx/start.S|7 +
 arch/powerpc/cpu/mpc85xx/u-boot.lds |1 +
 arch/powerpc/include/asm/config_mpc85xx.h   |4 +
 board/freescale/qemu-ppce500/Makefile   |   10 ++
 board/freescale/qemu-ppce500/qemu-ppce500.c |  260 +++
 board/freescale/qemu-ppce500/tlb.c  |   59 ++
 boards.cfg  |1 +
 include/configs/qemu-ppce500.h  |  235 
 9 files changed, 593 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/qemu-ppce500/Makefile
 create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c
 create mode 100644 board/freescale/qemu-ppce500/tlb.c
 create mode 100644 include/configs/qemu-ppce500.h

-- 
1.7.10.4

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[U-Boot] [PATCH 2/3] PPC 85xx: Add ELF entry point

2014-01-19 Thread Alexander Graf
We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.

To know where we have to start executing this ELF binary  we have to
tell the linker where our entry point is.

Signed-off-by: Alexander Graf 
---
 arch/powerpc/cpu/mpc85xx/u-boot.lds |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 2af4c80..b34d212 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -13,6 +13,7 @@
 #endif
 
 OUTPUT_ARCH(powerpc)
+ENTRY(_start_e500)
 
 PHDRS
 {
-- 
1.7.10.4

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[U-Boot] [PATCH 1/3] PPC 85xx: Detect e500v2 / e500mc during runtime

2014-01-19 Thread Alexander Graf
With the qemu-ppce500 machine type we can run the same board with
either an e500v2 or an e500mc core plugged in.

This means that the IVOR setup can't be based on compile time decisions,
so instead we have to do a runtime check which CPU generation we're
running on.

Signed-off-by: Alexander Graf 
---
 arch/powerpc/cpu/mpc85xx/fixed_ivor.S |   21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S 
b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
index ebbb8c0..635a97e 100644
--- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
+++ b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
@@ -36,17 +36,25 @@
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
SET_IVOR(15, 0x040) /* Debug */
 
-/* e500v1 & e500v2 only */
-#ifndef CONFIG_E500MC
+   /* Check for CPU */
+   mfpvr   r3
+   srwir3, r3, 16
+   /* Compare with e500mc PVR major number */
+   li  r4, 0
+   ori r4, r4, 0x8023
+   cmpwr3, r4
+
+   /* e500v1 & e500v2 only */
+   bge 1f
SET_IVOR(32, 0x200) /* SPE Unavailable */
SET_IVOR(33, 0x220) /* Embedded FP Data */
SET_IVOR(34, 0x240) /* Embedded FP Round */
-#endif
+1:
 
SET_IVOR(35, 0x260) /* Performance monitor */
 
-/* e500mc only */
-#ifdef CONFIG_E500MC
+   /* e500mc only */
+   blt 2f
SET_IVOR(36, 0x280) /* Processor doorbell */
SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
@@ -54,6 +62,8 @@
SET_IVOR(40, 0x300) /* Hypervisor system call */
SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
 
+#ifndef CONFIG_QEMU_E500
+   /* QEMU guests runs in guest mode and can't access GIVORs */
SET_GIVOR(2, 0x060) /* Guest Data Storage */
SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
SET_GIVOR(4, 0x0a0) /* Guest External Input */
@@ -61,3 +71,4 @@
SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
 #endif
+2:
-- 
1.7.10.4

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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Otavio Salvador
On Sun, Jan 19, 2014 at 12:34 PM, Andy Ng  wrote:
> The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10

Please:

 - Add Signed-off-by
 - Rebase it to imx/master as this does not apply in current source code.

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http://www.ossystems.com.brhttp://code.ossystems.com.br
Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Otavio Salvador
Andy,

On Sun, Jan 19, 2014 at 2:58 PM, Otavio Salvador
 wrote:
> On Sun, Jan 19, 2014 at 12:34 PM, Andy Ng  wrote:
>> The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10
>
> Please:
>
>  - Add Signed-off-by
>  - Rebase it to imx/master as this does not apply in current source code.
>
> --
> Otavio Salvador O.S. Systems
> http://www.ossystems.com.brhttp://code.ossystems.com.br
> Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750

This fixed one customer board I have as well.

I tested it using today's master tip.

Please change Q variant as well, rebased patch bellow:

diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 55cc9ad..3f41787 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01,0x05E0,
0x0210, 5, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,0x05E4, 0x0214, 0, 0x0850, 1, 0)
 MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x, 0, 0)
-MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2 |
IOMUX_CONFIG_SION, 0x080C, 0, 0)
 MX6_PAD_DECL(GPIO_16__SD1_LCTL,0x05E4, 0x0214, 3, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__SPDIF_IN,0x05E4, 0x0214, 4, 0x08F0, 2, 0)
 MX6_PAD_DECL(GPIO_16__GPIO7_IO11,  0x05E4, 0x0214, 5, 0x, 0, 0)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index ad31c33..3aae246 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -703,7 +703,7 @@ MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,  0x0614,
0x0244, 6, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,0x0618, 0x0248, 0, 0x0880, 1, 0)
 MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x, 0, 0)
-MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x0618, 0x0248, 2, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x0618, 0x0248, 2 |
IOMUX_CONFIG_SION, 0x083C, 1, 0)
 MX6_PAD_DECL(GPIO_16__SD1_LCTL,0x0618, 0x0248, 3, 0x, 0, 0)
 MX6_PAD_DECL(GPIO_16__SPDIF_IN,0x0618, 0x0248, 4, 0x0914, 3, 0)
 MX6_PAD_DECL(GPIO_16__GPIO7_IO11,  0x0618, 0x0248, 5, 0x, 0, 0)


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Re: [U-Boot] [PATCH 0/3] arm: vf610: Add QSPI support for VF610

2014-01-19 Thread Huan Wang
Hi, Jagan,

 Could you help to review the series? Thanks.

Best Regards,
Alison Wang


On Monday 13 January 2014 02:24 PM, Huan Wang wrote:
> Hi, Jagan,
>
>   I tested my driver based on your sf quad changes, and it is ok. For the 
> sf quad functions, I didn' t test, because my driver doesn't support sf quad 
> now.
Thanks for the test.

Just for confirmation, is it u-boot-spi/master-quad correct?

>  Thanks.
>
> Best Regards,
> Alison Wang
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadha.sutradharudu-t...@xilinx.com]
>> Sent: Monday, January 13, 2014 2:39 PM
>> To: Wang Huan-B18965; jagannadha.sutradharudu-t...@xilinx.com;
>> sba...@denx.de
>> Cc: u-boot@lists.denx.de
>> Subject: Re: [PATCH 0/3] arm: vf610: Add QSPI support for VF610
>>
>> Hi,
>>
>> Thanks for the series.
>> I will review once the today release done.
>>
>> And is it possible to test these changes on sf quad changes, if OK will
>> send the details.
>>
>> On Monday 13 January 2014 11:02 AM, Alison Wang wrote:
>>> This series contain QSPI support for Freescale Vybrid VF610.
>>>
>>> The QSPI(Quad Serial Peripheral Interface) acts as an interface to
>> one
>>> single or two external serial flash devices, each with up to 4
>> bidirectional data lines.
>>>
>>> QSPI has a Look-update-table(LUT) which consists of a number of
>>> pre-programmed sequences. Each sequence is basically a sequence of
>>> instruction-operand pairs which when executed sequentially generates
>> a valid serial flash transaction.
>>>
>>> This driver has been tested on VF610TWR.
>>>
>>> 
>>> Alison Wang (3):
>>> arm: imx: Add two macros for VF610 in IOMUX_PAD structure
>>> arm: vf610: Add QSPI support for VF610TWR
>>> arm: vf610: Add QSPI driver support
>>>
>>>arch/arm/include/asm/arch-vf610/crm_regs.h|  11 ++-
>>>arch/arm/include/asm/arch-vf610/imx-regs.h|   4 +-
>>>arch/arm/include/asm/arch-vf610/iomux-vf610.h |  14 +++
>>>arch/arm/include/asm/imx-common/iomux-v3.h|   2 +
>>>board/freescale/vf610twr/vf610twr.c   |  29 ++-
>>>drivers/spi/Makefile  |   1 +
>>>drivers/spi/fsl_qspi.c| 482
>> +++
>> 
>>>drivers/spi/fsl_qspi.h| 127
>> +++
>>>include/configs/vf610twr.h|  11 +++
>>>9 files changed, 677 insertions(+), 4 deletions(-)
>>>create mode 100644 drivers/spi/fsl_qspi.c
>>>create mode 100644 drivers/spi/fsl_qspi.h
>>>
>>>
>>
>> --
>> Thanks,
>> Jagan.
>>
>>
>> This email and any attachments are intended for the sole use of the
>> named recipient(s) and contain(s) confidential information that may be
>> proprietary, privileged or copyrighted under applicable law. If you are
>> not the intended recipient, do not read, copy, or forward this email
>> message or any attachments. Delete this email message and any
>> attachments immediately.
>>
>>
>
>

--
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Jagan.


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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Fabio Estevam
Hi Otavio/Andy,

On Sun, Jan 19, 2014 at 3:07 PM, Otavio Salvador
 wrote:

> --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> @@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01,0x05E0,
> 0x0210, 5, 0x, 0, 0)
>  MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x, 0, 0)
>  MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,0x05E4, 0x0214, 0, 0x0850, 1, 0)
>  MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x, 0, 
> 0)
> -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2, 0x080C, 0, 0)
> +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2 |

What about adding the SION bit in the board file only?

Then we would have the same behaviour as in the kernel.

Please check the hummingboard dts file:
https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi?id=refs/tags/next-20140117

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Otavio Salvador
On Sun, Jan 19, 2014 at 3:48 PM, Fabio Estevam  wrote:
> Hi Otavio/Andy,
>
> On Sun, Jan 19, 2014 at 3:07 PM, Otavio Salvador
>  wrote:
>
>> --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
>> +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
>> @@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01,0x05E0,
>> 0x0210, 5, 0x, 0, 0)
>>  MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x, 0, 0)
>>  MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,0x05E4, 0x0214, 0, 0x0850, 1, 0)
>>  MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x, 
>> 0, 0)
>> -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2, 0x080C, 0, 0)
>> +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,0x05E4, 0x0214, 2 |
>
> What about adding the SION bit in the board file only?
>
> Then we would have the same behaviour as in the kernel.
>
> Please check the hummingboard dts file:
> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi?id=refs/tags/next-20140117

Personally I think when using the ALT 2 people are expecting it works
out of box so I think this should be in the PAD declaration.

-- 
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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Fabio Estevam
On Sun, Jan 19, 2014 at 3:55 PM, Otavio Salvador
 wrote:

> Personally I think when using the ALT 2 people are expecting it works
> out of box so I think this should be in the PAD declaration.

This pin works out of the box in hummingboard, for example.

IOMUX_CONFIG_SION is not used anywhere in the
mx6q_pins.h/mx6dl_pins.h, so why GPIO_16__ENET_
REF_CLK should be an exception?

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected

2014-01-19 Thread Otavio Salvador
On Sun, Jan 19, 2014 at 4:03 PM, Fabio Estevam  wrote:
> On Sun, Jan 19, 2014 at 3:55 PM, Otavio Salvador
>  wrote:
>
>> Personally I think when using the ALT 2 people are expecting it works
>> out of box so I think this should be in the PAD declaration.
>
> This pin works out of the box in hummingboard, for example.
>
> IOMUX_CONFIG_SION is not used anywhere in the
> mx6q_pins.h/mx6dl_pins.h, so why GPIO_16__ENET_
> REF_CLK should be an exception?

Are you sure?

% git grep -c IOMUX_CONFIG_SION arch/arm/include/asm/arch-mx6/
arch/arm/include/asm/arch-mx6/mx6dl_pins.h:31
arch/arm/include/asm/arch-mx6/mx6q_pins.h:1

The q_pins is outdate it seems.

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[U-Boot] [PATCH] yaffs2: Remove block number check from summary verification

2014-01-19 Thread Charles Manning
The summary already has other verification. This one is not needed.

The check caused summaries to be ignored if they were not on the
numbered block. This caused problems when a summary was embedded in an
image and the image is written to a flash with bad blocks.

Signed-off-by: Charles Manning 
---
 fs/yaffs2/yaffs_summary.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c
index 46e42f6..e9e1b5d 100644
--- a/fs/yaffs2/yaffs_summary.c
+++ b/fs/yaffs2/yaffs_summary.c
@@ -232,7 +232,6 @@ int yaffs_summary_read(struct yaffs_dev *dev,
if (result == YAFFS_OK) {
/* Verify header */
if (hdr.version != YAFFS_SUMMARY_VERSION ||
-   hdr.block != blk ||
hdr.seq != bi->seq_number ||
hdr.sum != yaffs_summary_sum(dev))
result = YAFFS_FAIL;
-- 
1.7.9.5
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[U-Boot] changing default serial console from UART0 to UART 1

2014-01-19 Thread pshambhu
Hi,

   I am interested in changing the default serial console from UART 0 to
UART 1, which are the files need to be changed in u-boot code and what
changes are done , so that with new u-boot , the console should be on UART1. 

Thanks in advance.

Thanks and Regards
Pradeep S 



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Re: [U-Boot] changing default serial console from UART0 to UART 1

2014-01-19 Thread Abraham Varricatt
Ummm... what hardware are you working on ? processor+board ?

-Abraham V.

On Mon, Jan 20, 2014 at 12:20 PM, pshambhu  wrote:
> Hi,
>
>I am interested in changing the default serial console from UART 0 to
> UART 1, which are the files need to be changed in u-boot code and what
> changes are done , so that with new u-boot , the console should be on UART1.
>
> Thanks in advance.
>
> Thanks and Regards
> Pradeep S
>
>
>
> --
> View this message in context: 
> http://u-boot.10912.n7.nabble.com/changing-default-serial-console-from-UART0-to-UART-1-tp171838.html
> Sent from the U-Boot mailing list archive at Nabble.com.
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Re: [U-Boot] [PATCH v5 03/12] samsung: common: Add misc file and common function misc_init_r().

2014-01-19 Thread Minkyu Kang
On 17/01/14 17:36, Przemyslaw Marczak wrote:
> On 01/17/2014 07:26 AM, Minkyu Kang wrote:
>> On 15/01/14 17:18, Przemyslaw Marczak wrote:
>>>
>>> In this way we can add other functions in the future even without
> CONFIG_MISC_INIT_R.
>>
>> partly agree.
>> But, I doubt what is the role of misc.c file.
>> because of the meaning of miscellaneous is ambiguous, this file have
>> possibility to be messy.
>> So, please let me know what is your plan to this file.
>>
>
> I first planned put there only implementation of misc_init_r() and it's
> subfunctions - as the easy way to display logo and menu for Samsung
> boards.
> Piotr has suggested to change the purpose of this file as misc not only
> for misc_init_r implementation...
 Przemyslaw, I asked you question: what is the misc.c file for?
 If for misc_init_r only then I think the file name "misc.c" is confusing.
 If also other common functions can be put there, then the define 
 MISC_INIT_R
 to compile this file is wrong.

>>>
>>> Yes, and next I said that maybe I will change this config dependency, and 
>>> now I try to do it.
>>>
>>
>> Actually, I feel negative to this changes.
>> Because misc_init_r is a board specific.
>> How you can support if someone want to do something (board specific things) 
>> on misc_init_r?
>> I totally understand why you add misc_init_r to common directory. - It means 
>> you don't have to explain why you added it :)
>> but it looks little weird.
>> So we will discuss that misc_init_r should go to each boards or stay here? 
>> (misc_init_r function only, not including key, menu, logo.. etc)
>>
>> Please let me know your opinions.
>>
>> Thanks,
>> Minkyu Kang.
>>
>>
> 
> The reason why I used misc_init_r for a common purposes is that it is called 
> after all hardware initialization and before u-boot main_loop(), then I don't 
> need to introduce another generic function just to check buttons - this is 
> the only reason.
> 
> Moreover at this time misc_init_r() is implemented only in Trats2, and there 
> are easy to move things.
> 
> You're right - misc_init_r is board specific, but if we make it as a common 
> function, then we also can add board specific code, called here but 
> implemented in board files.

No. it looks wrong architecture.

> 
> If this is wrong, then where is the better place for check keys, display logo 
> and any more vendor common things?

Stay at common directory.

> 
> Or maybe the better solution is just add new function callback to 
> board_init_r() for some vendor specific purposes - and then it can be used 
> for other vendors platforms too.

No.

Here, I've made pseudo code for it.
How you think?

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
new file mode 100644
index 000..cdc48bb
--- /dev/null
+++ b/board/samsung/common/misc.c
@@ -0,0 +1,18 @@
+#ifdef CONFIG_LCD_MENU
+void keys_init(void)
+{
+   /* TODO */
+}
+
+void check_boot_mode(void)
+{
+   /* TODO */
+}
+#endif
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+   /* TODO */
+}
+#endif
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index be15357..eb4f4dc 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -623,6 +623,16 @@ int misc_init_r(void)
 
show_hw_revision();
 
+#ifdef CONFIG_LCD_MENU
+   keys_init();
+   check_boot_mode();
+#endif
+
+#ifdef CONFIG_CMD_BMP
+   if (panel_info.logo_on)
+   draw_logo();
+#endif
+
return 0;
 }
 #endif

Thanks,
Minkyu Kang.
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Re: [U-Boot] changing default serial console from UART0 to UART 1

2014-01-19 Thread pshambhu
Hi,

 I am using P2020 PowerPC QorIQ Family Processor.


Thanks and Regards
Pradeep S



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[U-Boot] Uboot_Header_Modification_by_CVS

2014-01-19 Thread Arun K. Varghese
Hi,

Issue.
---

1) Downloaded u-boot-2010.09 source code. 
(u-boot-2010.09.tar.bz2)
2) Some files, have version & header information along with the source code.

Ex:
1)  In  u-boot-2010.09/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h

 * @version $Revision: 0.1 $

2)  In u-boot-2010.09/arch/i386/cpu/sc520/sc520_asm.S

 * $Revision: 1.2 $
 * $Date: 1999/09/22 12:49:33 $
 * $Author: chipf $

3) When I do a check in for these files, using CVS, these header information is 
changed.
CVS is  automatically modifying these headers.

Eg :

In u-boot-2010.09/arch/i386/cpu/sc520/sc520_asm.S

 * $Revision: 1.2 $
 * $Date: 1999/09/22 12:49:33 $
 * $Author: chipf $

If I do a check in, it will be changed to

 * $Revision: 1.1.1.2 $
 * $Date: 2013/12/16 12:49:33 $
 * $Author: Arun $

Doubts
-

1. Why only few files have these kind of header information in Uboot repository 
?

2. If I do a check in via CVS, the headers will be modified,
   So will it be a violation to GPL ?

3.  If it is a Violation , please help me with a solution .

Thanks & Regards,
Arun

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[U-Boot] [PATCH 1/2] SECURE BOOT: add version info for ISBC

2014-01-19 Thread Aneesh Bansal
T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
---
 README| 3 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 9 +
 2 files changed, 12 insertions(+)

diff --git a/README b/README
index aea82be..6c3a8d1 100644
--- a/README
+++ b/README
@@ -423,6 +423,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
 
+   CONFIG_SYS_FSL_ISBC_VER
+   This value indicates the major ISBC version on the platform.
+
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL 
SoC's.
In this mode, a single differential clock is used to supply
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..ba5b6fe 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -151,6 +151,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ISBC_VER1
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
 
 /* P1011 is single core version of P1020 */
@@ -383,6 +384,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -421,6 +423,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -470,6 +473,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64   /* 64-bit core */
@@ -504,6 +508,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -536,6 +541,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS1
@@ -575,6 +581,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500
@@ -631,6 +638,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
 #define CONFIG_SYS_FSL_PCI_VER_3_X
+#define CONFIG_SYS_FSL_ISBC_VER2
 
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define CONFIG_E6500
@@ -657,6 +665,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
+#define CONFIG_SYS_FSL_ISBC_VER2
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
-- 
1.8.1.4


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[U-Boot] [PATCH 2/2] SECURE BOOT: Add secure boot target for B4860QDS

2014-01-19 Thread Aneesh Bansal
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c| 28 +++-
 arch/powerpc/cpu/mpc85xx/start.S   |  3 ++-
 arch/powerpc/include/asm/fsl_secure_boot.h |  6 ++
 boards.cfg |  1 +
 4 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..de1116b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -125,17 +125,15 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 #endif
 
 #ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+
+#ifdef CONFIG_RAMBOOT_PBL || defined(CONFIG_SECURE_HKAREA_CPC)
+static void disable_cpc_sram(void)
 {
int i;
-   u32 size = 0;
 
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
-   u32 cpccfg0 = in_be32(&cpc->cpccfg0);
-   size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
@@ -150,8 +148,21 @@ static void enable_cpc(void)
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
+   }
+}
 #endif
 
+static void enable_cpc(void)
+{
+   int i;
+   u32 size = 0;
+
+   cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+   for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+   size += CPC_CFG0_SZ_K(cpccfg0);
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 #endif
@@ -250,6 +261,10 @@ void cpu_init_f (void)
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
+
+#if defined(CONFIG_SECURE_HKAREA_CPC)
+   disable_cpc_sram();
+#endif
 #endif
 
 #ifdef CONFIG_CPM2
@@ -550,6 +565,9 @@ skip_l2:
puts("disabled\n");
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL)
+   disable_cpc_sram();
+#endif
enable_cpc();
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..5440bf5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -117,7 +117,8 @@ _start_e500:
 #endif
 
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+   !defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
 * Disable L2 cache here so that u-boot can enable it later
 * as part of it's normal flow
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 4c7f0b1..db124df 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -15,5 +15,11 @@
 #endif
 #define CONFIG_SYS_PBI_FLASH_WINDOW0xcff8
 
+#if CONFIG_SYS_FSL_ISBC_VER > 1
+#define CONFIG_SECURE_HKAREA_CPC
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR0xbff0
+#endif
+
 #endif
 #endif
diff --git a/boards.cfg b/boards.cfg
index 928e222..1d6a14c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -780,6 +780,7 @@ Active  powerpc mpc85xx-   freescale
   b4860qds
 Active  powerpc mpc85xx-   freescale   b4860qds
B4420QDS_NAND
B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   b4860qds
B4420QDS_SPIFLASH
B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   b4860qds
B4860QDS B4860QDS:PPC_B4860 

   -
+Active  powerpc mpc85xx  

[U-Boot] [PATCH 1/2][v2] powerpc/mpc85xx: SECURE BOOT- add version info for ISBC

2014-01-19 Thread Aneesh Bansal
T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
---
 README| 3 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 9 +
 2 files changed, 12 insertions(+)

Changes from v1:
Updated the commit message

diff --git a/README b/README
index aea82be..6c3a8d1 100644
--- a/README
+++ b/README
@@ -423,6 +423,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
 
+   CONFIG_SYS_FSL_ISBC_VER
+   This value indicates the major ISBC version on the platform.
+
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL 
SoC's.
In this mode, a single differential clock is used to supply
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..ba5b6fe 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -151,6 +151,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ISBC_VER1
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
 
 /* P1011 is single core version of P1020 */
@@ -383,6 +384,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -421,6 +423,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -470,6 +473,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64   /* 64-bit core */
@@ -504,6 +508,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -536,6 +541,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS1
@@ -575,6 +581,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
+#define CONFIG_SYS_FSL_ISBC_VER1
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500
@@ -631,6 +638,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
 #define CONFIG_SYS_FSL_PCI_VER_3_X
+#define CONFIG_SYS_FSL_ISBC_VER2
 
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define CONFIG_E6500
@@ -657,6 +665,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
+#define CONFIG_SYS_FSL_ISBC_VER2
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
-- 
1.8.1.4


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[U-Boot] [PATCH 2/2][v2] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

2014-01-19 Thread Aneesh Bansal
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c| 28 +++-
 arch/powerpc/cpu/mpc85xx/start.S   |  3 ++-
 arch/powerpc/include/asm/fsl_secure_boot.h |  6 ++
 boards.cfg |  1 +
 4 files changed, 32 insertions(+), 6 deletions(-)

Changes from v1:
Updated the commit message

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..de1116b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -125,17 +125,15 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 #endif
 
 #ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+
+#ifdef CONFIG_RAMBOOT_PBL || defined(CONFIG_SECURE_HKAREA_CPC)
+static void disable_cpc_sram(void)
 {
int i;
-   u32 size = 0;
 
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
-   u32 cpccfg0 = in_be32(&cpc->cpccfg0);
-   size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
@@ -150,8 +148,21 @@ static void enable_cpc(void)
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
+   }
+}
 #endif
 
+static void enable_cpc(void)
+{
+   int i;
+   u32 size = 0;
+
+   cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+   for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+   size += CPC_CFG0_SZ_K(cpccfg0);
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 #endif
@@ -250,6 +261,10 @@ void cpu_init_f (void)
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
+
+#if defined(CONFIG_SECURE_HKAREA_CPC)
+   disable_cpc_sram();
+#endif
 #endif
 
 #ifdef CONFIG_CPM2
@@ -550,6 +565,9 @@ skip_l2:
puts("disabled\n");
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL)
+   disable_cpc_sram();
+#endif
enable_cpc();
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..5440bf5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -117,7 +117,8 @@ _start_e500:
 #endif
 
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+   !defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
 * Disable L2 cache here so that u-boot can enable it later
 * as part of it's normal flow
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 4c7f0b1..db124df 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -15,5 +15,11 @@
 #endif
 #define CONFIG_SYS_PBI_FLASH_WINDOW0xcff8
 
+#if CONFIG_SYS_FSL_ISBC_VER > 1
+#define CONFIG_SECURE_HKAREA_CPC
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR0xbff0
+#endif
+
 #endif
 #endif
diff --git a/boards.cfg b/boards.cfg
index 928e222..1d6a14c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -780,6 +780,7 @@ Active  powerpc mpc85xx-   freescale
   b4860qds
 Active  powerpc mpc85xx-   freescale   b4860qds
B4420QDS_NAND
B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   b4860qds
B4420QDS_SPIFLASH
B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   b4860qds
B4860QDS B4860QDS:PPC_B4860