date:20130329

Re: [U-Boot] [PATCH] disk: add -mno-unaligned-access to CFLAGS

2013-03-29 Thread Albert ARIBAUD

Hi Marc,

On Thu, 28 Mar 2013 23:35 +0100, Marc Dietrich  wrote:

> Hi Albert,
> 
> On Thursday 28 March 2013 21:42:13 Albert ARIBAUD wrote:
> > On Thu, 28 Mar 2013 19:57:31 +0100, Marc Dietrich 
> > wrote:
> > > Many on-disk structures used in the directory are accessed in a
> > > non aligned manner. gcc => 4.7 (and gcc-4.6 from Linaro) switched
> > > to -munaligned-access on default causing exceptions on ARM. The
> > > easiest way to fix this is to force no-unaligned-access in this
> > > (non speed critical) directory.
> > > 
> > > Signed-off-by: Marc Dietrich 
> > > ---
> > > 
> > >  disk/Makefile |1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/disk/Makefile b/disk/Makefile
> > > index 5affe34..01134a3 100644
> > > --- a/disk/Makefile
> > > +++ b/disk/Makefile
> > > @@ -24,6 +24,7 @@
> > > 
> > >  include $(TOPDIR)/config.mk
> > >  
> > >  #CFLAGS += -DET_DEBUG -DDEBUG
> > > 
> > > +CFLAGS += -mno-unaligned-access
> > > 
> > >  LIB  = $(obj)libdisk.o
> > 
> > Which fields, which structures, which files are affected by the
> > unalignment issue?
> 
> in my test case, it is the start sector of a partition (check 
> include/part_efi.h). disk/part_efi.c reads the legacy mbr (to an aligned 
> buffer) which has a partition structure on offset 440+4+2 (<- not aligned to 
> 4 
> byte boundary) and inside this a 32 bit field start_sect (aligned to 4 byte 
> boundary). Reading this field (and also the next, nr_sects) will cause an 
> exception. Same is for part_dos, but there we still use le32_to_int which 
> reads byte by byte. I didn't checked others.

Thanks for clarifying.

Considering this is about a very small number of reads, I strongly
prefer that these reads be done through the get_unaligned(&field) macro
defined in e.g. arch/arm/include/asm/unaligned.h, even at the slightly
added cost of decomposing the reads into 8-bit accesses.

Doing so solves the issue at hand while still allowing the rest of the
code to detect cases where unalignment stems from error conditions, e.g.
bad pointers or erroneous changes in structures, etc.

> Marc

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH 1/1 v2] omap3_beagle: Enabling UART3 first allows the Transmitter to be empty

2013-03-29 Thread Manfred Huber


On 2013-03-27 10:29, Javier Martinez Canillas wrote:

On Wed, Mar 27, 2013 at 5:50 AM, Manfred Huber  wrote:




I still think that we should keep CONFIG_SYS_NS16550_BROKEN_TEMT or
something similar instead of just checking for CONFIG_OMAP34XX. Since
we don't know if this problem is also present on other TI OMAP
platforms (or any other platform). I would just change
CONFIG_SYS_NS16550_BROKEN_TEMT semantics once is confirmed that this
also fixes the issue on IGEP boards.

If we continue using CONFIG_SYS_NS16550_BROKEN_TEMT, there is no benefit 
by my patch. It works with the define alone.

Also, if you are removing CONFIG_SYS_NS16550_BROKEN_TEMT then you have
to update the README too since it is explained there what this config
option does.


And also in igep00x0.h




Thank a lot and best regards,
Javier



On 2013-03-25 23:02, Manfred Huber wrote:




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Re: [U-Boot] [PATCH 1/1 v2] omap3_beagle: Enabling UART3 first allows the Transmitter to be empty

2013-03-29 Thread Manfred Huber


Am 28.03.2013 09:45, schrieb Andreas Bießmann:

Dear Manfred Huber,

On 03/28/2013 07:06 AM, Manfred Huber wrote:

On 2013-03-27 14:37, Andreas Bießmann wrote:





On 03/25/2013 11:02 PM, Manfred Huber wrote:





+serial_out(UART_LCR_DLAB, &com_port->lcr);
+serial_out(baud_divisor & 0xff, &com_port->dll);
+serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+serial_out(UART_LCRVAL, &com_port->lcr);
+serial_out(0, &com_port->mdr1);





I wonder which use-case requires UART flushing in u-boot context before
initializing the UART for u-boot correctly. Can someone explain this to
me? Shouldn't we always start here from the very beginning and setup
UART as configured?
Beagleboard has several ways to boot (NAND, SD/MMC, UART, ...). For the 
boot mode with UART, Beagleboard configures the UART and ends with a non 
empty transmitter. In a booting sequence where UART is before NAND, 
SD/MMC or wherever SPL starts from, we have not a clean UART.







It's not critical. So I guess it's not needed for this release.


Well, if there are boards in the field that will not boot with the next
release I think it is critical.
We do have some omap3 (omap35xx and am37xx) based boards here. I can
recall a situation where some few boards did not boot from sd-card while
serial debug cable was attached (AFAIR this was not the case when
booting from NAND). The root cause was never investigated, so maybe we
suffered exactly this bug.

Can you test this boars with my patch?


Best regards

Andreas Bießmann



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[U-Boot] [PATCH 1/1 v3] omap3_beagle: Enabling UART3 first allows the Transmitter to be empty

2013-03-29 Thread Manfred Huber

On some OMAP3 devices when UART3 is configured for boot mode before SPL starts 
only THRE bit is set. We have to empty the transmitter before initialization 
starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.

Signed-off-by: Manfred Huber 
---
README |8 
 drivers/serial/ns16550.c   |   16 ++--
 include/configs/igep00x0.h |3 ---
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/README b/README
index a336476..e6b3a50 100644
--- a/README
+++ b/README
@@ -616,14 +616,6 @@ The following options need to be configured:
boot loader that has already initialized the UART.  Define this
variable to flush the UART at init time.
 
-   CONFIG_SYS_NS16550_BROKEN_TEMT
-
-   16550 UART set the Transmitter Empty (TEMT) Bit when all output
-   has finished and the transmitter is totally empty. U-Boot waits
-   for this bit to be set to initialize the serial console. On some
-   broken platforms this bit is not set in SPL making U-Boot to
-   hang while waiting for TEMT. Define this option to avoid it.
-
 
 - Console Interface:
Depending on board, define exactly one serial port

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..2922a2c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -36,10 +36,22 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
-#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+   /* On some OMAP3 devices when UART3 is configured for boot mode before
+  SPL starts only THRE bit is set. We have to empty the transmitter
+  before initialization starts. */
+   if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
+== UART_LSR_THRE) {
+   serial_out(UART_LCR_DLAB, &com_port->lcr);
+   serial_out(baud_divisor & 0xff, &com_port->dll);
+   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+   serial_out(UART_LCRVAL, &com_port->lcr);
+   serial_out(0, &com_port->mdr1);
+   }
+#endif
+
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
-#endif
 
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \

diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index f8131b1..0617a58 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -67,9 +67,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
 
-/* define to avoid U-Boot to hang while waiting for TEMT */
-#define CONFIG_SYS_NS16550_BROKEN_TEMT
-
 /* select serial console configuration */
 #define CONFIG_CONS_INDEX  3
 #define CONFIG_SYS_NS16550_COM3OMAP34XX_UART3
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Re: [U-Boot] [PATCH 1/1 v3] omap3_beagle: Enabling UART3 first allows the Transmitter to be empty

2013-03-29 Thread Albert ARIBAUD

Hi Manfred,

On Fri, 29 Mar 2013 10:20:25 +0100, Manfred Huber 
wrote:

> On some OMAP3 devices when UART3 is configured for boot mode before SPL 
> starts 
> only THRE bit is set. We have to empty the transmitter before initialization 
> starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.
> 
> Signed-off-by: Manfred Huber 
> ---

Patch history is missing here.

Also, I would like the commit summary (first commit message line, also
subject of the patch mail) to clearly state what the patch *does* as
opposed to what *happens*, because it is unclear right now if you're
describing the solution or the issue. Something like :

"omap3_beagle: flush UART3 xmit on enable if TEMT is broken"

> README |8 
>  drivers/serial/ns16550.c   |   16 ++--
>  include/configs/igep00x0.h |3 ---
>  3 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/README b/README
> index a336476..e6b3a50 100644
> --- a/README
> +++ b/README
> @@ -616,14 +616,6 @@ The following options need to be configured:
>   boot loader that has already initialized the UART.  Define this
>   variable to flush the UART at init time.
>  
> - CONFIG_SYS_NS16550_BROKEN_TEMT
> -
> - 16550 UART set the Transmitter Empty (TEMT) Bit when all output
> - has finished and the transmitter is totally empty. U-Boot waits
> - for this bit to be set to initialize the serial console. On some
> - broken platforms this bit is not set in SPL making U-Boot to
> - hang while waiting for TEMT. Define this option to avoid it.
> -
>  
>  - Console Interface:
>   Depending on board, define exactly one serial port
> 
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 87a0917..2922a2c 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -36,10 +36,22 @@
>  
>  void NS16550_init(NS16550_t com_port, int baud_divisor)
>  {
> -#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
> +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
> + /* On some OMAP3 devices when UART3 is configured for boot mode before
> +SPL starts only THRE bit is set. We have to empty the transmitter
> +before initialization starts. */
> + if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
> +  == UART_LSR_THRE) {
> + serial_out(UART_LCR_DLAB, &com_port->lcr);
> + serial_out(baud_divisor & 0xff, &com_port->dll);
> + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
> + serial_out(UART_LCRVAL, &com_port->lcr);
> + serial_out(0, &com_port->mdr1);
> + }
> +#endif
> +
>   while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
>   ;
> -#endif
>  
>   serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
>  #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
> 
> diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
> index f8131b1..0617a58 100644
> --- a/include/configs/igep00x0.h
> +++ b/include/configs/igep00x0.h
> @@ -67,9 +67,6 @@
>  #define CONFIG_SYS_NS16550_REG_SIZE  (-4)
>  #define CONFIG_SYS_NS16550_CLK   V_NS16550_CLK
>  
> -/* define to avoid U-Boot to hang while waiting for TEMT */
> -#define CONFIG_SYS_NS16550_BROKEN_TEMT
> -
>  /* select serial console configuration */
>  #define CONFIG_CONS_INDEX3
>  #define CONFIG_SYS_NS16550_COM3  OMAP34XX_UART3
> ___
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> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot


Amicalement,
-- 
Albert.
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[U-Boot] [ARM] Status for upcoming v2013.04

2013-03-29 Thread Albert ARIBAUD

Hello all,

I have gone through my todo list on Patchwork and I think I have
processed all patches and applied all the ones posted within the
merge window or that are bug fixes for v2013.04 and for which no
changes requests are pending.

However, I may have missed some, so as usual, do mail To: me and Cc:
the list for any patch(es) you think I forgot to take in before the
upcoming release.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH] common/lcd.c: cleanup use of global variables

2013-03-29 Thread Anatolij Gustschin

Hello Wolfgang,

On Sat,  5 Jan 2013 20:45:48 +0100
Wolfgang Denk  wrote:

> lcd_color_fg and lcd_color_bg had to be declared in board specific
> code, but were not actually used there; in addition, we have getter /
> setter functions for these, which were not used either.
> 
> Get rid of the global variables, and use the getter function where
> needed (so far no setter calls are needed).
> 
> Signed-off-by: Wolfgang Denk 
> Cc: Alessandro Rubini 
> Cc: Anatolij Gustschin 
> Cc: Bo Shen 
> Cc: Haavard Skinnemoen 
> Cc: Kyungmin Park 
> Cc: Marek Vasut 
> Cc: Minkyu Kang 
> Cc: Nikita Kiryanov 
> Cc: Simon Glass 
> Cc: Stelian Pop 
> Cc: Tom Warren 
> ---
>  arch/arm/cpu/pxa/pxafb.c  | 2 --
>  arch/powerpc/cpu/mpc8xx/lcd.c | 3 ---
>  board/mcc200/lcd.c| 3 ---
>  common/lcd.c  | 7 ---
>  drivers/video/amba.c  | 2 --
>  drivers/video/atmel_hlcdfb.c  | 2 --
>  drivers/video/atmel_lcdfb.c   | 2 --
>  drivers/video/exynos_fb.c | 2 --
>  drivers/video/tegra.c | 4 +---
>  include/lcd.h | 6 +++---
>  10 files changed, 8 insertions(+), 25 deletions(-)

Patch rebased and merged, thanks!

Anatolij
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Re: [U-Boot] [PATCH v2 00/10] common.lcd: remove globals and cleanup

2013-03-29 Thread Anatolij Gustschin

Hi,

On Tue, 22 Jan 2013 21:44:06 +0100
Jeroen Hofstee  wrote:

> As mentioned in http://lists.denx.de/pipermail/u-boot/2013-January/143459.html
> there does not seem to be a good reason why the frame buffer driver
> provide the variables for the lcd internal logic. So lets just remove it.
> If there is any good reason for a framebuffer driver to "call up" it should
> do so by a function call and not change the lcd its internal state (and
> there is actually none doing so at the moment).
> 
> This patchset first removes unused drivers and places drivers useing
> common/lcd.c in drivers/video. Then removes the unneeded globals and
> thereafter finishes with some cleanups.
> 
> This patch goes after http://patchwork.ozlabs.org/patch/209692/
> "common/lcd.c: cleanup use of global variables"
> 
> Version 2:
>  Marek Vasut : use format-patch -M to detect moves
>  Adjust the commit message not to exceed the max line length
>  Fix malformed email address.
>  check-patch clean (adjusted a space in patch 6)
>  remove bouncing email addresses and add acks
>  patch 7 and 10 are unchanged and not reposted
> 
> Jeroen Hofstee (10):
>   lcd, amba: remove this driver since it is not used
>   lcd, tegra: remove unused cursor functions
>   lcd, mpc8xx: move the mpc8xx driver to drivers/video
>   lcd, pxafb: move the pxafb to drivers/video
>   common/lcd.c: cleanup use of global variables
>   common/lcd.c: remove global lcd_base
>   common/lcd: cosmetic: clean up a bit
>   lcd, fb: remove duplicated prototypes and unused code
>   api/api_display: use the getters for console size info
>   common/lcd.c: move the macro's to the c file
> 
>  api/api_display.c  |4 +-
>  arch/arm/cpu/pxa/Makefile  |1 -
>  arch/powerpc/cpu/mpc8xx/Makefile   |1 -
>  board/mcc200/lcd.c |   21 +---
>  common/lcd.c   |  117 
> +++-
>  drivers/video/Makefile |3 +-
>  drivers/video/amba.c   |   77 -
>  drivers/video/atmel_hlcdfb.c   |8 --
>  drivers/video/atmel_lcdfb.c|8 --
>  drivers/video/exynos_fb.c  |   14 +--
>  .../cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c |   58 +-
>  .../arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c |   41 ---
>  drivers/video/tegra.c  |   64 +--
>  include/configs/R360MPI.h  |1 +
>  include/configs/RBC823.h   |1 +
>  include/configs/RPXlite_DW.h   |1 +
>  include/configs/RRvision.h |4 +-
>  include/configs/TQM823L.h  |1 +
>  include/configs/TQM823M.h  |1 +
>  include/configs/lubbock.h  |1 +
>  include/configs/lwmon.h|1 +
>  include/configs/palmld.h   |1 +
>  include/configs/palmtc.h   |1 +
>  include/configs/pxa255_idp.h   |1 +
>  include/configs/svm_sc8xx.h|1 +
>  include/configs/v37.h  |1 +
>  include/configs/zipitz2.h  |1 +
>  include/lcd.h  |   71 +++-
>  28 files changed, 109 insertions(+), 396 deletions(-)
>  delete mode 100644 drivers/video/amba.c
>  rename arch/powerpc/cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c (92%)
>  rename arch/arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c (93%)

Merged this series after rebasing, also merged patches
7 and 10 from previous series. Thanks!

Anatolij
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Re: [U-Boot] [PATCH 07/10] common/lcd: cosmetic: clean up a bit

2013-03-29 Thread Anatolij Gustschin

Hi,

On Sat, 12 Jan 2013 23:07:56 +0100
Jeroen Hofstee  wrote:

>  - Make the brackets of the function calls more consistent
>  - Remove really unnecessary brackets
>  - Removes the extern from the function definitions
>  - Remove curly brackets from single line statements
>  - Remove lcd_setmem proto since it is already in common.h
>  - Don't init globals to 0
> 
> cc: Anatolij Gustschin 
> Signed-off-by: Jeroen Hofstee 
> ---
>  common/lcd.c  |   84 
> ++---
>  include/lcd.h |   35 +++-
>  2 files changed, 48 insertions(+), 71 deletions(-)

merged rebased patch, thanks!

Anatolij
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Re: [U-Boot] [PATCH 10/10] common/lcd.c: move the macro's to the c file

2013-03-29 Thread Anatolij Gustschin

On Sat, 12 Jan 2013 23:07:59 +0100
Jeroen Hofstee  wrote:

> Hide the console macros since some reference global data which is
> no longer present.
> 
> cc: Anatolij Gustschin 
> Signed-off-by: Jeroen Hofstee 
> ---
>  common/lcd.c  |   28 
>  include/lcd.h |   28 
>  2 files changed, 28 insertions(+), 28 deletions(-)

merged rebased patch, thanks!

Anatolij
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Re: [U-Boot] [PATCH] Fix bitmap offsets for non 8-bit LCDs

2013-03-29 Thread Anatolij Gustschin

Hello,

On Thu, 14 Feb 2013 16:48:00 +1300
Andre Renaud  wrote:

> Currently bitmap logos don't interpret the X coordinate correctly if the bpp
> is anything other than 8.
> 
> Signed-off-by: Andre Renaud 
> ---
>  common/lcd.c |7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)

applied, thanks!

Anatolij
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Re: [U-Boot] [PATCH] video: Fix splash screen alignment

2013-03-29 Thread Anatolij Gustschin

Hello,

On Fri, 15 Feb 2013 14:35:12 +0100
Matthias Weisser  wrote:

> commit d484b52 "video: Skip bitmaps which do not fit into the screen in
> cfb_console" breaks splash screen alignment which is passed in as magic
> (BMP_ALIGN_CENTER) x/y coordinates. Moving the check after the alignment block
> fixes this.
> 
> Signed-off-by: Matthias Weisser 
> ---
>  drivers/video/cfb_console.c |   14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)

applied, thanks!

Anatolij
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Re: [U-Boot] [PATCH 0/4 v8] Add ACE HW support for SHA256 and SHA1

2013-03-29 Thread Minkyu Kang

On 21/03/13 16:00, Akshay Saraswat wrote:
> This patch set adds hardware acceleration for SHA 256
> with the help of ACE.
> 
> Changes since v1:
>   - Patch-1: Fixed few nits.
>   - Patch-2: Removed not required config.
>   - Patch-3: Added sha256 to hash command instead of new sha256 command.
> 
> Changes since v2:
> - Patch-1: 
>   - Added falling back to software sha256 in case length exceeds 
> buffer limit.
>   - Reduced one tab at lines 533, 559 and 571 in the patch.
>   - Removed space after a cast at line 506 in the patch.
>   - Removed blank line at line 561 in the patch.
>   - Removed space before semicolon at line 576 in the patch.
> - Patch-2: 
>   - Added "SHA1" in the comment for config.
> - Patch-3: 
>   - Added new nodes for SHA1 and SHA256 in struct hash_algo for 
> the case when
> ACE is enabled.
>   - Added new declaration for function pointer hash_func_ws with 
> different
> return type.
> - Patch-4: 
>   - New patch to enable config for hash command.
> 
> Changes since v3:
>   - Patch-1:
>   - Removed buffer limit since there are 2 regs for address 
> hash_msg_size_high
> and low.
> That means buffer length could go upto 2^64 bits which is 
> practically 
>   - Removed falling back to software sha256 because there is no 
> buffer limit.
>   - Removed "/ 4" to sha1 and sha256 lengths and added increment 
> to 4 in for
> loop at line 573.
>   - Timed out still kept to be 100 ms since this is enough for 
> hardware to
> switch status to idle from busy.
> In case it couldn't that means h/w is faulty.
>   - Patch-2:
>   - Added "Acked-by: Simon Glass ".
>   - Patch-3:
>   - New patch.
>   - Patch-4:
>   - Changed command names to lower case in algo struct.
>   - Added generic ace_sha config.
>   - Patch-5: Added acked-by Simon Glass
>   - Added new generic config for ace_sha to enable ace support in 
> hash.c.
> 
> Changes since v4:
>   - Patch-1:
>   - Added include for clk.h.
>   - Added define for MAX_FREQ.
>   - Added timeout calculation as per frequency.
>   - Changed "i+=4" to "i++" and "len" to "len/4" in for loop at 
> line 591
> in this patch.
>   - Added two new functions ace_sha256 and ace_sha1.
>   - Patch-2: None.
>   - Patch-3:
>   - Changed function names in struct algo.
>   - Replaced ACE_SHA_TYPE to CHUNSZ in struct algo.
>   - Patch-4: Added "Acked-by: Simon Glass ".
> 
> Changes since v5:
>   - Patch-1:
>   - Removed ace_sha.h.
>   - Renamed ace_sfr.h as ace_sha.h.
>   - Removed timeout and checking for PRNG_ERROR bit in 
> HASH_STATUS register.
> PRNG_ERROR bit high means setup was not done properly. Since 
> there is no
> way to detect faulty h/w, we consider the possible fact that 
> h/w should
> not be able to setup feed properly if it's faulty.
>   - Renamed function name ace_sha256 to hw_sha256 and ace_sha1 to 
> hw_sha1.
>   - Patch-2: None.
>   - Patch-3:
>   - Added file hw_sha.h.
>   - Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL.
>   - Renamed function names ace_sha1 and ace_sha256 to hw_sha1 and 
> hw_sha256
> respectively.
>   - Patch-4:
>   - Removed "Acked-by: Simon Glass " because 
> of a change.
>   - Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL.
> 
> Changes since v6:
>   - Patch-1: Added "Acked-by: Simon Glass ".
>   - Patch-2: None.
>   - Patch-3:
>   - Changed position of "hw_sha.h" among includes (alpha order).
>   - Rebased patch.
>   - Patch-4: Added "Acked-by: Simon Glass ".
> 
> Changes since v7:
>   - Patch-1:
>   - Moved ace_sha.h to drivers/crypto.
>   - Removed parantheses where not required in ace_sha.h.
>   - Removed leftover time limit comment in ace_sha.c.
>   - Replaced "break" with "return -EBUSY" in PRNGERROR check.
>   - Patch-2: None.
>   - Patch-3: Added "Acked-by: Simon Glass ".
>   - Patch-4: None.
> 
> Akshay Saraswat (4):
>   Exynos: Add hardware accelerated SHA256 and SHA1
>   Exynos: config: Enable ACE HW for SHA 256 for Exynos
>   gen: Add sha h/w acceleration to hash
>   Exynos: config: Enable hash command
> 
>  Makefile   |   1 +
>  arch/arm/include/asm/arch-exynos/cpu.h |   4 +
>  common/hash.c  |  18 ++
>  drivers/crypto/Makefile|  47 +
>  drivers/crypto/ace_sha.c

[U-Boot] [PATCH] disk: fix unaligned access in efi partitions

2013-03-29 Thread Marc Dietrich

start_sect is not aligned to a 4 byte boundary thus causing exceptions
on ARM platforms. Access this field via the get_unaligned macro.

Signed-off-by: Marc Dietrich 
---
 disk/part_efi.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/disk/part_efi.c b/disk/part_efi.c
index b3fd0e9..6678a4c 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -30,6 +30,7 @@
  *
  * This limits the maximum size of addressable storage to < 2 Terra Bytes
  */
+#include 
 #include 
 #include 
 #include 
@@ -505,7 +506,7 @@ err:
 static int pmbr_part_valid(struct partition *part)
 {
if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
-   le32_to_cpu(part->start_sect) == 1UL) {
+   le32_to_cpu(get_unaligned(&part->start_sect)) == 1UL) {
return 1;
}
 
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] disk: add -mno-unaligned-access to CFLAGS

2013-03-29 Thread Marc Dietrich

Albert,

On Friday 29 March 2013 08:00:54 Albert ARIBAUD wrote:
> On Thu, 28 Mar 2013 23:35 +0100, Marc Dietrich  wrote:
> > [ ... ]
> > On Thursday 28 March 2013 21:42:13 Albert ARIBAUD wrote:
> > > Which fields, which structures, which files are affected by the
> > > unalignment issue?
> > 
> > in my test case, it is the start sector of a partition (check
> > include/part_efi.h). disk/part_efi.c reads the legacy mbr (to an aligned
> > buffer) which has a partition structure on offset 440+4+2 (<- not aligned
> > to 4 byte boundary) and inside this a 32 bit field start_sect (aligned to
> > 4 byte boundary). Reading this field (and also the next, nr_sects) will
> > cause an exception. Same is for part_dos, but there we still use
> > le32_to_int which reads byte by byte. I didn't checked others.
> 
> Thanks for clarifying.
> 
> Considering this is about a very small number of reads, I strongly
> prefer that these reads be done through the get_unaligned(&field) macro
> defined in e.g. arch/arm/include/asm/unaligned.h, even at the slightly
> added cost of decomposing the reads into 8-bit accesses.

ok, this is what I was actually looking for :-) I've sent a new patch.

Marc


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Re: [U-Boot] [PATCH] Exynos5: clock: Fix a typo bug in exynos clock init

2013-03-29 Thread Minkyu Kang

On 21/03/13 21:13, Akshay Saraswat wrote:
> We intended to clear the bits of CLK_SRC_TOP2 register, instead we were
> writing on the reserved bits of src_core1 register. Since the default
> value of clk_src_top2 register were itself zero, this typo was not
> creating any big issue. But it is better to fix this error for better
> readability of the code.
> 
> Signed-off-by: Hatim Ali 
> Signed-off-by: Akshay Saraswat 
> ---
>  board/samsung/smdk5250/clock_init.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/board/samsung/smdk5250/clock_init.c 
> b/board/samsung/smdk5250/clock_init.c
> index c009ae5..0ee65ae 100644
> --- a/board/samsung/smdk5250/clock_init.c
> +++ b/board/samsung/smdk5250/clock_init.c
> @@ -434,10 +434,10 @@ void system_clock_init()
>   val = readl(&clk->mux_stat_core1);
>   } while ((val | MUX_MPLL_SEL_MASK) != val);
>  
> - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
>   tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
>   | MUX_GPLL_SEL_MASK;
>   do {
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang
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Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

2013-03-29 Thread Gupta Ruchika-R66431



> -Original Message-
> From: otavio.salva...@gmail.com [mailto:otavio.salva...@gmail.com] On Behalf
> Of Otavio Salvador
> Sent: Thursday, March 28, 2013 8:23 PM
> To: Gupta Ruchika-R66431
> Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
> Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next
> level image validation
> 
> On Thu, Mar 28, 2013 at 7:46 AM, Ruchika Gupta 
> wrote:
> > The patch set adds support for next level image validation (linux,
> > rootfs, dtb) in secure boot scenarios.
> 
> It seems to focus in PowerPC, do you know if same code could be ported to
> ARM?
For the code to be ported to ARM platform, corresponding hardware blocks like 
cryptographic accelerator/SW support for crypto operations, IOMMU and a 
security monitor block will be required.

Ruchika
> 
> --
> Otavio Salvador O.S. Systems
> E-mail: ota...@ossystems.com.br  http://www.ossystems.com.br
> Mobile: +55 53 9981-7854  http://projetos.ossystems.com.br


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[U-Boot] [PATCH 03/11] net: add FTMAC110 10/100Mbps ethernet support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:

(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K

(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid!!!

Signed-off-by: Kuo-Jung Su 
---
 drivers/net/Makefile   |1 +
 drivers/net/ftmac110.c |  484 
 drivers/net/ftmac110.h |  131 +
 3 files changed, 616 insertions(+)
 create mode 100644 drivers/net/ftmac110.c
 create mode 100644 drivers/net/ftmac110.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 786a656..0e23817 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_ETHOC) += ethoc.o
 COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
 COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o
+COBJS-$(CONFIG_FTMAC110) += ftmac110.o
 COBJS-$(CONFIG_FTMAC100) += ftmac100.o
 COBJS-$(CONFIG_GRETH) += greth.o
 COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
new file mode 100644
index 000..67373f5
--- /dev/null
+++ b/drivers/net/ftmac110.c
@@ -0,0 +1,484 @@
+/*
+ * Faraday 10/100Mbps Ethernet Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#include 
+#endif
+
+#include "ftmac110.h"
+
+#ifndef EMAC_REG32
+#define EMAC_REG32(dev, off)   *(volatile uint32_t *)((dev)->iobase + (off))
+#endif
+
+#define CFG_DEBUG_DESC 0
+#define CFG_DEBUG_TX   0
+#define CFG_DEBUG_RX   0
+
+#define CFG_RXDES_NUM  8
+#define CFG_TXDES_NUM  2
+#define CFG_XBUF_SIZE  1536
+
+/***/
+/*   FTMAC110 DMA design issue */
+/* Dante Su 2010.02.03 */
+/* */
+/* The DMA engine has a weird restriction that its Rx DMA engine   */
+/* accepts only 16-bits aligned address, 32-bits aligned is not*/
+/* acceptable. However this restriction does not apply to Tx DMA.  */
+/* Conclusion: */
+/* (1) Tx DMA Buffer Address:  */
+/* 1 bytes aligned: Invalid*/
+/* 2 bytes aligned: O.K*/
+/* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)   */
+/* (2) Rx DMA Buffer Address:  */
+/* 1 bytes aligned: Invalid*/
+/* 2 bytes aligned: O.K*/
+/* 4 bytes aligned: Invalid*/
+/***/
+
+struct ftmac110_priv {
+   uint32_tiobase;
+   uint32_tirqmask;
+   uint32_tmaccr;
+   uint32_tlnkup;
+
+   struct ftmac110_rxd *rx_descs;
+   ulong   rx_descs_dma;
+   uint32_trx_idx;
+
+   struct ftmac110_txd *tx_descs;
+   ulong   tx_descs_dma;
+   uint32_ttx_idx;
+
+   uint32_tphy_addr;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char ftmac110_mac_addr[] = {0x00, 0x41, 0x71, 0x00, 0x00, 0x52};
+
+static int ftmac110_reset(struct eth_device *dev);
+
+static uint16_t mdio_read(struct eth_device *dev, uint8_t phyaddr, uint8_t 
phyreg)
+{
+   uint32_t tmp;
+
+   tmp = MIIREG_READ
+ | (phyaddr << MIIREG_PHYADDR_SHIFT)
+ | (phyreg  << MIIREG_PHYREG_SHIFT)
+ | 0x3000;
+
+   EMAC_REG32(dev, REG_PHYCR) = tmp;
+
+   do {
+   tmp = EMAC_REG32(dev, REG_PHYCR);
+   } while (tmp & MIIREG_READ);
+
+   return (uint16_t)(tmp & 0x);
+}
+
+static void mdio_write(struct eth_device *dev, uint8_t phyaddr, uint8_t 
phyreg, uint16_t phydata)
+{
+   unsigned int tmp;
+
+   tmp = MIIREG_WRITE
+ | (phyaddr << MIIREG_PHYADDR_SHIFT)
+ | (phyreg  << MIIREG_PHYREG_SHIFT)
+ | 0x3000;
+
+   EMAC_REG32(dev, REG_PHYDR) = phydata;
+   EMAC_REG32(dev, REG_PHYCR) = tmp;
+
+   do {
+   tmp = EMAC_REG32(dev, REG_PHYCR);
+   } while (tmp & MIIREG_WRITE);
+}
+
+static uint32_t ftmac110_phyqry(struct eth_device *dev)
+{
+   ulong ts;
+   uint32_t maccr;
+   uint16_t pa, tmp;
+

[U-Boot] [PATCH 04/11] usb-ehci: add Faraday USB 2.0 EHCI controller support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

This patch add supports to both Faraday FUSBH200 and FOTG210,
these controllers slightly differ from standard EHCI specification.

Signed-off-by: Kuo-Jung Su 
---
 common/usb_hub.c|5 ++
 drivers/usb/host/Makefile   |1 +
 drivers/usb/host/ehci-faraday.c |  157 +++
 drivers/usb/host/ehci-hcd.c |   11 +++
 drivers/usb/host/ehci.h |5 ++
 5 files changed, 179 insertions(+)
 create mode 100644 drivers/usb/host/ehci-faraday.c

diff --git a/common/usb_hub.c b/common/usb_hub.c
index b5eeb62..099696e 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -375,6 +375,11 @@ static int usb_hub_configure(struct usb_device *dev)
return -1;
}

+#ifdef CONFIG_USB_EHCI_FARADAY
+   /* dante: fusbh200 requires a long long delay ... */
+   mdelay(250);
+#endif
+
if (usb_get_hub_status(dev, buffer) < 0) {
USB_HUB_PRINTF("usb_hub_configure: failed to get Status %lX\n",
dev->status);
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 9a6f982..d5577bd 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
 else
 COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
+COBJS-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
 COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
 COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c
new file mode 100644
index 000..a5a6394
--- /dev/null
+++ b/drivers/usb/host/ehci-faraday.c
@@ -0,0 +1,157 @@
+/*
+ * Faraday USB 2.0 EHCI Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+
+#include "ehci.h"
+
+#ifndef BIT
+#define BIT(nr)(1UL << (nr))
+#endif
+
+/* Lower Timing for FPGA Mode */
+#define CFG_LOWER_TIMING0
+
+struct faraday_usb_hcd {
+   uint32_t iobase;
+};
+
+static struct faraday_usb_hcd faraday_usb_hcd_info[] = {
+#ifdef CONFIG_USB_EHCI_BASE
+   { .iobase = CONFIG_USB_EHCI_BASE, },
+#endif
+#ifdef CONFIG_USB_EHCI_BASE1
+   { .iobase = CONFIG_USB_EHCI_BASE1, },
+#endif
+};
+
+#define HCD_REG32(chip, off) \
+*(volatile uint32_t *)((chip)->iobase + (off))
+
+static inline int ehci_hci_fotg2xx(struct ehci_hccr *hccr)
+{
+   uint32_t iobase = (uint32_t)hccr;
+   return !REG32(iobase + 0x34) || REG32(iobase + 0x34) == 0x;
+}
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
+   struct ehci_hcor **ret_hcor)
+{
+   struct faraday_usb_hcd *hcd = &faraday_usb_hcd_info[index];
+   struct ehci_hccr *hccr;
+   struct ehci_hcor *hcor;
+
+   hccr = (struct ehci_hccr *)hcd->iobase;
+   hcor = (struct ehci_hcor *)(hcd->iobase +
+   HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+   if (ehci_hci_fotg2xx(hccr)) {
+
+   /* A-device bus reset */
+   HCD_REG32(hcd, 0x80) |= BIT(5);
+   HCD_REG32(hcd, 0x80) &= ~BIT(4);
+   mdelay(1);
+   HCD_REG32(hcd, 0x80) &= ~BIT(5);
+   HCD_REG32(hcd, 0x80) |= BIT(4);
+   mdelay(1);
+
+   /* Reset interrupt */
+   HCD_REG32(hcd, 0xC0) = 7;
+
+   /* Disable OTG & device interrupts */
+   HCD_REG32(hcd, 0xC4) = 3;
+
+   /* Set interrupt polarity to active high */
+   HCD_REG32(hcd, 0xC4) |= BIT(3);
+
+   /* In FPGA mode (15MHz <= AHB <= 30MHz), enter half speed mode. 
*/
+   if (clk_get_rate("AHB") <= 3000) {
+   HCD_REG32(hcd, 0x100) |= BIT(1);
+   printf("fotg210: AHB is too slow, enter half-speed 
mode.\n");
+   }
+
+#ifdef CFG_LOWER_TIMING
+   HCD_REG32(hcd, 0x40) |= 0x0d;
+#endif
+
+   } else {
+
+   /* Set interrupt polarity to active high */
+   HCD_REG32(hcd, 0x40) |= BIT(3);
+
+   /* In FPGA mode (15MHz <= AHB <= 30MHz), enter half speed mode. 
*/
+   if (clk_get_rate("AHB") <= 3000) {
+   HCD_REG32(hcd, 0x40) |= BIT(2);
+   printf("fusbh200: AHB is too slow, enter half-speed 
mode.\n");
+   }
+
+#ifdef CFG_LOWER_TIMING
+   HCD_REG32(hcd, 0x34) |= (3 << 2) | (1 << 0);
+#endif
+
+   /* Turn on VBUS */
+   HCD_REG32(hcd, 0x40) &= ~BIT(4);
+
+   /* Enable over-current & vbus error interrupts */
+   HCD_REG32(hcd, 0x44) = 0x1F;
+   HCD_REG32(hcd, 0x48) |= BIT

[U-Boot] [PATCH 06/11] i2c: add FTI2C010 I2C controller support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.

Signed-off-by: Kuo-Jung Su 
---
 drivers/i2c/Makefile   |1 +
 drivers/i2c/fti2c010.c |  360 
 drivers/i2c/fti2c010.h |   68 +
 3 files changed, 429 insertions(+)
 create mode 100644 drivers/i2c/fti2c010.c
 create mode 100644 drivers/i2c/fti2c010.h

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 5dbdbe3..ed2b8c0 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
 COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
 COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
+COBJS-$(CONFIG_FTI2C010) += fti2c010.o
 COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
 COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
new file mode 100644
index 000..be5e02c
--- /dev/null
+++ b/drivers/i2c/fti2c010.c
@@ -0,0 +1,360 @@
+/*
+ * Faraday I2C Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+
+#include "fti2c010.h"
+
+#define I2C_RD1
+#define I2C_WR0
+
+struct fti2c010_chip {
+   uint32_t bus;
+   uint32_t speed;
+   uint32_t iobase;
+};
+
+#if defined(CONFIG_HARD_I2C)
+
+static struct fti2c010_chip fti2c010_info[] = {
+#ifdef CONFIG_I2C_MULTI_BUS
+# ifdef CONFIG_FTI2C010_BASE0
+   {
+   .bus= 0,
+   .speed  = 0,
+   .iobase = CONFIG_FTI2C010_BASE0,
+   },
+# endif
+# ifdef CONFIG_FTI2C010_BASE1
+   {
+   .bus= 1,
+   .speed  = 0,
+   .iobase = CONFIG_FTI2C010_BASE1,
+   },
+# endif
+# ifdef CONFIG_FTI2C010_BASE2
+   {
+   .bus= 2,
+   .speed  = 0,
+   .iobase = CONFIG_FTI2C010_BASE2,
+   },
+# endif
+# ifdef CONFIG_FTI2C010_BASE3
+   {
+   .bus= 3,
+   .speed  = 0,
+   .iobase = CONFIG_FTI2C010_BASE3,
+   },
+# endif
+#else/* #ifdef CONFIG_I2C_MULTI_BUS */
+   {
+   .bus= 0,
+   .speed  = 0,
+   .iobase = CONFIG_FTI2C010_BASE,
+   },
+#endif/* #ifdef CONFIG_I2C_MULTI_BUS */
+};
+
+static struct fti2c010_chip *priv = fti2c010_info;
+
+/* Register access macros */
+#define I2C_REG32(priv, off)   \
+   *(volatile uint32_t *)((priv)->iobase + (off))
+
+static int fti2c010_wait(uint32_t mask)
+{
+   int ret = -1;
+   uint32_t stat, t;
+
+   for (t = get_timer(0); get_timer(t) < 100; ) {
+   stat = I2C_REG32(priv, REG_SR);
+   if ((stat & mask) == mask) {
+   ret = 0;
+   break;
+   }
+   }
+
+   return ret;
+}
+
+/*
+ * u-boot I2C API
+ */
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+   if (speed || priv->speed == 0)
+   i2c_set_bus_speed(speed);
+}
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip)
+{
+   int rc;
+
+   i2c_init(0, chip);
+
+   /* 1. Select slave device (7bits Address + 1bit R/W) */
+   I2C_REG32(priv, REG_DR) = (chip << 1) + I2C_WR;
+   I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN | CR_START;
+   rc = fti2c010_wait(SR_DT);
+   if (rc)
+   return rc;
+
+   /* 2. Select device register */
+   I2C_REG32(priv, REG_DR) = 0;
+   I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN;
+   rc = fti2c010_wait(SR_DT);
+
+   return rc;
+}
+
+/*
+ * Read/Write interface:
+ *   chip:I2C chip address, range 0..127
+ *   addr:Memory (register) address within the chip
+ *   alen:Number of bytes to use for addr (typically 1, 2 for larger
+ *  memories, 0 for register type devices with only one
+ *  register)
+ *   buffer:  Where to read/write the data
+ *   len: How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+   int rc, pos;
+   uchar paddr[4];
+
+   i2c_init(0, chip);
+
+   paddr[0] = (addr >> 0)  & 0xFF;
+   paddr[1] = (addr >> 8)  & 0xFF;
+   paddr[2] = (addr >> 16) & 0xFF;
+   paddr[3] = (addr >> 24) & 0xFF;
+
+   /*
+* Phase A. Set register address
+*/
+
+   /* A.1 Select slave device (7bits Address + 1bit R/W) */
+   I2C_REG32(priv, REG_DR) = (chip << 1) +

[U-Boot] [PATCH 10/11] mmc: add an alternative FTSDC010 driver support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Faraday FTSDC010 is a MMC/SD host controller.
There is already a driver in u-boot, which is
modified from eSHDC and contributed by Andes Tech.

However it works extreamly slow in Faraday A36x SoC
Platforms, so I turn to implement this new version
of driver with 10 times faster speed, and improved
stability.

Signed-off-by: Kuo-Jung Su 
---
 drivers/mmc/Makefile   |1 +
 drivers/mmc/ftsdc010_mci.c |  362 
 drivers/mmc/ftsdc010_mci.h |   91 +++
 3 files changed, 454 insertions(+)
 create mode 100644 drivers/mmc/ftsdc010_mci.c
 create mode 100644 drivers/mmc/ftsdc010_mci.h

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 65791aa..dfe1b8c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
+COBJS-$(CONFIG_FTSDC010_MCI) += ftsdc010_mci.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
new file mode 100644
index 000..d07e4ff
--- /dev/null
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -0,0 +1,362 @@
+/*
+ * Faraday MMC/SD Host Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "ftsdc010_mci.h"
+
+#define SD_REG32(chip, off) \
+   *(volatile uint32_t *)((uint8_t *)(chip)->iobase + (off))
+
+struct ftsdc010_chip {
+   uint32_t iobase;
+   uint32_t wprot;   /* write protected (locked) */
+   uint32_t rate;/* actual SD clock in Hz */
+   uint32_t sclk;/* FTSDC010 source clock in Hz */
+   uint32_t fifo;/* fifo depth in bytes */
+   uint32_t acmd;
+};
+
+static inline int
+ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
+{
+   struct ftsdc010_chip *chip = mmc->priv;
+   uint32_t timeout;
+
+   uint32_t cmd   = mmc_cmd->cmdidx;
+   uint32_t arg   = mmc_cmd->cmdarg;
+   uint32_t flags = mmc_cmd->resp_type;
+
+   cmd |= CMD_EN;
+
+   if (chip->acmd) {
+   cmd |= CMD_APP;
+   chip->acmd = 0;
+   }
+
+   if (flags & MMC_RSP_PRESENT)
+   cmd |= CMD_WAIT_RSP;
+
+   if (flags & MMC_RSP_136)
+   cmd |= CMD_LONG_RSP;
+
+   SD_REG32(chip, REG_SCR) = SR_RSP_ERR | SR_RSP | SR_CMD;
+
+   SD_REG32(chip, REG_ARG) = arg;
+
+   SD_REG32(chip, REG_CMD) = cmd;
+
+   if ((flags & (MMC_RSP_PRESENT | MMC_RSP_136)) == 0) {
+   for (timeout = 25; timeout > 0; --timeout) {
+   if (SD_REG32(chip, REG_SR) & SR_CMD) {
+   SD_REG32(chip, REG_SCR) = SR_CMD;
+   break;
+   }
+   udelay(1);
+   }
+   } else {
+   for (timeout = 25; timeout > 0; --timeout) {
+   uint32_t st = SD_REG32(chip, REG_SR);
+   if (st & SR_RSP) {
+   SD_REG32(chip, REG_SCR) = SR_RSP;
+   if (flags & MMC_RSP_136) {
+   mmc_cmd->response[0] = SD_REG32(chip, 
REG_RSP3);
+   mmc_cmd->response[1] = SD_REG32(chip, 
REG_RSP2);
+   mmc_cmd->response[2] = SD_REG32(chip, 
REG_RSP1);
+   mmc_cmd->response[3] = SD_REG32(chip, 
REG_RSP0);
+   } else {
+   mmc_cmd->response[0] = SD_REG32(chip, 
REG_RSP0);
+   }
+   break;
+   } else if (st & SR_RSP_ERR) {
+   SD_REG32(chip, REG_SCR) = SR_RSP_ERR;
+   debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n", 
mmc_cmd->cmdidx, st);
+   return TIMEOUT;
+   }
+   udelay(1);
+   }
+   }
+
+   if (timeout == 0) {
+   debug("ftsdc010: cmd timeout (op code=%d)\n", mmc_cmd->cmdidx);
+   return TIMEOUT;
+   }
+
+   if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD)
+   chip->acmd = 1;
+
+   return 0;
+}
+
+static int
+ftsdc010_wait(struct mmc *mmc)
+{
+   struct ftsdc010_chip *chip = mmc->priv;
+   uint32_t mask = SR_DAT | SR_DAT_END | SR_DAT_ERR;
+   uint32_t timeout;
+
+   for (timeout = 25; timeout; --timeout) {
+   uint32_t st = SD_REG32(chip, REG_SR);
+

[U-Boot] [PATCH 09/11] mtd/spi: add FTSPI020 SPI Flash controller support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Faraday FTSPI020 is dedicated SPI bus designed for
SPI Flash chips. It supports Fast-Read-Dual,
Fast-Read-Dual-IO, Fast-Read-Quad and Fast-Read-Quad-IO.

Signed-off-by: Kuo-Jung Su 
---
 drivers/mtd/spi/Makefile   |4 +
 drivers/mtd/spi/ftspi020.c |  589 
 drivers/mtd/spi/ftspi020.h |  118 +
 drivers/mtd/spi/winbond.c  |   17 +-
 4 files changed, 727 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/spi/ftspi020.c
 create mode 100644 drivers/mtd/spi/ftspi020.h

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..ce60e1b 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -29,6 +29,9 @@ ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_SPI_LOAD)   += spi_spl_load.o
 endif
 
+ifeq ($(CONFIG_FTSPI020),y)
+COBJS-$(CONFIG_FTSPI020) += ftspi020.o
+else
 COBJS-$(CONFIG_SPI_FLASH)  += spi_flash.o
 COBJS-$(CONFIG_SPI_FLASH_ATMEL)+= atmel.o
 COBJS-$(CONFIG_SPI_FLASH_EON)  += eon.o
@@ -39,6 +42,7 @@ COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
 COBJS-$(CONFIG_SPI_FLASH_WINBOND)  += winbond.o
 COBJS-$(CONFIG_SPI_FRAM_RAMTRON)   += ramtron.o
 COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
+endif
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/mtd/spi/ftspi020.c b/drivers/mtd/spi/ftspi020.c
new file mode 100644
index 000..5c85203
--- /dev/null
+++ b/drivers/mtd/spi/ftspi020.c
@@ -0,0 +1,589 @@
+/*
+ * Faraday SPI Flash Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "ftspi020.h"
+
+#define CFG_USE_FASTRD  1
+#define CFG_USE_FASTRD_QUAD 1 /* Fast Read Quad */
+#define CFG_SHOW_PROGRESS  1 /* print a '.' at the end of each 
action */
+
+/* Register access macros */
+#define SPI_REG32(reg)  *(volatile uint32_t *)(CONFIG_FTSPI020_BASE + 
(reg))
+
+/* Flash opcodes. */
+#define OPCODE_WREN 0x06/* Write enable */
+#define OPCODE_RDSR 0x05/* Read status register */
+#define OPCODE_WRSR 0x01/* Write status register 1 byte */
+#define OPCODE_NORM_READ0x03/* Read data bytes (low frequency) 
*/
+#define OPCODE_NORM_READ4   0x13/* Read data bytes (low frequency, 
4 bytes address) */
+#define OPCODE_FAST_READ0x0b/* Read data bytes (high 
frequency) */
+#define OPCODE_FAST_READ4   0x0c/* Read data bytes (high 
frequency, 4 bytes address) */
+#define OPCODE_FAST_READ_DUAL   0x3b/* Read data bytes (high 
frequency) */
+#define OPCODE_FAST_READ4_DUAL  0x3c/* Read data bytes (high 
frequency, 4 bytes address) */
+#define OPCODE_FAST_READ_QUAD   0x6b/* Read data bytes (high 
frequency) */
+#define OPCODE_FAST_READ4_QUAD  0x6c/* Read data bytes (high 
frequency, 4 bytes address) */
+#define OPCODE_PP   0x02/* Page program (up to 256 bytes) 
*/
+#define OPCODE_PP4  0x12/* Page program (up to 256 bytes, 
4 bytes address) */
+#define OPCODE_BE_4K0x20/* Erase 4KiB block */
+#define OPCODE_BE_32K   0x52/* Erase 32KiB block */
+#define OPCODE_CHIP_ERASE   0xc7/* Erase whole flash chip */
+#define OPCODE_SE   0xd8/* Sector erase (usually 64KiB) */
+#define OPCODE_SE4  0xdc/* Sector erase (usually 64KiB, 4 
bytes address) */
+#define OPCODE_RDID 0x9f/* Read JEDEC ID */
+
+/* Status Register bits. */
+#define SR_WIP  BIT(0)  /* Write in progress */
+#define SR_WEL  BIT(1)  /* Write enable latch */
+
+struct spi_flash_param {
+   const char *name;
+   uint32_tid;
+   uint32_text_id;
+   uint32_tsz_sector;
+   uint32_tnr_sector;
+
+   uint32_tflags;
+#define SECT_4KBIT(0)  /* OPCODE_BE_4K works uniformly */
+#define FASTRD_DUALBIT(8)
+#if CFG_USE_FASTRD_QUAD
+#define FASTRD_QUADBIT(9)
+#else
+#define FASTRD_QUAD0
+#endif
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct spi_flash_info {
+   struct spi_flash flash;
+   const struct spi_flash_param *param;
+
+   unsigned fastrd_dual:1;
+   unsigned fastrd_quad:1;
+};
+
+static inline const struct spi_flash_param *flash_to_param(struct spi_flash 
*flash)
+{
+   struct spi_flash_info *fl = (struct spi_flash_info *)flash;
+   return fl->param;
+}
+
+static const struct spi_flash_param fl_list[] = {
+
+   /* Atmel -- some are (confusingly) marketed as "DataFlash" */
+   { "at25fs010",  0x1f6601, 0, 32 * 1024,   4 },
+   { "at25fs040",  0x1f6604, 0, 64 * 1024,   8 },
+
+   { "a

[U-Boot] [PATCH 01/11] arm: add MMU/d-cache support for Faraday cores

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

This patch would enable MMU for Faraday ARMv5TE cores.

Here is the abstract of the MMU design.

Assume SDRAM memory region starts at 0x1000, and its size = 0x80.

0x +---+
   |   |
   | UN-CACHED |
   |   |
   |   |
0x1000 +---+
   |  CACHED (SDRAM)   | <- It's where data/bss/stack lived.
   |   |
   |   |
0x1080 +---+
   |   |
   |   |
   | UN-CACHED |
   |   |
   |   |
0xFF80 +---+
   | UN-CACHED (SDRAM) | <- An un-cached shadow of the SDRAM.
   |   |dma_alloc_coherent() always returns
   |   |an address in this region.
0x +---+

Signed-off-by: Kuo-Jung Su 
---
 arch/arm/include/asm/dma-mapping.h |   55 --
 arch/arm/include/asm/global_data.h |4 ++
 arch/arm/include/asm/io.h  |   75 
 arch/arm/lib/cache-cp15.c  |   44 +
 common/cmd_boot.c  |4 ++
 5 files changed, 179 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h 
b/arch/arm/include/asm/dma-mapping.h
index 5bbb0a0..d4f779e 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -2,6 +2,8 @@
  * (C) Copyright 2007
  * Stelian Pop 
  * Lead Tech Design 
+ * (C) Copyright 2010
+ * Dante Su 
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -24,22 +26,69 @@
 #ifndef __ASM_ARM_DMA_MAPPING_H
 #define __ASM_ARM_DMA_MAPPING_H

+#include 
+#include 
+
 enum dma_data_direction {
DMA_BIDIRECTIONAL   = 0,
DMA_TO_DEVICE   = 1,
DMA_FROM_DEVICE = 2,
 };

-static void *dma_alloc_coherent(size_t len, unsigned long *handle)
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-   *handle = (unsigned long)malloc(len);
-   return (void *)*handle;
+   void *va = memalign(ARCH_DMA_MINALIGN, len);
+   if (va && handle)
+   *handle = virt_to_phys(va);
+
+#ifdef CONFIG_FARADAY
+# ifndef CONFIG_SYS_DCACHE_OFF
+#include  /* boot information for Linux kernel */
+#include/* global data used for startup functions */
+   DECLARE_GLOBAL_DATA_PTR;
+
+   if (gd->arch.cpu_mmu) {
+   /* invalidate the buffer, and change to un-cached memory 
address */
+   if (va != NULL) {
+   invalidate_dcache_range((ulong)va, (ulong)va + len);
+   va = __uncached(va);
+   }
+   }
+# endif
+#endif /* CONFIG_FARADAY */
+
+   return va;
+}
+
+static inline void dma_free_coherent(void *va)
+{
+   free(__cached(va));
 }

 static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
   enum dma_data_direction dir)
 {
+#if defined(CONFIG_FARADAY) && !defined(CONFIG_SYS_DCACHE_OFF)
+#include  /* boot information for Linux kernel */
+#include/* global data used for startup functions */
+   DECLARE_GLOBAL_DATA_PTR;
+
+   if (gd->arch.cpu_mmu) {
+   switch (dir) {
+   case DMA_BIDIRECTIONAL:
+   case DMA_TO_DEVICE:
+   flush_dcache_range((unsigned long)vaddr, (unsigned 
long)vaddr + len);
+   break;
+
+   case DMA_FROM_DEVICE:
+   invalidate_dcache_range((unsigned long)vaddr, (unsigned 
long)vaddr + len);
+   break;
+   }
+   }
+   return virt_to_phys((void *)vaddr);
+#else
return (unsigned long)vaddr;
+#endif
 }

 static inline void dma_unmap_single(volatile void *vaddr, size_t len,
diff --git a/arch/arm/include/asm/global_data.h 
b/arch/arm/include/asm/global_data.h
index 37ac0da..bd18ff7 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,6 +38,10 @@ struct arch_global_data {
unsigned long   pllb_rate_hz;
unsigned long   at91_pllb_usb_init;
 #endif
+#ifdef CONFIG_FARADAY
+   unsigned long   cpu_id;
+   unsigned long   cpu_mmu;/* has mmu */
+#endif
/* "static data" needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz;
unsigned long tbu;
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531..4659439 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -2,6 +2,7 @@
  *  linux/include/asm-arm/io.h
  *
  *  Copyright (C) 1996-2000 Russell King
+ *  Copyright (C) 2009-2010 Dante Su 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the

[U-Boot] [PATCH 07/11] spi: add FTSPI010 SPI controller support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only.
BTW the DMA and CS/Clock control logic has been
altered since revision 1.19.0. So this patch
would 1st detects the revision id of the underlying
chip, and then switch to the corresponding control
routines.

Signed-off-by: Kuo-Jung Su 
---
 drivers/spi/Makefile   |1 +
 drivers/spi/ftssp010_spi.c |  333 
 drivers/spi/ftssp010_spi.h |   85 +++
 3 files changed, 419 insertions(+)
 create mode 100644 drivers/spi/ftssp010_spi.c
 create mode 100644 drivers/spi/ftssp010_spi.h

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4268595..2db2a5c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 COBJS-$(CONFIG_ICH_SPI) +=  ich.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
new file mode 100644
index 000..fbd3601
--- /dev/null
+++ b/drivers/spi/ftssp010_spi.c
@@ -0,0 +1,333 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+
+#include "ftssp010_spi.h"
+
+struct ftssp010_chip {
+   uint32_t fifo;
+   uint32_t rev;
+   uint32_t bus;
+   uint32_t div;
+   uint32_t mode;
+   uint32_t iobase;
+   struct {
+   uint32_t iobase;
+   uint32_t pin;
+   } gpio;
+};
+
+static struct ftssp010_chip ftssp010_info[] = {
+#if defined(CONFIG_FTSSP010_BASE) || defined(CONFIG_FTSSP010_BASE0)
+   {
+   .bus= 0,
+   .div= 0,
+   .mode   = 0,
+   .iobase = CONFIG_FTSSP010_BASE,
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+   .gpio = { CONFIG_FTSSP010_GPIO_BASE, CONFIG_FTSSP010_GPIO_PIN },
+#endif
+   },
+#endif
+#ifdef CONFIG_FTSSP010_BASE1
+   {
+   .bus= 1,
+   .div= 0,
+   .mode   = 0,
+   .iobase = CONFIG_FTSSP010_BASE1,
+   },
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+   {
+   .bus= 2,
+   .div= 0,
+   .mode   = 0,
+   .iobase = CONFIG_FTSSP010_BASE2,
+   },
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+   {
+   .bus= 3,
+   .div= 0,
+   .mode   = 0,
+   .iobase = CONFIG_FTSSP010_BASE3,
+   },
+#endif
+};
+
+static struct ftssp010_chip *priv = ftssp010_info;
+
+/* Register access macros */
+#define SPI_REG32(priv, off)   \
+   *(volatile uint32_t *)((priv)->iobase + (off))
+
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define GPIO_REG32(priv, off)  \
+   *(volatile uint32_t *)((priv)->gpio.iobase + (off))
+#endif
+
+static int ftssp010_spi_work_transfer_v1_19(const void *tx_buf, void *rx_buf,
+   int len, unsigned int flags)
+{
+   const uint8_t *txb = tx_buf;
+   uint8_t   *rxb = rx_buf;
+   uint32_t  tmp;
+   uint8_t   *p8 = (uint8_t *)&tmp;
+
+   while (len > 0) {
+   int i, depth = min(priv->fifo >> 2, len);
+   uint32_t xmsk = 0;
+
+   if (tx_buf) {
+   for (i = 0; i < depth; ++i) {
+   while (!(SPI_REG32(priv, REG_SR) & SR_TFNF))
+   ;
+   tmp = 0;
+   p8[0] = *txb++;
+   SPI_REG32(priv, REG_DR) = tmp;
+   }
+   xmsk |= CR2_TXEN | CR2_TXDOE;
+   if ((SPI_REG32(priv, REG_CR2) & xmsk) != xmsk)
+   SPI_REG32(priv, REG_CR2) |= xmsk;
+
+   }
+   if (rx_buf) {
+   xmsk |= CR2_RXEN;
+   if ((SPI_REG32(priv, REG_CR2) & xmsk) != xmsk)
+   SPI_REG32(priv, REG_CR2) |= xmsk;
+   for (i = 0; i < depth; ++i) {
+   while (!SR_RFVE(SPI_REG32(priv, REG_SR)))
+   ;
+   tmp = SPI_REG32(priv, REG_DR);
+   *rxb++ = p8[0];
+   }
+   }
+
+   len -= depth;
+   }
+
+   return 0;
+}
+
+static int ftssp010_spi_work_transfer(const void *tx_buf, void *rx_buf,
+   int len, unsigned int flags)
+{
+   const uint8_

[U-Boot] [PATCH 05/11] usb-gadget: add FOTG210 USB gadget support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

This patch would try to use Faraday FOTG210 to implement
a USB RNDIS Ethernet.

Signed-off-by: Kuo-Jung Su 
---
 drivers/usb/gadget/Makefile   |1 +
 drivers/usb/gadget/fotg210.c  |  926 +
 drivers/usb/gadget/fotg210.h  |   99 
 drivers/usb/gadget/gadget_chips.h |8 +
 4 files changed, 1034 insertions(+)
 create mode 100644 drivers/usb/gadget/fotg210.c
 create mode 100644 drivers/usb/gadget/fotg210.h

diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index e545b6b..432cf17 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -35,6 +35,7 @@ endif
 # new USB gadget layer dependencies
 ifdef CONFIG_USB_GADGET
 COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+COBJS-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
 COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
 COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o
 endif
diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
new file mode 100644
index 000..640ae55
--- /dev/null
+++ b/drivers/usb/gadget/fotg210.c
@@ -0,0 +1,926 @@
+/*
+ * Faraday USB 2.0 OTG Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fotg210.h"
+
+#define CFG_HALF_SPEED 0
+#define CFG_LOW_TIMING 0
+#define CFG_NUM_ENDPOINTS  4
+#define CFG_EP0_MAX_PACKET_SIZE64
+#define CFG_EPX_MAX_PACKET_SIZE512
+
+struct fotg210_chip;
+
+struct fotg210_ep {
+   struct usb_ep ep;
+
+   uint32_t maxpacket:16;
+   uint32_t id:4;
+   uint32_t stopped:1;
+   uint32_t rsvd:11;
+
+   struct list_head  queue;
+   const struct usb_endpoint_descriptor *desc;
+   struct fotg210_chip  *chip;
+};
+
+struct fotg210_request {
+   struct usb_request req;
+   struct list_head   queue;
+   struct fotg210_ep *ep;
+};
+
+struct fotg210_chip {
+   struct usb_gadget gadget;
+   struct usb_gadget_driver *driver;
+   uint32_t  iobase;
+   uint8_t   irq;
+   uint16_t  addr;
+   int   pullup;
+   enum usb_device_state state;
+   struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS];
+};
+
+static struct usb_endpoint_descriptor ep0_desc = {
+   .bLength = sizeof(struct usb_endpoint_descriptor),
+   .bDescriptorType  = USB_DT_ENDPOINT,
+   .bEndpointAddress = USB_DIR_IN,
+   .bmAttributes =USB_ENDPOINT_XFER_CONTROL,
+};
+
+#define USB_REG32(chip, off)*(volatile uint32_t *)((chip)->iobase + (off))
+
+static inline int
+fifo_to_ep(struct fotg210_chip *chip, int id, int in)
+{
+   return (id < 0) ? 0 : ((id % 4) + 1);
+}
+
+static inline int
+ep_to_fifo(struct fotg210_chip *chip, int id)
+{
+   return (id <= 0) ? -1 : ((id - 1) % 4);
+}
+
+static inline int
+ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
+{
+   int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
+
+   if (ep_addr & USB_DIR_IN) {
+   /* input */
+   USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) |= BIT(12);
+   USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) &= ~BIT(12);
+   USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) &= ~BIT(11);
+   } else {
+   /* output */
+   USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) |= BIT(12);
+   USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) &= BIT(12);
+   USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) &= BIT(11);
+   }
+
+   return 0;
+}
+
+static int
+fotg210_reset(struct fotg210_chip *chip)
+{
+   chip->state = USB_STATE_POWERED;
+
+   /* device address reset */
+   chip->addr  = 0;
+   USB_REG32(chip, REG_DCAR)   = 0;
+
+   /* enable the chip and perform a soft reset later */
+   USB_REG32(chip, REG_DCCR)   = BIT(5);
+
+   /* set idle counter */
+   USB_REG32(chip, REG_DCIDLE) = 7;
+
+   /* disable interrupts */
+   USB_REG32(chip, REG_HCIER)  = 0;
+   USB_REG32(chip, REG_DCIMR)  = 0x3;
+   USB_REG32(chip, REG_DCIMR0) = 0x3F;
+   USB_REG32(chip, REG_DCIMR1) = 0xF00FF;
+   USB_REG32(chip, REG_DCIMR2) = 0x7FF;
+
+   /* clear interrupts */
+   USB_REG32(chip, REG_HCISR)  = 0x3F;
+   USB_REG32(chip, REG_OTGISR) = 0x1FFF;
+   USB_REG32(chip, REG_DCISR)  = 0;
+   USB_REG32(chip, REG_DCISR0) = 0;
+   USB_REG32(chip, REG_DCISR1) = 0;
+   USB_REG32(chip, REG_DCISR2) = 0;
+
+   /* soft reset */
+   USB_REG32(chip, REG_DCCR) |= BIT(4);
+   while (USB_REG32(chip, REG_DCCR) & BIT(4))
+   ;
+
+   /* CX FIFO reset */
+   USB_REG32(chip, REG_DCC

[U-Boot] [PATCH 00/11] arm: add Faraday A36x SoC platform support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

These patches introduce Faraday A36x SoC platform support.

Here are some public documents for your reference.

http://www.faraday-tech.com/html/documentation/index.html

There is also a A369 QEMU emulator available at my github account:

https://github.com/dantesu1218/qemu.git

Here is quick start for QEMU:

1. Download the QEMU source tree

$ git clone -b qemu-1.3.0 https://github.com/dantesu1218/qemu.git

2. Build & Install the QEMU:

$ ./configure --target-list=arm-softmmu
$ make
$ make install

3. Launch u-boot with QEMU:

$ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-2012.10/u-boot

Kuo-Jung Su (11):
  arm: add MMU/d-cache support for Faraday cores
  net/ftgmac100: add MMU/D-cache support
  net: add FTMAC110 10/100Mbps ethernet support
  usb-ehci: add Faraday USB 2.0 EHCI controller support
  usb-gadget: add FOTG210 USB gadget support
  i2c: add FTI2C010 I2C controller support
  spi: add FTSPI010 SPI controller support
  mtd/nand: add FTNANDC021 NAND flash controller support
  mtd/spi: add FTSPI020 SPI Flash controller support
  mmc: add an alternative FTSDC010 driver support
  arm: add Faraday A36x SoC platform support

 arch/arm/cpu/faraday/Makefile |   57 ++
 arch/arm/cpu/faraday/a360/Makefile|   49 ++
 arch/arm/cpu/faraday/a360/reset.c |   22 +
 arch/arm/cpu/faraday/a369/Makefile|   50 ++
 arch/arm/cpu/faraday/a369/cmd_fa606.c |   74 +++
 arch/arm/cpu/faraday/a369/reset.c |   22 +
 arch/arm/cpu/faraday/cmd_bootfa.c |  121 
 arch/arm/cpu/faraday/config.mk|   33 +
 arch/arm/cpu/faraday/cpu.c|  230 +++
 arch/arm/cpu/faraday/ftpwmtmr010.c|  165 +
 arch/arm/cpu/faraday/fttmr010.c   |  155 +
 arch/arm/cpu/faraday/fwimage.h|   38 ++
 arch/arm/cpu/faraday/fwimage2.h   |   70 +++
 arch/arm/cpu/faraday/interrupts.c |  169 ++
 arch/arm/cpu/faraday/start.S  |  535 +
 arch/arm/cpu/u-boot.lds   |   11 +
 arch/arm/include/asm/arch-a360/hardware.h |   80 +++
 arch/arm/include/asm/arch-a369/hardware.h |  106 
 arch/arm/include/asm/dma-mapping.h|   55 +-
 arch/arm/include/asm/global_data.h|4 +
 arch/arm/include/asm/io.h |   75 +++
 arch/arm/include/asm/mach-types.h |1 +
 arch/arm/lib/cache-cp15.c |   44 ++
 board/faraday/a360evb/Makefile|   49 ++
 board/faraday/a360evb/board.c |   65 ++
 board/faraday/a360evb/clk.c   |   48 ++
 board/faraday/a360evb/config.mk   |   33 +
 board/faraday/a360evb/lowlevel_init.S |   33 +
 board/faraday/a369evb/Makefile|   49 ++
 board/faraday/a369evb/board.c |  182 ++
 board/faraday/a369evb/clk.c   |   80 +++
 board/faraday/a369evb/config.mk   |   33 +
 board/faraday/a369evb/lowlevel_init.S |  133 +
 boards.cfg|3 +
 common/cmd_boot.c |4 +
 common/usb_hub.c  |5 +
 drivers/i2c/Makefile  |1 +
 drivers/i2c/fti2c010.c|  360 +++
 drivers/i2c/fti2c010.h|   68 +++
 drivers/mmc/Makefile  |1 +
 drivers/mmc/ftsdc010_mci.c|  362 +++
 drivers/mmc/ftsdc010_mci.h|   91 +++
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/ftnandc021.c |  550 +
 drivers/mtd/nand/ftnandc021.h |  165 +
 drivers/mtd/spi/Makefile  |4 +
 drivers/mtd/spi/ftspi020.c|  589 ++
 drivers/mtd/spi/ftspi020.h|  118 
 drivers/mtd/spi/winbond.c |   17 +-
 drivers/net/Makefile  |1 +
 drivers/net/ftgmac100.c   |   83 ++-
 drivers/net/ftmac110.c|  484 +++
 drivers/net/ftmac110.h|  131 
 drivers/spi/Makefile  |1 +
 drivers/spi/ftssp010_spi.c|  333 +++
 drivers/spi/ftssp010_spi.h|   85 +++
 drivers/usb/gadget/Makefile   |1 +
 drivers/usb/gadget/fotg210.c  |  926 +
 drivers/usb/gadget/fotg210.h  |   99 +++
 drivers/usb/gadget/gadget_chips.h |8 +
 drivers/usb/host/Makefile |1 +
 drivers/usb/host/ehci-faraday.c   |  157 +
 drivers/usb/host/ehci-hcd.c   |   11 +
 drivers/usb/host/ehci.h   |5 +
 include/common.h  |   13 +
 include/configs/a360.h|  180 ++
 include/configs/a369.h|   40 ++
 include/configs/a369_defaults.h   |  285 +
 include/configs/a369_fa606te.h

[U-Boot] [PATCH 08/11] mtd/nand: add FTNANDC021 NAND flash controller support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.

For example:

Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.

Signed-off-by: Kuo-Jung Su 
---
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/ftnandc021.c |  550 +
 drivers/mtd/nand/ftnandc021.h |  165 +
 3 files changed, 716 insertions(+)
 create mode 100644 drivers/mtd/nand/ftnandc021.c
 create mode 100644 drivers/mtd/nand/ftnandc021.h

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index c77c0c4..16b5016 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -63,6 +63,7 @@ COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+COBJS-$(CONFIG_NAND_FTNANDC021) += ftnandc021.o
 COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
diff --git a/drivers/mtd/nand/ftnandc021.c b/drivers/mtd/nand/ftnandc021.c
new file mode 100644
index 000..095206a
--- /dev/null
+++ b/drivers/mtd/nand/ftnandc021.c
@@ -0,0 +1,550 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include 
+#include 
+#include 
+
+#include "ftnandc021.h"
+
+/* common bitmask of nand flash status register */
+#define NAND_IOSTATUS_ERRORBIT(0)
+#define NAND_IOSTATUS_READYBIT(6)
+#define NAND_IOSTATUS_UNPROTCT BIT(7)
+
+struct ftnandc021_chip {
+   void *iobase;
+   unsigned int  cmd;
+
+   unsigned int  pgidx;
+
+   unsigned int  off;
+   uint8_t   buf[256];
+
+   unsigned int  adrc; /* address cycle */
+   unsigned int  pgsz; /* page size */
+   unsigned int  bksz; /* block size */
+};
+
+/* Register access macros */
+#define NAND_REG32(priv, off) \
+   *(volatile uint32_t *)((uint32_t)((priv)->iobase) + (off))
+
+static struct nand_ecclayout ftnandc021_oob_2k = {
+   .eccbytes = 24,
+   .eccpos = {
+   40, 41, 42, 43, 44, 45, 46, 47,
+   48, 49, 50, 51, 52, 53, 54, 55,
+   56, 57, 58, 59, 60, 61, 62, 63
+   },
+   .oobfree = {
+   {
+   .offset = 9,
+   .length = 3
+   }
+   }
+};
+
+static int
+ftnandc021_reset(struct nand_chip *chip)
+{
+   struct ftnandc021_chip *priv = chip->priv;
+   uint32_t bk = 2;/* 64 pages */
+   uint32_t pg = 1;/* 2k */
+   uint32_t ac = 2;/* 5 */
+   uint32_t mask = NANDC_NANDC_SW_RESET | NANDC_BMC_SW_RESET | 
NANDC_ECC_SW_RESET;
+
+#ifdef CONFIG_FTNANDC021_ACTIMING_1
+   NAND_REG32(priv, REG_AC1_CONTROL)   = CONFIG_FTNANDC021_ACTIMING_1;
+#endif
+#ifdef CONFIG_FTNANDC021_ACTIMING_2
+   NAND_REG32(priv, REG_AC2_CONTROL)   = CONFIG_FTNANDC021_ACTIMING_2;
+#endif
+
+   NAND_REG32(priv, REG_INT_EN)= 0;
+   NAND_REG32(priv, REG_PAGE_INDEX)= 0;
+   NAND_REG32(priv, REG_WRITE_BI)  = 0xff;
+   NAND_REG32(priv, REG_WRITE_LSN_CRC) = 0x;
+   if (chip->options & NAND_BUSWIDTH_16)
+   NAND_REG32(priv, REG_FLOW_CONTROL) = BIT(8) | BIT(7) | 
NANDC_IO_WIDTH_16BIT;
+   else
+   NAND_REG32(priv, REG_FLOW_CONTROL) = BIT(8) | BIT(7) | 
NANDC_IO_WIDTH_8BIT;
+
+   /* chip reset */
+   NAND_REG32(priv, REG_MLC_SW_RESET)  = mask;
+
+   /* wait until chip ready */
+   while (NAND_REG32(priv, REG_MLC_SW_RESET) & BIT(0))
+   ;
+
+   switch (priv->bksz / priv->pgsz) {
+   case 16:
+   bk = 0;
+   break;
+   case 32:
+   bk = 1;
+   break;
+   case 64:
+   bk = 2;
+   break;
+   case 128:
+   bk = 3;
+   break;
+   }
+
+   switch (priv->pgsz) {
+   case 512:
+   pg = 0;
+   break;
+   case 2048:
+   pg = 1;
+   break;
+   case 4096:
+   pg = 2;
+   break;
+   }
+
+   switch (priv->adrc) {
+   case 3:
+   ac = 0;
+   break;
+   case 4:
+   ac = 1;
+   break;
+   case 5:
+   ac = 2;
+   break;
+   }
+
+   NAND_REG32(priv, REG_MEMORY_CONFIG) = NANDC_MS_32GB | NANDC_MOD0_ENABLE
+   
| (bk << 16) | (pg << 8) | (ac << 10);
+
+   /* PIO mode */
+   NAND_REG32(priv, REG_BMC_PIO_MODE_READ

[U-Boot] [PATCH 02/11] net/ftgmac100: add MMU/D-cache support

2013-03-29 Thread Kuo-Jung Su

From: Kuo-Jung Su 

Signed-off-by: Kuo-Jung Su 
---
 drivers/net/ftgmac100.c |   83 ---
 1 file changed, 56 insertions(+), 27 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 69ba57d..0169a42 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -7,6 +7,9 @@
  * (C) Copyright 2010 Andes Technology
  * Macpaul Lin 
  *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -28,20 +31,25 @@
 #include 
 #include 
 #include 
+#include 

 #include "ftgmac100.h"

-#define ETH_ZLEN   60
+#define CFG_XBUF_SIZE  1536
+
+#define ETH_ZLEN   60

 /* RBSR - hw default init value is also 0x640 */
 #define RBSR_DEFAULT_VALUE 0x640

 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
-#define PKTBUFSTX  4   /* must be power of 2 */
+#define PKTBUFSTX  4   /* must be power of 2 */

 struct ftgmac100_data {
-   struct ftgmac100_txdes txdes[PKTBUFSTX];
-   struct ftgmac100_rxdes rxdes[PKTBUFSRX];
+   ulong txdes_dma;
+   struct ftgmac100_txdes *txdes;
+   ulong rxdes_dma;
+   struct ftgmac100_rxdes *rxdes;
int tx_index;
int rx_index;
int phy_addr;
@@ -375,13 +383,32 @@ static int ftgmac100_init(struct eth_device *dev, bd_t 
*bd)
 {
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
-   struct ftgmac100_txdes *txdes = priv->txdes;
-   struct ftgmac100_rxdes *rxdes = priv->rxdes;
+   struct ftgmac100_txdes *txdes;
+   struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
+   void *buf;
int i;

debug("%s()\n", __func__);

+   if (!priv->txdes) {
+   txdes = dma_alloc_coherent(sizeof(*txdes) * PKTBUFSTX, 
&priv->txdes_dma);
+   if (!txdes)
+   panic("ftgmac100: out of memory\n");
+   memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
+   priv->txdes = txdes;
+   }
+   txdes = priv->txdes;
+
+   if (!priv->rxdes) {
+   rxdes = dma_alloc_coherent(sizeof(*rxdes) * PKTBUFSRX, 
&priv->rxdes_dma);
+   if (!rxdes)
+   panic("ftgmac100: out of memory\n");
+   memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
+   priv->rxdes = rxdes;
+   }
+   rxdes = priv->rxdes;
+
/* set the ethernet address */
ftgmac100_set_mac_from_env(dev);

@@ -397,21 +424,31 @@ static int ftgmac100_init(struct eth_device *dev, bd_t 
*bd)

for (i = 0; i < PKTBUFSTX; i++) {
/* TXBUF_BADR */
-   txdes[i].txdes3 = 0;
+   if (!txdes[i].txdes2) {
+   buf = memalign(64, CFG_XBUF_SIZE);
+   if (!buf)
+   panic("ftgmac100: out of memory\n");
+   txdes[i].txdes3 = virt_to_phys(buf);
+   txdes[i].txdes2 = (uint)buf;
+   }
txdes[i].txdes1 = 0;
}

for (i = 0; i < PKTBUFSRX; i++) {
/* RXBUF_BADR */
-   rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i];
+   if (!rxdes[i].rxdes2) {
+   buf = NetRxPackets[i];
+   rxdes[i].rxdes3 = virt_to_phys(buf);
+   rxdes[i].rxdes2 = (uint)buf;
+   }
rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
}

/* transmit ring */
-   writel((unsigned int)txdes, &ftgmac100->txr_badr);
+   writel(priv->txdes_dma, &ftgmac100->txr_badr);

/* receive ring */
-   writel((unsigned int)rxdes, &ftgmac100->rxr_badr);
+   writel(priv->rxdes_dma, &ftgmac100->rxr_badr);

/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
@@ -466,8 +503,11 @@ static int ftgmac100_recv(struct eth_device *dev)
debug("%s(): RX buffer %d, %x received\n",
   __func__, priv->rx_index, rxlen);

+   /* invalidate d-cache */
+   dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
+
/* pass the packet up to the protocol layers. */
-   NetReceive((void *)curr_des->rxdes3, rxlen);
+   NetReceive((void *)curr_des->rxdes2, rxlen);

/* release buffer to DMA */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
@@ -485,7 +525,6 @@ static int ftgmac100_send(struct eth_device *dev, void 
*packet, int length)
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
-   int st

Re: [U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

2013-03-29 Thread TENART Antoine

>   Tom>  This is fine except it breaks bisectability, you need to also add
>   Tom>  CONFIG_TI81XX to ti814x_evm.h at this point.
>
> It afaik already has it.
>

Yes, it was introduced by Matt Porter in "ti814x_evm: add ti814x evm 
board support" patch :
+#define CONFIG_TI81XX
+#define CONFIG_TI814X
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Re: [U-Boot] [PATCH 2/8] Add TI816X mux definitions.

2013-03-29 Thread TENART Antoine

> Yes, please fix with a v2 of the series which also addreses the other
> feedback as well.  Also, patches 2-7 can be squashed into a single "Add
> ti816x support" patch.
>

Thanks for your review, I'll do a v2 following your advices.
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Re: [U-Boot] [PATCH 5/8] Add TI816X cpu definitions

2013-03-29 Thread TENART Antoine

>   TENART>   /* DMM */
>   TENART>  +#if defined(CONFIG_TI816X)
>   TENART>  +#define DMM_BASE  0x4E00
>   TENART>  +#else
>   TENART>   #define DMM_BASE  0x4E40
>   TENART>  +#endif
>
> I don't think that's right. Matt's series uses DMM_BASE to refer to the
> lisa registers, which are offset 0x40 from the DMM region, so I think
> you can drop this.
>

You're right, this is because I didn't use config_dmm(). I'll fix that.
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Re: [U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

2013-03-29 Thread Tom Rini

On Fri, Mar 29, 2013 at 10:09:30AM +0100, TENART Antoine wrote:
> >   Tom>  This is fine except it breaks bisectability, you need to also add
> >   Tom>  CONFIG_TI81XX to ti814x_evm.h at this point.
> >
> > It afaik already has it.
> >
> 
> Yes, it was introduced by Matt Porter in "ti814x_evm: add ti814x evm 
> board support" patch :
> +#define CONFIG_TI81XX
> +#define CONFIG_TI814X

OK, thanks, forgot Matt already set the symbol.

-- 
Tom


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Re: [U-Boot] [PATCH] disk: fix unaligned access in efi partitions

2013-03-29 Thread Albert ARIBAUD

Hi Marc,

On Fri, 29 Mar 2013 12:28:58 +0100, Marc Dietrich 
wrote:

> start_sect is not aligned to a 4 byte boundary thus causing exceptions
> on ARM platforms. Access this field via the get_unaligned macro.
> 
> Signed-off-by: Marc Dietrich 
> ---
>  disk/part_efi.c |3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/disk/part_efi.c b/disk/part_efi.c
> index b3fd0e9..6678a4c 100644
> --- a/disk/part_efi.c
> +++ b/disk/part_efi.c
> @@ -30,6 +30,7 @@
>   *
>   * This limits the maximum size of addressable storage to < 2 Terra Bytes
>   */
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -505,7 +506,7 @@ err:
>  static int pmbr_part_valid(struct partition *part)
>  {
>   if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
> - le32_to_cpu(part->start_sect) == 1UL) {
> + le32_to_cpu(get_unaligned(&part->start_sect)) == 1UL) {
>   return 1;
>   }

Suits me :) but did you not say the same issue was also affecting
nr_sects?

Also, beside the asm/unaligned.h file I gave as an example, other header
files in include/linux/unaligned/ exist that provide alignment-related
macros, notably with _le and _be versions. Maybe you can find one that
combines the effects of both le32_to_cpu() and get_unaligned()?

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH 1/1 v3] omap3_beagle: Enabling UART3 first allows the Transmitter to be empty

2013-03-29 Thread Tom Rini

On Fri, Mar 29, 2013 at 10:43:34AM +0100, Albert ARIBAUD wrote:
> Hi Manfred,
> 
> On Fri, 29 Mar 2013 10:20:25 +0100, Manfred Huber 
> wrote:
> 
> > On some OMAP3 devices when UART3 is configured for boot mode before SPL 
> > starts 
> > only THRE bit is set. We have to empty the transmitter before 
> > initialization 
> > starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.
> > 
> > Signed-off-by: Manfred Huber 
> > ---
> 
> Patch history is missing here.

That's largely because each iteration has been fairly different (we
started with adding CONFIG_SYS_NS16550_BROKEN_TEMPT to omap3_beagle).

> Also, I would like the commit summary (first commit message line, also
> subject of the patch mail) to clearly state what the patch *does* as
> opposed to what *happens*, because it is unclear right now if you're
> describing the solution or the issue. Something like :
> 
> "omap3_beagle: flush UART3 xmit on enable if TEMT is broken"

Agreed.

> 
> > README |8 
> >  drivers/serial/ns16550.c   |   16 ++--
> >  include/configs/igep00x0.h |3 ---
> >  3 files changed, 14 insertions(+), 13 deletions(-)
> > 
> > diff --git a/README b/README
> > index a336476..e6b3a50 100644
> > --- a/README
> > +++ b/README
> > @@ -616,14 +616,6 @@ The following options need to be configured:
> > boot loader that has already initialized the UART.  Define this
> > variable to flush the UART at init time.
> >  
> > -   CONFIG_SYS_NS16550_BROKEN_TEMT
> > -
> > -   16550 UART set the Transmitter Empty (TEMT) Bit when all output
> > -   has finished and the transmitter is totally empty. U-Boot waits
> > -   for this bit to be set to initialize the serial console. On some
> > -   broken platforms this bit is not set in SPL making U-Boot to
> > -   hang while waiting for TEMT. Define this option to avoid it.
> > -
> >  
> >  - Console Interface:
> > Depending on board, define exactly one serial port
> > 
> > diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> > index 87a0917..2922a2c 100644
> > --- a/drivers/serial/ns16550.c
> > +++ b/drivers/serial/ns16550.c
> > @@ -36,10 +36,22 @@
> >  
> >  void NS16550_init(NS16550_t com_port, int baud_divisor)
> >  {
> > -#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
> > +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
> > +   /* On some OMAP3 devices when UART3 is configured for boot mode before
> > +  SPL starts only THRE bit is set. We have to empty the transmitter
> > +  before initialization starts. */

/*
 * Multiline comments
 * must be like this.
 */

-- 
Tom


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[U-Boot] [PATCH 1/1 v4] omap3_beagle: Flush UART3 xmit on enable if TEMT is broken

2013-03-29 Thread Manfred Huber

From: Manfred Huber 

Flush UART3 xmit on enable if TEMT is broken

On some OMAP3 devices when UART3 is configured for boot mode before SPL starts 
only THRE bit is set. We have to empty the transmitter before initialization 
starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.

Signed-off-by: Manfred Huber 
---
Changes since v3:
- Changed commit summary and added version history.

Changes since v2:
- Removing CONFIG_SYS_NS16550_BROKEN_TEMT in README and igep00x0.h.

Changes since v1:
- Replaced CONFIG_SYS_NS16550_BROKEN_TEMT with initial configuration of
  UART.

README |8 
 drivers/serial/ns16550.c   |   16 ++--
 include/configs/igep00x0.h |3 ---
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/README b/README
index a336476..e6b3a50 100644
--- a/README
+++ b/README
@@ -616,14 +616,6 @@ The following options need to be configured:
boot loader that has already initialized the UART.  Define this
variable to flush the UART at init time.
 
-   CONFIG_SYS_NS16550_BROKEN_TEMT
-
-   16550 UART set the Transmitter Empty (TEMT) Bit when all output
-   has finished and the transmitter is totally empty. U-Boot waits
-   for this bit to be set to initialize the serial console. On some
-   broken platforms this bit is not set in SPL making U-Boot to
-   hang while waiting for TEMT. Define this option to avoid it.
-
 
 - Console Interface:
Depending on board, define exactly one serial port

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..2922a2c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -36,10 +36,22 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
-#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+   /* On some OMAP3 devices when UART3 is configured for boot mode before
+  SPL starts only THRE bit is set. We have to empty the transmitter
+  before initialization starts. */
+   if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
+== UART_LSR_THRE) {
+   serial_out(UART_LCR_DLAB, &com_port->lcr);
+   serial_out(baud_divisor & 0xff, &com_port->dll);
+   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+   serial_out(UART_LCRVAL, &com_port->lcr);
+   serial_out(0, &com_port->mdr1);
+   }
+#endif
+
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
-#endif
 
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \

diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index f8131b1..0617a58 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -67,9 +67,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
 
-/* define to avoid U-Boot to hang while waiting for TEMT */
-#define CONFIG_SYS_NS16550_BROKEN_TEMT
-
 /* select serial console configuration */
 #define CONFIG_CONS_INDEX  3
 #define CONFIG_SYS_NS16550_COM3OMAP34XX_UART3
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[U-Boot] [PATCH 1/1 v5] omap3_beagle: Flush UART3 xmit on enable if TEMT is broken

2013-03-29 Thread Manfred Huber

From: Manfred Huber 

Flush UART3 xmit on enable if TEMT is broken

On some OMAP3 devices when UART3 is configured for boot mode before SPL starts 
only THRE bit is set. We have to empty the transmitter before initialization 
starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.

Signed-off-by: Manfred Huber 
---
Changes since v4:
- Changed multiline comment.

Changes since v3:
- Changed commit summary and added version history.

Changes since v2:
- Removing CONFIG_SYS_NS16550_BROKEN_TEMT in README and igep00x0.h.

Changes since v1:
- Replaced CONFIG_SYS_NS16550_BROKEN_TEMT with initial configuration of
  UART.

 README |8 
 drivers/serial/ns16550.c   |   18 --
 include/configs/igep00x0.h |3 ---
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/README b/README
index a336476..e6b3a50 100644
--- a/README
+++ b/README
@@ -616,14 +616,6 @@ The following options need to be configured:
boot loader that has already initialized the UART.  Define this
variable to flush the UART at init time.
 
-   CONFIG_SYS_NS16550_BROKEN_TEMT
-
-   16550 UART set the Transmitter Empty (TEMT) Bit when all output
-   has finished and the transmitter is totally empty. U-Boot waits
-   for this bit to be set to initialize the serial console. On some
-   broken platforms this bit is not set in SPL making U-Boot to
-   hang while waiting for TEMT. Define this option to avoid it.
-
 
 - Console Interface:
Depending on board, define exactly one serial port
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..a9352fb 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -36,10 +36,24 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
-#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+   /*
+* On some OMAP3 devices when UART3 is configured for boot mode before
+* SPL starts only THRE bit is set. We have to empty the transmitter
+* before initialization starts.
+*/
+   if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
+== UART_LSR_THRE) {
+   serial_out(UART_LCR_DLAB, &com_port->lcr);
+   serial_out(baud_divisor & 0xff, &com_port->dll);
+   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+   serial_out(UART_LCRVAL, &com_port->lcr);
+   serial_out(0, &com_port->mdr1);
+   }
+#endif
+
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
-#endif
 
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index f8131b1..0617a58 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -67,9 +67,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
 
-/* define to avoid U-Boot to hang while waiting for TEMT */
-#define CONFIG_SYS_NS16550_BROKEN_TEMT
-
 /* select serial console configuration */
 #define CONFIG_CONS_INDEX  3
 #define CONFIG_SYS_NS16550_COM3OMAP34XX_UART3
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[U-Boot] Support required for loading U-boot on SDRAM

2013-03-29 Thread Sadashiva Reddy

Hi Sir,

I am using AMCC PPC440Gx processor for our project presently the board is 
working fine with vxWorks(BSP + OS + Application). 
But our customer new requirement is same board should be ported with linux.


1. We are using BDI2000 JTAG tool for porting u-boot and kernel.

2. We are not able to load the u-boot or u-boot.bin file directly to SDRAM 
location.

3. When we try to load its load to the flash loaction i.e what ever we mention 
in the macro  
CONFIG_SYS_TEXT_BASE from board.h file its loads to that location and when 
we 
give go command it throws an error called JTAG instruction overrun.

4. When we build the u-boot code the file size of u-boot.bin is always created 
with the macro 
initialized by CONFIG_SYS_TEXT_BASE from the board.h file.

5. We are able to load u-boot.bin to a flash location directly but u-boot is 
not coming up.
So to debug the u-boot we are trying to load directly to SDRAM location. 
VxWorks is 
coming up when we load directly to SDRAM location. 

6. I think the u-boot is creating a u-boot.bin file to load for flash loaction. 
How to create an 
image or bin file to load on SDRAM location directly.


Best Regards,
Sadashiv

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[U-Boot] [PATCH] video: bcm2835: fix build issues

2013-03-29 Thread Anatolij Gustschin

After merging LCD patches for v2013.04 the bcm2835 video
driver building is broken due to removal of many global
variables. Fix the driver.

Signed-off-by: Anatolij Gustschin 
Cc: Stephen Warren 
---
 common/lcd.c|   12 
 drivers/video/bcm2835.c |   11 ---
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index b98eea6..b81be31 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -493,6 +493,18 @@ static int lcd_init(void *lcdbase)
debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
 
lcd_ctrl_init(lcdbase);
+
+   /*
+* lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores
+* the 'lcdbase' argument and uses custom lcd base address
+* by setting up gd->fb_base. Check for this condition and fixup
+* 'lcd_base' address.
+*/
+   if ((unsigned long)lcdbase != gd->fb_base)
+   lcd_base = (void *)gd->fb_base;
+
+   debug("[LCD] Using LCD frambuffer at %p\n", lcd_base);
+
lcd_get_size(&lcd_line_length);
lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
lcd_is_enabled = 1;
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 1e9a84a..0c77d17 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -23,17 +23,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Global variables that lcd.c expects to exist */
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-void *lcd_base;
-void *lcd_console_address;
-short console_col;
-short console_row;
 vidinfo_t panel_info;
-char lcd_cursor_enabled;
-ushort lcd_cursor_width;
-ushort lcd_cursor_height;
 
 struct msg_query {
struct bcm2835_mbox_hdr hdr;
@@ -119,7 +109,6 @@ void lcd_ctrl_init(void *lcdbase)
panel_info.vl_bpix = LCD_COLOR16;
 
gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address;
-   lcd_base = (void *)gd->fb_base;
 }
 
 void lcd_enable(void)
-- 
1.7.5.4

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[U-Boot] Pull request: u-boot-staging

2013-03-29 Thread Anatolij Gustschin

Hello Tom,

The following changes since commit 009d75ccc11d27b9a083375a88bb93cb746b4800:

  Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-03-28 18:50:01 
+0100)

are available in the git repository at:

  git://git.denx.de/u-boot-staging.git ag...@denx.de

Anatolij Gustschin (1):
  menu: export menu_default_choice() function

Pali Rohár (3):
  menu: Add support for user defined item choice function
  New command bootmenu: ANSI terminal boot menu support
  RX-51: Add support for bootmenu

 board/ait/cam_enc_4xx/cam_enc_4xx.c |3 +-
 common/Makefile |1 +
 common/cmd_bootmenu.c   |  517 +++
 common/cmd_pxe.c|3 +-
 common/menu.c   |   44 +++-
 doc/README.bootmenu |  115 
 doc/README.menu |9 +-
 include/ansi.h  |   42 +++
 include/configs/nokia_rx51.h|   40 +++-
 include/menu.h  |5 +-
 10 files changed, 760 insertions(+), 19 deletions(-)
 create mode 100644 common/cmd_bootmenu.c
 create mode 100644 doc/README.bootmenu
 create mode 100644 include/ansi.h

Please pull. Thanks!

Anatolij
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Re: [U-Boot] [PATCH] video: bcm2835: fix build issues

2013-03-29 Thread Anatolij Gustschin

On Fri, 29 Mar 2013 14:10:09 +0100
Anatolij Gustschin  wrote:

> After merging LCD patches for v2013.04 the bcm2835 video
> driver building is broken due to removal of many global
> variables. Fix the driver.
> 
> Signed-off-by: Anatolij Gustschin 
> Cc: Stephen Warren 
> ---
>  common/lcd.c|   12 
>  drivers/video/bcm2835.c |   11 ---
>  2 files changed, 12 insertions(+), 11 deletions(-)

applied to u-boot-video/master.

Anatolij
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[U-Boot] Pull request: u-boot-video/master

2013-03-29 Thread Anatolij Gustschin

Hello Tom,

The following changes since commit 009d75ccc11d27b9a083375a88bb93cb746b4800:

  Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-03-28 18:50:01 
+0100)

are available in the git repository at:

  git://git.denx.de/u-boot-video.git master

Anatolij Gustschin (2):
  Merge branch 'for-v2013.04'
  video: bcm2835: fix build issues

Andre Renaud (1):
  Fix bitmap offsets for non 8-bit LCDs

Jeroen Hofstee (10):
  lcd, amba: remove this driver since it is not used
  lcd, tegra: remove unused cursor functions
  lcd, mpc8xx: move the mpc8xx driver to drivers/video
  lcd, pxafb: move the pxafb to drivers/video
  common/lcd.c: cleanup use of global variables
  common/lcd.c: remove global lcd_base
  common/lcd: cosmetic: clean up a bit
  lcd, fb: remove duplicated prototypes and unused code
  api/api_display: use the getters for console size info
  common/lcd.c: move the macro's to the c file

Matthias Weisser (1):
  video: Fix splash screen alignment

Wolfgang Denk (1):
  common/lcd.c: cleanup use of global variables

 api/api_display.c  |4 +-
 arch/arm/cpu/pxa/Makefile  |1 -
 arch/powerpc/cpu/mpc8xx/Makefile   |1 -
 board/cm_t35/display.c |8 -
 board/mcc200/lcd.c |   24 +---
 common/lcd.c   |  143 
 drivers/video/Makefile |3 +-
 drivers/video/amba.c   |   79 ---
 drivers/video/atmel_hlcdfb.c   |   10 --
 drivers/video/atmel_lcdfb.c|   10 --
 drivers/video/bcm2835.c|   11 --
 drivers/video/cfb_console.c|   14 +-
 drivers/video/exynos_fb.c  |   16 +--
 .../cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c |   61 +
 .../arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c |   43 --
 drivers/video/tegra.c  |   66 +-
 include/configs/R360MPI.h  |1 +
 include/configs/RBC823.h   |1 +
 include/configs/RPXlite_DW.h   |1 +
 include/configs/RRvision.h |4 +-
 include/configs/TQM823L.h  |1 +
 include/configs/TQM823M.h  |1 +
 include/configs/lubbock.h  |1 +
 include/configs/lwmon.h|1 +
 include/configs/palmld.h   |1 +
 include/configs/palmtc.h   |1 +
 include/configs/pxa255_idp.h   |1 +
 include/configs/svm_sc8xx.h|1 +
 include/configs/v37.h  |1 +
 include/configs/zipitz2.h  |1 +
 include/lcd.h  |   74 +++
 31 files changed, 138 insertions(+), 447 deletions(-)
 delete mode 100644 drivers/video/amba.c
 rename arch/powerpc/cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c (92%)
 rename arch/arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c (93%)

Please pull. Thanks!

Anatolij
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Re: [U-Boot] [PATCH] disk: fix unaligned access in efi partitions

2013-03-29 Thread Marc Dietrich

Albert,

On Friday 29 March 2013 13:32:26 Albert ARIBAUD wrote:
> On Fri, 29 Mar 2013 12:28:58 +0100, Marc Dietrich  wrote:
> > start_sect is not aligned to a 4 byte boundary thus causing exceptions
> > on ARM platforms. Access this field via the get_unaligned macro.
> > 
> > Signed-off-by: Marc Dietrich 
> > ---
> > 
> >  disk/part_efi.c |3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/disk/part_efi.c b/disk/part_efi.c
> > index b3fd0e9..6678a4c 100644
> > --- a/disk/part_efi.c
> > +++ b/disk/part_efi.c
> > @@ -30,6 +30,7 @@
> > 
> >   *
> >   * This limits the maximum size of addressable storage to < 2 Terra Bytes
> >   */
> > 
> > +#include 
> > 
> >  #include 
> >  #include 
> >  #include 
> > 
> > @@ -505,7 +506,7 @@ err:
> >  static int pmbr_part_valid(struct partition *part)
> >  {
> >  
> > if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
> > 
> > -   le32_to_cpu(part->start_sect) == 1UL) {
> > +   le32_to_cpu(get_unaligned(&part->start_sect)) == 1UL) {
> > 
> > return 1;
> > 
> > }
> 
> Suits me :) but did you not say the same issue was also affecting
> nr_sects?

I checked again and this field is never read - only written to but to an 
aligned buffer. So there shouldn't be a problem.

> Also, beside the asm/unaligned.h file I gave as an example, other header
> files in include/linux/unaligned/ exist that provide alignment-related
> macros, notably with _le and _be versions. Maybe you can find one that
> combines the effects of both le32_to_cpu() and get_unaligned()?

I looks like get_unaligned does the job for us already, so we can leave the 
le32_to_cpu out. But I cannot test it here because of missing big endian 
machine with efi and my two brain halfs are already swapped until confusion 
(start_sect is defined as _le32). 

Albert, I like to get a fix for this into 2013.04 if possible. Maybe someone 
with more endian experience can look at it quickly.

Marc


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Re: [U-Boot] [PATCH] disk: fix unaligned access in efi partitions

2013-03-29 Thread Stephen Warren

On 03/29/2013 09:13 AM, Marc Dietrich wrote:
> On Friday 29 March 2013 13:32:26 Albert ARIBAUD wrote:
>> On Fri, 29 Mar 2013 12:28:58 +0100, Marc Dietrich  wrote:
>>> start_sect is not aligned to a 4 byte boundary thus causing exceptions
>>> on ARM platforms. Access this field via the get_unaligned macro.

>>> -   le32_to_cpu(part->start_sect) == 1UL) {
>>> +   le32_to_cpu(get_unaligned(&part->start_sect)) == 1UL) {

>> Also, beside the asm/unaligned.h file I gave as an example, other header
>> files in include/linux/unaligned/ exist that provide alignment-related
>> macros, notably with _le and _be versions. Maybe you can find one that
>> combines the effects of both le32_to_cpu() and get_unaligned()?
> 
> I looks like get_unaligned does the job for us already, so we can leave the 
> le32_to_cpu out. But I cannot test it here because of missing big endian 
> machine with efi and my two brain halfs are already swapped until confusion 
> (start_sect is defined as _le32). 
> 
> Albert, I like to get a fix for this into 2013.04 if possible. Maybe someone 
> with more endian experience can look at it quickly.

Looking at include/linux/unaligned/generic.h, I think you can just use:

__get_unaligned_le(&part->start_sect) == 1UL

I don't believe the __le32 marking of the start_sect field will have any
effect, since the implementation of __get_unaligned_le accesses the
variable byte-by-byte.
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[U-Boot] [PATCH v2 0/3] Add TI816X EVM support

2013-03-29 Thread TENART Antoine

This serie introduce the support of the TI816X EVM board.
It applies on top of Matt Porter patches introducing the support of the
TI814X EVM board ("Add TI814x EVM Support").

The serie fits into the existing AM33XX SoC support and reuse some definitions
from the TI814X.

Based on the implementation in the TI-PSP-04.00.02.14 vendor tree:
http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary

It has been tested booting up a Linux kernel on TI8168 refs F and C cards,
with an MMC. SPL is working fine too.

Changes for v2:
- patches 2-7 squashed into a single patch "Add TI816X support"
- removed all unused definitions
- removed my definition of DMM_BASE and reworked the DMM initialization
  using the "common" config_dmm() from emif4.c
- fixed coding style problems
- now use the fallback CONFIG_SYS_BAUDRATE_TABLE
- kept LONGHELP support
- removed redefinition of the "device type" section in cpu_ti816x.h

Antoine Tenart (3):
  Prepare for TI816X : reuse existing code from TI814X
  Add TI816X support
  Add TI816X evm board support

 MAINTAINERS|4 +
 Makefile   |2 +-
 arch/arm/cpu/armv7/Makefile|2 +-
 arch/arm/cpu/armv7/omap-common/Makefile|2 +-
 arch/arm/include/asm/arch-am33xx/clock.h   |4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h   |  136 +++
 arch/arm/include/asm/arch-am33xx/cpu.h |6 +-
 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h  |  194 +
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|4 +
 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h |  248 ++
 arch/arm/include/asm/arch-am33xx/hardware.h|7 +-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |5 +
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |5 +
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   56 ++
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h|2 +
 arch/arm/include/asm/arch-am33xx/mux.h |2 +
 arch/arm/include/asm/arch-am33xx/mux_ti816x.h  |  363 
 arch/arm/include/asm/arch-am33xx/omap.h|2 +-
 arch/arm/include/asm/arch-am33xx/spl.h |9 +
 board/ti/ti816x/Makefile   |   48 ++
 board/ti/ti816x/evm.c  |  866 
 boards.cfg |1 +
 drivers/serial/ns16550.c   |4 +-
 include/configs/ti816x_evm.h   |  177 
 spl/Makefile   |2 +-
 25 files changed, 2138 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h
 create mode 100644 board/ti/ti816x/Makefile
 create mode 100644 board/ti/ti816x/evm.c
 create mode 100644 include/configs/ti816x_evm.h

-- 
1.7.10.4
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[U-Boot] [PATCH v2 1/3] Prepare for TI816X : reuse existing code from TI814X

2013-03-29 Thread TENART Antoine

Rename some CONFIG_TI814X to a more generic CONFIG_81XX

Signed-off-by: Antoine Tenart 
---
 Makefile|2 +-
 arch/arm/cpu/armv7/Makefile |2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |2 +-
 arch/arm/include/asm/arch-am33xx/cpu.h  |2 +-
 arch/arm/include/asm/arch-am33xx/omap.h |2 +-
 drivers/serial/ns16550.c|4 ++--
 spl/Makefile|2 +-
 7 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 7273fa4..811e7b6 100644
--- a/Makefile
+++ b/Makefile
@@ -330,7 +330,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index c961247..9bb2837 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
 COBJS  += cpu.o
 COBJS  += syslib.o
 
-ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI814X),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI81XX),)
 SOBJS  += lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 55e82ba..8da8f91 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS += emif-common.o
 COBJS  += vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 COBJS  += boot-common.o
 SOBJS  += lowlevel_init.o
 endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 3d3a7c8..13c0667 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -54,7 +54,7 @@
 /* Reset control */
 #ifdef CONFIG_AM33XX
 #define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
 #define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
 #endif
 #define PRM_RSTST  (PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h 
b/arch/arm/include/asm/arch-am33xx/omap.h
index d28f9a8..1a1cc18 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -31,7 +31,7 @@
 #ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START  0x40304000
 #define NON_SECURE_SRAM_END0x4030E000
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
 #define NON_SECURE_SRAM_START  0x4030
 #define NON_SECURE_SRAM_END0x4032
 #endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 02bc85b..c949423 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+   defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX)
serial_out(0x7, &com_port->mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
@@ -58,7 +58,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
-   defined(CONFIG_TI814X)
+   defined(CONFIG_TI81XX)
 
 #if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/spl/Makefile b/spl/Makefile
index c398a5f..8692f30 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -82,7 +82,7 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
 
-ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-- 
1.7.10.4
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[U-Boot] [PATCH v2 3/3] Add TI816X evm board support

2013-03-29 Thread TENART Antoine

Signed-off-by: Antoine Tenart 
---
 MAINTAINERS|4 +
 arch/arm/include/asm/arch-am33xx/spl.h |9 +
 board/ti/ti816x/Makefile   |   48 ++
 board/ti/ti816x/evm.c  |  866 
 boards.cfg |1 +
 include/configs/ti816x_evm.h   |  177 +++
 6 files changed, 1105 insertions(+)
 create mode 100644 board/ti/ti816x/Makefile
 create mode 100644 board/ti/ti816x/evm.c
 create mode 100644 include/configs/ti816x_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 6b2202c..3aaac7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -922,6 +922,10 @@ Lucas Stach 
 
colibri_t20_irisTegra20 (ARM7 & A9 Dual Core)
 
+Antoine Tenart 
+
+   TI816X  ARM ARMV7 (TI816x Soc)
+
 Nick Thompson 
 
da830evmARM926EJS (DA830/OMAP-L137)
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h 
b/arch/arm/include/asm/arch-am33xx/spl.h
index 9b5fe9e..d0c1ec9 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -23,6 +23,14 @@
 #ifndef_ASM_ARCH_SPL_H_
 #define_ASM_SPL_H_
 
+#if defined(CONFIG_TI816X)
+#define BOOT_DEVICE_XIP2
+#define BOOT_DEVICE_NAND   3
+#define BOOT_DEVICE_MMC1   6
+#define BOOT_DEVICE_MMC2   5
+#define BOOT_DEVICE_UART   0x43
+#define BOOT_DEVICE_MMC2_2 0xFF
+#else
 #define BOOT_DEVICE_XIP2
 #define BOOT_DEVICE_NAND   5
 #ifdef CONFIG_AM33XX
@@ -37,3 +45,4 @@
 #define BOOT_DEVICE_CPGMAC 70
 #define BOOT_DEVICE_MMC2_2  0xFF
 #endif
+#endif
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 000..59128ee
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2013, Adeneo Embedded 
+# Antoine Tenart, 
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS  := evm.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+   $(call cmd_link_o_target, $(OBJS))
+
+clean:
+   rm -f $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
+
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 000..bb9d604
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,866 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded 
+ * Antoine Tenart, 
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING
+static void ddr3_sw_levelling(int emif);
+#endif
+
+int board_init(void)
+{
+   gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+   return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+
+static struct module_pin_mux mmc_pin_mux[] = {
+   { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+   { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+   { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+   { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+   { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+   { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+   { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+   { -1 },
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+   .dmm_lisa_map_0 = 0x,
+   .dm

[U-Boot] [PATCH v2 2/3] Add TI816X support

2013-03-29 Thread TENART Antoine

Signed-off-by: Antoine Tenart 
---
 arch/arm/include/asm/arch-am33xx/clock.h   |4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h   |  136 
 arch/arm/include/asm/arch-am33xx/cpu.h |4 +
 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h  |  194 +++
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|4 +
 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h |  248 +
 arch/arm/include/asm/arch-am33xx/hardware.h|7 +-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |5 +
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |5 +
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   56 +++
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h|2 +
 arch/arm/include/asm/arch-am33xx/mux.h |2 +
 arch/arm/include/asm/arch-am33xx/mux_ti816x.h  |  363 
 13 files changed, 1025 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h 
b/arch/arm/include/asm/arch-am33xx/clock.h
index ecb5901..123cc61 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -19,6 +19,10 @@
 #ifndef _CLOCKS_H_
 #define _CLOCKS_H_
 
+#if defined(CONFIG_TI816X)
+#include 
+#else
 #include 
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h 
b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
new file mode 100644
index 000..403db33
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
@@ -0,0 +1,136 @@
+/*
+ * clocks_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded 
+ * Antoine Tenart, 
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * (C) Copyright 2006-2008
+ * Texas Instruments, 
+ * Richard Woodruff 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_TI816X_H_
+#define _CLOCKS_TI816X_H_
+
+/*
+ * Values supported 400,531,675,796
+ *
+ * On TI8168 rev C, use 400 or 531 MHz !
+ */
+#define DDR_PLL_400
+
+/* Main PLL */
+#define MAIN_N 64
+#define MAIN_P 0x1
+#define MAIN_INTFREQ1  0x8
+#define MAIN_FRACFREQ1 0x80
+#define MAIN_MDIV1 0x2
+#define MAIN_INTFREQ2  0xE
+#define MAIN_FRACFREQ2 0x0
+#define MAIN_MDIV2 0x1
+#define MAIN_INTFREQ3  0x8
+#define MAIN_FRACFREQ3 0xB0
+#define MAIN_MDIV3 0x3
+#define MAIN_INTFREQ4  0x9
+#define MAIN_FRACFREQ4 0x4F
+#define MAIN_MDIV4 0x3
+#define MAIN_INTFREQ5  0x9
+#define MAIN_FRACFREQ5 0x374BC6
+#define MAIN_MDIV5 0xC
+#define MAIN_MDIV6 0x48
+#define MAIN_MDIV7 0x4
+
+/* DDR PLL */
+/* For 400 MHz */
+#if defined(DDR_PLL_400)
+#define DDR_N  59
+#define DDR_P  0x1
+#define DDR_MDIV1  0x4
+#define DDR_INTFREQ2   0x8
+#define DDR_FRACFREQ2  0xD9
+#define DDR_MDIV2  0x1E
+#define DDR_INTFREQ3   0x8
+#define DDR_FRACFREQ3  0x0
+#define DDR_MDIV3  0x4
+#define DDR_INTFREQ4   0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4  0x0
+#define DDR_MDIV4  0x4
+#define DDR_INTFREQ5   0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5  0x0
+#define DDR_MDIV5  0x4
+#endif
+
+/* For 531 MHz */
+#if defined(DDR_PLL_531)
+#define DDR_N  59
+#define DDR_P  0x1
+#define DDR_MDIV1  0x3
+#define DDR_INTFREQ2   0x8
+#define DDR_FRACFREQ2  0xD9
+#define DDR_MDIV2  0x1E
+#define DDR_INTFREQ3   0x8
+#define DDR_FRACFREQ3  0x0
+#define DDR_MDIV3  0x4
+#define DDR_INTFREQ4   0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4  0x0
+#define DDR_MDIV4  0x4
+#define DDR_INTFREQ5   0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5  0x0
+#define DDR_MDIV

[U-Boot] [PATCH V2] disk: fix unaligned access in efi partitions

2013-03-29 Thread Marc Dietrich

start_sect is not aligned to a 4 byte boundary thus causing exceptions
on ARM platforms. Access this field via the get_unaligned_le32 macro.

Signed-off-by: Marc Dietrich 
---
V2: replace le32_to_cpu(get_unaligned()) with get_unaligned_le32

 disk/part_efi.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/disk/part_efi.c b/disk/part_efi.c
index b3fd0e9..e9987f0 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -30,6 +30,7 @@
  *
  * This limits the maximum size of addressable storage to < 2 Terra Bytes
  */
+#include 
 #include 
 #include 
 #include 
@@ -505,7 +506,7 @@ err:
 static int pmbr_part_valid(struct partition *part)
 {
if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
-   le32_to_cpu(part->start_sect) == 1UL) {
+   get_unaligned_le32(&part->start_sect) == 1UL) {
return 1;
}
 
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] build: Fix make errors generated when building 'distclean'

2013-03-29 Thread Simon Glass

On Wed, Mar 27, 2013 at 5:34 PM, Vadim Bendebury wrote:

> It was noticed that when `make distclean' is run, the make process
> terminates with error reporting something like:
>
> rm: cannot remove '/tmp/foobar/': Is a directory
> make: *** [clobber] Error 1
>
> The problem is that the list of files targeted for removal includes a
> directory in case CONFIG_SPL_TARGET is not set.
>
> The fix has been tested as follows:
>
>  Ran several times the following sequence of commands:
>
>  CROSS_COMPILE=/usr/bin/arm-linux-gnueabi- make O=/tmp/foobar
> smdk5250_config
>  CROSS_COMPILE=/usr/bin/arm-linux-gnueabi- make O=/tmp/foobar distclean
>
>  it did not cause an error, it used to before this change.
>
> Signed-off-by: Vadim Bendebury 
>

Acked-by: Simon Glass 
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[U-Boot] [PATCH] OMAP: Fix copy-paste bug that did not enable UART4 clock

2013-03-29 Thread Lubomir Popov

UART3 was enabled twice instead of UART4.

One more cosmetic change in a comment on EMIF clock.

Signed-off-by: Lubomir Popov 

---
 arch/arm/cpu/armv7/omap-common/clocks-common.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 9ed1899..2b955c7 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -612,7 +612,7 @@ void freq_update_core(void)

/*
 * Putting EMIF in HW_AUTO is seen to be causing issues with
-* EMIF clocks and the master DLL. Put EMIF in SW_WKUP
+* EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
 * in OMAP5430 ES1.0 silicon
 */
if (omap_rev != OMAP5430_ES1_0) {
@@ -659,7 +659,7 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);

-   clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
+   clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
-- 
1.7.9.5
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[U-Boot] [PATCH] OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work

2013-03-29 Thread Lubomir Popov

This fix is needed (but not sufficient) for USB EHCI operation.

Signed-off-by: Lubomir Popov 

---
 arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index ced274e..e5e41fd 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void)
};

u32 const clk_modules_hw_auto_essential[] = {
+   (*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};

@@ -411,7 +412,6 @@ void enable_basic_uboot_clocks(void)
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
-   (*prcm)->cm_l3init_hsusbtll_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
-- 
1.7.9.5
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[U-Boot] [PATCH] OMAP5: I2C: Enable i2c5 clocks

2013-03-29 Thread Lubomir Popov

I2C5 is used on all known OMAP5 hardware platforms, therefore enable.

Signed-off-by: Lubomir Popov 

---
 arch/arm/cpu/armv7/omap5/hw_data.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index e5e41fd..5698876 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -412,6 +412,7 @@ void enable_basic_uboot_clocks(void)
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
+   (*prcm)->cm_l4per_i2c5_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
-- 
1.7.9.5
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[U-Boot] [PATCH] OMAP5: I2C: Add I2C4 and I2C5 bases

2013-03-29 Thread Lubomir Popov

Need to add these base addresses in order to use I2C4 and I2C5.

Signed-off-by: Lubomir Popov 

---
 arch/arm/include/asm/arch-omap5/cpu.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h
b/arch/arm/include/asm/arch-omap5/cpu.h
index 5e62013..044ab55 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -142,6 +142,8 @@ struct watchdog {
 #define I2C_BASE1  (OMAP54XX_L4_PER_BASE + 0x7)
 #define I2C_BASE2  (OMAP54XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3  (OMAP54XX_L4_PER_BASE + 0x6)
+#define I2C_BASE4  (OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5  (OMAP54XX_L4_PER_BASE + 0x7C000)

 /* MUSB base */
 #define MUSB_BASE  (OMAP54XX_L4_CORE_BASE + 0xAB000)
-- 
1.7.9.5
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[U-Boot] [PATCH] OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5

2013-03-29 Thread Lubomir Popov

Needed in order to be able to select I2C4 and I2C5 via "i2c dev".

Signed-off-by: Lubomir Popov 

---
 arch/arm/include/asm/arch-omap5/i2c.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-omap5/i2c.h
b/arch/arm/include/asm/arch-omap5/i2c.h
index 68be03b..ec39a53 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -23,7 +23,7 @@
 #ifndef _OMAP5_I2C_H_
 #define _OMAP5_I2C_H_

-#define I2C_BUS_MAX3
+#define I2C_BUS_MAX5
 #define I2C_DEFAULT_BASE   I2C_BASE1

 struct i2c {
-- 
1.7.9.5
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[U-Boot] [PATCH 1/2] OMAP4/5: I2C: New I2C driver, Makefile fix

2013-03-29 Thread Lubomir Popov

See PATCH 2/2 on new I2C driver.

Signed-off-by: Lubomir Popov 
---
 drivers/i2c/Makefile |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 5dbdbe3..8afc621 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -36,6 +36,8 @@ COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
+COBJS-$(CONFIG_DRIVER_OMAP44XX_I2C) += omap4x5x_i2c.o
+COBJS-$(CONFIG_DRIVER_OMAP54XX_I2C) += omap4x5x_i2c.o
 COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
-- 
1.7.9.5
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[U-Boot] [PATCH 2/2] OMAP4/5: I2C: New I2C driver files added

2013-03-29 Thread Lubomir Popov

New I2C driver that fixes read-related issues with some types
of I2C chips. The i2c_read function now performs bulk read of
the requested number of bytes in a single transaction and
completes much faster. Whether to use Stop-Start or Repeated
Start between the address and data phases is configurable
(e.g. in the board config header).

Signed-off-by: Lubomir Popov 

---

The main feature of this new driver is that now i2c_read operates
correctly with chips that have addressable registers wider than 8 bits
(such as TI temperature sensors), or that have multiple non-addressable
registers that have to be retrieved in a bulk transaction (such as TI
clock distributors). The old driver (omap24xx_i2c.c) performs separate
read transactions for every byte requested and returns invalid data in
these cases (except possibly the first byte; this invalid data is in
fact presented by the chips, so the driver does not know that it is
invalid).

The new driver performs a standard bulk read transaction (with S-P by
default, or with Sr if configured so) and works correctly with all types
of I2C devices.

The i2c_write and i2c_probe functions have also been modified.

I have tested the driver on OMAP4430, 4460, 4470 and 5430 and found no
issues so far. Nevertheless, folks, any additional testing is strongly
encouraged; the driver should also work on OMAP3 and derivatives, but I
didn't have this opportunity, so any feedback is welcome.

 drivers/i2c/omap4x5x_i2c.c |  562 
 drivers/i2c/omap4x5x_i2c.h |  176 ++
 2 files changed, 738 insertions(+)
 create mode 100644 drivers/i2c/omap4x5x_i2c.c
 create mode 100644 drivers/i2c/omap4x5x_i2c.h

diff --git a/drivers/i2c/omap4x5x_i2c.c b/drivers/i2c/omap4x5x_i2c.c
new file mode 100644
index 000..44d7813
--- /dev/null
+++ b/drivers/i2c/omap4x5x_i2c.c
@@ -0,0 +1,562 @@
+/*
+ * Basic I2C functions
+ *
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software;  you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Author: Jian Zhang jzh...@ti.com, Texas Instruments
+ *
+ * Copyright (c) 2003 Wolfgang Denk, w...@denx.de
+ * Rewritten to fit into the current U-Boot framework
+ *
+ * Adapted for OMAP2420 I2C, r-woodru...@ti.com
+ *
+ * Copyright (c) 2013 Lubomir Popov , MM Solutions
+ * Based on omap24xx_i2c.c and modified for OMAP4/5:
+ * - i2c_read now operates correctly, with bulk transfer;
+ * - i2c_probe performs write access vs read;
+ * - Driver tries to identify I2C pads not properly padconf'd;
+ * - Should work with OMAP3/AM33xx as well, but is not tested.
+ */
+
+#include 
+
+#include 
+#include 
+
+#include "omap4x5x_i2c.h"
+
+#undef I2C_DBG
+
+#ifdef I2C_DBG
+#define I2C_PRINTF(fmt, args...)   printf(fmt , ##args)
+#else
+#define I2C_PRINTF(fmt, args...)
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_TIMEOUT1000
+
+static int wait_for_bus_free(void);
+static u16 wait_for_event(void);
+static void flush_fifo(void);
+
+/*
+ * For SPL boot some boards need i2c before SDRAM is initialised so force
+ * variables to live in SRAM
+ */
+static struct i2c __attribute__((section (".data"))) *i2c_base =
+   (struct i2c *)I2C_DEFAULT_BASE;
+static unsigned int __attribute__((section (".data"))) 
bus_initialized[I2C_BUS_MAX] =
+   { [0 ... (I2C_BUS_MAX-1)] = 0 };
+static unsigned int __attribute__((section (".data"))) current_bus = 0;
+
+void i2c_init(int speed, int slaveadd)
+{
+   int psc, fsscll, fssclh;
+   int hsscll = 0, hssclh = 0;
+   u32 scll, sclh;
+   int timeout = I2C_TIMEOUT;
+
+   /* Only handle standard, fast and high speeds */
+   if ((speed != OMAP_I2C_STANDARD) &&
+   (speed != OMAP_I2C_FAST_MODE) &&
+   (speed != OMAP_I2C_HIGH_SPEED)) {
+   printf("Error : I2C unsupported speed %d\n", speed);
+   return;
+   }
+
+   psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
+   psc -= 1;
+   if (psc < I2C_PSC_MIN) {
+   printf("Error : I2C unsupported prescalar %d\n", psc);
+   return;
+   }
+
+   if (speed == OMAP_I2C_HIGH_SPEED) {
+   /* High speed */
+
+   /* For first phase of HS mode */
+   fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
+   (2 * OMAP_I2C_FAST_MODE);
+
+   fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
+   fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
+   if (((fsscll < 0) || (fssclh < 0)) ||
+   ((fsscll > 255) || (fssclh > 255))) {
+

[U-Boot] [PATCH] Tegra: Configure L2 cache control reg properly.

2013-03-29 Thread Tom Warren

Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren 
---
 arch/arm/cpu/tegra-common/Makefile   |  2 +-
 arch/arm/cpu/tegra-common/ap.c   |  9 ++-
 arch/arm/cpu/tegra-common/cache.c| 48 
 arch/arm/include/asm/arch-tegra/ap.h |  1 +
 4 files changed, 52 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/tegra-common/cache.c

diff --git a/arch/arm/cpu/tegra-common/Makefile 
b/arch/arm/cpu/tegra-common/Makefile
index 8e95c7e..4e0301c 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB= $(obj)libcputegra-common.o
 
 SOBJS += lowlevel_init.o
-COBJS-y+= ap.o board.o sys_info.o timer.o clock.o
+COBJS-y+= ap.o board.o sys_info.o timer.o clock.o cache.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 3f30805..a739fe2 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -139,11 +139,6 @@ void s_init(void)
 
enable_scu();
 
-   /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-   asm volatile(
-   "mrcp15, 0, r0, c1, c0, 1\n"
-   "orrr0, r0, #0x41\n"
-   "mcrp15, 0, r0, c1, c0, 1\n");
-
-   /* FIXME: should have SoC's L2 disabled too? */
+   /* init the cache */
+   config_cache();
 }
diff --git a/arch/arm/cpu/tegra-common/cache.c 
b/arch/arm/cpu/tegra-common/cache.c
new file mode 100644
index 000..48e9319
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+/* Tegra cache routines */
+
+#include 
+#include 
+#include 
+#include 
+
+void config_cache(void)
+{
+   struct apb_misc_gp_ctlr *gp =
+   (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+   u32 reg = 0;
+
+   /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
+   asm volatile(
+   "mrc p15, 0, r0, c1, c0, 1\n"
+   "orr r0, r0, #0x41\n"
+   "mcr p15, 0, r0, c1, c0, 1\n");
+
+   /* Currently, only T114 needs this L2 cache change to boot Linux */
+   reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
+   if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+   return;
+   /*
+* Systems with an architectural L2 cache must not use the PL310.
+* Config L2CTLR here for a data RAM latency of 3 cycles.
+*/
+   asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+   reg &= ~7;
+   reg |= 2;
+   asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index 73dfd39..5999f55 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -64,3 +64,4 @@ extern void _start(void);
  * @return SOC type - see TEGRA_SOC...
  */
 int tegra_get_chip_type(void);
+void config_cache(void);
-- 
1.8.1.5

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Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

2013-03-29 Thread Kim Phillips

On Fri, 29 Mar 2013 04:43:23 +
Gupta Ruchika-R66431  wrote:

> > From: otavio.salva...@gmail.com [mailto:otavio.salva...@gmail.com] On Behalf
> > Of Otavio Salvador
> > Sent: Thursday, March 28, 2013 8:23 PM
> > To: Gupta Ruchika-R66431
> > Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
> > Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next
> > level image validation
> > 
> > On Thu, Mar 28, 2013 at 7:46 AM, Ruchika Gupta 
> > wrote:
> > > The patch set adds support for next level image validation (linux,
> > > rootfs, dtb) in secure boot scenarios.
> > 
> > It seems to focus in PowerPC, do you know if same code could be ported to
> > ARM?
> For the code to be ported to ARM platform, corresponding hardware blocks like 
> cryptographic accelerator/SW support for crypto operations, IOMMU and a 
> security monitor block will be required.

i.mx6 has, and other future ARM-based devices will have, a CAAM, so
I see no reason why any of this code should be restricted to power
arch at all.

How does this patchseries integrate with this SHA offload
patchseries:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156321

and this "verified boot" implementation:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156422

?

Kim

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Re: [U-Boot] [PATCH] Tegra: Configure L2 cache control reg properly.

2013-03-29 Thread Stephen Warren

On 03/29/2013 02:38 PM, Tom Warren wrote:
> Without this change, kernel fails at calling function cache_clean_flush
> during kernel early boot.
> 
> Aprocryphally, intended for T114 only, so I check for a T114 SoC.
> Works (i.e. dalmore 3.8 kernel now starts printing to console).

I don't know enough about the caches to really review this, but I have
no particular objection to it. My one comment is ...

> diff --git a/arch/arm/cpu/tegra-common/cache.c 
> b/arch/arm/cpu/tegra-common/cache.c

> +void config_cache(void)

> + /* Currently, only T114 needs this L2 cache change to boot Linux */
> + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
> + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
> + return;

Can we introduce a standard function for that instead? We already have
tegra_get_chip_type() which returns a SKU-based ID. I think we need to
introduce a tegra_get_soc_type() that returns a pure Tegra20/30/114
value, and probably use this in most places we currently use the result
of tegra_get_chip_type(), since most care about SW-compatibility of
features rather than SKU which drivers performance levels instead
typically. Then, perhaps rename tegra_get_chip_type() to
tegra_get_soc_sku() and re-write it to use tegra_get_soc_type()?
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Re: [U-Boot] [PATCH] Tegra: Configure L2 cache control reg properly.

2013-03-29 Thread Tom Warren

Stephen,


On Fri, Mar 29, 2013 at 3:43 PM, Stephen Warren wrote:

> On 03/29/2013 02:38 PM, Tom Warren wrote:
> > Without this change, kernel fails at calling function cache_clean_flush
> > during kernel early boot.
> >
> > Aprocryphally, intended for T114 only, so I check for a T114 SoC.
> > Works (i.e. dalmore 3.8 kernel now starts printing to console).
>
> I don't know enough about the caches to really review this, but I have
> no particular objection to it. My one comment is ...
>
> > diff --git a/arch/arm/cpu/tegra-common/cache.c
> b/arch/arm/cpu/tegra-common/cache.c
>
> > +void config_cache(void)
>
> > + /* Currently, only T114 needs this L2 cache change to boot Linux */
> > + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
> > + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
> > + return;
>
> Can we introduce a standard function for that instead? We already have
> tegra_get_chip_type() which returns a SKU-based ID. I think we need to
> introduce a tegra_get_soc_type() that returns a pure Tegra20/30/114
> value, and probably use this in most places we currently use the result
> of tegra_get_chip_type(), since most care about SW-compatibility of
> features rather than SKU which drivers performance levels instead
> typically. Then, perhaps rename tegra_get_chip_type() to
> tegra_get_soc_sku() and re-write it to use tegra_get_soc_type()?
>

I can do that, but I'd prefer to do it as a separate patch since
tegra_get_chip_type is used in a few other places.

This patch is needed by a customer to get their kernel loading (or at least
past the 'Decompressing Linux...' part). I'll correct this patch later to
use tegra_get_soc_type().

Thanks,

Tom
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Re: [U-Boot] [PATCH 1/3] ppc4xx: Add SPL support

2013-03-29 Thread Rommel G Custodio

Dear Stefan Rose,

On 2013.02/22, Stefan Roese wrote:

> diff --git a/arch/powerpc/cpu/ppc4xx/Makefile 
> b/arch/powerpc/cpu/ppc4xx/Makefile
> index 8da2f86..e301dc6 100644
> --- a/arch/powerpc/cpu/ppc4xx/Makefile
> +++ b/arch/powerpc/cpu/ppc4xx/Makefile
> @@ -68,6 +68,10 @@ COBJS  += miiphy.o
>  COBJS+= uic.o
>  endif
>  
> +ifdef CONFIG_SPL_BUILD
> +COBJS-y += spl_boot.o
> +endif
> +
>  SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
>  OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
>  START:= $(addprefix $(obj),$(START))

I think spl_boot.c is missing from this patch series.

All the best,
Rommel



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Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

2013-03-29 Thread Gupta Ruchika-R66431



> -Original Message-
> From: Phillips Kim-R1AAHA
> Sent: Saturday, March 30, 2013 4:08 AM
> To: Gupta Ruchika-R66431
> Cc: Otavio Salvador; U-Boot Mailing List; Fleming Andy-AFLEMING
> Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next
> level image validation
> 
> On Fri, 29 Mar 2013 04:43:23 +
> Gupta Ruchika-R66431  wrote:
> 
> > > From: otavio.salva...@gmail.com [mailto:otavio.salva...@gmail.com]
> > > On Behalf Of Otavio Salvador
> > > Sent: Thursday, March 28, 2013 8:23 PM
> > > To: Gupta Ruchika-R66431
> > > Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
> > > Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for
> > > next level image validation
> > >
> > > On Thu, Mar 28, 2013 at 7:46 AM, Ruchika Gupta
> > > 
> > > wrote:
> > > > The patch set adds support for next level image validation (linux,
> > > > rootfs, dtb) in secure boot scenarios.
> > >
> > > It seems to focus in PowerPC, do you know if same code could be
> > > ported to ARM?
> > For the code to be ported to ARM platform, corresponding hardware blocks
> like cryptographic accelerator/SW support for crypto operations, IOMMU and a
> security monitor block will be required.
> 
> i.mx6 has, and other future ARM-based devices will have, a CAAM, so I see no
> reason why any of this code should be restricted to power arch at all.
> 
> How does this patchseries integrate with this SHA offload
> patchseries:
> 
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156321
> 
> and this "verified boot" implementation:
> 
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156422
> 
> ?
> 
> Kim

Thanks for the suggestion Kim. I will have a look at the links you mentioned 
and see how my patches can fit in. Since I am on leave this week so my response 
on this will be a little delayed.

Ruchika

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Re: [U-Boot] [PATCH 04/11] usb-ehci: add Faraday USB 2.0 EHCI controller support

2013-03-29 Thread Marek Vasut

Dear Kuo-Jung Su,

> From: Kuo-Jung Su 
> 
> This patch add supports to both Faraday FUSBH200 and FOTG210,
> these controllers slightly differ from standard EHCI specification.
> 
> Signed-off-by: Kuo-Jung Su 

You want to fix the magic values here, use readl()/writel() to operate 
registers, kill the BIT() macro and review comments in common files.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 05/11] usb-gadget: add FOTG210 USB gadget support

2013-03-29 Thread Marek Vasut

Dear Kuo-Jung Su,

> From: Kuo-Jung Su 
> 
> This patch would try to use Faraday FOTG210 to implement
> a USB RNDIS Ethernet.
> 
> Signed-off-by: Kuo-Jung Su 

[...]

> +static inline int
> +ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
> +{
> + int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
> +
> + if (ep_addr & USB_DIR_IN) {
> + /* input */
> + USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) |= BIT(12);
> + USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) &= ~BIT(12);
> + USB_REG32(chip, REG_IEP1 + (ep - 1) * 4) &= ~BIT(11);
> + } else {
> + /* output */
> + USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) |= BIT(12);
> + USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) &= BIT(12);
> + USB_REG32(chip, REG_OEP1 + (ep - 1) * 4) &= BIT(11);
> + }

Use readl(), writel(), clrsetbits_le32() etc.

For example see drivers/i2c/mxs_i2c.c

[...]

> +/*
> + * Global Registers
> + */
> +#define REG_ISR 0x0C0/* Interrupt Status */
> +#define REG_IMR 0x0C4/* Interrupt Control */

Use structure based access, ie.

arch/arm/include/asm/arch-mxs/regs-i2c.h

struct regs {
uint32_t reg1;
uint32_t reg2;
...
};

writel(val, ®s->reg1);
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