[Qemu-devel] [PATCH] hw/i386: add legacy cpu hotplug for pc-lite
From: Simon Guo Currently pc-lite cpu hot plug will leads to error like: "acpi: device plug request for not supported device type: host-x86_64-cpu" . However pc_lite_machine_options() didn't setup flag legacy_cpu_hotplug correctly, which will leads to a later mess state, and causes the error above. This patch corrects this by initialize legacy_cpu_hotplug flag correctly at pc_lite_machine_options(). Signed-off-by: Simon Guo --- hw/i386/pc_lite.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/i386/pc_lite.c b/hw/i386/pc_lite.c index 707f2fd..5fd05b1 100644 --- a/hw/i386/pc_lite.c +++ b/hw/i386/pc_lite.c @@ -196,6 +196,7 @@ static void pc_lite_machine_options(MachineClass *m) m->units_per_default_bus = 1; m->no_floppy = 1; pcmc->type = PC_MACHINE_TYPE_LITE; + pcmc->legacy_cpu_hotplug = true; } static void pc_lite_2_7_machine_options(MachineClass *m) -- 1.8.3.1
[Qemu-devel] [PATCH] PowerPC: Add TM bits into msr_mask
From: Simon Guo During migration, cpu_post_load() will use msr_mask to determine which PPC MSR bits will be sync to the target side. Hardware Transaction Memory(HTM) has been supported since Power8. This patch adds TM/TS bits into msr_mask for Power8, so that transactional application can be migrated across qemu. Signed-off-by: Simon Guo --- target/ppc/translate_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 55c99c9..a438721 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8689,6 +8689,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | +(1ull << MSR_TM) | +(1ull << MSR_TS0) | +(1ull << MSR_TS1) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) -- 1.8.3.1
[Qemu-devel] [PATCH v2] PowerPC: Add TS bits into msr_mask
From: Simon Guo During migration, after MSR bits is synced, cpu_post_load() will use msr_mask to determine which PPC MSR bits will be applied into the target side. Hardware Transaction Memory(HTM) has been supported since Power8, but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM from loading TM checkpointed values. This patch adds TS bits into msr_mask for Power8, so that transactional application can be migrated across qemu. Signed-off-by: Simon Guo --- target/ppc/translate_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 55c99c9..ca06028 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8689,6 +8689,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | +(1ull << MSR_TS0) | +(1ull << MSR_TS1) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) -- 1.8.3.1
