[Qemu-devel] [PATCH 1/2] microblaze: Support setting of TLS ptr
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
linux-user/syscall.c|2 ++
target-microblaze/cpu.h |1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 471d060..c6a6337 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6888,6 +6888,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(do_fork(cpu_env, arg1, arg2, arg3, arg5, arg4));
#elif defined(TARGET_CRIS)
ret = get_errno(do_fork(cpu_env, arg2, arg1, arg3, arg4, arg5));
+#elif defined(TARGET_MICROBLAZE)
+ret = get_errno(do_fork(cpu_env, arg1, arg2, arg4, arg6, arg5));
#elif defined(TARGET_S390X)
ret = get_errno(do_fork(cpu_env, arg2, arg1, arg3, arg5, arg4));
#else
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 4968c24..88430b5 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -345,6 +345,7 @@ static inline void cpu_clone_regs(CPUMBState *env,
target_ulong newsp)
static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
{
+env->regs[21] = newtls;
}
static inline int cpu_interrupts_enabled(CPUMBState *env)
--
1.7.8.6
[Qemu-devel] [PATCH 2/2] microblaze: Update PC before simulating syscall
From: "Edgar E. Iglesias" Fixes a clone() emulation bug were the new thread starts at the point of the syscall and thus clones in a loop. Signed-off-by: Edgar E. Iglesias --- linux-user/main.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index f4bbe69..5827ee6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2527,6 +2527,7 @@ void cpu_loop(CPUMBState *env) case EXCP_BREAK: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; +env->sregs[SR_PC] = env->regs[14]; ret = do_syscall(env, env->regs[12], env->regs[5], @@ -2537,7 +2538,6 @@ void cpu_loop(CPUMBState *env) env->regs[10], 0, 0); env->regs[3] = ret; -env->sregs[SR_PC] = env->regs[14]; break; case EXCP_HW_EXCP: env->regs[17] = env->sregs[SR_PC] + 4; -- 1.7.8.6
[Qemu-devel] [PATCH] Allow qtest to be used together with a virtual CPU
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
vl.c |4
1 file changed, 4 insertions(+)
diff --git a/vl.c b/vl.c
index c566caf..0dbac29 100644
--- a/vl.c
+++ b/vl.c
@@ -4143,6 +4143,10 @@ int main(int argc, char **argv, char **envp)
configure_accelerator();
+if (!qtest_enabled() && qtest_chrdev) {
+qtest_init();
+}
+
machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
if (machine_opts) {
kernel_filename = qemu_opt_get(machine_opts, "kernel");
--
1.7.10.4
[Qemu-devel] [PATCH] microblaze: Add internal base vectors reg
From: "Edgar E. Iglesias"
Configurable at CPU synthesis/instantiation.
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu.h|1 +
target-microblaze/helper.c |8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 1813939..dc07595 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -235,6 +235,7 @@ struct CPUMBState {
uint32_t btaken;
uint32_t btarget;
uint32_t bimm;
+uint32_t base_vectors;
uint32_t imm;
uint32_t regs[33];
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index a0416d0..4246ce8 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
-env->sregs[SR_PC] = 0x20;
+env->sregs[SR_PC] = env->base_vectors + 0x20;
break;
case EXCP_MMU:
@@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
-env->sregs[SR_PC] = 0x20;
+env->sregs[SR_PC] = env->base_vectors + 0x20;
break;
case EXCP_IRQ:
@@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC];
-env->sregs[SR_PC] = 0x10;
+env->sregs[SR_PC] = env->base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, env, 0);
break;
@@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
if (env->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP;
-env->sregs[SR_PC] = 0x18;
+env->sregs[SR_PC] = env->base_vectors + 0x18;
} else
env->sregs[SR_PC] = env->btarget;
break;
--
1.7.10.4
[Qemu-devel] [PATCH v2] microblaze: Add internal base vectors reg
From: "Edgar E. Iglesias"
Configurable at CPU synthesis/instantiation.
Signed-off-by: Edgar E. Iglesias
---
Peter Crosthwaite commented off-list that it would be a good idea
to make this a device property. I agree but am a bit unsure of
how it should look. Any comments on this attempt?
v2:
Make base_vectors a CPU/device property.
target-microblaze/cpu-qom.h |1 +
target-microblaze/cpu.c |8
target-microblaze/helper.c |8
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index aa51cf6..ce92a4e 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -56,6 +56,7 @@ typedef struct MicroBlazeCPUClass {
typedef struct MicroBlazeCPU {
/*< private >*/
CPUState parent_obj;
+uint32_t base_vectors;
/*< public >*/
CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0f4293d..404f82c 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "qemu-common.h"
+#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@@ -119,6 +120,11 @@ static const VMStateDescription vmstate_mb_cpu = {
.unmigratable = 1,
};
+static Property mb_properties[] = {
+DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -133,6 +139,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = mb_cpu_do_interrupt;
dc->vmsd = &vmstate_mb_cpu;
+
+dc->props = mb_properties;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index a0416d0..0dd669d 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
-env->sregs[SR_PC] = 0x20;
+env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
case EXCP_MMU:
@@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
-env->sregs[SR_PC] = 0x20;
+env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
case EXCP_IRQ:
@@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC];
-env->sregs[SR_PC] = 0x10;
+env->sregs[SR_PC] = cpu->base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, env, 0);
break;
@@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
if (env->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP;
-env->sregs[SR_PC] = 0x18;
+env->sregs[SR_PC] = cpu->base_vectors + 0x18;
} else
env->sregs[SR_PC] = env->btarget;
break;
--
1.7.10.4
[Qemu-devel] [PATCH v3 00/22] Steps towards per CPU address-spaces
From: "Edgar E. Iglesias" Hi, I'm looking at modeling systems where multiple CPUs co-exist with different views of their attached buses/devs. With this series I'm trying to take some steps towards having an address-space per CPU. It's not complete but good enough for making it possible to model (to some extent) CPU local memories for MicroBlaze systems in emulation mode (TCG). I'm updating the petalogix-ml605 here and will follow-up later with the petalogix-s3adsp. The per-cpu address space is added into the CPUState. I tried to measure performance diff with having it in the CPUState->env. For "normal" and even for IO heavy workloads on linux kernels, the diff is not measurable. I also tested with a tight guest loop that continuously does I/O accesses and there I can see a 2.5% drop in perf. I dont think the runtime type check involved when casting from env to CS will be much of a problem. I've reordered the series and moved the AS props to the end, hoping we can get through the bulk of the series with less controversy and get it commited soon. I've kept the interface with properties to set AddressSpace pointers which I think is the more flexible approach but we can explore other ideas if there are. There is lots of future work needed, for example to transform more of the cpu_* bus accessing functions. To add more usage of AddressSpace properties to pass on address spaces to DMA models. Qtest mechanisms to target specific address spaces, etc... Cheers, Edgar v2 -> v3: Move CPU address-space prop into CPUState level. v1 -> v2: Add braces in cpu_memory_rw_debug. Avoid mixing var/code declarations in tcg_commit. Move per-cpu address space into CPUState. Reorder patch series to add the AS properties last. Edgar E. Iglesias (22): exec: Make tb_invalidate_phys_addr input an AS exec: Make iotlb_to_region input an AS exec: Always initialize MemorySection address spaces exec: Make memory_region_section_get_iotlb use section AS memory: Add MemoryListener to typedefs.h cpu: Add per-cpu address space exec: On AS changes, only flush affected CPU TLBs exec: Make ldl_*_phys input an AddressSpace exec: Make ldq/ldub_*_phys input an AddressSpace exec: Make lduw_*_phys input an AddressSpace exec: Make stq_*_phys input an AddressSpace exec: Make stl_*_phys input an AddressSpace exec: Make stl_phys_notdirty input an AddressSpace exec: Make stw_*_phys input an AddressSpace exec: Make stb_phys input an AddressSpace exec: Make cpu_physical_memory_write_rom input an AS exec: Make cpu_memory_rw_debug use the CPUs AS memory: Add address_space_find_by_name() qdev: Add qdev property type for AddressSpaces cpu: Add address-space property petalogix-ml605: Create the CPU with object_new() petalogix-ml605: Make the LMB visible only to the CPU cpu-exec.c |5 +- cpus.c |2 + cputlb.c|7 +- exec.c | 183 +++-- hw/alpha/dp264.c|5 +- hw/alpha/typhoon.c |2 +- hw/arm/boot.c |9 +- hw/arm/highbank.c |6 +- hw/core/loader.c|3 +- hw/core/qdev-properties-system.c| 10 ++ hw/core/qdev-properties.c | 54 +++ hw/display/sm501.c |1 + hw/display/sm501_template.h |2 +- hw/dma/pl080.c |9 +- hw/dma/sun4m_iommu.c|3 +- hw/intc/apic.c |3 +- hw/microblaze/petalogix_ml605_mmu.c | 28 +++- hw/net/vmware_utils.h | 16 +- hw/pci/msi.c|2 +- hw/pci/msix.c |2 +- hw/ppc/ppc405_uc.c | 45 +++--- hw/ppc/spapr_hcall.c| 50 +++--- hw/s390x/css.c | 11 +- hw/s390x/s390-virtio-bus.c | 36 +++-- hw/s390x/s390-virtio.c |2 +- hw/s390x/virtio-ccw.c | 40 +++-- hw/scsi/megasas.c | 22 ++- hw/scsi/vmw_pvscsi.c|6 +- hw/sh4/r2d.c|4 +- hw/sparc/sun4m.c|3 +- hw/timer/hpet.c |3 +- hw/virtio/virtio.c | 31 ++-- include/exec/cpu-common.h | 44 ++--- include/exec/exec-all.h |5 +- include/exec/memory.h | 11 +- include/exec/softmmu_template.h |7 +- include/hw/ppc/spapr.h |4 +- include/hw/qdev-properties.h|5 + include/qemu/typedefs.h |1 + include/qom/cpu.h |3 + memory.c| 12 ++ monitor.c |2 +- qom/cpu.c |7 + stubs/Makefile.objs |1 + stubs/memory.c |6 + target-alpha/helper.c
[Qemu-devel] [PATCH v3 01/22] exec: Make tb_invalidate_phys_addr input an AS
From: "Edgar E. Iglesias"
No functional change.
Signed-off-by: Edgar E. Iglesias
---
exec.c|3 ++-
include/exec/exec-all.h |2 +-
target-xtensa/op_helper.c |3 ++-
translate-all.c |4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 7e49e8e..98ca024 100644
--- a/exec.c
+++ b/exec.c
@@ -485,7 +485,8 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+tb_invalidate_phys_addr(&address_space_memory,
+phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ea90b64..b4dfc07 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -101,7 +101,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env,
uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
-tb_invalidate_phys_addr(paddr);
+tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index 105c25a..3cbe0d4 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1355,13 +1355,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
-mr = address_space_translate(&address_space_memory, addr, &addr, &l,
false);
+mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.7.10.4
[Qemu-devel] [PATCH v3 02/22] exec: Make iotlb_to_region input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|2 +-
exec.c |5 ++---
include/exec/exec-all.h |2 +-
include/exec/softmmu_template.h |5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 9270055..20dc88e 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -312,7 +312,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(pd);
+mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 98ca024..abc4f2f 100644
--- a/exec.c
+++ b/exec.c
@@ -1727,10 +1727,9 @@ static uint16_t dummy_section(PhysPageMap *map,
MemoryRegion *mr)
return phys_section_add(map, §ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
-return address_space_memory.dispatch->map.sections[
- index & ~TARGET_PAGE_MASK].mr;
+return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b4dfc07..6129365 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,7 +324,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see
[Qemu-devel] [PATCH v3 03/22] exec: Always initialize MemorySection address spaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index abc4f2f..c9724c0 100644
--- a/exec.c
+++ b/exec.c
@@ -879,6 +879,7 @@ static void register_subpage(AddressSpaceDispatch *d,
MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&d->map, &subsection));
@@ -1718,6 +1719,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr
base)
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
{
MemoryRegionSection section = {
+.address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.7.10.4
[Qemu-devel] [PATCH v3 04/22] exec: Make memory_region_section_get_iotlb use section AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index c9724c0..6def6b5 100644
--- a/exec.c
+++ b/exec.c
@@ -783,7 +783,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
-iotlb = section - address_space_memory.dispatch->map.sections;
+iotlb = section - section->address_space->dispatch->map.sections;
iotlb += xlat;
}
--
1.7.10.4
[Qemu-devel] [PATCH v3 05/22] memory: Add MemoryListener to typedefs.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |2 --
include/qemu/typedefs.h |1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 480dfbf..2d0b614 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -165,8 +165,6 @@ struct MemoryRegion {
NotifierList iommu_notify;
};
-typedef struct MemoryListener MemoryListener;
-
/**
* MemoryListener: callbacks structure for updates to the physical memory map
*
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index a4c1b84..425ca1a 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -24,6 +24,7 @@ typedef struct BusClass BusClass;
typedef struct AddressSpace AddressSpace;
typedef struct MemoryRegion MemoryRegion;
typedef struct MemoryRegionSection MemoryRegionSection;
+typedef struct MemoryListener MemoryListener;
typedef struct MemoryMappingList MemoryMappingList;
--
1.7.10.4
[Qemu-devel] [PATCH v3 07/22] exec: On AS changes, only flush affected CPU TLBs
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |5 +
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index dfad286..54aa790 100644
--- a/exec.c
+++ b/exec.c
@@ -1809,6 +1809,11 @@ static void tcg_commit(MemoryListener *listener)
CPU_FOREACH(cpu) {
CPUArchState *env = cpu->env_ptr;
+/* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+if (cpu->tcg_as_listener != listener) {
+continue;
+}
tlb_flush(env, 1);
}
}
--
1.7.10.4
[Qemu-devel] [PATCH v3 09/22] exec: Make ldq/ldub_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c| 22 +++
hw/alpha/typhoon.c|2 +-
hw/display/sm501.c|1 +
hw/display/sm501_template.h |2 +-
hw/net/vmware_utils.h |4 +-
hw/ppc/spapr_hcall.c | 11 ++--
hw/s390x/s390-virtio-bus.c|5 +-
hw/s390x/virtio-ccw.c | 18 +++---
hw/scsi/megasas.c |3 +-
hw/virtio/virtio.c|2 +-
include/exec/cpu-common.h |8 +--
monitor.c |2 +-
target-alpha/helper.c |7 ++-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c |3 +-
target-i386/arch_memory_mapping.c | 10 ++--
target-i386/helper.c | 20 +++
target-i386/smm_helper.c | 32 +-
target-i386/svm_helper.c | 117 +++--
target-ppc/mmu-hash64.h |7 ++-
target-s390x/helper.c |3 +-
target-s390x/mem_helper.c |3 +-
target-sparc/ldst_helper.c| 25
25 files changed, 185 insertions(+), 137 deletions(-)
diff --git a/exec.c b/exec.c
index 56e017f..2354bea 100644
--- a/exec.c
+++ b/exec.c
@@ -1593,7 +1593,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
-case 1: return ldub_phys(addr);
+case 1: return ldub_phys(&address_space_memory, addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
@@ -2398,7 +2398,7 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(hwaddr addr,
+static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2407,7 +2407,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
hwaddr l = 8;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2441,26 +2441,26 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
return val;
}
-uint64_t ldq_phys(hwaddr addr)
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(hwaddr addr)
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(hwaddr addr)
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(hwaddr addr)
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
uint8_t val;
-cpu_physical_memory_read(addr, &val, 1);
+address_space_rw(as, addr, &val, 1, 0);
return val;
}
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 71a5a37..67a1070 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -613,7 +613,7 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask,
IOMMUTLBEntry *ret)
translation, given the address of the PTE. */
static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
{
-uint64_t pte = ldq_phys(pte_addr);
+uint64_t pte = ldq_phys(&address_space_memory, pte_addr);
/* Check valid bit. */
if ((pte & 1) == 0) {
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c75d6ac..0b5f993 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
+#include "exec/address-spaces.h"
/*
* Status: 2010/05/07
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 2d4a3d8..d4cea9e 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -120,7 +120,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *
s, int crt,
/* get pixel value */
if (i % 4 == 0) {
-bitset = ldub_phys(cursor_addr);
+bitset = ldub_phys(&address_space_memory, cursor_addr);
cursor_addr++;
}
v = bitset & 3;
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index b465eb6..eb98d2a 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -65,7 +65,7 @@ vmw_shmem_set(hwaddr addr, uint8 val, int len)
static
[Qemu-devel] [PATCH v3 10/22] exec: Make lduw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 18 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/css.c |3 ++-
hw/s390x/virtio-ccw.c |8 +---
hw/virtio/virtio.c | 16
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c | 15 ---
target-sparc/ldst_helper.c |6 +++---
10 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index 2354bea..91d6377 100644
--- a/exec.c
+++ b/exec.c
@@ -1594,7 +1594,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
case 1: return ldub_phys(&address_space_memory, addr);
-case 2: return lduw_phys(addr);
+case 2: return lduw_phys(&address_space_memory, addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
@@ -2465,7 +2465,7 @@ uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(hwaddr addr,
+static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2474,7 +2474,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2508,19 +2508,19 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
return val;
}
-uint32_t lduw_phys(hwaddr addr)
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(hwaddr addr)
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(hwaddr addr)
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index eb98d2a..7877cb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -80,7 +80,7 @@ vmw_shmem_st8(hwaddr addr, uint8_t value)
static inline uint32_t
vmw_shmem_ld16(hwaddr addr)
{
-uint16_t res = lduw_le_phys(addr);
+uint16_t res = lduw_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 6e61a91..a2893ad 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -355,7 +355,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
}
/* FIXME: bounds check the address */
-size = lduw_be_phys(vpa + 0x4);
+size = lduw_be_phys(cs->as, vpa + 0x4);
if (size < VPA_MIN_SIZE) {
return H_PARAMETER;
@@ -544,7 +544,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
args[0] = ldub_phys(cs->as, addr);
return H_SUCCESS;
case 2:
-args[0] = lduw_phys(addr);
+args[0] = lduw_phys(cs->as, addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(cs->as, addr);
@@ -614,7 +614,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
tmp = ldub_phys(cs->as, src);
break;
case 1:
-tmp = lduw_phys(src);
+tmp = lduw_phys(cs->as, src);
break;
case 2:
tmp = ldl_phys(cs->as, src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 41b1903..d42d7ec 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -677,7 +677,8 @@ static void css_update_chnmon(SubchDev *sch)
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
-count = lduw_phys(channel_subsys->chnmon_area + offset);
+count = lduw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset);
count++;
stw_phys(channel_subsys->chnmon_area + offset, count);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index d301f00..50d852a 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -265,9 +265,11 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
info.queue = ldq_phys(&address_space_memory, ccw.cda);
[Qemu-devel] [PATCH v3 06/22] cpu: Add per-cpu address space
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpus.c |2 ++
cputlb.c|7 ---
exec.c | 27 +++
include/exec/exec-all.h |1 +
include/exec/softmmu_template.h |6 --
include/qom/cpu.h |3 +++
6 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/cpus.c b/cpus.c
index ca4c59f..945d85b 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1119,6 +1119,8 @@ void resume_all_vcpus(void)
static void qemu_tcg_init_vcpu(CPUState *cpu)
{
+tcg_cpu_address_space_init(cpu, cpu->as);
+
/* share a single thread for all cpus with TCG */
if (!tcg_cpu_thread) {
cpu->thread = g_malloc0(sizeof(QemuThread));
diff --git a/cputlb.c b/cputlb.c
index 20dc88e..b7d1a78 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -232,6 +232,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
uintptr_t addend;
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
+CPUState *cpu = ENV_GET_CPU(env);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -239,7 +240,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
-section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+section = address_space_translate_for_iotlb(cpu->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -304,6 +305,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
int mmu_idx, page_index, pd;
void *p;
MemoryRegion *mr;
+CPUState *cpu = ENV_GET_CPU(env1);
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = cpu_mmu_index(env1);
@@ -312,9 +314,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(&address_space_memory, pd);
+mr = iotlb_to_region(cpu->as, pd);
if (memory_region_is_unassigned(mr)) {
-CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->do_unassigned_access) {
diff --git a/exec.c b/exec.c
index 6def6b5..dfad286 100644
--- a/exec.c
+++ b/exec.c
@@ -137,6 +137,7 @@ typedef struct subpage_t {
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -435,6 +436,22 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+/* We only support one address space per cpu at the moment. */
+assert(cpu->as == as);
+
+if (cpu->tcg_as_listener) {
+memory_listener_unregister(cpu->tcg_as_listener);
+} else {
+cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+}
+cpu->tcg_as_listener->commit = tcg_commit;
+memory_listener_register(cpu->tcg_as_listener, as);
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -454,6 +471,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+cpu->as = &address_space_memory;
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -485,7 +503,7 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(&address_space_memory,
+tb_invalidate_phys_addr(cpu->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1811,10 +1829,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
-.commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1850,9 +1864,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
-if (tcg_enabled()) {
-memory_listener_register(&tcg_memory_listener, &address_space_memory);
-}
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6129365..f255afd 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,6 +95,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, tar
[Qemu-devel] [PATCH v3 08/22] exec: Make ldl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c|5 +-
exec.c| 19 ---
hw/dma/pl080.c|9 ++--
hw/dma/sun4m_iommu.c |3 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c | 13 +++--
hw/s390x/css.c|3 +-
hw/s390x/s390-virtio-bus.c|2 +-
hw/s390x/virtio-ccw.c |5 +-
hw/scsi/megasas.c |4 +-
hw/scsi/vmw_pvscsi.c |3 +-
hw/virtio/virtio.c|3 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h|2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c | 15 +++---
target-i386/arch_memory_mapping.c | 36 +++--
target-i386/helper.c |9 ++--
target-i386/seg_helper.c |6 ++-
target-i386/smm_helper.c | 103 +++--
target-i386/svm_helper.c | 28 +-
target-ppc/excp_helper.c |4 +-
target-ppc/mmu-hash32.h |6 ++-
target-s390x/cpu.c|2 +-
target-sparc/ldst_helper.c|8 +--
target-sparc/mmu_helper.c | 20 +++
target-unicore32/softmmu.c|5 +-
target-xtensa/helper.c|3 +-
30 files changed, 190 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a6c01f4..8943493 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -395,7 +395,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
-intno = ldl_phys(env->vm_vmcb + offsetof(struct
vmcb, control.int_vector));
+intno = ldl_phys(cpu->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing
virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index 54aa790..56e017f 100644
--- a/exec.c
+++ b/exec.c
@@ -1595,7 +1595,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
-case 4: return ldl_phys(addr);
+case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2340,7 +2340,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2349,8 +2349,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2383,19 +2382,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index cb7bda9..741dd20 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
-ch->src = ldl_le_phys(ch->lli);
-ch->dest = ldl_le_phys(ch->lli + 4);
-ch
[Qemu-devel] [PATCH v3 11/22] exec: Make stq_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 12 +++---
hw/alpha/dp264.c |5 ++-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 ++-
hw/s390x/s390-virtio-bus.c |3 +-
hw/s390x/virtio-ccw.c |4 +-
hw/scsi/megasas.c |3 +-
include/exec/cpu-common.h |6 +--
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |7 +--
target-alpha/translate.c |2 +-
target-i386/helper.c |3 +-
target-i386/smm_helper.c | 33 +++---
target-i386/svm_helper.c | 103 +++-
target-ppc/mmu-hash64.h|7 ++-
target-s390x/helper.c |8 +++-
target-s390x/mem_helper.c |3 +-
target-sparc/ldst_helper.c | 15 ---
18 files changed, 132 insertions(+), 92 deletions(-)
diff --git a/exec.c b/exec.c
index 91d6377..4267926 100644
--- a/exec.c
+++ b/exec.c
@@ -2674,22 +2674,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stq_phys(hwaddr addr, uint64_t val)
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_le_phys(hwaddr addr, uint64_t val)
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_be_phys(hwaddr addr, uint64_t val)
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
/* virtual memory access for debug (includes writing to ROM) */
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 20795ac..1351ba5 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
-stq_phys(param_offset + 0x100, initrd_base +
0xfc00ULL);
-stq_phys(param_offset + 0x108, initrd_size);
+stq_phys(&address_space_memory,
+ param_offset + 0x100, initrd_base +
0xfc00ULL);
+stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 7877cb6..4cf0e79 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
-stq_le_phys(addr, value);
+stq_le_phys(&address_space_memory, addr, value);
}
/* Macros for simplification of operations on array-style registers */
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index a2893ad..5ce43ab 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -559,6 +559,8 @@ static target_ulong h_logical_load(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
+CPUState *cs = CPU(cpu);
+
target_ulong size = args[0];
target_ulong addr = args[1];
target_ulong val = args[2];
@@ -574,7 +576,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
-stq_phys(addr, val);
+stq_phys(cs->as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -639,7 +641,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
-stq_phys(dst, tmp);
+stq_phys(cs->as, dst, tmp);
break;
}
dst = dst + step;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 83e7287..87a1591 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
-stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
+stq_be_phys(&address_space_memory,
+vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM,
virtio_queue_get_num(dev->vdev, i));
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 50d852a..20ad77e 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -873,7 +873,7 @@ static void virtio_ccw_notify(Device
[Qemu-devel] [PATCH v3 12/22] exec: Make stl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 19 +
hw/net/vmware_utils.h |2 +-
hw/pci/msi.c |2 +-
hw/pci/msix.c |2 +-
hw/ppc/ppc405_uc.c | 33 ---
hw/ppc/spapr_hcall.c |4 +-
hw/s390x/css.c |2 +-
hw/s390x/s390-virtio-bus.c |2 +-
hw/s390x/virtio-ccw.c |2 +-
hw/scsi/megasas.c |6 ++-
hw/scsi/vmw_pvscsi.c |3 +-
hw/sh4/r2d.c |2 +-
hw/timer/hpet.c|3 +-
hw/virtio/virtio.c |4 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h |2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |7 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c|3 +-
target-i386/seg_helper.c |8 ++--
target-i386/smm_helper.c | 100 ++--
target-i386/svm_helper.c | 28 -
target-ppc/mmu-hash32.h|6 ++-
target-sparc/ldst_helper.c |6 +--
25 files changed, 137 insertions(+), 119 deletions(-)
diff --git a/exec.c b/exec.c
index 4267926..cefd3be 100644
--- a/exec.c
+++ b/exec.c
@@ -1612,7 +1612,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stw_phys(addr, val);
break;
case 4:
-stl_phys(addr, val);
+stl_phys(&address_space_memory, addr, val);
break;
default: abort();
}
@@ -2555,7 +2555,8 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(hwaddr addr, uint32_t val,
+static inline void stl_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2563,7 +2564,7 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
@@ -2595,19 +2596,19 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stl_phys(hwaddr addr, uint32_t val)
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(hwaddr addr, uint32_t val)
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(hwaddr addr, uint32_t val)
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 4cf0e79..2ed73af 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -104,7 +104,7 @@ static inline void
vmw_shmem_st32(hwaddr addr, uint32_t value)
{
VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
-stl_le_phys(addr, value);
+stl_le_phys(&address_space_memory, addr, value);
}
static inline uint64_t
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 2a04d18..a4a3040 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
"notify vector 0x%x"
" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
vector, msg.address, msg.data);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
/* Normally called by pci_default_write_config(). */
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 3430770..5c49bfc 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
msg = msix_get_message(dev, vector);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
void msix_reset(PCIDevice *dev)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8109f92..47a4242 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -44,6 +44,7 @@
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
+CPUState *cs = ENV_GET_CPU(env);
ram_addr_t bdloc;
int i, n;
@@ -52,30 +53,30 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
bdloc = 0x0100UL - sizeof(struct ppc4xx_bd_info_t);
else
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
-stl_be_phys(bdloc
[Qemu-devel] [PATCH v3 15/22] exec: Make stb_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |6 +++---
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c | 10 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++-
hw/s390x/s390-virtio.c |2 +-
hw/scsi/megasas.c |6 --
include/exec/cpu-common.h |2 +-
target-i386/svm_helper.c |2 +-
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c |6 +++---
11 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/exec.c b/exec.c
index e399d18..99c8193 100644
--- a/exec.c
+++ b/exec.c
@@ -1606,7 +1606,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(&address_space_memory, addr, val);
break;
case 2:
stw_phys(&address_space_memory, addr, val);
@@ -2612,10 +2612,10 @@ void stl_be_phys(AddressSpace *as, hwaddr addr,
uint32_t val)
}
/* XXX: optimize */
-void stb_phys(hwaddr addr, uint32_t val)
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t v = val;
-cpu_physical_memory_write(addr, &v, 1);
+address_space_rw(as, addr, &v, 1, 1);
}
/* warning: addr must be aligned */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index d8f734f..1099df6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -74,7 +74,7 @@ static inline void
vmw_shmem_st8(hwaddr addr, uint8_t value)
{
VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
-stb_phys(addr, value);
+stb_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b0a59c3..ca520e8 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -63,27 +63,27 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
-stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
+stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
-stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
if (flags & 0x0001) {
for (i = 0; i < 6; i++)
-stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
+stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
n += 4;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index ebf09e9..3ffcc65 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -370,7 +370,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
-stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
@@ -567,7 +567,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(cs->as, addr, val);
return H_SUCCESS;
case 2:
stw_phys(cs->as, addr, val);
@@ -632,7 +632,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
}
switch (esize) {
case 0:
-stb_phys(dst, tmp);
+stb_phys(cs->as, dst, tmp);
break;
case 1:
stw_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 68f3e5a..e4fc353 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -359,15 +359,21 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_reset(dev->vdev);
/* Sync dev space */
-stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
+stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
-stb_phys(dev->dev_of
[Qemu-devel] [PATCH v3 13/22] exec: Make stl_phys_notdirty input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|4 ++--
hw/arm/boot.c |9 +
hw/arm/highbank.c |6 +++---
include/exec/cpu-common.h |2 +-
target-i386/helper.c | 16
target-sparc/mmu_helper.c |2 +-
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/exec.c b/exec.c
index cefd3be..a64577d 100644
--- a/exec.c
+++ b/exec.c
@@ -2526,14 +2526,14 @@ uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(hwaddr addr, uint32_t val)
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
io_mem_write(mr, addr1, val, 4);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 1c1b0e5..0e91a1a 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -16,6 +16,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#include "exec/address-spaces.h"
/* Kernel boot protocol is specified in the kernel docs
* Documentation/arm/Booting and Documentation/arm64/booting.txt
@@ -169,13 +170,13 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
-stl_phys_notdirty(info->smp_bootreg_addr, 0);
+stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
-#define WRITE_WORD(p, value) do { \
-stl_phys_notdirty(p, value); \
-p += 4; \
+#define WRITE_WORD(p, value) do {\
+stl_phys_notdirty(&address_space_memory, p, value); \
+p += 4; \
} while (0)
static void set_kernel_args(const struct arm_boot_info *info)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index d76a1d1..f66d57b 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -69,11 +69,11 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct
arm_boot_info *info)
switch (info->nb_cpus) {
case 4:
-stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
case 3:
-stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
case 2:
-stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
env->regs[15] = SMP_BOOT_ADDR;
break;
default:
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d005c98..525fb62 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,7 +102,7 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t
val);
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
-void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 0606908..55c0457 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -574,7 +574,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pml4e_addr, pml4e);
+stl_phys_notdirty(cs->as, pml4e_addr, pml4e);
}
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) <<
3)) &
@@ -591,7 +591,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pdpe_addr, pdpe);
+stl_phys_notdirty(cs->as, pdpe_addr, pdpe);
}
} else
#endif
@@ -661,7 +661,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
-stl_phys_notdirty(pde_addr, pde);
+stl_phys_notdirty(cs->as, pde_addr, pde);
}
/* align to page_size */
pt
[Qemu-devel] [PATCH v3 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 758f458..ee3c3c8 100644
--- a/exec.c
+++ b/exec.c
@@ -2711,11 +2711,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong
addr,
if (l > len)
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
-if (is_write)
-cpu_physical_memory_write_rom(&address_space_memory,
- phys_addr, buf, l);
-else
-cpu_physical_memory_rw(phys_addr, buf, l, is_write);
+if (is_write) {
+cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
+} else {
+address_space_rw(cpu->as, phys_addr, buf, l, 0);
+}
len -= l;
buf += l;
addr += l;
--
1.7.10.4
[Qemu-devel] [PATCH v3 20/22] cpu: Add address-space property
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
qom/cpu.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/qom/cpu.c b/qom/cpu.c
index 9d62479..fc6dbff 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -24,6 +24,7 @@
#include "qemu/notify.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
bool cpu_exists(int64_t id)
{
@@ -237,6 +238,11 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
+static Property cpu_properties[] = {
+DEFINE_PROP_ADDRESS_SPACE("address-space", CPUState, as),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -253,6 +259,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
+dc->props = cpu_properties;
dc->realize = cpu_common_realizefn;
/*
* Reason: CPUs still need special care by board code: wiring up
--
1.7.10.4
[Qemu-devel] [PATCH v3 16/22] exec: Make cpu_physical_memory_write_rom input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c| 15 ---
hw/core/loader.c |3 ++-
hw/intc/apic.c|3 ++-
hw/sparc/sun4m.c |3 ++-
include/exec/cpu-common.h |2 +-
5 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index 99c8193..758f458 100644
--- a/exec.c
+++ b/exec.c
@@ -2094,7 +2094,7 @@ enum write_rom_type {
FLUSH_CACHE,
};
-static inline void cpu_physical_memory_write_rom_internal(
+static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
{
hwaddr l;
@@ -2104,8 +2104,7 @@ static inline void cpu_physical_memory_write_rom_internal(
while (len > 0) {
l = len;
-mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2131,10 +2130,10 @@ static inline void
cpu_physical_memory_write_rom_internal(
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
-cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA);
+cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
}
void cpu_flush_icache_range(hwaddr start, int len)
@@ -2149,7 +2148,8 @@ void cpu_flush_icache_range(hwaddr start, int len)
return;
}
-cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE);
+cpu_physical_memory_write_rom_internal(&address_space_memory,
+ start, NULL, len, FLUSH_CACHE);
}
typedef struct {
@@ -2712,7 +2712,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
-cpu_physical_memory_write_rom(phys_addr, buf, l);
+cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 0634bee..e1c3f3a 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
-cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 3d3deb6..361ae90 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int
sync_type)
}
vapic_state.irr = vector & 0xff;
-cpu_physical_memory_write_rom(s->vapic_paddr + start,
+cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..2957d90 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
-cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d0fe123..a21b65a 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
void cpu_flush_icache_range(hwaddr start, int len);
--
1.7.10.4
[Qemu-devel] [PATCH v3 18/22] memory: Add address_space_find_by_name()
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |9 +
memory.c | 12
translate-all.c | 10 --
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 2d0b614..a673567 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1056,4 +1056,13 @@ void address_space_unmap(AddressSpace *as, void *buffer,
hwaddr len,
#endif
+/**
+ * address_space_find_by_name: Find an AddressSpace * by name
+ *
+ * Returns an AddressSpace * if found.
+ *
+ * @name: name of an address space too look for.
+ */
+AddressSpace *address_space_find_by_name(const char *name);
+
#endif
diff --git a/memory.c b/memory.c
index 7764314..4695879 100644
--- a/memory.c
+++ b/memory.c
@@ -1725,6 +1725,18 @@ void address_space_init(AddressSpace *as, MemoryRegion
*root, const char *name)
memory_region_transaction_commit();
}
+AddressSpace *address_space_find_by_name(const char *name)
+{
+AddressSpace *as;
+
+QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
+if (strcmp(as->name, name) == 0) {
+return as;
+}
+}
+return NULL;
+}
+
void address_space_destroy(AddressSpace *as)
{
/* Flush out anything from MemoryListeners listening in on this */
diff --git a/translate-all.c b/translate-all.c
index 3cbe0d4..ce55106 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -52,9 +52,8 @@
#include
#endif
#endif
-#else
-#include "exec/address-spaces.h"
#endif
+#include "exec/address-spaces.h"
#include "exec/cputlb.h"
#include "translate-all.h"
@@ -1563,6 +1562,13 @@ void cpu_interrupt(CPUState *cpu, int mask)
cpu->tcg_exit_req = 1;
}
+/* Find an address space by name in user emulation. */
+AddressSpace *address_space_find_by_name(const char *name)
+{
+/* Unsupported. */
+return NULL;
+}
+
/*
* Walks guest process memory "regions" one by one
* and calls callback function 'fn' for each region.
--
1.7.10.4
[Qemu-devel] [PATCH v3 19/22] qdev: Add qdev property type for AddressSpaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/core/qdev-properties-system.c | 10 +++
hw/core/qdev-properties.c| 54 ++
include/hw/qdev-properties.h |5
stubs/Makefile.objs |1 +
stubs/memory.c |6 +
5 files changed, 76 insertions(+)
create mode 100644 stubs/memory.c
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 729efa8..52fc4c2 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -369,6 +369,16 @@ void qdev_prop_set_netdev(DeviceState *dev, const char
*name,
assert_no_error(errp);
}
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value)
+{
+Error *errp = NULL;
+assert(!value || value->name);
+object_property_set_str(OBJECT(dev),
+value ? value->name : "", name, &errp);
+assert_no_error(errp);
+}
+
void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
{
qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index dc8ae69..a4f6a6b 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -1196,3 +1196,57 @@ PropertyInfo qdev_prop_size = {
.get = get_size,
.set = set_size,
};
+
+/* --- AddressSpace --- */
+
+static int parse_address_space(DeviceState *dev, const char *name,
+ AddressSpace **ptr)
+{
+AddressSpace *as = address_space_find_by_name(name);
+if (as == NULL) {
+return -ENOENT;
+}
+*ptr = as;
+return 0;
+}
+
+static void get_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+AddressSpace *as = qdev_get_prop_ptr(DEVICE(obj), opaque);
+char *p = (char *) (as ? as->name : "");
+
+visit_type_str(v, &p, name, errp);
+}
+
+static void set_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+Error *local_err = NULL;
+AddressSpace **as = qdev_get_prop_ptr(dev, prop);
+char *str;
+int ret;
+
+if (dev->realized) {
+qdev_prop_set_after_realize(dev, name, errp);
+return;
+}
+
+visit_type_str(v, &str, name, &local_err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+
+ret = parse_address_space(dev, str, as);
+error_set_from_qdev_prop_error(errp, ret, dev, prop, str);
+g_free(str);
+}
+
+PropertyInfo qdev_prop_address_space = {
+.name = "address_space",
+.get = get_address_space,
+.set = set_address_space,
+};
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 77c6f7c..020439f 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -19,6 +19,7 @@ extern PropertyInfo qdev_prop_size;
extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
+extern PropertyInfo qdev_prop_address_space;
extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
@@ -141,6 +142,8 @@ extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
+#define DEFINE_PROP_ADDRESS_SPACE(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_address_space, AddressSpace*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@@ -177,6 +180,8 @@ void qdev_prop_set_uint32(DeviceState *dev, const char
*name, uint32_t value);
void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value);
void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value);
void qdev_prop_set_string(DeviceState *dev, const char *name, const char
*value);
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value);
void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState
*value);
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState
*value);
int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState
*value) QEMU_WARN_UNUSED_RESULT;
diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs
index df92fe5..9e1e5da 100644
--- a/stubs/Makefile.objs
+++ b/stubs/Makefile.objs
@@ -26,4 +26,5 @@ stub-obj-y += uuid.o
stub-obj-y += vm-stop.o
stub-obj-y += vmstate.o
stub-obj-$(CONFIG_WIN32) += fd-register.o
+stub-obj-y += memory.o
stub-obj-y += cpus.o
diff --git a/stubs/memory.c b/stubs/memory.c
new file mode 100644
index 000..b3b4736
--- /dev/null
[Qemu-devel] [PATCH v3 21/22] petalogix-ml605: Create the CPU with object_new()
From: "Edgar E. Iglesias"
This is to allow future patches to set properties before cpu::realize().
Reviewed-by: Andreas Färber
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 10970e0..4009ff5 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -76,7 +76,7 @@ static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
-const char *cpu_model = args->cpu_model;
+Error *err = NULL;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
@@ -91,10 +91,13 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
-if (cpu_model == NULL) {
-cpu_model = "microblaze";
+cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err) {
+error_report("%s", error_get_pretty(err));
+exit(EXIT_FAILURE);
}
-cpu = cpu_mb_init(cpu_model);
+
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
--
1.7.10.4
[Qemu-devel] [PATCH v3 22/22] petalogix-ml605: Make the LMB visible only to the CPU
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 4009ff5..0a13b0e 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
+MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
+AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
qemu_irq irq[32], *cpu_irq;
+/* Setup the CPU specific address-space. */
+memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
+address_space_init(as_cpu, mr_cpu_root, "as/cpu");
+
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err) {
error_report("%s", error_get_pretty(err));
@@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
env = &cpu->env;
+/* Populate the CPU AS with the LMB only visible to the CPU. */
+memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
+ address_space_mem, 0,
+ memory_region_size(address_space_mem));
+memory_region_add_subregion(mr_cpu_root, 0x, sysmem_alias);
+
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
-memory_region_add_subregion(address_space_mem, 0x, phys_lmb_bram);
+memory_region_add_subregion_overlap(mr_cpu_root, 0x,
+phys_lmb_bram, 2);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
--
1.7.10.4
[Qemu-devel] [PATCH v3 14/22] exec: Make stw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 20 ++--
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c |2 +-
hw/ppc/spapr_hcall.c |4 ++--
hw/s390x/css.c |3 ++-
hw/s390x/s390-virtio-bus.c |8 +---
hw/s390x/virtio-ccw.c |3 ++-
hw/sh4/r2d.c |2 +-
hw/virtio/virtio.c | 10 ++
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c |4 ++--
target-s390x/mem_helper.c |3 ++-
target-sparc/ldst_helper.c |6 +++---
14 files changed, 46 insertions(+), 39 deletions(-)
diff --git a/exec.c b/exec.c
index a64577d..e399d18 100644
--- a/exec.c
+++ b/exec.c
@@ -1609,7 +1609,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stb_phys(addr, val);
break;
case 2:
-stw_phys(addr, val);
+stw_phys(&address_space_memory, addr, val);
break;
case 4:
stl_phys(&address_space_memory, addr, val);
@@ -2619,7 +2619,8 @@ void stb_phys(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(hwaddr addr, uint32_t val,
+static inline void stw_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2627,8 +2628,7 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@@ -2659,19 +2659,19 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stw_phys(hwaddr addr, uint32_t val)
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(hwaddr addr, uint32_t val)
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(hwaddr addr, uint32_t val)
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 2ed73af..d8f734f 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -89,7 +89,7 @@ static inline void
vmw_shmem_st16(hwaddr addr, uint16_t value)
{
VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
-stw_le_phys(addr, value);
+stw_le_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 47a4242..b0a59c3 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -65,7 +65,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
-stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f47c3ec..ebf09e9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(addr, val);
return H_SUCCESS;
case 2:
-stw_phys(addr, val);
+stw_phys(cs->as, addr, val);
return H_SUCCESS;
case 4:
stl_phys(cs->as, addr, val);
@@ -635,7 +635,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(dst, tmp);
break;
case 1:
-stw_phys(dst, tmp);
+stw_phys(cs->as, dst, tmp);
break;
case 2:
stl_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index cfa8a9b..75b04b4 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
count = lduw_phys(&address_space_memory,
channel_subsys->chnmon_area + offset);
count++;
-stw_phys(channel_subsys->chnmon_area + offset, count);
+stw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset, coun
[Qemu-devel] [RFC 0/2] Break the debug session on sw errors
From: "Edgar E. Iglesias" Hi, I've been using variations of this scheme to aid with debugging guest errors that QEMU can detect. I'm posting this RFC to see if there is interest to get something like this upstreamed. Patch 1 adds the mechanism to break the debugger session from within emulation models. Patch 2 hardcodes the interruption of the GDB session on log_guest_error calls to qemu_log_mask. Some possible ways to conditionalize the behaviour could be through cmdline options or through GDB remote commands. Any thoughts/ideas on this? Cheers, Edgar Edgar E. Iglesias (2): gdbstub: Add gdbserver_break() qemu-log: Interrupt the GDB session on guest-errors gdbstub.c | 68 ++-- include/exec/gdbstub.h |2 ++ qemu-log.c | 20 ++ 3 files changed, 76 insertions(+), 14 deletions(-) -- 1.7.10.4
[Qemu-devel] [RFC 1/2] gdbstub: Add gdbserver_break()
From: "Edgar E. Iglesias"
Makes it possible to request interruption of the GDB
debug session.
Signed-off-by: Edgar E. Iglesias
---
gdbstub.c | 68 ++--
include/exec/gdbstub.h |2 ++
2 files changed, 56 insertions(+), 14 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index e80e1d3..84232f6 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -297,6 +297,7 @@ typedef struct GDBState {
uint8_t last_packet[MAX_PACKET_LENGTH + 4];
int last_packet_len;
int signal;
+int client_connected;
#ifdef CONFIG_USER_ONLY
int fd;
int running_state;
@@ -2505,12 +2506,56 @@ static int gdb_handle_packet(GDBState *s, const char
*line_buf)
return RS_IDLE;
}
+static void gdb_output(GDBState *s, const char *msg, int len)
+{
+char buf[MAX_PACKET_LENGTH];
+
+buf[0] = 'O';
+if (len > (MAX_PACKET_LENGTH/2) - 1) {
+len = (MAX_PACKET_LENGTH/2) - 1;
+}
+memtohex(buf + 1, (uint8_t *)msg, len);
+put_packet(s, buf);
+}
+
void gdb_set_stop_cpu(CPUArchState *env)
{
gdbserver_state->c_cpu = env;
gdbserver_state->g_cpu = env;
}
+static int gdbserver_has_client(void)
+{
+return gdbserver_state && gdbserver_state->client_connected;
+}
+
+int gdbserver_break(const char *msg)
+{
+
+if (!gdbserver_has_client()) {
+return 1;
+}
+
+if (msg) {
+gdb_output(gdbserver_state, msg, strlen(msg));
+}
+
+/* If there's a CPU running, break it's execution. */
+if (cpu_single_env) {
+CPUState *cpu = ENV_GET_CPU(cpu_single_env);
+cpu_single_env->exception_index = EXCP_DEBUG;
+if (cpu->current_tb) {
+/* Break out of current TB and request debug action. */
+cpu_loop_exit(cpu_single_env);
+}
+}
+#ifndef CONFIG_USER_ONLY
+/* Request global debug action. */
+qemu_system_debug_request();
+#endif
+return 0;
+}
+
#ifndef CONFIG_USER_ONLY
static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
@@ -2815,6 +2860,7 @@ gdb_handlesig (CPUArchState *env, int sig)
{
/* XXX: Connection closed. Should probably wait for another
connection before continuing. */
+ s->client_connected = false;
return sig;
}
}
@@ -2868,7 +2914,7 @@ static void gdb_accept(void)
gdb_has_xml = 0;
gdbserver_state = s;
-
+s->client_connected = true;
fcntl(fd, F_SETFL, O_NONBLOCK);
}
@@ -2952,23 +2998,17 @@ static void gdb_chr_event(void *opaque, int event)
case CHR_EVENT_OPENED:
vm_stop(RUN_STATE_PAUSED);
gdb_has_xml = 0;
+gdbserver_state->client_connected = true;
break;
+case CHR_EVENT_CLOSED: {
+gdbserver_state->client_connected = false;
+break;
+}
default:
break;
}
}
-static void gdb_monitor_output(GDBState *s, const char *msg, int len)
-{
-char buf[MAX_PACKET_LENGTH];
-
-buf[0] = 'O';
-if (len > (MAX_PACKET_LENGTH/2) - 1)
-len = (MAX_PACKET_LENGTH/2) - 1;
-memtohex(buf + 1, (uint8_t *)msg, len);
-put_packet(s, buf);
-}
-
static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
{
const char *p = (const char *)buf;
@@ -2977,10 +3017,10 @@ static int gdb_monitor_write(CharDriverState *chr,
const uint8_t *buf, int len)
max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
for (;;) {
if (len <= max_sz) {
-gdb_monitor_output(gdbserver_state, p, len);
+gdb_output(gdbserver_state, p, len);
break;
}
-gdb_monitor_output(gdbserver_state, p, max_sz);
+gdb_output(gdbserver_state, p, max_sz);
p += max_sz;
len -= max_sz;
}
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index ba20afa..6f29d2a 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -47,6 +47,8 @@ int gdbserver_start(int);
int gdbserver_start(const char *port);
#endif
+int gdbserver_break(const char *msg);
+
/* in gdbstub-xml.c, generated by scripts/feature_to_c.sh */
extern const char *const xml_builtin[][2];
--
1.7.10.4
[Qemu-devel] [RFC 2/2] qemu-log: Interrupt the GDB session on guest-errors
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
qemu-log.c | 20
1 file changed, 20 insertions(+)
diff --git a/qemu-log.c b/qemu-log.c
index 797f2af..693bc94 100644
--- a/qemu-log.c
+++ b/qemu-log.c
@@ -19,6 +19,7 @@
#include "qemu-common.h"
#include "qemu/log.h"
+#include "exec/gdbstub.h"
static char *logfilename;
FILE *qemu_logfile;
@@ -45,6 +46,25 @@ void qemu_log_mask(int mask, const char *fmt, ...)
vfprintf(qemu_logfile, fmt, ap);
}
va_end(ap);
+
+/*
+ * Break the GDB session (if connected) so that the user can inspect the
+ * guest state.
+ *
+ * TODO: Consider conditionalizing this on a cmdline option.
+ */
+if (mask & LOG_GUEST_ERROR) {
+char *msg;
+
+va_start(ap, fmt);
+if (vasprintf(&msg, fmt, ap) < 0) {
+msg = NULL;
+}
+va_end(ap);
+
+gdbserver_break(msg);
+g_free(msg);
+}
}
/* enable or disable low levels log */
--
1.7.10.4
[Qemu-devel] [PATCH] qom/cpu: Remove cpu->exit_request from reset state
From: "Edgar E. Iglesias" cpu->exit_request is part of the execution environment and should not be cleared when a CPU resets. Otherwise, we might deadlock QEMU if a CPU resets while there is I/O going on. Signed-off-by: Edgar E. Iglesias --- qom/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/qom/cpu.c b/qom/cpu.c index 9d62479..40d82dd 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -195,7 +195,6 @@ static void cpu_common_reset(CPUState *cpu) log_cpu_state(cpu, cc->reset_dump_flags); } -cpu->exit_request = 0; cpu->interrupt_request = 0; cpu->current_tb = NULL; cpu->halted = 0; -- 1.8.1.2
[Qemu-devel] [PATCH 1/6] cris: Add a CRISv32 default "any" CPU for user mode emulation
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-cris/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 44301a4..21f1860 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -239,7 +239,14 @@ static const TypeInfo cris_cpu_model_type_infos[] = {
.name = TYPE("crisv32"),
.parent = TYPE_CRIS_CPU,
.class_init = crisv32_cpu_class_init,
+},
+#if defined(CONFIG_USER_ONLY)
+{
+.name = TYPE("any"),
+.parent = TYPE_CRIS_CPU,
+.class_init = crisv32_cpu_class_init,
}
+#endif
};
#undef TYPE
--
1.8.3.2
[Qemu-devel] [PATCH 0/6] CRIS queue
From: "Edgar E. Iglesias" These fixes and cleanups are sitting on my CRIS queue. Restores CRISv32 as default linux-user CPU. Fix CRIS linux-user signal handling. Removes CRIS PIC glue. Cheers, Edgar Edgar E. Iglesias (5): cris: Add a CRISv32 default "any" CPU for user mode emulation cris: Abort when a v10 takes interrupts while in a delayslot cris: Add interrupt signals to the CPU device axis-dev88: Connect the PIC upstream IRQs directly to the CPU cris: Remove the CRIS PIC glue Stefan Weil (1): linux-user: Fix trampoline code for CRIS hw/cris/Makefile.objs | 1 - hw/cris/axis_dev88.c | 7 +++ hw/cris/pic_cpu.c | 47 --- include/hw/cris/etraxfs.h | 2 -- linux-user/signal.c | 8 target-cris/cpu.c | 27 +++ target-cris/cpu.h | 4 target-cris/helper.c | 5 + 8 files changed, 43 insertions(+), 58 deletions(-) delete mode 100644 hw/cris/pic_cpu.c -- 1.8.3.2
[Qemu-devel] [PATCH 2/6] cris: Abort when a v10 takes interrupts while in a delayslot
From: "Edgar E. Iglesias"
This is an internal error as the CRISv10 should mask interrupts
while executing delay slots. Bail out sooner rather than later.
Signed-off-by: Edgar E. Iglesias
---
target-cris/helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index d274b38..c940582 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -126,6 +126,11 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
env->exception_index,
cs->interrupt_request);
+if (env->dslot) {
+/* CRISv10 never takes interrupts while in a delay-slot. */
+cpu_abort(env, "CRIS: Interrupt on delay-slot\n");
+}
+
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (env->exception_index) {
case EXCP_BREAK:
--
1.8.3.2
[Qemu-devel] [PATCH 3/6] cris: Add interrupt signals to the CPU device
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-cris/cpu.c | 20
target-cris/cpu.h | 4
2 files changed, 24 insertions(+)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 21f1860..7dea0f0 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -146,6 +146,21 @@ static void cris_cpu_realizefn(DeviceState *dev, Error
**errp)
ccc->parent_realize(dev, errp);
}
+#ifndef CONFIG_USER_ONLY
+static void cris_cpu_set_irq(void *opaque, int irq, int level)
+{
+CRISCPU *cpu = opaque;
+CPUState *cs = CPU(cpu);
+int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
+
+if (level) {
+cpu_interrupt(cs, type);
+} else {
+cpu_reset_interrupt(cs, type);
+}
+}
+#endif
+
static void cris_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
@@ -159,6 +174,11 @@ static void cris_cpu_initfn(Object *obj)
env->pregs[PR_VR] = ccc->vr;
+#ifndef CONFIG_USER_ONLY
+/* IRQ and NMI lines. */
+qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
+#endif
+
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = true;
if (env->pregs[PR_VR] < 32) {
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 4b9fc4c..1d7d80d 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -42,6 +42,10 @@
/* CRIS-specific interrupt pending bits. */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
+/* CRUS CPU device objects interrupt lines. */
+#define CRIS_CPU_IRQ 0
+#define CRIS_CPU_NMI 1
+
/* Register aliases. R0 - R15 */
#define R_FP 8
#define R_SP 14
--
1.8.3.2
[Qemu-devel] [PATCH 5/6] cris: Remove the CRIS PIC glue
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/cris/Makefile.objs | 1 -
hw/cris/pic_cpu.c | 47 ---
include/hw/cris/etraxfs.h | 2 --
3 files changed, 50 deletions(-)
delete mode 100644 hw/cris/pic_cpu.c
diff --git a/hw/cris/Makefile.objs b/hw/cris/Makefile.objs
index 776db7c..7624173 100644
--- a/hw/cris/Makefile.objs
+++ b/hw/cris/Makefile.objs
@@ -1,3 +1,2 @@
-obj-y += pic_cpu.o
obj-y += boot.o
obj-y += axis_dev88.o
diff --git a/hw/cris/pic_cpu.c b/hw/cris/pic_cpu.c
deleted file mode 100644
index bd47bf1..000
--- a/hw/cris/pic_cpu.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * QEMU CRIS CPU interrupt wrapper logic.
- *
- * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "hw/sysbus.h"
-#include "hw/hw.h"
-#include "hw/cris/etraxfs.h"
-
-#define D(x)
-
-static void cris_pic_cpu_handler(void *opaque, int irq, int level)
-{
-CRISCPU *cpu = opaque;
-CPUState *cs = CPU(cpu);
-int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
-
-if (level) {
-cpu_interrupt(cs, type);
-} else {
-cpu_reset_interrupt(cs, type);
-}
-}
-
-qemu_irq *cris_pic_init_cpu(CPUCRISState *env)
-{
-return qemu_allocate_irqs(cris_pic_cpu_handler, cris_env_get_cpu(env), 2);
-}
diff --git a/include/hw/cris/etraxfs.h b/include/hw/cris/etraxfs.h
index ab30559..73a6134 100644
--- a/include/hw/cris/etraxfs.h
+++ b/include/hw/cris/etraxfs.h
@@ -28,8 +28,6 @@
#include "net/net.h"
#include "hw/cris/etraxfs_dma.h"
-qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
-
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
--
1.8.3.2
[Qemu-devel] [PATCH 4/6] axis-dev88: Connect the PIC upstream IRQs directly to the CPU
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/cris/axis_dev88.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c
index 5524088..645e45c 100644
--- a/hw/cris/axis_dev88.c
+++ b/hw/cris/axis_dev88.c
@@ -254,7 +254,7 @@ void axisdev88_init(QEMUMachineInitArgs *args)
DeviceState *dev;
SysBusDevice *s;
DriveInfo *nand;
-qemu_irq irq[30], nmi[2], *cpu_irq;
+qemu_irq irq[30], nmi[2];
void *etraxfs_dmac;
struct etraxfs_dma_client *dma_eth;
int i;
@@ -296,15 +296,14 @@ void axisdev88_init(QEMUMachineInitArgs *args)
&gpio_state.iomem);
-cpu_irq = cris_pic_init_cpu(env);
dev = qdev_create(NULL, "etraxfs,pic");
/* FIXME: Is there a proper way to signal vectors to the CPU core? */
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0x3001c000);
-sysbus_connect_irq(s, 0, cpu_irq[0]);
-sysbus_connect_irq(s, 1, cpu_irq[1]);
+sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
+sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
for (i = 0; i < 30; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
--
1.8.3.2
[Qemu-devel] [PATCH 6/6] linux-user: Fix trampoline code for CRIS
From: Stefan Weil
__put_user can write bytes, words (2 bytes) or longwords (4 bytes).
Here obviously words should have been written, but bytes were written,
so values like 0x9c5f were truncated to 0x5f.
Fix this by changing retcode from uint8_t to to uint16_t in
target_signal_frame and also in the unused rt_signal_frame.
This problem was reported by static code analysis (smatch).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Stefan Weil
Reviewed-by: Peter Maydell
Tested-by: Edgar E. Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
linux-user/signal.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 01d7c39..82e8592 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -3659,7 +3659,7 @@ struct target_sigcontext {
struct target_signal_frame {
struct target_sigcontext sc;
uint32_t extramask[TARGET_NSIG_WORDS - 1];
-uint8_t retcode[8]; /* Trampoline code. */
+uint16_t retcode[4]; /* Trampoline code. */
};
struct rt_signal_frame {
@@ -3667,7 +3667,7 @@ struct rt_signal_frame {
void *puc;
siginfo_t info;
struct ucontext uc;
-uint8_t retcode[8]; /* Trampoline code. */
+uint16_t retcode[4]; /* Trampoline code. */
};
static void setup_sigcontext(struct target_sigcontext *sc, CPUCRISState *env)
@@ -3745,8 +3745,8 @@ static void setup_frame(int sig, struct target_sigaction
*ka,
*/
err |= __put_user(0x9c5f, frame->retcode+0);
err |= __put_user(TARGET_NR_sigreturn,
- frame->retcode+2);
- err |= __put_user(0xe93d, frame->retcode+4);
+ frame->retcode + 1);
+ err |= __put_user(0xe93d, frame->retcode + 2);
/* Save the mask. */
err |= __put_user(set->sig[0], &frame->sc.oldmask);
--
1.8.3.2
[Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS
From: "Edgar E. Iglesias"
No functional change.
Signed-off-by: Edgar E. Iglesias
---
exec.c|3 ++-
include/exec/exec-all.h |2 +-
target-xtensa/op_helper.c |3 ++-
translate-all.c |4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 00526d1..7ed34e2 100644
--- a/exec.c
+++ b/exec.c
@@ -484,7 +484,8 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+tb_invalidate_phys_addr(&address_space_memory,
+phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ea90b64..b4dfc07 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -101,7 +101,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env,
uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
-tb_invalidate_phys_addr(paddr);
+tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index 1c63d78..2ff8781 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1356,13 +1356,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
-mr = address_space_translate(&address_space_memory, addr, &addr, &l,
false);
+mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.7.10.4
[Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces
From: "Edgar E. Iglesias" Hi, I'm looking at modeling systems where multiple CPUs co-exist with different views of their attached buses/devs. With this series I'm trying to take some steps towards having an address-space per CPU. It's not complete but good enough for making it possible to model (to some extent) CPU local memories for MicroBlaze systems in emulation mode (tcg). I'm updating the petalogix-ml605 here and will follow-up later with the petalogix-s3adsp. There is lots of future work needed, for example to transform more of the cpu_* bus accessing functions. To add more usage of AddressSpace properties to pass on address spaces to DMA models. Qtest mechanisms to target specific address spaces, etc... Cheers, Edgar Edgar E. Iglesias (22): exec: Make tb_invalidate_phys_addr input an AS exec: Make iotlb_to_region input an AS exec: Always initialize MemorySection address spaces exec: Make memory_region_section_get_iotlb use section AS memory: Add MemoryListener to typedefs.h memory: Add address_space_find_by_name() qdev: Add qdev property type for AddressSpaces cpu: Add per-cpu address space target-microblaze: Add address-space property exec: On AS changes, only flush affected CPU TLBs exec: Make ldl_*_phys input an AddressSpace exec: Make ldq/ldub_*_phys input an AddressSpace exec: Make lduw_*_phys input an AddressSpace exec: Make stq_*_phys input an AddressSpace exec: Make stl_*_phys input an AddressSpace exec: Make stl_phys_notdirty input an AddressSpace exec: Make stw_*_phys input an AddressSpace exec: Make stb_phys input an AddressSpace exec: Make cpu_physical_memory_write_rom input an AS exec: Make cpu_memory_rw_debug use the CPUs AS petalogix-ml605: Create the CPU with object_new() petalogix-ml605: Make the LMB visible only to the CPU cpu-exec.c |5 +- cputlb.c|4 +- exec.c | 176 - hw/alpha/dp264.c|5 +- hw/alpha/typhoon.c |2 +- hw/arm/boot.c |9 +- hw/arm/highbank.c |6 +- hw/core/loader.c|3 +- hw/core/qdev-properties-system.c| 46 ++ hw/display/sm501.c |1 + hw/display/sm501_template.h |2 +- hw/dma/pl080.c |9 +- hw/dma/sun4m_iommu.c|3 +- hw/intc/apic.c |3 +- hw/microblaze/petalogix_ml605_mmu.c | 28 +++- hw/net/vmware_utils.h | 16 +- hw/pci/msi.c|2 +- hw/pci/msix.c |2 +- hw/ppc/ppc405_uc.c | 44 +++--- hw/ppc/spapr_hcall.c| 42 ++--- hw/s390x/css.c | 11 +- hw/s390x/s390-virtio-bus.c | 36 +++-- hw/s390x/s390-virtio.c |2 +- hw/s390x/virtio-ccw.c | 40 +++-- hw/scsi/megasas.c | 22 ++- hw/scsi/vmw_pvscsi.c|6 +- hw/sh4/r2d.c|4 +- hw/sparc/sun4m.c|3 +- hw/timer/hpet.c |3 +- hw/virtio/virtio.c | 31 ++-- include/exec/cpu-common.h | 44 +++--- include/exec/cpu-defs.h |3 + include/exec/exec-all.h |5 +- include/exec/memory.h | 10 +- include/exec/softmmu_template.h |5 +- include/hw/ppc/spapr.h |4 +- include/hw/qdev-properties.h|5 + include/qemu/typedefs.h |1 + include/qom/cpu.h |2 + memory.c| 12 ++ monitor.c |2 +- target-alpha/helper.c |6 +- target-alpha/helper.h |8 +- target-alpha/mem_helper.c | 28 ++-- target-alpha/translate.c|8 +- target-arm/helper.c | 16 +- target-i386/arch_memory_mapping.c | 46 +++--- target-i386/helper.c| 47 +++--- target-i386/seg_helper.c| 12 +- target-i386/smm_helper.c| 298 ++- target-i386/svm_helper.c| 291 -- target-microblaze/cpu.c | 14 ++ target-ppc/excp_helper.c|2 +- target-ppc/mmu-hash32.h |8 +- target-ppc/mmu-hash64.h | 10 +- target-s390x/cpu.c |2 +- target-s390x/helper.c |8 +- target-s390x/mem_helper.c |6 +- target-sparc/ldst_helper.c | 68 target-sparc/mmu_helper.c | 20 +-- target-unicore32/softmmu.c |4 +- target-xtensa/helper.c |2 +- target-xtensa/op_helper.c |3 +- translate-all.c |4 +- 64 files changed, 906 insertions(+), 6
[Qemu-devel] [PATCH v1 02/22] exec: Make iotlb_to_region input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|2 +-
exec.c |5 ++---
include/exec/exec-all.h |2 +-
include/exec/softmmu_template.h |5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index fff0afb..0399172 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(pd);
+mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 7ed34e2..c34f642 100644
--- a/exec.c
+++ b/exec.c
@@ -1726,10 +1726,9 @@ static uint16_t dummy_section(PhysPageMap *map,
MemoryRegion *mr)
return phys_section_add(map, §ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
-return address_space_memory.dispatch->map.sections[
- index & ~TARGET_PAGE_MASK].mr;
+return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b4dfc07..6129365 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,7 +324,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see
[Qemu-devel] [PATCH v1 03/22] exec: Always initialize MemorySection address spaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index c34f642..6d88931 100644
--- a/exec.c
+++ b/exec.c
@@ -878,6 +878,7 @@ static void register_subpage(AddressSpaceDispatch *d,
MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&d->map, &subsection));
@@ -1717,6 +1718,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr
base)
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
{
MemoryRegionSection section = {
+.address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.7.10.4
[Qemu-devel] [PATCH v1 04/22] exec: Make memory_region_section_get_iotlb use section AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 6d88931..803bbde 100644
--- a/exec.c
+++ b/exec.c
@@ -782,7 +782,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
-iotlb = section - address_space_memory.dispatch->map.sections;
+iotlb = section - section->address_space->dispatch->map.sections;
iotlb += xlat;
}
--
1.7.10.4
[Qemu-devel] [PATCH v1 05/22] memory: Add MemoryListener to typedefs.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |2 --
include/qemu/typedefs.h |1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 480dfbf..2d0b614 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -165,8 +165,6 @@ struct MemoryRegion {
NotifierList iommu_notify;
};
-typedef struct MemoryListener MemoryListener;
-
/**
* MemoryListener: callbacks structure for updates to the physical memory map
*
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index a4c1b84..425ca1a 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -24,6 +24,7 @@ typedef struct BusClass BusClass;
typedef struct AddressSpace AddressSpace;
typedef struct MemoryRegion MemoryRegion;
typedef struct MemoryRegionSection MemoryRegionSection;
+typedef struct MemoryListener MemoryListener;
typedef struct MemoryMappingList MemoryMappingList;
--
1.7.10.4
[Qemu-devel] [PATCH v1 07/22] qdev: Add qdev property type for AddressSpaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/core/qdev-properties-system.c | 46 ++
include/hw/qdev-properties.h |5 +
2 files changed, 51 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 729efa8..f78bd50 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -170,6 +170,42 @@ PropertyInfo qdev_prop_chr = {
.release = release_chr,
};
+/* --- AddressSpace --- */
+
+static int parse_address_space(DeviceState *dev, const char *name, void **ptr)
+{
+AddressSpace *as = address_space_find_by_name(name);
+if (as == NULL) {
+return -ENOENT;
+}
+*ptr = as;
+return 0;
+}
+
+static const char *print_address_space(void *ptr)
+{
+AddressSpace *as = ptr;
+return as->name;
+}
+
+static void get_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+get_pointer(obj, v, opaque, print_address_space, name, errp);
+}
+
+static void set_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+set_pointer(obj, v, opaque, parse_address_space, name, errp);
+}
+
+PropertyInfo qdev_prop_address_space = {
+.name = "address_space",
+.get = get_address_space,
+.set = set_address_space,
+};
+
/* --- netdev device --- */
static int parse_netdev(DeviceState *dev, const char *str, void **ptr)
@@ -369,6 +405,16 @@ void qdev_prop_set_netdev(DeviceState *dev, const char
*name,
assert_no_error(errp);
}
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value)
+{
+Error *errp = NULL;
+assert(!value || value->name);
+object_property_set_str(OBJECT(dev),
+value ? value->name : "", name, &errp);
+assert_no_error(errp);
+}
+
void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
{
qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 692f82e..0e1076d 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -19,6 +19,7 @@ extern PropertyInfo qdev_prop_size;
extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
+extern PropertyInfo qdev_prop_address_space;
extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
@@ -124,6 +125,8 @@ extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
+#define DEFINE_PROP_ADDRESS_SPACE(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_address_space, AddressSpace*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@@ -160,6 +163,8 @@ void qdev_prop_set_uint32(DeviceState *dev, const char
*name, uint32_t value);
void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value);
void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value);
void qdev_prop_set_string(DeviceState *dev, const char *name, const char
*value);
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value);
void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState
*value);
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState
*value);
int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState
*value) QEMU_WARN_UNUSED_RESULT;
--
1.7.10.4
[Qemu-devel] [PATCH v1 06/22] memory: Add address_space_find_by_name()
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |8
memory.c | 12
2 files changed, 20 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 2d0b614..02f4012 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -941,6 +941,14 @@ void mtree_info(fprintf_function mon_printf, void *f);
*/
void address_space_init(AddressSpace *as, MemoryRegion *root, const char
*name);
+/**
+ * address_space_find_by_name: Find an AddressSpace * by name
+ *
+ * Returns an AddressSpace * if found.
+ *
+ * @name: name of an address space too look for.
+ */
+AddressSpace *address_space_find_by_name(const char *name);
/**
* address_space_destroy: destroy an address space
diff --git a/memory.c b/memory.c
index 7764314..4695879 100644
--- a/memory.c
+++ b/memory.c
@@ -1725,6 +1725,18 @@ void address_space_init(AddressSpace *as, MemoryRegion
*root, const char *name)
memory_region_transaction_commit();
}
+AddressSpace *address_space_find_by_name(const char *name)
+{
+AddressSpace *as;
+
+QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
+if (strcmp(as->name, name) == 0) {
+return as;
+}
+}
+return NULL;
+}
+
void address_space_destroy(AddressSpace *as)
{
/* Flush out anything from MemoryListeners listening in on this */
--
1.7.10.4
[Qemu-devel] [PATCH v1 09/22] target-microblaze: Add address-space property
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0ef9aa4..ada9556 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -88,11 +88,22 @@ static void mb_cpu_reset(CPUState *s)
#endif
}
+static void mb_cpu_setup_as(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+CPUMBState *env = &cpu->env;
+
+cpu_address_space_init(cs, env->as);
+#endif
+}
+
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+mb_cpu_setup_as(cs);
cpu_reset(cs);
qemu_init_vcpu(cs);
@@ -123,6 +134,9 @@ static const VMStateDescription vmstate_mb_cpu = {
};
static Property mb_properties[] = {
+#ifndef CONFIG_USER_ONLY
+DEFINE_PROP_ADDRESS_SPACE("address-space", MicroBlazeCPU, env.as),
+#endif
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
1.7.10.4
[Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|4 ++--
exec.c | 31 +++
include/exec/cpu-defs.h |3 +++
include/exec/exec-all.h |1 +
include/exec/softmmu_template.h |4 ++--
include/qom/cpu.h |2 ++
6 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 0399172..a2264a3 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -254,7 +254,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
-section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+section = address_space_translate_for_iotlb(env->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(&address_space_memory, pd);
+mr = iotlb_to_region(env1->as, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 803bbde..edb6a43 100644
--- a/exec.c
+++ b/exec.c
@@ -136,6 +136,7 @@ typedef struct subpage_t {
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -434,6 +435,25 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+CPUArchState *env = cpu->env_ptr;
+
+if (tcg_enabled()) {
+if (cpu->tcg_as_listener) {
+memory_listener_unregister(cpu->tcg_as_listener);
+} else {
+cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+}
+cpu->tcg_as_listener->commit = tcg_commit;
+memory_listener_register(cpu->tcg_as_listener, as);
+}
+
+env->as = as;
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -453,6 +473,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+cpu_address_space_init(cpu, &address_space_memory);
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -482,9 +503,10 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
#else
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
+CPUArchState *env = cpu->env_ptr;
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(&address_space_memory,
+tb_invalidate_phys_addr(env->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1810,10 +1832,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
-.commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1849,9 +1867,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
-if (tcg_enabled()) {
-memory_listener_register(&tcg_memory_listener, &address_space_memory);
-}
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 01cd8c7..406b36c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -176,6 +176,9 @@ typedef struct CPUWatchpoint {
sigjmp_buf jmp_env; \
int exception_index;\
\
+/* Per CPU address-space. */ \
+AddressSpace *as; \
+\
/* user data */ \
void *opaque; \
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6129365..61770ee 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,6 +95,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArc
[Qemu-devel] [PATCH v1 12/22] exec: Make ldq/ldub_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c| 22
hw/alpha/typhoon.c|2 +-
hw/display/sm501.c|1 +
hw/display/sm501_template.h |2 +-
hw/net/vmware_utils.h |4 +-
hw/ppc/spapr_hcall.c | 10 ++--
hw/s390x/s390-virtio-bus.c|5 +-
hw/s390x/virtio-ccw.c | 18 +++---
hw/scsi/megasas.c |3 +-
hw/virtio/virtio.c|2 +-
include/exec/cpu-common.h |8 +--
monitor.c |2 +-
target-alpha/helper.c |6 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |8 +--
target-alpha/translate.c |2 +-
target-arm/helper.c |2 +-
target-i386/arch_memory_mapping.c | 10 ++--
target-i386/helper.c | 20 +++
target-i386/smm_helper.c | 32 +--
target-i386/svm_helper.c | 112 ++---
target-ppc/mmu-hash64.h |5 +-
target-s390x/helper.c |2 +-
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c| 24
25 files changed, 169 insertions(+), 137 deletions(-)
diff --git a/exec.c b/exec.c
index 0e898bb..db64e13 100644
--- a/exec.c
+++ b/exec.c
@@ -1596,7 +1596,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
-case 1: return ldub_phys(addr);
+case 1: return ldub_phys(&address_space_memory, addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
@@ -2368,7 +2368,7 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(hwaddr addr,
+static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2377,7 +2377,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
hwaddr l = 8;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2411,26 +2411,26 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
return val;
}
-uint64_t ldq_phys(hwaddr addr)
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(hwaddr addr)
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(hwaddr addr)
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(hwaddr addr)
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
uint8_t val;
-cpu_physical_memory_read(addr, &val, 1);
+address_space_rw(as, addr, &val, 1, 0);
return val;
}
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 59e1bb8..d07cfe5 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -613,7 +613,7 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask,
IOMMUTLBEntry *ret)
translation, given the address of the PTE. */
static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
{
-uint64_t pte = ldq_phys(pte_addr);
+uint64_t pte = ldq_phys(&address_space_memory, pte_addr);
/* Check valid bit. */
if ((pte & 1) == 0) {
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c75d6ac..0b5f993 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
+#include "exec/address-spaces.h"
/*
* Status: 2010/05/07
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 2d4a3d8..d4cea9e 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -120,7 +120,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *
s, int crt,
/* get pixel value */
if (i % 4 == 0) {
-bitset = ldub_phys(cursor_addr);
+bitset = ldub_phys(&address_space_memory, cursor_addr);
cursor_addr++;
}
v = bitset & 3;
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index b465eb6..eb98d2a 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -65,7 +65,7 @@ vmw_shmem_set(hwaddr addr, uint8 val, int len)
static i
[Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |5 +
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index edb6a43..203c8e4 100644
--- a/exec.c
+++ b/exec.c
@@ -1810,6 +1810,11 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
+/* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+if (cpu->tcg_as_listener != listener) {
+continue;
+}
CPUArchState *env = cpu->env_ptr;
tlb_flush(env, 1);
--
1.7.10.4
[Qemu-devel] [PATCH v1 11/22] exec: Make ldl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c|5 +-
exec.c| 19 ---
hw/dma/pl080.c|9 ++--
hw/dma/sun4m_iommu.c |3 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |8 +--
hw/s390x/css.c|3 +-
hw/s390x/s390-virtio-bus.c|2 +-
hw/s390x/virtio-ccw.c |5 +-
hw/scsi/megasas.c |4 +-
hw/scsi/vmw_pvscsi.c |3 +-
hw/virtio/virtio.c|3 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h|2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |8 +--
target-alpha/translate.c |2 +-
target-arm/helper.c | 12 ++---
target-i386/arch_memory_mapping.c | 36 ++---
target-i386/helper.c |8 +--
target-i386/seg_helper.c |4 +-
target-i386/smm_helper.c | 102 +++--
target-i386/svm_helper.c | 26 +-
target-ppc/excp_helper.c |2 +-
target-ppc/mmu-hash32.h |4 +-
target-s390x/cpu.c|2 +-
target-sparc/ldst_helper.c|6 +--
target-sparc/mmu_helper.c | 18 +++
target-unicore32/softmmu.c|4 +-
target-xtensa/helper.c|2 +-
30 files changed, 163 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..8f6766b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -374,7 +374,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
-intno = ldl_phys(env->vm_vmcb + offsetof(struct
vmcb, control.int_vector));
+intno = ldl_phys(env->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing
virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index 203c8e4..0e898bb 100644
--- a/exec.c
+++ b/exec.c
@@ -1598,7 +1598,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
-case 4: return ldl_phys(addr);
+case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2310,7 +2310,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2319,8 +2319,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2353,19 +2352,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 35b9015..58556f3 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
-ch->src = ldl_le_phys(ch->lli);
-ch->dest = ldl_le_phys(ch->lli + 4);
-ch->ctrl
[Qemu-devel] [PATCH v1 13/22] exec: Make lduw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 18 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/css.c |3 ++-
hw/s390x/virtio-ccw.c |8 +---
hw/virtio/virtio.c | 16
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c | 15 ---
target-sparc/ldst_helper.c |6 +++---
10 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index db64e13..7ab6153 100644
--- a/exec.c
+++ b/exec.c
@@ -1597,7 +1597,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
case 1: return ldub_phys(&address_space_memory, addr);
-case 2: return lduw_phys(addr);
+case 2: return lduw_phys(&address_space_memory, addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
@@ -2435,7 +2435,7 @@ uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(hwaddr addr,
+static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2444,7 +2444,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2478,19 +2478,19 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
return val;
}
-uint32_t lduw_phys(hwaddr addr)
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(hwaddr addr)
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(hwaddr addr)
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index eb98d2a..7877cb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -80,7 +80,7 @@ vmw_shmem_st8(hwaddr addr, uint8_t value)
static inline uint32_t
vmw_shmem_ld16(hwaddr addr)
{
-uint16_t res = lduw_le_phys(addr);
+uint16_t res = lduw_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 942751b..b1d5b91 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -354,7 +354,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
}
/* FIXME: bounds check the address */
-size = lduw_be_phys(vpa + 0x4);
+size = lduw_be_phys(env->as, vpa + 0x4);
if (size < VPA_MIN_SIZE) {
return H_PARAMETER;
@@ -540,7 +540,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
args[0] = ldub_phys(cpu->env.as, addr);
return H_SUCCESS;
case 2:
-args[0] = lduw_phys(addr);
+args[0] = lduw_phys(cpu->env.as, addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(cpu->env.as, addr);
@@ -608,7 +608,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
tmp = ldub_phys(cpu->env.as, src);
break;
case 1:
-tmp = lduw_phys(src);
+tmp = lduw_phys(cpu->env.as, src);
break;
case 2:
tmp = ldl_phys(cpu->env.as, src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 41b1903..d42d7ec 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -677,7 +677,8 @@ static void css_update_chnmon(SubchDev *sch)
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
-count = lduw_phys(channel_subsys->chnmon_area + offset);
+count = lduw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset);
count++;
stw_phys(channel_subsys->chnmon_area + offset, count);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index b86d94e..a92cbde 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -268,9 +268,11 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
info.queue = ldq_phys(&address_spac
[Qemu-devel] [PATCH v1 16/22] exec: Make stl_phys_notdirty input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|4 ++--
hw/arm/boot.c |9 +
hw/arm/highbank.c |6 +++---
include/exec/cpu-common.h |2 +-
target-i386/helper.c | 16
target-sparc/mmu_helper.c |2 +-
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/exec.c b/exec.c
index 1dfdc3c..0b92ec1 100644
--- a/exec.c
+++ b/exec.c
@@ -2496,14 +2496,14 @@ uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(hwaddr addr, uint32_t val)
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
io_mem_write(mr, addr1, val, 4);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 55d552f..b04d386 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -16,6 +16,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#include "exec/address-spaces.h"
#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x0001
@@ -88,13 +89,13 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
-stl_phys_notdirty(info->smp_bootreg_addr, 0);
+stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
-#define WRITE_WORD(p, value) do { \
-stl_phys_notdirty(p, value); \
-p += 4; \
+#define WRITE_WORD(p, value) do {\
+stl_phys_notdirty(&address_space_memory, p, value); \
+p += 4; \
} while (0)
static void set_kernel_args(const struct arm_boot_info *info)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index fe98ef1..2e95967 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -68,11 +68,11 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct
arm_boot_info *info)
switch (info->nb_cpus) {
case 4:
-stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
case 3:
-stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
case 2:
-stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
env->regs[15] = SMP_BOOT_ADDR;
break;
default:
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b29065d..dd5feab 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,7 +102,7 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t
val);
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
-void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 27461f1..114acb7 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -567,7 +567,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pml4e_addr, pml4e);
+stl_phys_notdirty(env->as, pml4e_addr, pml4e);
}
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) <<
3)) &
@@ -584,7 +584,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pdpe_addr, pdpe);
+stl_phys_notdirty(env->as, pdpe_addr, pdpe);
}
} else
#endif
@@ -654,7 +654,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
-stl_phys_notdirty(pde_addr, pde);
+stl_phys_notdirty(env->as, pde_addr, pde);
}
/* align to page_size */
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xff
[Qemu-devel] [PATCH v1 17/22] exec: Make stw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 20 ++--
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c |2 +-
hw/ppc/spapr_hcall.c |4 ++--
hw/s390x/css.c |3 ++-
hw/s390x/s390-virtio-bus.c |8 +---
hw/s390x/virtio-ccw.c |3 ++-
hw/sh4/r2d.c |2 +-
hw/virtio/virtio.c | 10 ++
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c |4 ++--
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c |6 +++---
14 files changed, 45 insertions(+), 39 deletions(-)
diff --git a/exec.c b/exec.c
index 0b92ec1..cf35cd4 100644
--- a/exec.c
+++ b/exec.c
@@ -1612,7 +1612,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stb_phys(addr, val);
break;
case 2:
-stw_phys(addr, val);
+stw_phys(&address_space_memory, addr, val);
break;
case 4:
stl_phys(&address_space_memory, addr, val);
@@ -2589,7 +2589,8 @@ void stb_phys(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(hwaddr addr, uint32_t val,
+static inline void stw_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2597,8 +2598,7 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@@ -2629,19 +2629,19 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stw_phys(hwaddr addr, uint32_t val)
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(hwaddr addr, uint32_t val)
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(hwaddr addr, uint32_t val)
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 2ed73af..d8f734f 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -89,7 +89,7 @@ static inline void
vmw_shmem_st16(hwaddr addr, uint16_t value)
{
VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
-stw_le_phys(addr, value);
+stw_le_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 09a23ce..4d22048 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -64,7 +64,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
-stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+stw_be_phys(env->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(env->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(env->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(env->as, bdloc + 0x34, bd->bi_baudrate);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 8f5a242..520ffd5 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -564,7 +564,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(addr, val);
return H_SUCCESS;
case 2:
-stw_phys(addr, val);
+stw_phys(cpu->env.as, addr, val);
return H_SUCCESS;
case 4:
stl_phys(cpu->env.as, addr, val);
@@ -627,7 +627,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(dst, tmp);
break;
case 1:
-stw_phys(dst, tmp);
+stw_phys(cpu->env.as, dst, tmp);
break;
case 2:
stl_phys(cpu->env.as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index cfa8a9b..75b04b4 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
count = lduw_phys(&address_space_memory,
channel_subsys->chnmon_area + offset);
count++;
-stw_phys(channel_subsys->chnmon_area + offset, count);
+stw_phys(&address_space_memory,
+ channel_subsys->chn
[Qemu-devel] [PATCH v1 18/22] exec: Make stb_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |6 +++---
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c | 10 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++-
hw/s390x/s390-virtio.c |2 +-
hw/scsi/megasas.c |6 --
include/exec/cpu-common.h |2 +-
target-i386/svm_helper.c |2 +-
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c |6 +++---
11 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/exec.c b/exec.c
index cf35cd4..f027091 100644
--- a/exec.c
+++ b/exec.c
@@ -1609,7 +1609,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(&address_space_memory, addr, val);
break;
case 2:
stw_phys(&address_space_memory, addr, val);
@@ -2582,10 +2582,10 @@ void stl_be_phys(AddressSpace *as, hwaddr addr,
uint32_t val)
}
/* XXX: optimize */
-void stb_phys(hwaddr addr, uint32_t val)
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t v = val;
-cpu_physical_memory_write(addr, &v, 1);
+address_space_rw(as, addr, &v, 1, 1);
}
/* warning: addr must be aligned */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index d8f734f..1099df6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -74,7 +74,7 @@ static inline void
vmw_shmem_st8(hwaddr addr, uint8_t value)
{
VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
-stb_phys(addr, value);
+stb_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 4d22048..36a394b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -62,27 +62,27 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
stl_be_phys(env->as, bdloc + 0x1C, bd->bi_bootflags);
stl_be_phys(env->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+stb_phys(env->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(env->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(env->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(env->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(env->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
-stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
+stb_phys(env->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
-stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+stb_phys(env->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
stl_be_phys(env->as, bdloc + 0x5C, bd->bi_plb_busfreq);
stl_be_phys(env->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+stb_phys(env->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
if (flags & 0x0001) {
for (i = 0; i < 6; i++)
-stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
+stb_phys(env->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(env->as, bdloc + n, bd->bi_opbfreq);
n += 4;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 520ffd5..5c0df80 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -369,7 +369,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
tmp = ldub_phys(env->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
-stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+stb_phys(env->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
@@ -561,7 +561,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(cpu->env.as, addr, val);
return H_SUCCESS;
case 2:
stw_phys(cpu->env.as, addr, val);
@@ -624,7 +624,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
}
switch (esize) {
case 0:
-stb_phys(dst, tmp);
+stb_phys(cpu->env.as, dst, tmp);
break;
case 1:
stw_phys(cpu->env.as, dst, tmp);
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index f05ca70..170d851 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -359,15 +359,21 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_reset(dev->vdev);
/* Sync dev space */
-stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
+stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->dev
[Qemu-devel] [PATCH v1 14/22] exec: Make stq_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 12 +++---
hw/alpha/dp264.c |5 ++-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |4 +-
hw/s390x/s390-virtio-bus.c |3 +-
hw/s390x/virtio-ccw.c |4 +-
hw/scsi/megasas.c |3 +-
include/exec/cpu-common.h |6 +--
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |6 +--
target-alpha/translate.c |2 +-
target-i386/helper.c |3 +-
target-i386/smm_helper.c | 32 +++---
target-i386/svm_helper.c | 102 +++-
target-ppc/mmu-hash64.h|5 ++-
target-s390x/helper.c |6 ++-
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c | 14 +++---
18 files changed, 121 insertions(+), 92 deletions(-)
diff --git a/exec.c b/exec.c
index 7ab6153..57aebd1 100644
--- a/exec.c
+++ b/exec.c
@@ -2644,22 +2644,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stq_phys(hwaddr addr, uint64_t val)
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_le_phys(hwaddr addr, uint64_t val)
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_be_phys(hwaddr addr, uint64_t val)
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
/* virtual memory access for debug (includes writing to ROM) */
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 20795ac..1351ba5 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
-stq_phys(param_offset + 0x100, initrd_base +
0xfc00ULL);
-stq_phys(param_offset + 0x108, initrd_size);
+stq_phys(&address_space_memory,
+ param_offset + 0x100, initrd_base +
0xfc00ULL);
+stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 7877cb6..4cf0e79 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
-stq_le_phys(addr, value);
+stq_le_phys(&address_space_memory, addr, value);
}
/* Macros for simplification of operations on array-style registers */
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index b1d5b91..5becf91 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
-stq_phys(addr, val);
+stq_phys(cpu->env.as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -633,7 +633,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
-stq_phys(dst, tmp);
+stq_phys(cpu->env.as, dst, tmp);
break;
}
dst = dst + step;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index e8e6e10..5da28d7 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
-stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
+stq_be_phys(&address_space_memory,
+vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM,
virtio_queue_get_num(dev->vdev, i));
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index a92cbde..0bb98ae 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -876,7 +876,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t
vector)
}
indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
-stq_phys(dev->indicators, indicators);
+stq_phys(&address_space_memory, dev->indicators, indicators);
} else {
if (!dev->indicators2) {
return;
@@ -884,7 +884,7 @@ static void virtio_ccw_noti
[Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index 686f0d1..e672824 100644
--- a/exec.c
+++ b/exec.c
@@ -2669,6 +2669,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
int l;
hwaddr phys_addr;
target_ulong page;
+CPUArchState *env = cpu->env_ptr;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -2681,10 +2682,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
-cpu_physical_memory_write_rom(&address_space_memory,
- phys_addr, buf, l);
+cpu_physical_memory_write_rom(env->as, phys_addr, buf, l);
else
-cpu_physical_memory_rw(phys_addr, buf, l, is_write);
+address_space_rw(env->as, phys_addr, buf, l, 0);
len -= l;
buf += l;
addr += l;
--
1.7.10.4
[Qemu-devel] [PATCH v1 19/22] exec: Make cpu_physical_memory_write_rom input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|8
hw/core/loader.c |3 ++-
hw/intc/apic.c|3 ++-
hw/sparc/sun4m.c |3 ++-
include/exec/cpu-common.h |2 +-
5 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/exec.c b/exec.c
index f027091..686f0d1 100644
--- a/exec.c
+++ b/exec.c
@@ -2093,7 +2093,7 @@ void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
hwaddr l;
@@ -2103,8 +2103,7 @@ void cpu_physical_memory_write_rom(hwaddr addr,
while (len > 0) {
l = len;
-mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2682,7 +2681,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
-cpu_physical_memory_write_rom(phys_addr, buf, l);
+cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 60d2ebd..5598b30 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
-cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index a913186..b48b5ef 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int
sync_type)
}
vapic_state.irr = vector & 0xff;
-cpu_physical_memory_write_rom(s->vapic_paddr + start,
+cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..2957d90 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
-cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 20d3518..1710c51 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_rom;
--
1.7.10.4
[Qemu-devel] [PATCH v1 15/22] exec: Make stl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 19 +
hw/net/vmware_utils.h |2 +-
hw/pci/msi.c |2 +-
hw/pci/msix.c |2 +-
hw/ppc/ppc405_uc.c | 32 +++---
hw/ppc/spapr_hcall.c |4 +-
hw/s390x/css.c |2 +-
hw/s390x/s390-virtio-bus.c |2 +-
hw/s390x/virtio-ccw.c |2 +-
hw/scsi/megasas.c |6 ++-
hw/scsi/vmw_pvscsi.c |3 +-
hw/sh4/r2d.c |2 +-
hw/timer/hpet.c|3 +-
hw/virtio/virtio.c |4 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h |2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |6 +--
target-alpha/translate.c |2 +-
target-arm/helper.c|2 +-
target-i386/seg_helper.c |8 ++--
target-i386/smm_helper.c | 100 ++--
target-i386/svm_helper.c | 28 -
target-ppc/mmu-hash32.h|4 +-
target-sparc/ldst_helper.c |6 +--
25 files changed, 132 insertions(+), 119 deletions(-)
diff --git a/exec.c b/exec.c
index 57aebd1..1dfdc3c 100644
--- a/exec.c
+++ b/exec.c
@@ -1615,7 +1615,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stw_phys(addr, val);
break;
case 4:
-stl_phys(addr, val);
+stl_phys(&address_space_memory, addr, val);
break;
default: abort();
}
@@ -2525,7 +2525,8 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(hwaddr addr, uint32_t val,
+static inline void stl_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2533,7 +2534,7 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
@@ -2565,19 +2566,19 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stl_phys(hwaddr addr, uint32_t val)
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(hwaddr addr, uint32_t val)
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(hwaddr addr, uint32_t val)
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 4cf0e79..2ed73af 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -104,7 +104,7 @@ static inline void
vmw_shmem_st32(hwaddr addr, uint32_t value)
{
VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
-stl_le_phys(addr, value);
+stl_le_phys(&address_space_memory, addr, value);
}
static inline uint64_t
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 2a04d18..a4a3040 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
"notify vector 0x%x"
" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
vector, msg.address, msg.data);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
/* Normally called by pci_default_write_config(). */
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 3430770..5c49bfc 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
msg = msix_get_message(dev, vector);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
void msix_reset(PCIDevice *dev)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8109f92..09a23ce 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -52,30 +52,30 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
bdloc = 0x0100UL - sizeof(struct ppc4xx_bd_info_t);
else
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
-stl_be_phys(bdloc + 0x00, bd->bi_memstart);
-stl_be_phys(bdloc + 0x04, bd->bi_memsize);
-stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
-stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
-stl_be_phys(bdloc + 0x10, bd->bi_flashoffse
[Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new()
From: "Edgar E. Iglesias"
This is to allow future patches to set properties before cpu::realize().
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 10970e0..4009ff5 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -76,7 +76,7 @@ static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
-const char *cpu_model = args->cpu_model;
+Error *err = NULL;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
@@ -91,10 +91,13 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
-if (cpu_model == NULL) {
-cpu_model = "microblaze";
+cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err) {
+error_report("%s", error_get_pretty(err));
+exit(EXIT_FAILURE);
}
-cpu = cpu_mb_init(cpu_model);
+
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
--
1.7.10.4
[Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 4009ff5..0a13b0e 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
+MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
+AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
qemu_irq irq[32], *cpu_irq;
+/* Setup the CPU specific address-space. */
+memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
+address_space_init(as_cpu, mr_cpu_root, "as/cpu");
+
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err) {
error_report("%s", error_get_pretty(err));
@@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
env = &cpu->env;
+/* Populate the CPU AS with the LMB only visible to the CPU. */
+memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
+ address_space_mem, 0,
+ memory_region_size(address_space_mem));
+memory_region_add_subregion(mr_cpu_root, 0x, sysmem_alias);
+
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
-memory_region_add_subregion(address_space_mem, 0x, phys_lmb_bram);
+memory_region_add_subregion_overlap(mr_cpu_root, 0x,
+phys_lmb_bram, 2);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
--
1.7.10.4
[Qemu-devel] [PATCH v2 00/22] Steps towards per CPU address-spaces
From: "Edgar E. Iglesias" Hi, I'm looking at modeling systems where multiple CPUs co-exist with different views of their attached buses/devs. With this series I'm trying to take some steps towards having an address-space per CPU. It's not complete but good enough for making it possible to model (to some extent) CPU local memories for MicroBlaze systems in emulation mode (TCG). I'm updating the petalogix-ml605 here and will follow-up later with the petalogix-s3adsp. The per-cpu address space is added into the CPUState. I tried to measure performance diff with having it in the CPUState->env. For "normal" and even for IO heavy workloads on linux kernels, the diff is not measurable. I also tested with a tight guest loop that continuously does I/O accesses and there I can see a 2.5% drop in perf. I dont think the runtime type check will be much of a problem after all. I've reordered the series and moved the AS props to the end, hoping we can get through the bulk of the series with less controversy. I've kept the interface with properties to set AddressSpace pointers which I think is the more flexible approach but we can explore other ideas if there are. There is lots of future work needed, for example to transform more of the cpu_* bus accessing functions. To add more usage of AddressSpace properties to pass on address spaces to DMA models. Qtest mechanisms to target specific address spaces, etc... Cheers, Edgar Changes v1 -> v2: Add braces in cpu_memory_rw_debug. Avoid mixing var/code declarations in tcg_commit. Move per-cpu address space into CPUState. Reorder patch series to add the AS properties last. Edgar E. Iglesias (22): exec: Make tb_invalidate_phys_addr input an AS exec: Make iotlb_to_region input an AS exec: Always initialize MemorySection address spaces exec: Make memory_region_section_get_iotlb use section AS memory: Add MemoryListener to typedefs.h cpu: Add per-cpu address space exec: On AS changes, only flush affected CPU TLBs exec: Make ldl_*_phys input an AddressSpace exec: Make ldq/ldub_*_phys input an AddressSpace exec: Make lduw_*_phys input an AddressSpace exec: Make stq_*_phys input an AddressSpace exec: Make stl_*_phys input an AddressSpace exec: Make stl_phys_notdirty input an AddressSpace exec: Make stw_*_phys input an AddressSpace exec: Make stb_phys input an AddressSpace exec: Make cpu_physical_memory_write_rom input an AS exec: Make cpu_memory_rw_debug use the CPUs AS memory: Add address_space_find_by_name() qdev: Add qdev property type for AddressSpaces target-microblaze: Add address-space property petalogix-ml605: Create the CPU with object_new() petalogix-ml605: Make the LMB visible only to the CPU cpu-exec.c |5 +- cputlb.c|7 +- exec.c | 177 - hw/alpha/dp264.c|5 +- hw/alpha/typhoon.c |2 +- hw/arm/boot.c |9 +- hw/arm/highbank.c |6 +- hw/core/loader.c|3 +- hw/core/qdev-properties-system.c| 46 ++ hw/display/sm501.c |1 + hw/display/sm501_template.h |2 +- hw/dma/pl080.c |9 +- hw/dma/sun4m_iommu.c|3 +- hw/intc/apic.c |3 +- hw/microblaze/petalogix_ml605_mmu.c | 28 +++- hw/net/vmware_utils.h | 16 +- hw/pci/msi.c|2 +- hw/pci/msix.c |2 +- hw/ppc/ppc405_uc.c | 45 +++--- hw/ppc/spapr_hcall.c| 50 +++--- hw/s390x/css.c | 11 +- hw/s390x/s390-virtio-bus.c | 36 +++-- hw/s390x/s390-virtio.c |2 +- hw/s390x/virtio-ccw.c | 40 +++-- hw/scsi/megasas.c | 22 ++- hw/scsi/vmw_pvscsi.c|6 +- hw/sh4/r2d.c|4 +- hw/sparc/sun4m.c|3 +- hw/timer/hpet.c |3 +- hw/virtio/virtio.c | 31 ++-- include/exec/cpu-common.h | 44 ++--- include/exec/exec-all.h |5 +- include/exec/memory.h | 10 +- include/exec/softmmu_template.h |7 +- include/hw/ppc/spapr.h |4 +- include/hw/qdev-properties.h|5 + include/qemu/typedefs.h |1 + include/qom/cpu.h |3 + memory.c| 12 ++ monitor.c |2 +- target-alpha/helper.c |7 +- target-alpha/helper.h |8 +- target-alpha/mem_helper.c | 36 +++-- target-alpha/translate.c|8 +- target-arm/helper.c | 21 ++- target-i386/arch_memory_mapping.c | 46 +++--- target-i386/helper.c| 48 +++--- target-i
[Qemu-devel] [PATCH v2 01/22] exec: Make tb_invalidate_phys_addr input an AS
From: "Edgar E. Iglesias"
No functional change.
Signed-off-by: Edgar E. Iglesias
---
exec.c|3 ++-
include/exec/exec-all.h |2 +-
target-xtensa/op_helper.c |3 ++-
translate-all.c |4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 00526d1..7ed34e2 100644
--- a/exec.c
+++ b/exec.c
@@ -484,7 +484,8 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+tb_invalidate_phys_addr(&address_space_memory,
+phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ea90b64..b4dfc07 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -101,7 +101,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env,
uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
-tb_invalidate_phys_addr(paddr);
+tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index 1c63d78..2ff8781 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1356,13 +1356,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
-mr = address_space_translate(&address_space_memory, addr, &addr, &l,
false);
+mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.7.10.4
[Qemu-devel] [PATCH v2 04/22] exec: Make memory_region_section_get_iotlb use section AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 6d88931..803bbde 100644
--- a/exec.c
+++ b/exec.c
@@ -782,7 +782,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
-iotlb = section - address_space_memory.dispatch->map.sections;
+iotlb = section - section->address_space->dispatch->map.sections;
iotlb += xlat;
}
--
1.7.10.4
[Qemu-devel] [PATCH v2 03/22] exec: Always initialize MemorySection address spaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index c34f642..6d88931 100644
--- a/exec.c
+++ b/exec.c
@@ -878,6 +878,7 @@ static void register_subpage(AddressSpaceDispatch *d,
MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&d->map, &subsection));
@@ -1717,6 +1718,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr
base)
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
{
MemoryRegionSection section = {
+.address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.7.10.4
[Qemu-devel] [PATCH v2 02/22] exec: Make iotlb_to_region input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|2 +-
exec.c |5 ++---
include/exec/exec-all.h |2 +-
include/exec/softmmu_template.h |5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index fff0afb..0399172 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(pd);
+mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 7ed34e2..c34f642 100644
--- a/exec.c
+++ b/exec.c
@@ -1726,10 +1726,9 @@ static uint16_t dummy_section(PhysPageMap *map,
MemoryRegion *mr)
return phys_section_add(map, §ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
-return address_space_memory.dispatch->map.sections[
- index & ~TARGET_PAGE_MASK].mr;
+return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b4dfc07..6129365 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,7 +324,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see
[Qemu-devel] [PATCH v2 06/22] cpu: Add per-cpu address space
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|7 ---
exec.c | 28
include/exec/exec-all.h |1 +
include/exec/softmmu_template.h |6 --
include/qom/cpu.h |3 +++
5 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 0399172..014f5da 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -247,6 +247,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
uintptr_t addend;
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
+CPUState *cpu = ENV_GET_CPU(env);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -254,7 +255,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
-section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+section = address_space_translate_for_iotlb(cpu->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -319,6 +320,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
int mmu_idx, page_index, pd;
void *p;
MemoryRegion *mr;
+CPUState *cpu = ENV_GET_CPU(env1);
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = cpu_mmu_index(env1);
@@ -327,9 +329,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(&address_space_memory, pd);
+mr = iotlb_to_region(cpu->as, pd);
if (memory_region_is_unassigned(mr)) {
-CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->do_unassigned_access) {
diff --git a/exec.c b/exec.c
index 803bbde..eba889a 100644
--- a/exec.c
+++ b/exec.c
@@ -136,6 +136,7 @@ typedef struct subpage_t {
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -434,6 +435,23 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+if (tcg_enabled()) {
+if (cpu->tcg_as_listener) {
+memory_listener_unregister(cpu->tcg_as_listener);
+} else {
+cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+}
+cpu->tcg_as_listener->commit = tcg_commit;
+memory_listener_register(cpu->tcg_as_listener, as);
+}
+
+cpu->as = as;
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -453,6 +471,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+cpu_address_space_init(cpu, &address_space_memory);
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -484,7 +503,7 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(&address_space_memory,
+tb_invalidate_phys_addr(cpu->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1810,10 +1829,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
-.commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1849,9 +1864,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
-if (tcg_enabled()) {
-memory_listener_register(&tcg_memory_listener, &address_space_memory);
-}
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6129365..61770ee 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,6 +95,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 69d856a..26215f9 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -119,7 +119,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState
*env,
uintptr_t retaddr)
{
uint6
[Qemu-devel] [PATCH v2 05/22] memory: Add MemoryListener to typedefs.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |2 --
include/qemu/typedefs.h |1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 480dfbf..2d0b614 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -165,8 +165,6 @@ struct MemoryRegion {
NotifierList iommu_notify;
};
-typedef struct MemoryListener MemoryListener;
-
/**
* MemoryListener: callbacks structure for updates to the physical memory map
*
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index a4c1b84..425ca1a 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -24,6 +24,7 @@ typedef struct BusClass BusClass;
typedef struct AddressSpace AddressSpace;
typedef struct MemoryRegion MemoryRegion;
typedef struct MemoryRegionSection MemoryRegionSection;
+typedef struct MemoryListener MemoryListener;
typedef struct MemoryMappingList MemoryMappingList;
--
1.7.10.4
[Qemu-devel] [PATCH v2 07/22] exec: On AS changes, only flush affected CPU TLBs
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |5 +
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index eba889a..8fa63b7 100644
--- a/exec.c
+++ b/exec.c
@@ -1809,6 +1809,11 @@ static void tcg_commit(MemoryListener *listener)
CPU_FOREACH(cpu) {
CPUArchState *env = cpu->env_ptr;
+/* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+if (cpu->tcg_as_listener != listener) {
+continue;
+}
tlb_flush(env, 1);
}
}
--
1.7.10.4
[Qemu-devel] [PATCH v2 08/22] exec: Make ldl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c|5 +-
exec.c| 19 ---
hw/dma/pl080.c|9 ++--
hw/dma/sun4m_iommu.c |3 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c | 13 +++--
hw/s390x/css.c|3 +-
hw/s390x/s390-virtio-bus.c|2 +-
hw/s390x/virtio-ccw.c |5 +-
hw/scsi/megasas.c |4 +-
hw/scsi/vmw_pvscsi.c |3 +-
hw/virtio/virtio.c|3 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h|2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c | 15 +++---
target-i386/arch_memory_mapping.c | 36 +++--
target-i386/helper.c |9 ++--
target-i386/seg_helper.c |6 ++-
target-i386/smm_helper.c | 103 +++--
target-i386/svm_helper.c | 28 +-
target-ppc/excp_helper.c |4 +-
target-ppc/mmu-hash32.h |6 ++-
target-s390x/cpu.c|2 +-
target-sparc/ldst_helper.c|8 +--
target-sparc/mmu_helper.c | 20 +++
target-unicore32/softmmu.c|5 +-
target-xtensa/helper.c|3 +-
30 files changed, 190 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..fd990af 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -374,7 +374,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
-intno = ldl_phys(env->vm_vmcb + offsetof(struct
vmcb, control.int_vector));
+intno = ldl_phys(cpu->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing
virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index 8fa63b7..aefb486 100644
--- a/exec.c
+++ b/exec.c
@@ -1595,7 +1595,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
-case 4: return ldl_phys(addr);
+case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2307,7 +2307,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2316,8 +2316,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2350,19 +2349,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 35b9015..58556f3 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
-ch->src = ldl_le_phys(ch->lli);
-ch->dest = ldl_le_phys(ch->lli + 4);
-ch
[Qemu-devel] [PATCH v2 10/22] exec: Make lduw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 18 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/css.c |3 ++-
hw/s390x/virtio-ccw.c |8 +---
hw/virtio/virtio.c | 16
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c | 15 ---
target-sparc/ldst_helper.c |6 +++---
10 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index ccf2420..793efa9 100644
--- a/exec.c
+++ b/exec.c
@@ -1594,7 +1594,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
case 1: return ldub_phys(&address_space_memory, addr);
-case 2: return lduw_phys(addr);
+case 2: return lduw_phys(&address_space_memory, addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
@@ -2432,7 +2432,7 @@ uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(hwaddr addr,
+static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2441,7 +2441,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2475,19 +2475,19 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
return val;
}
-uint32_t lduw_phys(hwaddr addr)
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(hwaddr addr)
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(hwaddr addr)
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
-return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index eb98d2a..7877cb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -80,7 +80,7 @@ vmw_shmem_st8(hwaddr addr, uint8_t value)
static inline uint32_t
vmw_shmem_ld16(hwaddr addr)
{
-uint16_t res = lduw_le_phys(addr);
+uint16_t res = lduw_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 6e61a91..a2893ad 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -355,7 +355,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
}
/* FIXME: bounds check the address */
-size = lduw_be_phys(vpa + 0x4);
+size = lduw_be_phys(cs->as, vpa + 0x4);
if (size < VPA_MIN_SIZE) {
return H_PARAMETER;
@@ -544,7 +544,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
args[0] = ldub_phys(cs->as, addr);
return H_SUCCESS;
case 2:
-args[0] = lduw_phys(addr);
+args[0] = lduw_phys(cs->as, addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(cs->as, addr);
@@ -614,7 +614,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
tmp = ldub_phys(cs->as, src);
break;
case 1:
-tmp = lduw_phys(src);
+tmp = lduw_phys(cs->as, src);
break;
case 2:
tmp = ldl_phys(cs->as, src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 41b1903..d42d7ec 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -677,7 +677,8 @@ static void css_update_chnmon(SubchDev *sch)
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
-count = lduw_phys(channel_subsys->chnmon_area + offset);
+count = lduw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset);
count++;
stw_phys(channel_subsys->chnmon_area + offset, count);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index b86d94e..a92cbde 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -268,9 +268,11 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
info.queue = ldq_phys(&address_space_memory, ccw.cda);
[Qemu-devel] [PATCH v2 09/22] exec: Make ldq/ldub_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c| 22 +++
hw/alpha/typhoon.c|2 +-
hw/display/sm501.c|1 +
hw/display/sm501_template.h |2 +-
hw/net/vmware_utils.h |4 +-
hw/ppc/spapr_hcall.c | 11 ++--
hw/s390x/s390-virtio-bus.c|5 +-
hw/s390x/virtio-ccw.c | 18 +++---
hw/scsi/megasas.c |3 +-
hw/virtio/virtio.c|2 +-
include/exec/cpu-common.h |8 +--
monitor.c |2 +-
target-alpha/helper.c |7 ++-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c |3 +-
target-i386/arch_memory_mapping.c | 10 ++--
target-i386/helper.c | 20 +++
target-i386/smm_helper.c | 32 +-
target-i386/svm_helper.c | 117 +++--
target-ppc/mmu-hash64.h |7 ++-
target-s390x/helper.c |3 +-
target-s390x/mem_helper.c |3 +-
target-sparc/ldst_helper.c| 25
25 files changed, 185 insertions(+), 137 deletions(-)
diff --git a/exec.c b/exec.c
index aefb486..ccf2420 100644
--- a/exec.c
+++ b/exec.c
@@ -1593,7 +1593,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
-case 1: return ldub_phys(addr);
+case 1: return ldub_phys(&address_space_memory, addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
@@ -2365,7 +2365,7 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(hwaddr addr,
+static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2374,7 +2374,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
hwaddr l = 8;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2408,26 +2408,26 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
return val;
}
-uint64_t ldq_phys(hwaddr addr)
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(hwaddr addr)
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(hwaddr addr)
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(hwaddr addr)
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
uint8_t val;
-cpu_physical_memory_read(addr, &val, 1);
+address_space_rw(as, addr, &val, 1, 0);
return val;
}
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 59e1bb8..d07cfe5 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -613,7 +613,7 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask,
IOMMUTLBEntry *ret)
translation, given the address of the PTE. */
static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
{
-uint64_t pte = ldq_phys(pte_addr);
+uint64_t pte = ldq_phys(&address_space_memory, pte_addr);
/* Check valid bit. */
if ((pte & 1) == 0) {
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c75d6ac..0b5f993 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
+#include "exec/address-spaces.h"
/*
* Status: 2010/05/07
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 2d4a3d8..d4cea9e 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -120,7 +120,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *
s, int crt,
/* get pixel value */
if (i % 4 == 0) {
-bitset = ldub_phys(cursor_addr);
+bitset = ldub_phys(&address_space_memory, cursor_addr);
cursor_addr++;
}
v = bitset & 3;
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index b465eb6..eb98d2a 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -65,7 +65,7 @@ vmw_shmem_set(hwaddr addr, uint8 val, int len)
static
[Qemu-devel] [PATCH v2 11/22] exec: Make stq_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 12 +++---
hw/alpha/dp264.c |5 ++-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 ++-
hw/s390x/s390-virtio-bus.c |3 +-
hw/s390x/virtio-ccw.c |4 +-
hw/scsi/megasas.c |3 +-
include/exec/cpu-common.h |6 +--
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |7 +--
target-alpha/translate.c |2 +-
target-i386/helper.c |3 +-
target-i386/smm_helper.c | 33 +++---
target-i386/svm_helper.c | 103 +++-
target-ppc/mmu-hash64.h|7 ++-
target-s390x/helper.c |8 +++-
target-s390x/mem_helper.c |3 +-
target-sparc/ldst_helper.c | 15 ---
18 files changed, 132 insertions(+), 92 deletions(-)
diff --git a/exec.c b/exec.c
index 793efa9..ce9b2eb 100644
--- a/exec.c
+++ b/exec.c
@@ -2641,22 +2641,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stq_phys(hwaddr addr, uint64_t val)
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_le_phys(hwaddr addr, uint64_t val)
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_be_phys(hwaddr addr, uint64_t val)
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
-cpu_physical_memory_write(addr, &val, 8);
+address_space_rw(as, addr, (void *) &val, 8, 1);
}
/* virtual memory access for debug (includes writing to ROM) */
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 20795ac..1351ba5 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
-stq_phys(param_offset + 0x100, initrd_base +
0xfc00ULL);
-stq_phys(param_offset + 0x108, initrd_size);
+stq_phys(&address_space_memory,
+ param_offset + 0x100, initrd_base +
0xfc00ULL);
+stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 7877cb6..4cf0e79 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
-stq_le_phys(addr, value);
+stq_le_phys(&address_space_memory, addr, value);
}
/* Macros for simplification of operations on array-style registers */
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index a2893ad..5ce43ab 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -559,6 +559,8 @@ static target_ulong h_logical_load(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
+CPUState *cs = CPU(cpu);
+
target_ulong size = args[0];
target_ulong addr = args[1];
target_ulong val = args[2];
@@ -574,7 +576,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
-stq_phys(addr, val);
+stq_phys(cs->as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -639,7 +641,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
-stq_phys(dst, tmp);
+stq_phys(cs->as, dst, tmp);
break;
}
dst = dst + step;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index e8e6e10..5da28d7 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
-stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
+stq_be_phys(&address_space_memory,
+vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM,
virtio_queue_get_num(dev->vdev, i));
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index a92cbde..0bb98ae 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -876,7 +876,7 @@ static void virtio_ccw_notify(Device
[Qemu-devel] [PATCH v2 12/22] exec: Make stl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 19 +
hw/net/vmware_utils.h |2 +-
hw/pci/msi.c |2 +-
hw/pci/msix.c |2 +-
hw/ppc/ppc405_uc.c | 33 ---
hw/ppc/spapr_hcall.c |4 +-
hw/s390x/css.c |2 +-
hw/s390x/s390-virtio-bus.c |2 +-
hw/s390x/virtio-ccw.c |2 +-
hw/scsi/megasas.c |6 ++-
hw/scsi/vmw_pvscsi.c |3 +-
hw/sh4/r2d.c |2 +-
hw/timer/hpet.c|3 +-
hw/virtio/virtio.c |4 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h |2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |7 ++--
target-alpha/translate.c |2 +-
target-arm/helper.c|3 +-
target-i386/seg_helper.c |8 ++--
target-i386/smm_helper.c | 100 ++--
target-i386/svm_helper.c | 28 -
target-ppc/mmu-hash32.h|6 ++-
target-sparc/ldst_helper.c |6 +--
25 files changed, 137 insertions(+), 119 deletions(-)
diff --git a/exec.c b/exec.c
index ce9b2eb..032e6dc 100644
--- a/exec.c
+++ b/exec.c
@@ -1612,7 +1612,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stw_phys(addr, val);
break;
case 4:
-stl_phys(addr, val);
+stl_phys(&address_space_memory, addr, val);
break;
default: abort();
}
@@ -2522,7 +2522,8 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(hwaddr addr, uint32_t val,
+static inline void stl_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2530,7 +2531,7 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
@@ -2562,19 +2563,19 @@ static inline void stl_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stl_phys(hwaddr addr, uint32_t val)
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(hwaddr addr, uint32_t val)
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(hwaddr addr, uint32_t val)
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 4cf0e79..2ed73af 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -104,7 +104,7 @@ static inline void
vmw_shmem_st32(hwaddr addr, uint32_t value)
{
VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
-stl_le_phys(addr, value);
+stl_le_phys(&address_space_memory, addr, value);
}
static inline uint64_t
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 2a04d18..a4a3040 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
"notify vector 0x%x"
" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
vector, msg.address, msg.data);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
/* Normally called by pci_default_write_config(). */
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 3430770..5c49bfc 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
msg = msix_get_message(dev, vector);
-stl_le_phys(msg.address, msg.data);
+stl_le_phys(&address_space_memory, msg.address, msg.data);
}
void msix_reset(PCIDevice *dev)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8109f92..47a4242 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -44,6 +44,7 @@
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
+CPUState *cs = ENV_GET_CPU(env);
ram_addr_t bdloc;
int i, n;
@@ -52,30 +53,30 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
bdloc = 0x0100UL - sizeof(struct ppc4xx_bd_info_t);
else
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
-stl_be_phys(bdloc
[Qemu-devel] [PATCH v2 14/22] exec: Make stw_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 20 ++--
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c |2 +-
hw/ppc/spapr_hcall.c |4 ++--
hw/s390x/css.c |3 ++-
hw/s390x/s390-virtio-bus.c |8 +---
hw/s390x/virtio-ccw.c |3 ++-
hw/sh4/r2d.c |2 +-
hw/virtio/virtio.c | 10 ++
include/exec/cpu-common.h |6 +++---
target-i386/smm_helper.c | 12 ++--
target-i386/svm_helper.c |4 ++--
target-s390x/mem_helper.c |3 ++-
target-sparc/ldst_helper.c |6 +++---
14 files changed, 46 insertions(+), 39 deletions(-)
diff --git a/exec.c b/exec.c
index c88b6f0..f840326 100644
--- a/exec.c
+++ b/exec.c
@@ -1609,7 +1609,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stb_phys(addr, val);
break;
case 2:
-stw_phys(addr, val);
+stw_phys(&address_space_memory, addr, val);
break;
case 4:
stl_phys(&address_space_memory, addr, val);
@@ -2586,7 +2586,8 @@ void stb_phys(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(hwaddr addr, uint32_t val,
+static inline void stw_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2594,8 +2595,7 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
hwaddr l = 2;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@@ -2626,19 +2626,19 @@ static inline void stw_phys_internal(hwaddr addr,
uint32_t val,
}
}
-void stw_phys(hwaddr addr, uint32_t val)
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(hwaddr addr, uint32_t val)
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(hwaddr addr, uint32_t val)
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
-stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 2ed73af..d8f734f 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -89,7 +89,7 @@ static inline void
vmw_shmem_st16(hwaddr addr, uint16_t value)
{
VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
-stw_le_phys(addr, value);
+stw_le_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 47a4242..b0a59c3 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -65,7 +65,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
-stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f47c3ec..ebf09e9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(addr, val);
return H_SUCCESS;
case 2:
-stw_phys(addr, val);
+stw_phys(cs->as, addr, val);
return H_SUCCESS;
case 4:
stl_phys(cs->as, addr, val);
@@ -635,7 +635,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
stb_phys(dst, tmp);
break;
case 1:
-stw_phys(dst, tmp);
+stw_phys(cs->as, dst, tmp);
break;
case 2:
stl_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index cfa8a9b..75b04b4 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
count = lduw_phys(&address_space_memory,
channel_subsys->chnmon_area + offset);
count++;
-stw_phys(channel_subsys->chnmon_area + offset, count);
+stw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset, coun
[Qemu-devel] [PATCH v2 13/22] exec: Make stl_phys_notdirty input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|4 ++--
hw/arm/boot.c |9 +
hw/arm/highbank.c |6 +++---
include/exec/cpu-common.h |2 +-
target-i386/helper.c | 16
target-sparc/mmu_helper.c |2 +-
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/exec.c b/exec.c
index 032e6dc..c88b6f0 100644
--- a/exec.c
+++ b/exec.c
@@ -2493,14 +2493,14 @@ uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(hwaddr addr, uint32_t val)
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
io_mem_write(mr, addr1, val, 4);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 55d552f..b04d386 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -16,6 +16,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#include "exec/address-spaces.h"
#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x0001
@@ -88,13 +89,13 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
-stl_phys_notdirty(info->smp_bootreg_addr, 0);
+stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
-#define WRITE_WORD(p, value) do { \
-stl_phys_notdirty(p, value); \
-p += 4; \
+#define WRITE_WORD(p, value) do {\
+stl_phys_notdirty(&address_space_memory, p, value); \
+p += 4; \
} while (0)
static void set_kernel_args(const struct arm_boot_info *info)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index fe98ef1..2e95967 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -68,11 +68,11 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct
arm_boot_info *info)
switch (info->nb_cpus) {
case 4:
-stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
case 3:
-stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
case 2:
-stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
+stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
env->regs[15] = SMP_BOOT_ADDR;
break;
default:
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b29065d..dd5feab 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,7 +102,7 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t
val);
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
-void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 294cfdb..d2f0f3e 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -568,7 +568,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pml4e_addr, pml4e);
+stl_phys_notdirty(cs->as, pml4e_addr, pml4e);
}
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) <<
3)) &
@@ -585,7 +585,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
-stl_phys_notdirty(pdpe_addr, pdpe);
+stl_phys_notdirty(cs->as, pdpe_addr, pdpe);
}
} else
#endif
@@ -655,7 +655,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
-stl_phys_notdirty(pde_addr, pde);
+stl_phys_notdirty(cs->as, pde_addr, pde);
}
/* align to page_size */
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
[Qemu-devel] [PATCH v2 15/22] exec: Make stb_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |6 +++---
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c | 10 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++-
hw/s390x/s390-virtio.c |2 +-
hw/scsi/megasas.c |6 --
include/exec/cpu-common.h |2 +-
target-i386/svm_helper.c |2 +-
target-s390x/mem_helper.c |2 +-
target-sparc/ldst_helper.c |6 +++---
11 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/exec.c b/exec.c
index f840326..eab68b3 100644
--- a/exec.c
+++ b/exec.c
@@ -1606,7 +1606,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(&address_space_memory, addr, val);
break;
case 2:
stw_phys(&address_space_memory, addr, val);
@@ -2579,10 +2579,10 @@ void stl_be_phys(AddressSpace *as, hwaddr addr,
uint32_t val)
}
/* XXX: optimize */
-void stb_phys(hwaddr addr, uint32_t val)
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t v = val;
-cpu_physical_memory_write(addr, &v, 1);
+address_space_rw(as, addr, &v, 1, 1);
}
/* warning: addr must be aligned */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index d8f734f..1099df6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -74,7 +74,7 @@ static inline void
vmw_shmem_st8(hwaddr addr, uint8_t value)
{
VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
-stb_phys(addr, value);
+stb_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b0a59c3..ca520e8 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -63,27 +63,27 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env,
ppc4xx_bd_info_t *bd,
stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
-stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
+stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
-stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
-stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
if (flags & 0x0001) {
for (i = 0; i < 6; i++)
-stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
+stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
n += 4;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index ebf09e9..3ffcc65 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -370,7 +370,7 @@ static target_ulong register_vpa(CPUPPCState *env,
target_ulong vpa)
tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
-stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
@@ -567,7 +567,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
switch (size) {
case 1:
-stb_phys(addr, val);
+stb_phys(cs->as, addr, val);
return H_SUCCESS;
case 2:
stw_phys(cs->as, addr, val);
@@ -632,7 +632,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
}
switch (esize) {
case 0:
-stb_phys(dst, tmp);
+stb_phys(cs->as, dst, tmp);
break;
case 1:
stw_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index f05ca70..170d851 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -359,15 +359,21 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_reset(dev->vdev);
/* Sync dev space */
-stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
+stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
-stb_phys(dev->dev_of
[Qemu-devel] [PATCH v2 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index f606376..2872b86 100644
--- a/exec.c
+++ b/exec.c
@@ -2677,11 +2677,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong
addr,
if (l > len)
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
-if (is_write)
-cpu_physical_memory_write_rom(&address_space_memory,
- phys_addr, buf, l);
-else
-cpu_physical_memory_rw(phys_addr, buf, l, is_write);
+if (is_write) {
+cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
+} else {
+address_space_rw(cpu->as, phys_addr, buf, l, 0);
+}
len -= l;
buf += l;
addr += l;
--
1.7.10.4
[Qemu-devel] [PATCH v2 18/22] memory: Add address_space_find_by_name()
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |8
memory.c | 12
2 files changed, 20 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 2d0b614..02f4012 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -941,6 +941,14 @@ void mtree_info(fprintf_function mon_printf, void *f);
*/
void address_space_init(AddressSpace *as, MemoryRegion *root, const char
*name);
+/**
+ * address_space_find_by_name: Find an AddressSpace * by name
+ *
+ * Returns an AddressSpace * if found.
+ *
+ * @name: name of an address space too look for.
+ */
+AddressSpace *address_space_find_by_name(const char *name);
/**
* address_space_destroy: destroy an address space
diff --git a/memory.c b/memory.c
index 7764314..4695879 100644
--- a/memory.c
+++ b/memory.c
@@ -1725,6 +1725,18 @@ void address_space_init(AddressSpace *as, MemoryRegion
*root, const char *name)
memory_region_transaction_commit();
}
+AddressSpace *address_space_find_by_name(const char *name)
+{
+AddressSpace *as;
+
+QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
+if (strcmp(as->name, name) == 0) {
+return as;
+}
+}
+return NULL;
+}
+
void address_space_destroy(AddressSpace *as)
{
/* Flush out anything from MemoryListeners listening in on this */
--
1.7.10.4
[Qemu-devel] [PATCH v2 21/22] petalogix-ml605: Create the CPU with object_new()
From: "Edgar E. Iglesias"
This is to allow future patches to set properties before cpu::realize().
Reviewed-by: Andreas Färber
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 10970e0..4009ff5 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -76,7 +76,7 @@ static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
-const char *cpu_model = args->cpu_model;
+Error *err = NULL;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
@@ -91,10 +91,13 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
-if (cpu_model == NULL) {
-cpu_model = "microblaze";
+cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err) {
+error_report("%s", error_get_pretty(err));
+exit(EXIT_FAILURE);
}
-cpu = cpu_mb_init(cpu_model);
+
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
--
1.7.10.4
[Qemu-devel] [PATCH v2 19/22] qdev: Add qdev property type for AddressSpaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/core/qdev-properties-system.c | 46 ++
include/hw/qdev-properties.h |5 +
2 files changed, 51 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 729efa8..f78bd50 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -170,6 +170,42 @@ PropertyInfo qdev_prop_chr = {
.release = release_chr,
};
+/* --- AddressSpace --- */
+
+static int parse_address_space(DeviceState *dev, const char *name, void **ptr)
+{
+AddressSpace *as = address_space_find_by_name(name);
+if (as == NULL) {
+return -ENOENT;
+}
+*ptr = as;
+return 0;
+}
+
+static const char *print_address_space(void *ptr)
+{
+AddressSpace *as = ptr;
+return as->name;
+}
+
+static void get_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+get_pointer(obj, v, opaque, print_address_space, name, errp);
+}
+
+static void set_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+set_pointer(obj, v, opaque, parse_address_space, name, errp);
+}
+
+PropertyInfo qdev_prop_address_space = {
+.name = "address_space",
+.get = get_address_space,
+.set = set_address_space,
+};
+
/* --- netdev device --- */
static int parse_netdev(DeviceState *dev, const char *str, void **ptr)
@@ -369,6 +405,16 @@ void qdev_prop_set_netdev(DeviceState *dev, const char
*name,
assert_no_error(errp);
}
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value)
+{
+Error *errp = NULL;
+assert(!value || value->name);
+object_property_set_str(OBJECT(dev),
+value ? value->name : "", name, &errp);
+assert_no_error(errp);
+}
+
void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
{
qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 692f82e..0e1076d 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -19,6 +19,7 @@ extern PropertyInfo qdev_prop_size;
extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
+extern PropertyInfo qdev_prop_address_space;
extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
@@ -124,6 +125,8 @@ extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
+#define DEFINE_PROP_ADDRESS_SPACE(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_address_space, AddressSpace*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@@ -160,6 +163,8 @@ void qdev_prop_set_uint32(DeviceState *dev, const char
*name, uint32_t value);
void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value);
void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value);
void qdev_prop_set_string(DeviceState *dev, const char *name, const char
*value);
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value);
void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState
*value);
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState
*value);
int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState
*value) QEMU_WARN_UNUSED_RESULT;
--
1.7.10.4
[Qemu-devel] [PATCH v2 22/22] petalogix-ml605: Make the LMB visible only to the CPU
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 4009ff5..0a13b0e 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
+MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
+AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
qemu_irq irq[32], *cpu_irq;
+/* Setup the CPU specific address-space. */
+memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
+address_space_init(as_cpu, mr_cpu_root, "as/cpu");
+
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err) {
error_report("%s", error_get_pretty(err));
@@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
env = &cpu->env;
+/* Populate the CPU AS with the LMB only visible to the CPU. */
+memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
+ address_space_mem, 0,
+ memory_region_size(address_space_mem));
+memory_region_add_subregion(mr_cpu_root, 0x, sysmem_alias);
+
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
-memory_region_add_subregion(address_space_mem, 0x, phys_lmb_bram);
+memory_region_add_subregion_overlap(mr_cpu_root, 0x,
+phys_lmb_bram, 2);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
--
1.7.10.4
[Qemu-devel] [PATCH v2 20/22] target-microblaze: Add address-space property
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0ef9aa4..6d39d3d 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -93,6 +93,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+#ifndef CONFIG_USER_ONLY
+cpu_address_space_init(cs, cs->as);
+#endif
cpu_reset(cs);
qemu_init_vcpu(cs);
@@ -123,6 +126,9 @@ static const VMStateDescription vmstate_mb_cpu = {
};
static Property mb_properties[] = {
+#ifndef CONFIG_USER_ONLY
+DEFINE_PROP_ADDRESS_SPACE("address-space", CPUState, as),
+#endif
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
1.7.10.4
[Qemu-devel] [PATCH v2 16/22] exec: Make cpu_physical_memory_write_rom input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|8
hw/core/loader.c |3 ++-
hw/intc/apic.c|3 ++-
hw/sparc/sun4m.c |3 ++-
include/exec/cpu-common.h |2 +-
5 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/exec.c b/exec.c
index eab68b3..f606376 100644
--- a/exec.c
+++ b/exec.c
@@ -2090,7 +2090,7 @@ void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
hwaddr l;
@@ -2100,8 +2100,7 @@ void cpu_physical_memory_write_rom(hwaddr addr,
while (len > 0) {
l = len;
-mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2679,7 +2678,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
-cpu_physical_memory_write_rom(phys_addr, buf, l);
+cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 60d2ebd..5598b30 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
-cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index a913186..b48b5ef 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int
sync_type)
}
vapic_state.irr = vector & 0xff;
-cpu_physical_memory_write_rom(s->vapic_paddr + start,
+cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..2957d90 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
-cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 20d3518..1710c51 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_rom;
--
1.7.10.4
[Qemu-devel] [RFC PATCH 4/8] exec: Make memory_region_section_get_iotlb use section AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 05df217..0162eb3 100644
--- a/exec.c
+++ b/exec.c
@@ -709,7 +709,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
-iotlb = section - address_space_memory.dispatch->sections;
+iotlb = section - section->address_space->dispatch->sections;
iotlb += xlat;
}
--
1.7.10.4
[Qemu-devel] [RFC PATCH 2/8] exec: Make iotlb_to_region input an AS
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|2 +-
exec.c |4 ++--
include/exec/exec-all.h |2 +-
include/exec/softmmu_template.h |5 +++--
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index fff0afb..0399172 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(pd);
+mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 189c324..5e17110 100644
--- a/exec.c
+++ b/exec.c
@@ -1618,9 +1618,9 @@ static uint16_t dummy_section(MemoryRegion *mr)
return phys_section_add(§ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
-return address_space_memory.dispatch->sections[index &
~TARGET_PAGE_MASK].mr;
+return as->dispatch->sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b4dfc07..6129365 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,7 +324,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see
[Qemu-devel] [RFC PATCH 0/8] Steps towards per CPU address-spaces
From: "Edgar E. Iglesias" Hi, I'm looking at modelling a system where multiple CPUs co-exist with different views of their attached buses/devs. With this RFC series I'm trying to take small steps towards having an address-space per CPU. This is still incomplete but I would like to get comments early before changing to much. As there are no users in the tree yet, this code restructure should not result in any functional changes. Patch 6 shows an issue with circular header deps between qemu-common.h, cpu.h. I've got a branch with a possible solution to that but its very intrusive so I opted to keep that for later. Patch 8 shows a possible transform to ld*/st*_phys here only implemented for ldl_*_phys. Future work will have to transform more of the cpu_* bus accessing functions. Cheers, Edgar Edgar E. Iglesias (8): exec: Make tb_invalidate_phys_addr input an AS exec: Make iotlb_to_region input an AS exec: Always initialize MemorySection address spaces exec: Make memory_region_section_get_iotlb use section AS memory: Add MemoryListener to typedefs cpu: Add per-cpu address space exec: On AS changes, only flush affected CPU TLBs exec: Make ldl_*_phys input an AddressSpace cpu-exec.c|5 +- cputlb.c |4 +- exec.c| 64 +++ hw/dma/pl080.c|9 ++-- hw/dma/sun4m_iommu.c |3 +- hw/net/vmware_utils.h |2 +- hw/ppc/spapr_hcall.c |8 +-- hw/s390x/css.c|3 +- hw/s390x/s390-virtio-bus.c|2 +- hw/s390x/virtio-ccw.c |5 +- hw/scsi/megasas.c |4 +- hw/scsi/vmw_pvscsi.c |3 +- hw/virtio/virtio.c|3 +- include/exec/cpu-common.h |6 +-- include/exec/cpu-defs.h |3 ++ include/exec/exec-all.h |5 +- include/exec/softmmu_template.h |5 +- include/hw/ppc/spapr.h|2 +- include/qemu/typedefs.h |1 + include/qom/cpu.h |2 + target-alpha/helper.h |2 +- target-alpha/mem_helper.c |8 +-- target-alpha/translate.c |2 +- target-arm/helper.c | 12 ++--- target-i386/arch_memory_mapping.c | 36 ++--- target-i386/helper.c |8 +-- target-i386/seg_helper.c |4 +- target-i386/smm_helper.c | 102 +++-- target-i386/svm_helper.c | 26 +- target-ppc/excp_helper.c |2 +- target-ppc/mmu-hash32.h |4 +- target-s390x/cpu.c|2 +- target-sparc/ldst_helper.c|6 +-- target-sparc/mmu_helper.c | 18 +++ target-unicore32/softmmu.c|4 +- target-xtensa/helper.c|2 +- target-xtensa/op_helper.c |3 +- translate-all.c |4 +- 38 files changed, 215 insertions(+), 169 deletions(-) -- 1.7.10.4
[Qemu-devel] [RFC PATCH 6/8] cpu: Add per-cpu address space
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|4 ++--
exec.c | 31 +++
include/exec/cpu-defs.h |3 +++
include/exec/exec-all.h |1 +
include/exec/softmmu_template.h |4 ++--
include/qom/cpu.h |2 ++
6 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 0399172..a2264a3 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -254,7 +254,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
-section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+section = address_space_translate_for_iotlb(env->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
-mr = iotlb_to_region(&address_space_memory, pd);
+mr = iotlb_to_region(env1->as, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 0162eb3..acbd2e6 100644
--- a/exec.c
+++ b/exec.c
@@ -129,6 +129,7 @@ static PhysPageMap next_map;
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -361,6 +362,25 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+CPUArchState *env = cpu->env_ptr;
+
+if (tcg_enabled()) {
+if (cpu->tcg_as_listener) {
+memory_listener_unregister(cpu->tcg_as_listener);
+} else {
+cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+}
+cpu->tcg_as_listener->commit = tcg_commit;
+memory_listener_register(cpu->tcg_as_listener, as);
+}
+
+env->as = as;
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -380,6 +400,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+cpu_address_space_init(cpu, &address_space_memory);
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -409,9 +430,10 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
#else
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
+CPUArchState *env = cpu->env_ptr;
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(&address_space_memory,
+tb_invalidate_phys_addr(env->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1717,10 +1739,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
-.commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1755,9 +1773,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
-if (tcg_enabled()) {
-memory_listener_register(&tcg_memory_listener, &address_space_memory);
-}
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 01cd8c7..406b36c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -176,6 +176,9 @@ typedef struct CPUWatchpoint {
sigjmp_buf jmp_env; \
int exception_index;\
\
+/* Per CPU address-space. */ \
+AddressSpace *as; \
+\
/* user data */ \
void *opaque; \
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6129365..61770ee 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,6 +95,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUA
[Qemu-devel] [RFC PATCH 3/8] exec: Always initialize MemorySection address spaces
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index 5e17110..05df217 100644
--- a/exec.c
+++ b/exec.c
@@ -806,6 +806,7 @@ static void register_subpage(AddressSpaceDispatch *d,
MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&subsection));
@@ -1609,6 +1610,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr
base)
static uint16_t dummy_section(MemoryRegion *mr)
{
MemoryRegionSection section = {
+.address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.7.10.4
[Qemu-devel] [RFC PATCH 1/8] exec: Make tb_invalidate_phys_addr input an AS
From: "Edgar E. Iglesias"
No functional change.
Signed-off-by: Edgar E. Iglesias
---
exec.c|3 ++-
include/exec/exec-all.h |2 +-
target-xtensa/op_helper.c |3 ++-
translate-all.c |4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 95c4356..189c324 100644
--- a/exec.c
+++ b/exec.c
@@ -411,7 +411,8 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
-tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+tb_invalidate_phys_addr(&address_space_memory,
+phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ea90b64..b4dfc07 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -101,7 +101,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env,
uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
-tb_invalidate_phys_addr(paddr);
+tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index aeda54d..7596b8d 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1352,13 +1352,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
-mr = address_space_translate(&address_space_memory, addr, &addr, &l,
false);
+mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.7.10.4
[Qemu-devel] [RFC PATCH 5/8] memory: Add MemoryListener to typedefs
From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- include/qemu/typedefs.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index a4c1b84..425ca1a 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -24,6 +24,7 @@ typedef struct BusClass BusClass; typedef struct AddressSpace AddressSpace; typedef struct MemoryRegion MemoryRegion; typedef struct MemoryRegionSection MemoryRegionSection; +typedef struct MemoryListener MemoryListener; typedef struct MemoryMappingList MemoryMappingList; -- 1.7.10.4
[Qemu-devel] [RFC PATCH 8/8] exec: Make ldl_*_phys input an AddressSpace
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c|5 +-
exec.c| 19 ---
hw/dma/pl080.c|9 ++--
hw/dma/sun4m_iommu.c |3 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |8 +--
hw/s390x/css.c|3 +-
hw/s390x/s390-virtio-bus.c|2 +-
hw/s390x/virtio-ccw.c |5 +-
hw/scsi/megasas.c |4 +-
hw/scsi/vmw_pvscsi.c |3 +-
hw/virtio/virtio.c|3 +-
include/exec/cpu-common.h |6 +--
include/hw/ppc/spapr.h|2 +-
target-alpha/helper.h |2 +-
target-alpha/mem_helper.c |8 +--
target-alpha/translate.c |2 +-
target-arm/helper.c | 12 ++---
target-i386/arch_memory_mapping.c | 36 ++---
target-i386/helper.c |8 +--
target-i386/seg_helper.c |4 +-
target-i386/smm_helper.c | 102 +++--
target-i386/svm_helper.c | 26 +-
target-ppc/excp_helper.c |2 +-
target-ppc/mmu-hash32.h |4 +-
target-s390x/cpu.c|2 +-
target-sparc/ldst_helper.c|6 +--
target-sparc/mmu_helper.c | 18 +++
target-unicore32/softmmu.c|4 +-
target-xtensa/helper.c|2 +-
30 files changed, 163 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..8f6766b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -374,7 +374,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
-intno = ldl_phys(env->vm_vmcb + offsetof(struct
vmcb, control.int_vector));
+intno = ldl_phys(env->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing
virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index f273a46..ba67f98 100644
--- a/exec.c
+++ b/exec.c
@@ -1490,7 +1490,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
-case 4: return ldl_phys(addr);
+case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2216,7 +2216,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2225,8 +2225,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
-mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2259,19 +2258,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
-return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 35b9015..58556f3 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
-ch->src = ldl_le_phys(ch->lli);
-ch->dest = ldl_le_phys(ch->lli + 4);
-ch->ctrl
[Qemu-devel] [RFC PATCH 7/8] exec: On AS changes, only flush affected CPU TLBs
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |5 +
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index acbd2e6..f273a46 100644
--- a/exec.c
+++ b/exec.c
@@ -1715,6 +1715,11 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
+/* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+if (cpu->tcg_as_listener != listener) {
+continue;
+}
CPUArchState *env = cpu->env_ptr;
tlb_flush(env, 1);
--
1.7.10.4
[Qemu-devel] [PATCH 00/10] MicroBlaze queue
From: "Edgar E. Iglesias" Hi, These are various MicroBlaze patches sitting in my queue. A few optimizations, sysemu initrd boot loading support and improvement to the exclusive load/store for system emulation. Cheers, Edgar Edgar E. Iglesias (10): microblaze: Clarify expected input of write_carry microblaze: Make write_carryi input a boolean microblaze: Simplify andn by using tcg_gen_andc microblaze: Improve srl microblaze: Improve src microblaze: Move the saving of the reservation addr into gen_load microblaze: Turn res_addr into a tcg global microblaze: At swx, check that the reserved word is unmodified hw/microblaze: Indentation cleanups hw/microblaze: Add support for loading initrd images hw/microblaze/boot.c | 50 +--- hw/microblaze/boot.h |4 +- hw/microblaze/petalogix_ml605_mmu.c |6 ++- hw/microblaze/petalogix_s3adsp1800_mmu.c |4 +- target-microblaze/cpu.h |1 + target-microblaze/translate.c| 75 +- 6 files changed, 98 insertions(+), 42 deletions(-) -- 1.7.10.4
[Qemu-devel] [PATCH 02/10] microblaze: Make write_carryi input a boolean
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 76b2570..d183e17 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -166,10 +166,10 @@ static void write_carry(DisasContext *dc, TCGv v)
tcg_temp_free(t0);
}
-static void write_carryi(DisasContext *dc, int carry)
+static void write_carryi(DisasContext *dc, bool carry)
{
TCGv t0 = tcg_temp_new();
-tcg_gen_movi_tl(t0, carry ? 1 : 0);
+tcg_gen_movi_tl(t0, carry);
write_carry(dc, t0);
tcg_temp_free(t0);
}
--
1.7.10.4
[Qemu-devel] [PATCH 04/10] microblaze: Improve srl
From: "Edgar E. Iglesias"
write_carry only looks at bit zero, no need to mask out the others.
Meassured a 12% speed improvement in linux-user srl loops.
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c |7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 916db15..93aafac 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -780,13 +780,10 @@ static void dec_bit(DisasContext *dc)
case 0x1:
case 0x41:
/* srl. */
-t0 = tcg_temp_new();
LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
-/* Update carry. */
-tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
-write_carry(dc, t0);
-tcg_temp_free(t0);
+/* Update carry. Note that write carry only looks at the LSB. */
+write_carry(dc, cpu_R[dc->ra]);
if (dc->rd) {
if (op == 0x41)
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
--
1.7.10.4
[Qemu-devel] [PATCH 03/10] microblaze: Simplify andn by using tcg_gen_andc
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c |5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index d183e17..916db15 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -390,10 +390,7 @@ static void dec_and(DisasContext *dc)
return;
if (not) {
-TCGv t = tcg_temp_new();
-tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
-tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
-tcg_temp_free(t);
+tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
} else
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}
--
1.7.10.4
[Qemu-devel] [PATCH 01/10] microblaze: Clarify expected input of write_carry
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c |4
1 file changed, 4 insertions(+)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 1b937b3..76b2570 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -150,6 +150,10 @@ static void read_carry(DisasContext *dc, TCGv d)
tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
}
+/*
+ * write_carry sets the carry bits in MSR based on bit 0 of v.
+ * v[31:1] are ignored.
+ */
static void write_carry(DisasContext *dc, TCGv v)
{
TCGv t0 = tcg_temp_new();
--
1.7.10.4
[Qemu-devel] [PATCH 05/10] microblaze: Improve src
From: "Edgar E. Iglesias"
Microblaze carry is mirrored in MSR[31], pick it directly from
there. Also, no need to mask cpu_R[dc->ra] when calling
write_carry.
15% improvement in linux-user src loops.
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 93aafac..232015a 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -750,7 +750,7 @@ static void dec_barrel(DisasContext *dc)
static void dec_bit(DisasContext *dc)
{
-TCGv t0, t1;
+TCGv t0;
unsigned int op;
int mem_index = cpu_mmu_index(dc->env);
@@ -761,19 +761,12 @@ static void dec_bit(DisasContext *dc)
t0 = tcg_temp_new();
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
-tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
+tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC);
+write_carry(dc, cpu_R[dc->ra]);
if (dc->rd) {
-t1 = tcg_temp_new();
-read_carry(dc, t1);
-tcg_gen_shli_tl(t1, t1, 31);
-
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
-tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
-tcg_temp_free(t1);
+tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0);
}
-
-/* Update carry. */
-write_carry(dc, t0);
tcg_temp_free(t0);
break;
--
1.7.10.4
