[PATCH] docs:remove cxl3 device size
cxl device typ3 size is read from the memory backend device, removing the size option specified in cxl sample command. Updating sample command to reflect target architecture as x86_64. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..b228146cec 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -302,7 +302,7 @@ Example command lines - A very simple setup with just one directly attached CXL Type 3 device:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ @@ -315,7 +315,7 @@ A setup suitable for 4 way interleave. Only one fixed window provided, to enable interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with the CXL Type3 device directly attached (no switches).:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ @@ -339,7 +339,7 @@ the CXL Type3 device directly attached (no switches).:: An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M \ @@ -354,13 +354,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ -device cxl-upstream,bus=root_port0,id=us0 \ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ - -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,size=256M \ + -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ - -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,size=256M \ + -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ - -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,size=256M \ + -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ - -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,size=256M \ + -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k Kernel Configuration Options -- 2.34.1
[PATCH v1 1/2] docs/cxl: Remove incorrect CXL type 3 size parameter
cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..46f9ae9bf1 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -354,13 +354,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ -device cxl-upstream,bus=root_port0,id=us0 \ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ - -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,size=256M \ + -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ - -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,size=256M \ + -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ - -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,size=256M \ + -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ - -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,size=256M \ + -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k Kernel Configuration Options -- 2.34.1
[PATCH v1 0/2] Update CXL documentation
Thanks Jonathan for quick review/comments on earlier patch, as suggested splitting into two separate patches https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html Removed the unsupported size option for cxl-type3 device, Qemu reads the device size directly from the backend memory device config. Currently the Qemu CXL emulation for AARCH64 is not available and its only supported on x86_64 platform emulations. Removing the incorrect information and populating with supported x86_64 sample command to emulate cxl devices. The document will be updated when the AARCH64 support is mainlined. Raghu H (2): docs/cxl: Remove incorrect CXL type 3 size parameter docs/cxl: Replace unsupported AARCH64 with x86_64 docs/system/devices/cxl.rst | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) base-commit: 7d0334e49111787ae19fbc8d29ff6e7347f0605e -- 2.34.1
[PATCH v1 2/2] docs/cxl: Replace unsupported AARCH64 with x86_64
Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 46f9ae9bf1..c786f0f312 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -302,7 +302,8 @@ Example command lines - A very simple setup with just one directly attached CXL Type 3 device:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 \ + -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ @@ -315,7 +316,8 @@ A setup suitable for 4 way interleave. Only one fixed window provided, to enable interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with the CXL Type3 device directly attached (no switches).:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 \ + -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ @@ -339,7 +341,8 @@ the CXL Type3 device directly attached (no switches).:: An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 \ + -machine type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ ... -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M \ -- 2.34.1
[PATCH v2 2/2] docs/cxl: Replace unsupported AARCH64 with x86_64
Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 46f9ae9bf1..2ca5a78c51 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -302,7 +302,7 @@ Example command lines - A very simple setup with just one directly attached CXL Type 3 device:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ @@ -315,7 +315,7 @@ A setup suitable for 4 way interleave. Only one fixed window provided, to enable interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with the CXL Type3 device directly attached (no switches).:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ @@ -339,7 +339,7 @@ the CXL Type3 device directly attached (no switches).:: An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M \ -- 2.34.1
[PATCH v2 1/2] docs/cxl: Remove incorrect CXL type 3 size parameter
cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option Signed-off-by: Raghu H --- docs/system/devices/cxl.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..46f9ae9bf1 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -354,13 +354,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ -device cxl-upstream,bus=root_port0,id=us0 \ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ - -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,size=256M \ + -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ - -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,size=256M \ + -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ - -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,size=256M \ + -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ - -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,size=256M \ + -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k Kernel Configuration Options -- 2.34.1
[PATCH v1 0/2] Update CXL documentation
Thanks Jonathan for quick review/comments on earlier patch, as suggested splitting into two separate patches https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html Removed the unsupported size option for cxl-type3 device, Qemu reads the device size directly from the backend memory device config. Currently the Qemu CXL emulation for AARCH64 is not available and its only supported on x86_64 platform emulations. Removing the incorrect information and populating with supported x86_64 sample command to emulate cxl devices. The document will be updated when the AARCH64 support is mainlined. Raghu H (2): docs/cxl: Remove incorrect CXL type 3 size parameter docs/cxl: Replace unsupported AARCH64 with x86_64 docs/system/devices/cxl.rst | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) base-commit: 7d0334e49111787ae19fbc8d29ff6e7347f0605e -- 2.34.1
Re: [PATCH v1 0/2] Update CXL documentation
Thanks Jonathan! I assume it will be merged sometime later with your other patches in the 8.x version! On Thu, Apr 13, 2023 at 2:58 PM Jonathan Cameron wrote: > > On Thu, 6 Apr 2023 18:58:37 +0530 > Raghu H wrote: > > > Thanks Jonathan for quick review/comments on earlier patch, as suggested > > splitting into two separate patches > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html > > > > Removed the unsupported size option for cxl-type3 device, Qemu reads > > the device size directly from the backend memory device config. > > > > Currently the Qemu CXL emulation for AARCH64 is not available and its > > only supported on x86_64 platform emulations. Removing the incorrect > > information and populating with supported x86_64 sample command to > > emulate cxl devices. > > > > The document will be updated when the AARCH64 support is mainlined. > > Both look good to me. No need to rush these in. > > I'll queue these up in my local tree (and update gitlab/jic23/qemu > sometime later this week) but if anyone wants to pick > them directly that's fine too. > > Reviewed-by: Jonathan Cameron > > > > > > > Raghu H (2): > > docs/cxl: Remove incorrect CXL type 3 size parameter > > docs/cxl: Replace unsupported AARCH64 with x86_64 > > > > docs/system/devices/cxl.rst | 17 ++--- > > 1 file changed, 10 insertions(+), 7 deletions(-) > > > > > > base-commit: 7d0334e49111787ae19fbc8d29ff6e7347f0605e >
Error : "cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log"
Hello, I am using qemu config listed in CXL documentation to emulate CXL device -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ -object memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M \ -object memory-backend-file,id=cxl-mem4,share=on,mem-path=/tmp/cxltest4.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ -object memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M \ -object memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M \ -object memory-backend-file,id=cxl-lsa4,share=on,mem-path=/tmp/lsa4.raw,size=256M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ -device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ -device cxl-type3,bus=root_port14,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ -device cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ -device cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k Kernel logs show cxl_pci module error while setting up irq (cxl_event_irqsetup in drivers/cxl/pci.c) cxl_pci :0d:00.0: Failed to get interrupt for event Info log [3.984800] cxl_pci :e0:00.0: Failed to get interrupt for event Info log [3.984841] cxl_pci :df:00.0: Failed to get interrupt for event Info log Is this expected in an emulated environment? Regards Raghu
Re: Error : "cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log"
Hi Jonathan, The log is from the upstream version. I have your repo, I can work on it if you provide some basic details like the commit ID. Regards Raghu On Fri, Apr 21, 2023 at 6:05 PM Jonathan Cameron wrote: > > On Thu, 20 Apr 2023 18:07:40 +0530 > RAGHU H wrote: > > > Hello, > > > > I am using qemu config listed in CXL documentation to emulate CXL device > > > > > > -object > > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-mem4,share=on,mem-path=/tmp/cxltest4.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M > > \ > > -object > > memory-backend-file,id=cxl-lsa4,share=on,mem-path=/tmp/lsa4.raw,size=256M > > \ > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > -device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 > > \ > > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ > > -device cxl-type3,bus=root_port14,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 > > \ > > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ > > -device cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 > > \ > > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ > > -device cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 > > \ > > -M > > cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k > > > > Kernel logs show cxl_pci module error while setting up irq > > (cxl_event_irqsetup in drivers/cxl/pci.c) > > > > cxl_pci :0d:00.0: Failed to get interrupt for event Info log > > [3.984800] cxl_pci :e0:00.0: Failed to get interrupt for event Info > > log > > [3.984841] cxl_pci :df:00.0: Failed to get interrupt for event Info > > log > > > > > > Is this expected in an emulated environment? > > Upstream QEMU? Or a version of my staging tree? > > Upstream doesn't support events logs yet, so this may the outcome of that. > It missed the 8.0 cycle due to some problems with other series that I'd > based it on top of. Hopefully will start to get those resolved shortly > and get as far as events support this cycle. > > Thanks, > > Jonathan > > > > > Regards > > Raghu >
