[Qemu-devel] [PATCH v5 00/15] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller
This series reworks the SSI bus framework for SPI and add some new SPI controllers and devices: Patches 1-5 reworks SSI to add chip-select support to SPI devices and allow for multiple SPI devices attach ed to the same bus. Patches 6-7 fix the SPI setup in the stellaris machine model. Patch 8 is a trivial cleanup I did along the way. Patch 9 is a general FIFO helper API used by the upcomming patches. Patch 10 is a device model for the m25p80 SPI flash family. Patches 11 & 13 are the Xilinx SPI flash controller devices Patches 12 & 14 add SPI controllers to the ML605 and Zynq machine models. Patch 15 is Maintainerships. CHANGELOG: changed from v4 (Major changes): Completely reworked SPI refactor. Please re-review from scratch. Added Zynq SPI flash. Factored out FIFO functionality from SPI flash controller. changed from v3: addressed reviewer comments from P Maydell and S Hajnoczi added patch 5 (re Paul Brooks request) changed from v2: folded former SPI bus functionality into existing SSI infrastructure (suggested - Paul Brook) (all patches) made m25p80 use async io (suggested - Stefan Hajnoczi) (2/4) instantiated two spi flashes instead of one in ml605 ref design (4/4) changed from v1: minor sylistic changes (1/4) converted spi api to modified txrx style (1-3/4) heavily refactored m25p80 model (2/4) Peter A. G. Crosthwaite (15): ssi: Support for multiple attached devices ssi: Added VMSD stub ssi: Implemented CS behaviour ssi: Added create_slave_no_init() qdev: allow multiple qdev_init_gpio_in() calls hw/stellaris: Removed gpio_out init array. stellaris: Removed SSI mux ssd0323: abort() instead of exit(1) on error. hw: Added generic FIFO API. m25p80: Initial implementation of SPI flash device xilinx_spi: Initial impl. of Xilinx SPI controller petalogix-ml605: added SPI controller with n25q128 xilinx_spips: Xilinx Zynq SPI cntrlr device model xilinx_zynq: Added SPI controllers + flashes MAINTAINERS: Added maintainerships for SSI MAINTAINERS |8 + default-configs/arm-softmmu.mak |1 + default-configs/microblaze-softmmu.mak |2 + default-configs/microblazeel-softmmu.mak |2 + hw/Makefile.objs |2 + hw/ads7846.c |1 + hw/arm/Makefile.objs |1 + hw/fifo.c| 79 hw/fifo.h| 47 +++ hw/m25p80.c | 572 ++ hw/max111x.c |1 + hw/microblaze/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 28 ++- hw/qdev.c| 16 +- hw/spitz.c |2 + hw/ssd0323.c | 11 +- hw/ssi-sd.c |7 + hw/ssi.c | 76 - hw/ssi.h | 38 ++ hw/stellaris.c | 111 ++- hw/xilinx_spi.c | 390 hw/xilinx_spips.c| 352 ++ hw/xilinx_zynq.c | 34 ++ hw/z2.c |1 + 24 files changed, 1675 insertions(+), 108 deletions(-) create mode 100644 hw/fifo.c create mode 100644 hw/fifo.h create mode 100644 hw/m25p80.c create mode 100644 hw/xilinx_spi.c create mode 100644 hw/xilinx_spips.c
[Qemu-devel] [PATCH v5 01/15] ssi: Support for multiple attached devices
Removed assertion that only one device is attached to the SSI bus.
When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is active, and if not returning 0. The returned data is the logical or of
all responses from the (mulitple) devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssi.c | 24 +---
1 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/ssi.c b/hw/ssi.c
index e5f14a0..35d0a04 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -2,6 +2,8 @@
* QEMU Synchronous Serial Interface support
*
* Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
* Written by Paul Brook
*
* This code is licensed under the GNU GPL v2.
@@ -29,14 +31,6 @@ static int ssi_slave_init(DeviceState *dev)
{
SSISlave *s = SSI_SLAVE(dev);
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
-SSIBus *bus;
-BusChild *kid;
-
-bus = FROM_QBUS(SSIBus, qdev_get_parent_bus(dev));
-kid = QTAILQ_FIRST(&bus->qbus.children);
-if (kid->child != dev || QTAILQ_NEXT(kid, sibling) != NULL) {
-hw_error("Too many devices on SSI bus");
-}
return ssc->init(s);
}
@@ -74,16 +68,16 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char
*name)
uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
{
BusChild *kid;
-SSISlave *slave;
SSISlaveClass *ssc;
+uint32_t r = 0;
-kid = QTAILQ_FIRST(&bus->qbus.children);
-if (!kid) {
-return 0;
+QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+SSISlave *slave = SSI_SLAVE(kid->child);
+ssc = SSI_SLAVE_GET_CLASS(slave);
+r |= ssc->transfer(slave, val);
}
-slave = SSI_SLAVE(kid->child);
-ssc = SSI_SLAVE_GET_CLASS(slave);
-return ssc->transfer(slave, val);
+
+return r;
}
static void ssi_slave_register_types(void)
--
1.7.0.4
[Qemu-devel] [PATCH v5 11/15] xilinx_spi: Initial impl. of Xilinx SPI controller
Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4 (Near total rewrite):
removed timer delay. This was innacturate anyways removed for simlicity.
updated for new SSI interface.
factored out txrx fifos using fifo.h
changed from v3:
typedef'd struct XilinxSPI
changed unsigned int -> uin32_t
removed unused vars (c_fifo_exist and cmd_ongoing)
txfifo_reset removed duplicate s->regs[R_SPISR] &= ~SR_TX_FULL (PMM review)
reset: changed to Device Class style reset
reset: stope the ptimer (pmm review)
xlx_spi_update_irq: dont -> don't (PMM review)
init: set irq_line to 1 (force refresh on vmsd load)
init: dropped call to reset
implemetned vmsd
changed from v2:
converted spi api to ssi api
changed from v1:
converted spi api to modified txrx style
hw/microblaze/Makefile.objs |1 +
hw/xilinx_spi.c | 390 +++
2 files changed, 391 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_spi.c
diff --git a/hw/microblaze/Makefile.objs b/hw/microblaze/Makefile.objs
index 274d2c5..3028e65 100644
--- a/hw/microblaze/Makefile.objs
+++ b/hw/microblaze/Makefile.objs
@@ -1,6 +1,7 @@
obj-y = petalogix_s3adsp1800_mmu.o
obj-y += petalogix_ml605_mmu.o
obj-y += microblaze_boot.o
+obj-y += xilinx_spi.o
obj-y += microblaze_pic_cpu.o
obj-y += xilinx_ethlite.o
diff --git a/hw/xilinx_spi.c b/hw/xilinx_spi.c
new file mode 100644
index 000..933858f
--- /dev/null
+++ b/hw/xilinx_spi.c
@@ -0,0 +1,390 @@
+/*
+ * QEMU model of the Xilinx SPI Controller
+ *
+ * Copyright (C) 2010 Edgar E. Iglesias.
+ * Copyright (C) 2012 Peter A. G. Crosthwaite
+ * Copyright (C) 2012 PetaLogix
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu.h"
+#include "qemu-log.h"
+#include "fifo.h"
+
+#include "ssi.h"
+
+#ifdef XILINX_SPI_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+#define R_DGIER (0x1c / 4)
+#define R_DGIER_IE (1 << 31)
+
+#define R_IPISR (0x20 / 4)
+#define IRQ_DRR_NOT_EMPTY(1 << (31 - 23))
+#define IRQ_DRR_OVERRUN (1 << (31 - 26))
+#define IRQ_DRR_FULL (1 << (31 - 27))
+#define IRQ_TX_FF_HALF_EMPTY (1 << 6)
+#define IRQ_DTR_UNDERRUN (1 << 3)
+#define IRQ_DTR_EMPTY(1 << (31 - 29))
+
+#define R_IPIER (0x28 / 4)
+#define R_SRR (0x40 / 4)
+#define R_SPICR (0x60 / 4)
+#define R_SPICR_TXFF_RST (1 << 5)
+#define R_SPICR_RXFF_RST (1 << 6)
+#define R_SPICR_MTI (1 << 8)
+
+#define R_SPISR (0x64 / 4)
+#define SR_TX_FULL(1 << 3)
+#define SR_TX_EMPTY (1 << 2)
+#define SR_RX_FULL(1 << 1)
+#define SR_RX_EMPTY (1 << 0)
+
+#define R_SPIDTR(0x68 / 4)
+#define R_SPIDRR(0x6C / 4)
+#define R_SPISSR(0x70 / 4)
+#define R_TX_FF_OCY (0x74 / 4)
+#define R_RX_FF_OCY (0x78 / 4)
+#define R_MAX (0x7C / 4)
+
+#define FIFO_CAPACITY 256
+
+typedef struct XilinxSPI {
+SysBusDevice busdev;
+MemoryRegion mmio;
+
+qemu_irq irq;
+int irqline;
+
+uint8_t num_cs;
+qemu_irq *cs_lines;
+
+SSIBus *spi;
+
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+
+uint32_t regs[R_MAX];
+} XilinxSPI;
+
+static void txfifo_reset(XilinxSPI *s)
+{
+fifo8_reset(&s->tx_fifo);
+
+s->regs[R_SPISR] &= ~SR_TX_FULL;
+s->regs[R_SPISR] |= SR_TX_EMPTY;
+}
+
+static void rxfifo_reset(XilinxSPI *s)
+{
+fifo8_reset(&s->rx_fifo);
+
+s->regs[R_SPISR] |= SR_RX_EMPTY;
+s->regs[R_SPISR] &= ~SR_RX_FULL;
+}
+
+static void xlx_spi_update_cs(XilinxSPI *s)
+{
+ int i;
+
+for (i = 0; i < s->num_cs; ++i
[Qemu-devel] [PATCH v5 14/15] xilinx_zynq: Added SPI controllers + flashes
Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx_zynq.c | 34 ++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 7e6c273..e273711 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -24,6 +24,9 @@
#include "flash.h"
#include "blockdev.h"
#include "loader.h"
+#include "ssi.h"
+
+#define NUM_SPI_FLASHES 2
#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)
@@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq
irq)
sysbus_connect_irq(s, 0, irq);
}
+static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *busdev;
+SSIBus *spi;
+int i;
+
+dev = qdev_create(NULL, "xilinx,spips");
+qdev_init_nofail(dev);
+busdev = sysbus_from_qdev(dev);
+sysbus_mmio_map(busdev, 0, base_addr);
+sysbus_connect_irq(busdev, 0, irq);
+
+spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
+
+for (i = 0; i < NUM_SPI_FLASHES; ++i) {
+qemu_irq cs_line;
+
+dev = ssi_create_slave_no_init(spi, "m25p80");
+qdev_prop_set_string(dev, "partname", (char *)"n25q128");
+qdev_init_nofail(dev);
+
+cs_line = qdev_get_gpio_in(dev, 0);
+sysbus_connect_irq(busdev, i+1, cs_line);
+}
+
+}
+
static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char
*kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
pic[n] = qdev_get_gpio_in(dev, n);
}
+zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]);
+zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]);
+
sysbus_create_simple("cadence_uart", 0xE000, pic[59-IRQ_OFFSET]);
sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
--
1.7.0.4
[Qemu-devel] [PATCH v5 13/15] xilinx_spips: Xilinx Zynq SPI cntrlr device model
Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/arm/Makefile.objs |1 +
hw/xilinx_spips.c| 352 ++
2 files changed, 353 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_spips.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index c413780..bb5a5ba 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -6,6 +6,7 @@ obj-y += cadence_uart.o
obj-y += cadence_ttc.o
obj-y += cadence_gem.o
obj-y += xilinx_zynq.o zynq_slcr.o
+obj-y += xilinx_spips.o
obj-y += arm_gic.o arm_gic_common.o
obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
new file mode 100644
index 000..7aa8e4a
--- /dev/null
+++ b/hw/xilinx_spips.c
@@ -0,0 +1,352 @@
+/*
+ * QEMU model of the Xilinx Zynq SPI controller
+ *
+ * Copyright (c) 2012 Peter A. G. Crosthwaite
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu.h"
+#include "ptimer.h"
+#include "qemu-log.h"
+#include "fifo.h"
+#include "ssi.h"
+
+#ifdef XILINX_SPIPS_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+/* config register */
+#define R_CONFIG(0x00 / 4)
+#define MODEFAIL_GEN_EN (1 << 17)
+#define MAN_START_COM (1 << 16)
+#define MAN_START_EN(1 << 15)
+#define MANUAL_CS (1 << 14)
+#define CS (0xF << 10)
+#define CS_SHIFT(10)
+#define PERI_SEL(1 << 9)
+#define REF_CLK (1 << 8)
+#define FIFO_WIDTH (3 << 6)
+#define BAUD_RATE_DIV (7 << 3)
+#define CLK_PH (1 << 2)
+#define CLK_POL (1 << 1)
+#define MODE_SEL(1 << 1)
+
+/* interrupt mechanism */
+#define R_INTR_STATUS (0x04 / 4)
+#define R_INTR_EN (0x08 / 4)
+#define R_INTR_DIS (0x0C / 4)
+#define R_INTR_MASK (0x10 / 4)
+#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
+#define IXR_RX_FIFO_FULL(1 << 5)
+#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
+#define IXR_TX_FIFO_FULL(1 << 3)
+#define IXR_TX_FIFO_NOT_FULL(1 << 2)
+#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
+#define IXR_RX_FIFO_OVERFLOW(1 << 0)
+#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
+
+#define R_EN(0x14 / 4)
+#define R_DELAY (0x18 / 4)
+#define R_TX_DATA (0x1C / 4)
+#define R_RX_DATA (0x20 / 4)
+#define R_SLAVE_IDLE_COUNT (0x24 / 4)
+#define R_TX_THRES (0x28 / 4)
+#define R_RX_THRES (0x2C / 4)
+#define R_MOD_ID(0xFC / 4)
+
+#define R_MAX (R_MOD_ID+1)
+
+/* size of TXRX FIFOs */
+#define NUM_CS_LINES4
+#define RXFF_A 32
+#define TXFF_A 32
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq irq;
+int irqline;
+
+qemu_irq cs_lines[NUM_CS_LINES];
+SSIBus *spi;
+
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+
+uint32_t regs[R_MAX];
+} XilinxSPIPS;
+
+static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
+{
+int i;
+bool found = false;
+int field = s->regs[R_CONFIG] >> CS_SHIFT;
+
+for (i = 0; i < NUM_CS_LINES; i++) {
+if (~field & (1 << i) & !found) {
+found = true;
+DB_PRINT("selecting slave %d\n", i);
+qemu_set_irq(s->cs_lines[i], 0);
+} else {
+qemu_set_irq(s->cs_lines[i], 1);
+}
+ }
+}
+
+static v
[Qemu-devel] [PATCH v5 10/15] m25p80: Initial implementation of SPI flash device
Added device model for m25p80 style SPI flash family.
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4:
Added write-1 flag (EEPROM mode).
n25q128 table entry indentation fix.
updated for new SSI interface.
various debug messages cleaned up and added.
changed from v3:
changed licence to v2 or later (PMM review)
generalised device model - rather than being fixed to the fl064k, it can handle
a wide range of m25p80 devices
refactored erase commands (previously they were fl064k specific and used
spansions broken terminology)
typdef'd strcuts and enums
fixed some camel casing
added comment to explain why bdrv_sync_complete is a nop (PMM review)
removed hardcoded "512" for BDRV_SECTOR_SIZE
flash_sync_area: use bdrv_aio_writev instead of bdrv_write
flash_chip_erase/flash_block_erase32k/flash_sector_erase: consolidated to one
function
decode_new_cmd: fixed multi-statement lines (PMM review)
CHIP_ERASE->BULK_ERASE
init: drive_get -> drive_get_next (PMM review)
changed from v2:
updated for SSI slave interface
used async io (suggested - Stefan Hajnoczi)
changed from v1:
converted spi api to modified txrx style
factored out lots of common code and inlined overly short single call functions.
undated for txrx style spi interface
default-configs/arm-softmmu.mak |1 +
default-configs/microblaze-softmmu.mak |2 +
default-configs/microblazeel-softmmu.mak |2 +
hw/Makefile.objs |1 +
hw/m25p80.c | 572 ++
5 files changed, 578 insertions(+), 0 deletions(-)
create mode 100644 hw/m25p80.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index e542b4f..ce5ff25 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -22,6 +22,7 @@ CONFIG_ADS7846=y
CONFIG_MAX111X=y
CONFIG_SSI=y
CONFIG_SSI_SD=y
+CONFIG_SSI_M25P80=y
CONFIG_LAN9118=y
CONFIG_SMC91C111=y
CONFIG_DS1338=y
diff --git a/default-configs/microblaze-softmmu.mak
b/default-configs/microblaze-softmmu.mak
index 64c9485..2f442e5 100644
--- a/default-configs/microblaze-softmmu.mak
+++ b/default-configs/microblaze-softmmu.mak
@@ -5,3 +5,5 @@ CONFIG_PFLASH_CFI01=y
CONFIG_SERIAL=y
CONFIG_XILINX=y
CONFIG_XILINX_AXI=y
+CONFIG_SSI=y
+CONFIG_SSI_M25P80=y
diff --git a/default-configs/microblazeel-softmmu.mak
b/default-configs/microblazeel-softmmu.mak
index a962276..af9a3cd 100644
--- a/default-configs/microblazeel-softmmu.mak
+++ b/default-configs/microblazeel-softmmu.mak
@@ -5,3 +5,5 @@ CONFIG_PFLASH_CFI01=y
CONFIG_SERIAL=y
CONFIG_XILINX=y
CONFIG_XILINX_AXI=y
+CONFIG_SSI=y
+CONFIG_SSI_M25P80=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 6ba570e..e6a94d6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -143,6 +143,7 @@ common-obj-y += scsi-disk.o cdrom.o hd-geometry.o
block-common.o
common-obj-y += scsi-generic.o scsi-bus.o
common-obj-y += hid.o
common-obj-$(CONFIG_SSI) += ssi.o
+common-obj-$(CONFIG_SSI_M25P80) += m25p80.o
common-obj-$(CONFIG_SSI_SD) += ssi-sd.o
common-obj-$(CONFIG_SD) += sd.o
common-obj-y += bt.o bt-l2cap.o bt-sdp.o bt-hci.o bt-hid.o
diff --git a/hw/m25p80.c b/hw/m25p80.c
new file mode 100644
index 000..389adf6
--- /dev/null
+++ b/hw/m25p80.c
@@ -0,0 +1,572 @@
+/*
+ * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80
command
+ * set. Known devices table current as of Jun/2012 and taked from linux.
+ * See drivers/mtd/devices/m25p80.c.
+ *
+ * Copyright (C) 2011 Edgar E. Iglesias
+ * Copyright (C) 2012 Peter A. G. Crosthwaite
+ * Copyright (C) 2012 PetaLogix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) a later version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw.h"
+#include "blockdev.h"
+#include "ssi.h"
+#include "devices.h"
+
+#ifdef M25P80_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+typedef struct FlashPartInfo {
+const char *part_name;
+/* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
+uint32_t jedec;
+/* extended jedec code */
+uint16_t ext_jedec;
+/* there is confusion between manufacturers as to what a sector is. In this
+ * device model, a "sector" is the si
[Qemu-devel] [PATCH v5 02/15] ssi: Added VMSD stub
Added VMSD stub for SSI slaves. Fields may be added to this VMSD for generic
SSI slave state (e.g. the CS line state).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ads7846.c |1 +
hw/max111x.c |1 +
hw/spitz.c |2 ++
hw/ssi.c | 10 ++
hw/ssi.h | 10 ++
hw/stellaris.c |1 +
hw/z2.c|1 +
7 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/hw/ads7846.c b/hw/ads7846.c
index 41c7f10..6a523f6 100644
--- a/hw/ads7846.c
+++ b/hw/ads7846.c
@@ -124,6 +124,7 @@ static const VMStateDescription vmstate_ads7846 = {
.minimum_version_id_old = 0,
.post_load = ads7856_post_load,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, ADS7846State),
VMSTATE_INT32_ARRAY(input, ADS7846State, 8),
VMSTATE_INT32(noise, ADS7846State),
VMSTATE_INT32(cycle, ADS7846State),
diff --git a/hw/max111x.c b/hw/max111x.c
index 706d89f..948fd97 100644
--- a/hw/max111x.c
+++ b/hw/max111x.c
@@ -103,6 +103,7 @@ static const VMStateDescription vmstate_max111x = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, MAX111xState),
VMSTATE_UINT8(tb1, MAX111xState),
VMSTATE_UINT8(rb2, MAX111xState),
VMSTATE_UINT8(rb3, MAX111xState),
diff --git a/hw/spitz.c b/hw/spitz.c
index 20e7835..f5d502d 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -1087,6 +1087,7 @@ static const VMStateDescription vmstate_corgi_ssp_regs = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
+VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
VMSTATE_END_OF_LIST(),
}
@@ -1115,6 +1116,7 @@ static const VMStateDescription vmstate_spitz_lcdtg_regs
= {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
+VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
VMSTATE_UINT32(bl_power, SpitzLCDTG),
VMSTATE_END_OF_LIST(),
diff --git a/hw/ssi.c b/hw/ssi.c
index 35d0a04..2db88fc 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -80,6 +80,16 @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
return r;
}
+const VMStateDescription vmstate_ssi_slave = {
+.name = "SSISlave",
+.version_id = 1,
+.minimum_version_id = 1,
+.minimum_version_id_old = 1,
+.fields = (VMStateField[]) {
+VMSTATE_END_OF_LIST()
+}
+};
+
static void ssi_slave_register_types(void)
{
type_register_static(&ssi_bus_info);
diff --git a/hw/ssi.h b/hw/ssi.h
index 06657d7..975f9fb 100644
--- a/hw/ssi.h
+++ b/hw/ssi.h
@@ -38,6 +38,16 @@ struct SSISlave {
#define SSI_SLAVE_FROM_QDEV(dev) DO_UPCAST(SSISlave, qdev, dev)
#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
+extern const VMStateDescription vmstate_ssi_slave;
+
+#define VMSTATE_SSI_SLAVE(_field, _state) { \
+.name = (stringify(_field)), \
+.size = sizeof(SSISlave), \
+.vmsd = &vmstate_ssi_slave,\
+.flags = VMS_STRUCT,\
+.offset = vmstate_offset_value(_state, _field, SSISlave),\
+}
+
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
/* Master interface. */
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 562fbbf..4d26857 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1188,6 +1188,7 @@ static const VMStateDescription vmstate_stellaris_ssi_bus
= {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, stellaris_ssi_bus_state),
VMSTATE_INT32(current_dev, stellaris_ssi_bus_state),
VMSTATE_END_OF_LIST()
}
diff --git a/hw/z2.c b/hw/z2.c
index 289cee9..721aaf1 100644
--- a/hw/z2.c
+++ b/hw/z2.c
@@ -165,6 +165,7 @@ static VMStateDescription vmstate_zipit_lcd_state = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, ZipitLCD),
VMSTATE_INT32(selected, ZipitLCD),
VMSTATE_INT32(enabled, ZipitLCD),
VMSTATE_BUFFER(buf, ZipitLCD),
--
1.7.0.4
[Qemu-devel] [PATCH v5 03/15] ssi: Implemented CS behaviour
Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |6 ++
hw/ssi-sd.c |6 ++
hw/ssi.c | 39 ++-
hw/ssi.h | 27 +++
4 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index b0b2e94..db16d20 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -277,6 +277,7 @@ static void ssd0323_cd(void *opaque, int n, int level)
static void ssd0323_save(QEMUFile *f, void *opaque)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
@@ -294,10 +295,13 @@ static void ssd0323_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->remap);
qemu_put_be32(f, s->mode);
qemu_put_buffer(f, s->framebuffer, sizeof(s->framebuffer));
+
+qemu_put_be32(f, ss->cs ? 1 : 0);
}
static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
@@ -319,6 +323,8 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int
version_id)
s->mode = qemu_get_be32(f);
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
+ss->cs = !!qemu_get_be32(f);
+
return 0;
}
diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c
index b519bdb..6fd9ab9 100644
--- a/hw/ssi-sd.c
+++ b/hw/ssi-sd.c
@@ -197,6 +197,7 @@ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
static void ssi_sd_save(QEMUFile *f, void *opaque)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
@@ -209,10 +210,13 @@ static void ssi_sd_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->arglen);
qemu_put_be32(f, s->response_pos);
qemu_put_be32(f, s->stopping);
+
+qemu_put_be32(f, ss->cs ? 1 : 0);
}
static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
@@ -229,6 +233,8 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int
version_id)
s->response_pos = qemu_get_be32(f);
s->stopping = qemu_get_be32(f);
+ss->cs = !!qemu_get_be32(f);
+
return 0;
}
diff --git a/hw/ssi.c b/hw/ssi.c
index 2db88fc..2e4f2fe 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -27,19 +27,55 @@ static const TypeInfo ssi_bus_info = {
.instance_size = sizeof(SSIBus),
};
+static void ssi_cs_default(void *opaque, int n, int level)
+{
+SSISlave *s = SSI_SLAVE(opaque);
+bool cs = !!level;
+assert(n == 0);
+if (s->cs != cs) {
+SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
+if (ssc->set_cs) {
+ssc->set_cs(s, cs);
+}
+}
+s->cs = cs;
+}
+
+static uint32_t ssi_transfer_raw_default(SSISlave *dev, uint32_t val)
+{
+SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(dev);
+
+if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
+(!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
+ssc->cs_polarity == SSI_CS_NONE) {
+return ssc->transfer(dev, val);
+}
+return 0;
+}
+
static int ssi_slave_init(DeviceState *dev)
{
SSISlave *s = SSI_SLAVE(dev);
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
+if (ssc->transfer_raw == ssi_transfer_raw_default &&
+ssc->cs_polarity != SSI_CS_NONE) {
+qdev_init_gpio_in(&s->qdev, ssi_cs_default, 1);
+}
+
return ssc->init(s);
}
static void ssi_slave_class_init(ObjectClass *klass, void *data)
{
+SSISlaveClass *ssc = SSI_SLAVE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+
dc->init = ssi_slave_init;
dc->bus_type = TYPE_SSI_BUS;
+if (!ssc->transfer_raw) {
+ssc->transfer_raw = ssi_transfer_raw_default;
+}
}
static TypeInfo ssi_slave_info = {
@@ -74,7 +110,7 @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
SSISlave *slave = SSI_SLAVE(kid->child);
ssc = SSI_SLAVE_GET_CLASS(slave);
-r |= ssc->transfer(slave, val);
+r |= ssc->transfer_raw(slave, val);
}
return r;
@@ -86,6 +122,7 @@ const VMStateDescription vmstate_ssi_slave = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
+VMSTATE_BOOL(cs, SSISlave),
VMSTATE_END_OF_LIST()
}
};
diff --git a/hw/ssi.h b/hw/ssi.h
index 975f9fb..5b69a3b 100644
--- a/hw/ssi.h
+++ b/hw/ssi.h
@@ -23,16 +23,43 @@ typedef struct SSISlave SSISlave;
#define SSI_SLAVE_GET_CLASS(obj) \
OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAV
[Qemu-devel] [PATCH v5 06/15] hw/stellaris: Removed gpio_out init array.
stellaris_init() defines arrays of qemu_irq to decides what each of the GPIO
pins are connected to. This is ok for inputs (as an input can only have one
source) but is flawed for outputs as an output can connect to any number of
sinks. Removed the gpio_out array completely and just replaced its setters with
direct calls to qdev_connect_gpio_out().
Signed-off-by: Peter A. G. Crosthwaite
---
hw/stellaris.c | 26 --
1 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 4d26857..ec55c0e 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1244,7 +1244,6 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
qemu_irq *pic;
DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8];
-qemu_irq gpio_out[7][8];
qemu_irq adc;
int sram_size;
int flash_size;
@@ -1284,8 +1283,9 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
pic[gpio_irq[i]]);
for (j = 0; j < 8; j++) {
gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
-gpio_out[i][j] = NULL;
}
+} else {
+gpio_dev[i] = NULL;
}
}
@@ -1308,20 +1308,27 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
if (board->peripherals & BP_OLED_SSI) {
DeviceState *mux;
void *bus;
+qemu_irq select_pin;
bus = qdev_get_child_bus(dev, "ssi");
mux = ssi_create_slave(bus, "evb6965-ssi");
-gpio_out[GPIO_D][0] = qdev_get_gpio_in(mux, 0);
+select_pin = qdev_get_gpio_in(mux, 0);
+if (gpio_dev[GPIO_D]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0, select_pin);
+}
bus = qdev_get_child_bus(mux, "ssi0");
ssi_create_slave(bus, "ssi-sd");
bus = qdev_get_child_bus(mux, "ssi1");
dev = ssi_create_slave(bus, "ssd0323");
-gpio_out[GPIO_C][7] = qdev_get_gpio_in(dev, 0);
+if (gpio_dev[GPIO_C]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_C], 7,
+qdev_get_gpio_in(dev, 0));
+}
/* Make sure the select pin is high. */
-qemu_irq_raise(gpio_out[GPIO_D][0]);
+qemu_irq_raise(select_pin);
}
}
if (board->dc4 & (1 << 28)) {
@@ -1347,15 +1354,6 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
}
-for (i = 0; i < 7; i++) {
-if (board->dc4 & (1 << i)) {
-for (j = 0; j < 8; j++) {
-if (gpio_out[i][j]) {
-qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
-}
-}
-}
-}
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
--
1.7.0.4
[Qemu-devel] [PATCH v5 15/15] MAINTAINERS: Added maintainerships for SSI
Added maintainership for SSI, M25P80 and the Xilinx SPI controllers. Signed-off-by: Peter A. G. Crosthwaite --- MAINTAINERS |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2d219d2..0f28f19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -268,6 +268,7 @@ S: Maintained F: hw/xilinx_zynq.c F: hw/zynq_slcr.c F: hw/cadence_* +F: hw/xilinx_spips.c CRIS Machines - @@ -455,6 +456,12 @@ M: Paul Brook S: Odd Fixes F: hw/lsi53c895a.c +SSI +M: Peter Crosthwaite +S: Maintained +F: hw/ssi.* +F: hw/m25p80.c + USB M: Gerd Hoffmann S: Maintained @@ -498,6 +505,7 @@ F: hw/xilinx_intc.c F: hw/xilinx_ethlite.c F: hw/xilinx_timer.c F: hw/xilinx.h +F: hw/xilinx_spi.c Subsystems -- -- 1.7.0.4
[Qemu-devel] [PATCH v5 08/15] ssd0323: abort() instead of exit(1) on error.
To be more consistent with the newer ways of error signalling. That and SIGABT
is easier to debug with than exit(1).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index d8a0c14..0800866 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -19,7 +19,9 @@
#define DPRINTF(fmt, ...) \
do { printf("ssd0323: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
-do { fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); exit(1);} while
(0)
+do { \
+fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); abort(); \
+} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
--
1.7.0.4
[Qemu-devel] [PATCH v5 05/15] qdev: allow multiple qdev_init_gpio_in() calls
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy both
define GPIO functionality, as a single GPIO handler with an index selecter is
not possible.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/qdev.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index b5b74b9..ce91a72 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -293,9 +293,19 @@ BusState *qdev_get_parent_bus(DeviceState *dev)
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n)
{
-assert(dev->num_gpio_in == 0);
-dev->num_gpio_in = n;
-dev->gpio_in = qemu_allocate_irqs(handler, dev, n);
+qemu_irq *new_irqs = qemu_allocate_irqs(handler, dev, n);
+
+if (dev->num_gpio_in == 0) {
+dev->gpio_in = qemu_allocate_irqs(handler, dev, n);
+} else {
+qemu_irq *all_irqs = g_new(qemu_irq, n + dev->num_gpio_in);
+memcpy(all_irqs, dev->gpio_in, sizeof(*all_irqs) * dev->num_gpio_in);
+g_free(dev->gpio_in);
+memcpy(&all_irqs[dev->num_gpio_in], new_irqs, sizeof(*all_irqs) * n),
+g_free(new_irqs);
+dev->gpio_in = all_irqs;
+}
+dev->num_gpio_in += n;
}
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n)
--
1.7.0.4
[Qemu-devel] [PATCH v5 09/15] hw: Added generic FIFO API.
Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/fifo.c| 79 ++
hw/fifo.h| 47
3 files changed, 127 insertions(+), 0 deletions(-)
create mode 100644 hw/fifo.c
create mode 100644 hw/fifo.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..6ba570e 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -15,6 +15,7 @@ hw-obj-$(CONFIG_ECC) += ecc.o
hw-obj-$(CONFIG_NAND) += nand.o
hw-obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o
hw-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
+hw-obj-y += fifo.o
hw-obj-$(CONFIG_M48T59) += m48t59.o
hw-obj-$(CONFIG_ESCC) += escc.o
diff --git a/hw/fifo.c b/hw/fifo.c
new file mode 100644
index 000..5e14e1e
--- /dev/null
+++ b/hw/fifo.c
@@ -0,0 +1,79 @@
+/*
+ * Generic FIFO component, implemented as a circular buffer.
+ *
+ * Copyright (c) 2012 Peter A. G. Crosthwaite
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "fifo.h"
+
+void fifo8_create(Fifo8 *fifo, uint32_t capacity)
+{
+fifo->data = g_new(uint8_t, capacity);
+fifo->capacity = capacity;
+fifo->head = 0;
+fifo->num = 0;
+}
+
+void fifo8_destroy(Fifo8 *fifo)
+{
+g_free(fifo->data);
+}
+
+void fifo8_push(Fifo8 *fifo, uint8_t data)
+{
+if (fifo->num == fifo->capacity) {
+abort();
+}
+fifo->data[(fifo->head + fifo->num) % fifo->capacity] = data;
+fifo->num++;
+}
+
+uint8_t fifo8_pop(Fifo8 *fifo)
+{
+uint8_t ret;
+
+if (fifo->num == 0) {
+abort();
+}
+ret = fifo->data[fifo->head++];
+fifo->head %= fifo->capacity;
+fifo->num--;
+return ret;
+}
+
+void fifo8_reset(Fifo8 *fifo)
+{
+fifo->num = 0;
+}
+
+bool fifo8_is_empty(Fifo8 *fifo)
+{
+return (fifo->num == 0);
+}
+
+bool fifo8_is_full(Fifo8 *fifo)
+{
+return (fifo->num == fifo->capacity);
+}
+
+const VMStateDescription vmstate_fifo8 = {
+.name = "SSISlave",
+.version_id = 1,
+.minimum_version_id = 1,
+.minimum_version_id_old = 1,
+.fields = (VMStateField[]) {
+VMSTATE_VBUFFER_UINT32(data, Fifo8, 1, NULL, 0, capacity),
+VMSTATE_UINT32(head, Fifo8),
+VMSTATE_UINT32(num, Fifo8),
+VMSTATE_END_OF_LIST()
+}
+};
+
diff --git a/hw/fifo.h b/hw/fifo.h
new file mode 100644
index 000..3fb09ff
--- /dev/null
+++ b/hw/fifo.h
@@ -0,0 +1,47 @@
+#ifndef FIFO_H
+#define FIFO_H
+
+#include "hw.h"
+
+typedef struct {
+/* All fields are private */
+uint8_t *data;
+uint32_t capacity;
+uint32_t head;
+uint32_t num;
+} Fifo8;
+
+/* create a fifo of the specified size */
+
+void fifo8_create(Fifo8 *, uint32_t);
+
+/* cleanup a fifo */
+
+void fifo8_destroy(Fifo8 *);
+
+/* push a data byte to the fifo. Behaviour is undefined if the fifo is full */
+
+void fifo8_push(Fifo8 *, uint8_t);
+
+/* pop a data byte from the fifo. Behviour is undefined if the fifo is empty */
+
+uint8_t fifo8_pop(Fifo8 *);
+
+/* reset (empty) the fifo */
+
+void fifo8_reset(Fifo8 *);
+
+bool fifo8_is_empty(Fifo8 *);
+bool fifo8_is_full(Fifo8 *);
+
+extern const VMStateDescription vmstate_fifo8;
+
+#define VMSTATE_FIFO8(_field, _state) { \
+.name = (stringify(_field)), \
+.size = sizeof(Fifo8), \
+.vmsd = &vmstate_fifo8,\
+.flags = VMS_STRUCT,\
+.offset = vmstate_offset_value(_state, _field, Fifo8), \
+}
+
+#endif /* FIFO_H */
--
1.7.0.4
[Qemu-devel] [PATCH v5 07/15] stellaris: Removed SSI mux
Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |1 +
hw/ssi-sd.c|1 +
hw/stellaris.c | 98 ++--
3 files changed, 19 insertions(+), 81 deletions(-)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index db16d20..d8a0c14 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -352,6 +352,7 @@ static void ssd0323_class_init(ObjectClass *klass, void
*data)
k->init = ssd0323_init;
k->transfer = ssd0323_transfer;
+k->cs_polarity = SSI_CS_HIGH;
}
static TypeInfo ssd0323_info = {
diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c
index 6fd9ab9..1b1f625 100644
--- a/hw/ssi-sd.c
+++ b/hw/ssi-sd.c
@@ -256,6 +256,7 @@ static void ssi_sd_class_init(ObjectClass *klass, void
*data)
k->init = ssi_sd_init;
k->transfer = ssi_sd_transfer;
+k->cs_polarity = SSI_CS_LOW;
}
static TypeInfo ssi_sd_info = {
diff --git a/hw/stellaris.c b/hw/stellaris.c
index ec55c0e..acb297b 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1154,58 +1154,6 @@ static int stellaris_adc_init(SysBusDevice *dev)
return 0;
}
-/* Some boards have both an OLED controller and SD card connected to
- the same SSI port, with the SD card chip select connected to a
- GPIO pin. Technically the OLED chip select is connected to the SSI
- Fss pin. We do not bother emulating that as both devices should
- never be selected simultaneously, and our OLED controller ignores stray
- 0xff commands that occur when deselecting the SD card. */
-
-typedef struct {
-SSISlave ssidev;
-qemu_irq irq;
-int current_dev;
-SSIBus *bus[2];
-} stellaris_ssi_bus_state;
-
-static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
-{
-stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
-
-s->current_dev = level;
-}
-
-static uint32_t stellaris_ssi_bus_transfer(SSISlave *dev, uint32_t val)
-{
-stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
-
-return ssi_transfer(s->bus[s->current_dev], val);
-}
-
-static const VMStateDescription vmstate_stellaris_ssi_bus = {
-.name = "stellaris_ssi_bus",
-.version_id = 1,
-.minimum_version_id = 1,
-.minimum_version_id_old = 1,
-.fields = (VMStateField[]) {
-VMSTATE_SSI_SLAVE(ssidev, stellaris_ssi_bus_state),
-VMSTATE_INT32(current_dev, stellaris_ssi_bus_state),
-VMSTATE_END_OF_LIST()
-}
-};
-
-static int stellaris_ssi_bus_init(SSISlave *dev)
-{
-stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
-
-s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
-s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
-qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
-
-vmstate_register(&dev->qdev, -1, &vmstate_stellaris_ssi_bus, s);
-return 0;
-}
-
/* Board init. */
static stellaris_board_info stellaris_boards[] = {
{ "LM3S811EVB",
@@ -1306,29 +1254,33 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
if (board->dc2 & (1 << 4)) {
dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
if (board->peripherals & BP_OLED_SSI) {
-DeviceState *mux;
void *bus;
-qemu_irq select_pin;
+/* Some boards have both an OLED controller and SD card connected
to
+ * the same SSI port, with the SD card chip select connected to a
+ * GPIO pin. Technically the OLED chip select is connected to the
+ * SSI Fss pin. We do not bother emulating that as both devices
+ * should never be selected simultaneously, and our OLED controller
+ * ignores stray 0xff commands that occur when deselecting the SD
+ * card.
+ */
bus = qdev_get_child_bus(dev, "ssi");
-mux = ssi_create_slave(bus, "evb6965-ssi");
-select_pin = qdev_get_gpio_in(mux, 0);
+
+dev = ssi_create_slave(bus, "ssi-sd");
if (gpio_dev[GPIO_D]) {
-qdev_connect_gpio_out(gpio_dev[GPIO_D], 0, select_pin);
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0,
+qdev_get_gpio_in(dev, 0));
}
-bus = qdev_get_child_bus(mux, "ssi0");
-ssi_create_slave(bus, "ssi-sd");
-
-bus = qdev_get_child_bus(mux, "ssi1");
dev = ssi_create_slave(bus, "ssd0323");
+if (gpio_dev[GPIO_D]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0,
+qdev_get_gpio_in(dev, 0));
+}
if (gpio_dev[GPIO_C]) {
qdev_connec
[Qemu-devel] [PATCH v5 12/15] petalogix-ml605: added SPI controller with n25q128
Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/petalogix_ml605_mmu.c | 28 +++-
1 files changed, 27 insertions(+), 1 deletions(-)
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 6a7d0c0..f0ecc1f 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -36,6 +36,7 @@
#include "blockdev.h"
#include "pc.h"
#include "exec-memory.h"
+#include "ssi.h"
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
@@ -54,6 +55,8 @@
#define AXIENET_BASEADDR 0x8278
#define AXIDMA_BASEADDR 0x8460
+#define NUM_SPI_FLASHES 2
+
static void machine_cpu_reset(MicroBlazeCPU *cpu)
{
CPUMBState *env = &cpu->env;
@@ -78,6 +81,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
MicroBlazeCPU *cpu;
+SysBusDevice *busdev;
CPUMBState *env;
DriveInfo *dinfo;
int i;
@@ -135,9 +139,31 @@ petalogix_ml605_init(ram_addr_t ram_size,
irq[1], irq[0], 100 * 100);
}
+{
+SSIBus *spi;
+
+dev = qdev_create(NULL, "xilinx,spi");
+qdev_prop_set_uint8(dev, "num-cs", NUM_SPI_FLASHES);
+qdev_init_nofail(dev);
+busdev = sysbus_from_qdev(dev);
+sysbus_mmio_map(busdev, 0, 0x40a0);
+sysbus_connect_irq(busdev, 0, irq[4]);
+
+spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
+
+for (i = 0; i < NUM_SPI_FLASHES; i++) {
+qemu_irq cs_line;
+
+dev = ssi_create_slave_no_init(spi, "m25p80");
+qdev_prop_set_string(dev, "partname", (char *)"n25q128");
+qdev_init_nofail(dev);
+cs_line = qdev_get_gpio_in(dev, 0);
+sysbus_connect_irq(busdev, i+1, cs_line);
+}
+}
+
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
-
}
static QEMUMachine petalogix_ml605_machine = {
--
1.7.0.4
[Qemu-devel] [PATCH v5 04/15] ssi: Added create_slave_no_init()
Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a change to set properties.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssi.c |9 +++--
hw/ssi.h |1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/ssi.c b/hw/ssi.c
index 2e4f2fe..c47419d 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -86,10 +86,15 @@ static TypeInfo ssi_slave_info = {
.abstract = true,
};
+DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name)
+{
+return qdev_create(&bus->qbus, name);
+}
+
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
{
-DeviceState *dev;
-dev = qdev_create(&bus->qbus, name);
+DeviceState *dev = ssi_create_slave_no_init(bus, name);
+
qdev_init_nofail(dev);
return dev;
}
diff --git a/hw/ssi.h b/hw/ssi.h
index 5b69a3b..80b9664 100644
--- a/hw/ssi.h
+++ b/hw/ssi.h
@@ -76,6 +76,7 @@ extern const VMStateDescription vmstate_ssi_slave;
}
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
+DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name);
/* Master interface. */
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
--
1.7.0.4
[Qemu-devel] [PULL 0/2] QOMify AXI stream for Xilinx AXI ethernet/DMA
are available in the git repository at: git://developer.petalogix.com/public/qemu.git for-upstream/axi-stream.next Anthony Liguori (1): qom: Reimplement Interfaces Peter A. G. Crosthwaite (1): xilinx_axi*: Re-implemented interconnect hw/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 24 +++-- hw/stream.c | 23 + hw/stream.h | 31 +++ hw/xilinx.h | 22 ++--- hw/xilinx_axidma.c | 74 +--- hw/xilinx_axidma.h | 39 hw/xilinx_axienet.c | 32 --- include/qemu/object.h| 46 ++ qom/object.c | 220 ++ 10 files changed, 255 insertions(+), 257 deletions(-) create mode 100644 hw/stream.c create mode 100644 hw/stream.h delete mode 100644 hw/xilinx_axidma.h
[Qemu-devel] [PATCH 1/2] qom: Reimplement Interfaces
From: Anthony Liguori
The current implementation of Interfaces is poorly designed. Each interface
that an object implements ends up being an object that's tracked by the
implementing object. There's all sorts of gymnastics to deal with casting
between these objects.
But an interface shouldn't be associated with an Object. Interfaces are global
to a class. This patch moves all Interface knowledge to ObjectClass eliminating
the relationship between Object and Interfaces.
Interfaces are now abstract (as they should be) but this is okay. Interfaces
essentially act as additional parents for the classes and are treated as such.
With this new implementation, we should fully support derived interfaces
including reimplementing an inherited interface.
PC: Rebased against qom-next merge Jun-2012.
PC: Removed replication of cast logic for interfaces, i.e. there is only
one cast function - object_dynamic_cast() (and object_dynamic_cast_assert())
Signed-off-by: Anthony Liguori
Signed-off-by: Peter A. G. Crosthwaite
---
include/qemu/object.h | 46 +++
qom/object.c | 220 +++--
2 files changed, 116 insertions(+), 150 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index 8b17776..cc75fee 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -239,6 +239,7 @@ struct ObjectClass
{
/*< private >*/
Type type;
+GSList *interfaces;
};
/**
@@ -260,7 +261,6 @@ struct Object
{
/*< private >*/
ObjectClass *class;
-GSList *interfaces;
QTAILQ_HEAD(, ObjectProperty) properties;
uint32_t ref;
Object *parent;
@@ -387,6 +387,16 @@ struct TypeInfo
OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name)
/**
+ * InterfaceInfo:
+ * @type: The name of the interface.
+ *
+ * The information associated with an interface.
+ */
+struct InterfaceInfo {
+const char *type;
+};
+
+/**
* InterfaceClass:
* @parent_class: the base class
*
@@ -396,26 +406,30 @@ struct TypeInfo
struct InterfaceClass
{
ObjectClass parent_class;
+/*< private >*/
+ObjectClass *concrete_class;
};
+#define TYPE_INTERFACE "interface"
+
/**
- * InterfaceInfo:
- * @type: The name of the interface.
- * @interface_initfn: This method is called during class initialization and is
- * used to initialize an interface associated with a class. This function
- * should initialize any default virtual functions for a class and/or
override
- * virtual functions in a parent class.
- *
- * The information associated with an interface.
+ * INTERFACE_CLASS:
+ * @klass: class to cast from
+ * Returns: An #InterfaceClass or raise an error if cast is invalid
*/
-struct InterfaceInfo
-{
-const char *type;
+#define INTERFACE_CLASS(klass) \
+OBJECT_CLASS_CHECK(InterfaceClass, klass, TYPE_INTERFACE)
-void (*interface_initfn)(ObjectClass *class, void *data);
-};
-
-#define TYPE_INTERFACE "interface"
+/**
+ * INTERFACE_CHECK:
+ * @interface: the type to return
+ * @obj: the object to convert to an interface
+ * @name: the interface type name
+ *
+ * Returns: @obj casted to @interface if cast is valid, otherwise raise error.
+ */
+#define INTERFACE_CHECK(interface, obj, name) \
+((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name)))
/**
* object_new:
diff --git a/qom/object.c b/qom/object.c
index 00bb3b0..a552be2 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -31,9 +31,7 @@ typedef struct TypeImpl TypeImpl;
struct InterfaceImpl
{
-const char *parent;
-void (*interface_initfn)(ObjectClass *class, void *data);
-TypeImpl *type;
+const char *typename;
};
struct TypeImpl
@@ -64,14 +62,6 @@ struct TypeImpl
InterfaceImpl interfaces[MAX_INTERFACES];
};
-typedef struct Interface
-{
-Object parent;
-Object *obj;
-} Interface;
-
-#define INTERFACE(obj) OBJECT_CHECK(Interface, obj, TYPE_INTERFACE)
-
static Type type_interface;
static GHashTable *type_table_get(void)
@@ -98,6 +88,7 @@ static TypeImpl *type_table_lookup(const char *name)
static TypeImpl *type_register_internal(const TypeInfo *info)
{
TypeImpl *ti = g_malloc0(sizeof(*ti));
+int i;
g_assert(info->name != NULL);
@@ -122,15 +113,10 @@ static TypeImpl *type_register_internal(const TypeInfo
*info)
ti->abstract = info->abstract;
-if (info->interfaces) {
-int i;
-
-for (i = 0; info->interfaces[i].type; i++) {
-ti->interfaces[i].parent = info->interfaces[i].type;
-ti->interfaces[i].interface_initfn =
info->interfaces[i].interface_initfn;
-ti->num_interfaces++;
-}
+for (i = 0; info->interfaces && info->interfaces[i].type; i++) {
+ti->interfaces[i].typename = g_strdup(info->interfaces[i].type);
}
+ti->num_interfaces = i;
type_table_add(ti);
[Qemu-devel] [PATCH 2/2] xilinx_axi*: Re-implemented interconnect
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
controllers. A QOM interface "stream" is created, for the two stream interfaces.
As per Edgars request, this is designed to be more generic than AXI-stream,
so in the future we may see more clients of this interface beyond AXI stream.
This is based primarily on Paolos original refactoring of the interconnect.
Signed-off-by: Paolo Bonzini
Signed-off-by: Peter A.G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/petalogix_ml605_mmu.c | 24 +--
hw/stream.c | 23 ++
hw/stream.h | 31 +++
hw/xilinx.h | 22 +
hw/xilinx_axidma.c | 74 +
hw/xilinx_axidma.h | 39
hw/xilinx_axienet.c | 32 ---
8 files changed, 139 insertions(+), 107 deletions(-)
create mode 100644 hw/stream.c
create mode 100644 hw/stream.h
delete mode 100644 hw/xilinx_axidma.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..a2d537d 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -65,6 +65,7 @@ hw-obj-$(CONFIG_XILINX) += xilinx_timer.o
hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+hw-obj-$(CONFIG_XILINX_AXI) += stream.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 6a7d0c0..dced648 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -39,7 +39,8 @@
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
-#include "xilinx_axidma.h"
+
+#include "stream.h"
#define LMB_BRAM_SIZE (128 * 1024)
#define FLASH_SIZE (32 * 1024 * 1024)
@@ -76,7 +77,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
-DeviceState *dev;
+DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
CPUMBState *env;
DriveInfo *dinfo;
@@ -125,15 +126,18 @@ petalogix_ml605_init(ram_addr_t ram_size,
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 100);
-/* axi ethernet and dma initialization. TODO: Dynamically connect them. */
-{
-static struct XilinxDMAConnection dmach;
+/* axi ethernet and dma initialization. */
+dma = qdev_create(NULL, "xlnx.axi-dma");
-xilinx_axiethernet_create(&dmach, &nd_table[0], 0x8278,
- irq[3], 0x1000, 0x1000);
-xilinx_axiethernetdma_create(&dmach, 0x8460,
- irq[1], irq[0], 100 * 100);
-}
+/* FIXME: attach to the sysbus instead */
+object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ "xilinx-dma", OBJECT(dma), NULL);
+
+eth0 = xilinx_axiethernet_create(&nd_table[0], STREAM_SLAVE(dma),
+ 0x8278, irq[3], 0x1000, 0x1000);
+
+xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
+ 0x8460, irq[1], irq[0], 100 * 100);
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
diff --git a/hw/stream.c b/hw/stream.c
new file mode 100644
index 000..001e2bd
--- /dev/null
+++ b/hw/stream.c
@@ -0,0 +1,23 @@
+#include "stream.h"
+
+void
+axi_stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app)
+{
+StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+
+k->push(sink, buf, len, app);
+}
+
+static TypeInfo axi_stream_slave_info = {
+.name = TYPE_STREAM_SLAVE,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(StreamSlaveClass),
+};
+
+
+static void axi_stream_slave_register_types(void)
+{
+type_register_static(&axi_stream_slave_info);
+}
+
+type_init(axi_stream_slave_register_types)
diff --git a/hw/stream.h b/hw/stream.h
new file mode 100644
index 000..b7f3b3e
--- /dev/null
+++ b/hw/stream.h
@@ -0,0 +1,31 @@
+#ifndef STREAM_H
+#define STREAM_H 1
+
+#include "qemu-common.h"
+#include "qemu/object.h"
+
+/* AXI stream slave. Used until qdev provides a generic way. */
+#define TYPE_STREAM_SLAVE "stream-slave"
+
+#define STREAM_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE(obj) \
+ INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
+
+typedef struct StreamSlave {
+Object Parent;
+} StreamSlave;
+
+typedef struct StreamSlaveClass {
+InterfaceClass parent;
+
+void (*push)(StreamSlave *obj, unsigned char *buf, size_t
[Qemu-devel] [PATCH v6 0/4] Standard SD host controller model
[Original cover by Igor] First patch introduces standard SD host controller model. This is accumulated version of my previous patch I sent a while ago and a recent SDHCI patch by Peter A. G. Crosthwaite. Second patch introduces Exynos4210-specific SDHCI built on top of standard SDHCI model. [New] Third patch changes the -sd command line argument to be repeatable, to support multiple SD controllers in one system. Fourth patch adds 2x SDHCI controllers to the Xilinx Zynq machine This revision is typo fixes and rebasing only. Changelog: Changed from v5: Igors IRQ changes RE PMM review. Changed from v4: Igors changes re PMM review (P1/2) Typo in commit msg (P3) removed redundant braces in P4 Changed from v3: Rebased for new Makefile system Fixed include guard in sdhci.h Typos in commit messages Changed from v2: corrected typo errors in ADMA1 support added patches 3-4 v1->v2 PATCH1: add support for ADMA1 (I havn't tested it though). fixed s->prnsts <-> s->pwrcon typo (thanks to Peter, strange that it even worked before). PATCH2: change header prefix from "target-arm" to "exynos4210". Peter A. G. Crosthwaite (2): vl.c: allow for repeated -sd arguments xilinx_zynq: Added SD controllers *** BLURB HERE *** Igor Mitsyanko (2): hw: introduce standard SD host controller exynos4210: Added SD host controller model Peter A. G. Crosthwaite (2): vl.c: allow for repeated -sd arguments xilinx_zynq: Added SD controllers default-configs/arm-softmmu.mak |1 + hw/Makefile.objs|1 + hw/arm/Makefile.objs|1 + hw/exynos4210.c | 20 + hw/exynos4210_sdhci.c | 444 ++ hw/sdhci.c | 1262 +++ hw/sdhci.h | 309 ++ hw/xilinx_zynq.c| 10 + vl.c|2 +- 9 files changed, 2049 insertions(+), 1 deletions(-) create mode 100644 hw/exynos4210_sdhci.c create mode 100644 hw/sdhci.c create mode 100644 hw/sdhci.h
[Qemu-devel] [PATCH v6 2/4] exynos4210: Added SD host controller model
From: Igor Mitsyanko
Custom Exynos4210 SD/MMC host controller, based on SD association standard host
controller ver. 2.00.
Signed-off-by: Igor Mitsyanko
---
changed from v5 (Igor):
Updated for new IRQ system
changed from v4 (Igor):
set irq on SLOTINT status instead of interrupt registers status; instead;
conditional in exynos4210_sdhci_can_issue_command() made more readable and
documented;
add a comment to exynos4210_sdhci_writefn()'s SDHC_CLKCON case statement;
do not override superclass property in exynos4210.sdhci class, set properties
to required value in realize function
changed from v3:
rebased for new Makefile system
fixed commit msg typo (Andreas review)
hw/arm/Makefile.objs |1 +
hw/exynos4210.c | 20 +++
hw/exynos4210_sdhci.c | 444 +
3 files changed, 465 insertions(+), 0 deletions(-)
create mode 100644 hw/exynos4210_sdhci.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 236786e..4cc1002 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -12,6 +12,7 @@ obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
obj-y += exynos4210_pmu.o exynos4210_mct.o exynos4210_fimd.o
obj-y += exynos4210_rtc.o
+obj-y += exynos4210_sdhci.o
obj-y += arm_l2x0.o
obj-y += arm_mptimer.o a15mpcore.o
obj-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
diff --git a/hw/exynos4210.c b/hw/exynos4210.c
index 7c58c90..eb35407 100644
--- a/hw/exynos4210.c
+++ b/hw/exynos4210.c
@@ -59,6 +59,12 @@
#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x1044
#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
+/* SD/MMC host controllers SFR base addresses */
+#define EXYNOS4210_SDHC0_BASE_ADDR 0x1251
+#define EXYNOS4210_SDHC1_BASE_ADDR 0x1252
+#define EXYNOS4210_SDHC2_BASE_ADDR 0x1253
+#define EXYNOS4210_SDHC3_BASE_ADDR 0x1254
+
/* PMU SFR base address */
#define EXYNOS4210_PMU_BASE_ADDR0x1002
@@ -300,6 +306,20 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP,
3)]);
+/*** SD/MMC host controllers ***/
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC0_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 0)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC1_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 1)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC2_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 2)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC3_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 3)]);
+
/*** Display controller (FIMD) ***/
sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
s->irq_table[exynos4210_get_irq(11, 0)],
diff --git a/hw/exynos4210_sdhci.c b/hw/exynos4210_sdhci.c
new file mode 100644
index 000..84917f9
--- /dev/null
+++ b/hw/exynos4210_sdhci.c
@@ -0,0 +1,444 @@
+/*
+ * Samsung Exynos4210 SD/MMC host controller model
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Mitsyanko Igor
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see
[Qemu-devel] [PATCH v6 4/4] xilinx_zynq: Added SD controllers
The Xilinx Zynq device has two SDHCI controllers. Added to the machine model. Signed-off-by: Peter A. G. Crosthwaite Reviewed-by: Peter Maydell --- changed from v4: removed redundant braces changed from v3: fixed indentation tweaked commit msg hw/xilinx_zynq.c | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..a7feabe 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -130,6 +130,16 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, } } +dev = qdev_create(NULL, "sdhci"); +qdev_init_nofail(dev); +sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xE010); +sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[56-IRQ_OFFSET]); + +dev = qdev_create(NULL, "sdhci"); +qdev_init_nofail(dev); +sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xE0101000); +sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[79-IRQ_OFFSET]); + zynq_binfo.ram_size = ram_size; zynq_binfo.kernel_filename = kernel_filename; zynq_binfo.kernel_cmdline = kernel_cmdline; -- 1.7.0.4
[Qemu-devel] [PATCH v6 3/4] vl.c: allow for repeated -sd arguments
Allows for repeating of -sd arguments in the same way as -pflash and -mtdblock. Signed-off-by: Peter A. G. Crosthwaite Acked-by: Igor Mitsyanko Reviewed-by: Peter Maydell --- changed from v4: fixed (another) commit msg typo changed from v3: fixed commit msg typo vl.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/vl.c b/vl.c index 1329c30..fe1f33b 100644 --- a/vl.c +++ b/vl.c @@ -2431,7 +2431,7 @@ int main(int argc, char **argv, char **envp) drive_add(IF_MTD, -1, optarg, MTD_OPTS); break; case QEMU_OPTION_sd: -drive_add(IF_SD, 0, optarg, SD_OPTS); +drive_add(IF_SD, -1, optarg, SD_OPTS); break; case QEMU_OPTION_pflash: drive_add(IF_PFLASH, -1, optarg, PFLASH_OPTS); -- 1.7.0.4
[Qemu-devel] [PATCH] arm: translate: comment typo - s/middel/middle/
Signed-off-by: Peter A. G. Crosthwaite
---
target-arm/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 29008a4..494c682 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9892,7 +9892,7 @@ static inline void
gen_intermediate_code_internal(CPUARMState *env,
} else {
/* While branches must always occur at the end of an IT block,
there are a few other things that can cause us to terminate
- the TB in the middel of an IT block:
+ the TB in the middle of an IT block:
- Exception generating instructions (bkpt, swi, undefined).
- Page boundaries.
- Hardware watchpoints.
--
1.7.0.4
[Qemu-devel] [PATCH] armv7m: Guard against no -kernel argument
A -kernel argument must be specified for this machine. Gaurd against no -kernel
argument. Previously gave an unhelpful "bad address" error message.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/armv7m.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 8cec78d..9f7 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -227,6 +227,11 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
big_endian = 0;
#endif
+if (!kernel_filename) {
+fprintf(stderr, "Guest image must be specified (using -kernel)\n");
+exit(1);
+}
+
image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
NULL, big_endian, ELF_MACHINE, 1);
if (image_size < 0) {
--
1.7.0.4
[Qemu-devel] [PULL 0/2] QOMify AXI stream for Xilinx AXI ethernet/DMA
are available in the git repository at: git://developer.petalogix.com/public/qemu.git ..BRANCH.NOT.VERIFIED.. Anthony Liguori (1): qom: Reimplement Interfaces Peter A. G. Crosthwaite (1): xilinx_axi*: Re-implemented interconnect hw/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 24 +++-- hw/stream.c | 23 + hw/stream.h | 31 +++ hw/xilinx.h | 22 ++--- hw/xilinx_axidma.c | 74 +--- hw/xilinx_axidma.h | 39 hw/xilinx_axienet.c | 32 --- include/qemu/object.h| 46 ++ qom/object.c | 220 ++ 10 files changed, 255 insertions(+), 257 deletions(-) create mode 100644 hw/stream.c create mode 100644 hw/stream.h delete mode 100644 hw/xilinx_axidma.h
[Qemu-devel] [PATCH 1/2] qom: Reimplement Interfaces
From: Anthony Liguori
The current implementation of Interfaces is poorly designed. Each interface
that an object implements ends up being an object that's tracked by the
implementing object. There's all sorts of gymnastics to deal with casting
between these objects.
But an interface shouldn't be associated with an Object. Interfaces are global
to a class. This patch moves all Interface knowledge to ObjectClass eliminating
the relationship between Object and Interfaces.
Interfaces are now abstract (as they should be) but this is okay. Interfaces
essentially act as additional parents for the classes and are treated as such.
With this new implementation, we should fully support derived interfaces
including reimplementing an inherited interface.
PC: Rebased against qom-next merge Jun-2012.
PC: Removed replication of cast logic for interfaces, i.e. there is only
one cast function - object_dynamic_cast() (and object_dynamic_cast_assert())
Signed-off-by: Anthony Liguori
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Paolo Bonzini
---
include/qemu/object.h | 46 +++
qom/object.c | 220 +++--
2 files changed, 116 insertions(+), 150 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index 8b17776..cc75fee 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -239,6 +239,7 @@ struct ObjectClass
{
/*< private >*/
Type type;
+GSList *interfaces;
};
/**
@@ -260,7 +261,6 @@ struct Object
{
/*< private >*/
ObjectClass *class;
-GSList *interfaces;
QTAILQ_HEAD(, ObjectProperty) properties;
uint32_t ref;
Object *parent;
@@ -387,6 +387,16 @@ struct TypeInfo
OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name)
/**
+ * InterfaceInfo:
+ * @type: The name of the interface.
+ *
+ * The information associated with an interface.
+ */
+struct InterfaceInfo {
+const char *type;
+};
+
+/**
* InterfaceClass:
* @parent_class: the base class
*
@@ -396,26 +406,30 @@ struct TypeInfo
struct InterfaceClass
{
ObjectClass parent_class;
+/*< private >*/
+ObjectClass *concrete_class;
};
+#define TYPE_INTERFACE "interface"
+
/**
- * InterfaceInfo:
- * @type: The name of the interface.
- * @interface_initfn: This method is called during class initialization and is
- * used to initialize an interface associated with a class. This function
- * should initialize any default virtual functions for a class and/or
override
- * virtual functions in a parent class.
- *
- * The information associated with an interface.
+ * INTERFACE_CLASS:
+ * @klass: class to cast from
+ * Returns: An #InterfaceClass or raise an error if cast is invalid
*/
-struct InterfaceInfo
-{
-const char *type;
+#define INTERFACE_CLASS(klass) \
+OBJECT_CLASS_CHECK(InterfaceClass, klass, TYPE_INTERFACE)
-void (*interface_initfn)(ObjectClass *class, void *data);
-};
-
-#define TYPE_INTERFACE "interface"
+/**
+ * INTERFACE_CHECK:
+ * @interface: the type to return
+ * @obj: the object to convert to an interface
+ * @name: the interface type name
+ *
+ * Returns: @obj casted to @interface if cast is valid, otherwise raise error.
+ */
+#define INTERFACE_CHECK(interface, obj, name) \
+((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name)))
/**
* object_new:
diff --git a/qom/object.c b/qom/object.c
index 00bb3b0..a552be2 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -31,9 +31,7 @@ typedef struct TypeImpl TypeImpl;
struct InterfaceImpl
{
-const char *parent;
-void (*interface_initfn)(ObjectClass *class, void *data);
-TypeImpl *type;
+const char *typename;
};
struct TypeImpl
@@ -64,14 +62,6 @@ struct TypeImpl
InterfaceImpl interfaces[MAX_INTERFACES];
};
-typedef struct Interface
-{
-Object parent;
-Object *obj;
-} Interface;
-
-#define INTERFACE(obj) OBJECT_CHECK(Interface, obj, TYPE_INTERFACE)
-
static Type type_interface;
static GHashTable *type_table_get(void)
@@ -98,6 +88,7 @@ static TypeImpl *type_table_lookup(const char *name)
static TypeImpl *type_register_internal(const TypeInfo *info)
{
TypeImpl *ti = g_malloc0(sizeof(*ti));
+int i;
g_assert(info->name != NULL);
@@ -122,15 +113,10 @@ static TypeImpl *type_register_internal(const TypeInfo
*info)
ti->abstract = info->abstract;
-if (info->interfaces) {
-int i;
-
-for (i = 0; info->interfaces[i].type; i++) {
-ti->interfaces[i].parent = info->interfaces[i].type;
-ti->interfaces[i].interface_initfn =
info->interfaces[i].interface_initfn;
-ti->num_interfaces++;
-}
+for (i = 0; info->interfaces && info->interfaces[i].type; i++) {
+ti->interfaces[i].typename = g_strdup(info->interfaces[i].type);
}
+ti->num_interfaces = i;
[Qemu-devel] [PATCH 2/2] xilinx_axi*: Re-implemented interconnect
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
controllers. A QOM interface "stream" is created, for the two stream interfaces.
As per Edgars request, this is designed to be more generic than AXI-stream,
so in the future we may see more clients of this interface beyond AXI stream.
This is based primarily on Paolos original refactoring of the interconnect.
Signed-off-by: Paolo Bonzini
Signed-off-by: Peter A.G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/petalogix_ml605_mmu.c | 24 +--
hw/stream.c | 23 ++
hw/stream.h | 31 +++
hw/xilinx.h | 22 +
hw/xilinx_axidma.c | 74 +
hw/xilinx_axidma.h | 39
hw/xilinx_axienet.c | 32 ---
8 files changed, 139 insertions(+), 107 deletions(-)
create mode 100644 hw/stream.c
create mode 100644 hw/stream.h
delete mode 100644 hw/xilinx_axidma.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..a2d537d 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -65,6 +65,7 @@ hw-obj-$(CONFIG_XILINX) += xilinx_timer.o
hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+hw-obj-$(CONFIG_XILINX_AXI) += stream.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 6a7d0c0..dced648 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -39,7 +39,8 @@
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
-#include "xilinx_axidma.h"
+
+#include "stream.h"
#define LMB_BRAM_SIZE (128 * 1024)
#define FLASH_SIZE (32 * 1024 * 1024)
@@ -76,7 +77,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
-DeviceState *dev;
+DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
CPUMBState *env;
DriveInfo *dinfo;
@@ -125,15 +126,18 @@ petalogix_ml605_init(ram_addr_t ram_size,
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 100);
-/* axi ethernet and dma initialization. TODO: Dynamically connect them. */
-{
-static struct XilinxDMAConnection dmach;
+/* axi ethernet and dma initialization. */
+dma = qdev_create(NULL, "xlnx.axi-dma");
-xilinx_axiethernet_create(&dmach, &nd_table[0], 0x8278,
- irq[3], 0x1000, 0x1000);
-xilinx_axiethernetdma_create(&dmach, 0x8460,
- irq[1], irq[0], 100 * 100);
-}
+/* FIXME: attach to the sysbus instead */
+object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ "xilinx-dma", OBJECT(dma), NULL);
+
+eth0 = xilinx_axiethernet_create(&nd_table[0], STREAM_SLAVE(dma),
+ 0x8278, irq[3], 0x1000, 0x1000);
+
+xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
+ 0x8460, irq[1], irq[0], 100 * 100);
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
diff --git a/hw/stream.c b/hw/stream.c
new file mode 100644
index 000..be57e8b
--- /dev/null
+++ b/hw/stream.c
@@ -0,0 +1,23 @@
+#include "stream.h"
+
+void
+stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app)
+{
+StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+
+k->push(sink, buf, len, app);
+}
+
+static TypeInfo stream_slave_info = {
+.name = TYPE_STREAM_SLAVE,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(StreamSlaveClass),
+};
+
+
+static void stream_slave_register_types(void)
+{
+type_register_static(&stream_slave_info);
+}
+
+type_init(stream_slave_register_types)
diff --git a/hw/stream.h b/hw/stream.h
new file mode 100644
index 000..21123a9
--- /dev/null
+++ b/hw/stream.h
@@ -0,0 +1,31 @@
+#ifndef STREAM_H
+#define STREAM_H 1
+
+#include "qemu-common.h"
+#include "qemu/object.h"
+
+/* stream slave. Used until qdev provides a generic way. */
+#define TYPE_STREAM_SLAVE "stream-slave"
+
+#define STREAM_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE(obj) \
+ INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
+
+typedef struct StreamSlave {
+Object Parent;
+} StreamSlave;
+
+typedef struct StreamSlaveClass {
+InterfaceClass parent;
+
+void (*push)(StreamSlave *obj, unsigned char *buf, size_t len,
+
[Qemu-devel] [PULL 0/2] QOMify AXI stream for Xilinx AXI ethernet/DMA
The following changes since commit 3d1d9652978ac5a32a0beb4bdf6065ca39440d89: Bruce Rogers (1): handle device help before accelerator set up are available in the git repository at: git://developer.petalogix.com/public/qemu.git for-upstream/axi-stream.next Anthony Liguori (1): qom: Reimplement Interfaces Peter A. G. Crosthwaite (1): xilinx_axi*: Re-implemented interconnect hw/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 24 +++-- hw/stream.c | 23 + hw/stream.h | 31 +++ hw/xilinx.h | 22 ++--- hw/xilinx_axidma.c | 74 +--- hw/xilinx_axidma.h | 39 hw/xilinx_axienet.c | 32 --- include/qemu/object.h| 46 ++ qom/object.c | 220 ++ 10 files changed, 255 insertions(+), 257 deletions(-) create mode 100644 hw/stream.c create mode 100644 hw/stream.h delete mode 100644 hw/xilinx_axidma.h
[Qemu-devel] [PATCH 1/2] qom: Reimplement Interfaces
From: Anthony Liguori
The current implementation of Interfaces is poorly designed. Each interface
that an object implements ends up being an object that's tracked by the
implementing object. There's all sorts of gymnastics to deal with casting
between these objects.
But an interface shouldn't be associated with an Object. Interfaces are global
to a class. This patch moves all Interface knowledge to ObjectClass eliminating
the relationship between Object and Interfaces.
Interfaces are now abstract (as they should be) but this is okay. Interfaces
essentially act as additional parents for the classes and are treated as such.
With this new implementation, we should fully support derived interfaces
including reimplementing an inherited interface.
PC: Rebased against qom-next merge Jun-2012.
PC: Removed replication of cast logic for interfaces, i.e. there is only
one cast function - object_dynamic_cast() (and object_dynamic_cast_assert())
Signed-off-by: Anthony Liguori
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Paolo Bonzini
---
include/qemu/object.h | 46 +++
qom/object.c | 220 +++--
2 files changed, 116 insertions(+), 150 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index 8b17776..cc75fee 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -239,6 +239,7 @@ struct ObjectClass
{
/*< private >*/
Type type;
+GSList *interfaces;
};
/**
@@ -260,7 +261,6 @@ struct Object
{
/*< private >*/
ObjectClass *class;
-GSList *interfaces;
QTAILQ_HEAD(, ObjectProperty) properties;
uint32_t ref;
Object *parent;
@@ -387,6 +387,16 @@ struct TypeInfo
OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name)
/**
+ * InterfaceInfo:
+ * @type: The name of the interface.
+ *
+ * The information associated with an interface.
+ */
+struct InterfaceInfo {
+const char *type;
+};
+
+/**
* InterfaceClass:
* @parent_class: the base class
*
@@ -396,26 +406,30 @@ struct TypeInfo
struct InterfaceClass
{
ObjectClass parent_class;
+/*< private >*/
+ObjectClass *concrete_class;
};
+#define TYPE_INTERFACE "interface"
+
/**
- * InterfaceInfo:
- * @type: The name of the interface.
- * @interface_initfn: This method is called during class initialization and is
- * used to initialize an interface associated with a class. This function
- * should initialize any default virtual functions for a class and/or
override
- * virtual functions in a parent class.
- *
- * The information associated with an interface.
+ * INTERFACE_CLASS:
+ * @klass: class to cast from
+ * Returns: An #InterfaceClass or raise an error if cast is invalid
*/
-struct InterfaceInfo
-{
-const char *type;
+#define INTERFACE_CLASS(klass) \
+OBJECT_CLASS_CHECK(InterfaceClass, klass, TYPE_INTERFACE)
-void (*interface_initfn)(ObjectClass *class, void *data);
-};
-
-#define TYPE_INTERFACE "interface"
+/**
+ * INTERFACE_CHECK:
+ * @interface: the type to return
+ * @obj: the object to convert to an interface
+ * @name: the interface type name
+ *
+ * Returns: @obj casted to @interface if cast is valid, otherwise raise error.
+ */
+#define INTERFACE_CHECK(interface, obj, name) \
+((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name)))
/**
* object_new:
diff --git a/qom/object.c b/qom/object.c
index 00bb3b0..a552be2 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -31,9 +31,7 @@ typedef struct TypeImpl TypeImpl;
struct InterfaceImpl
{
-const char *parent;
-void (*interface_initfn)(ObjectClass *class, void *data);
-TypeImpl *type;
+const char *typename;
};
struct TypeImpl
@@ -64,14 +62,6 @@ struct TypeImpl
InterfaceImpl interfaces[MAX_INTERFACES];
};
-typedef struct Interface
-{
-Object parent;
-Object *obj;
-} Interface;
-
-#define INTERFACE(obj) OBJECT_CHECK(Interface, obj, TYPE_INTERFACE)
-
static Type type_interface;
static GHashTable *type_table_get(void)
@@ -98,6 +88,7 @@ static TypeImpl *type_table_lookup(const char *name)
static TypeImpl *type_register_internal(const TypeInfo *info)
{
TypeImpl *ti = g_malloc0(sizeof(*ti));
+int i;
g_assert(info->name != NULL);
@@ -122,15 +113,10 @@ static TypeImpl *type_register_internal(const TypeInfo
*info)
ti->abstract = info->abstract;
-if (info->interfaces) {
-int i;
-
-for (i = 0; info->interfaces[i].type; i++) {
-ti->interfaces[i].parent = info->interfaces[i].type;
-ti->interfaces[i].interface_initfn =
info->interfaces[i].interface_initfn;
-ti->num_interfaces++;
-}
+for (i = 0; info->interfaces && info->interfaces[i].type; i++) {
+ti->interfaces[i].typename = g_strdup(info->interfaces[i].type);
}
+ti->num_interfaces = i;
[Qemu-devel] [PATCH 2/2] xilinx_axi*: Re-implemented interconnect
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
controllers. A QOM interface "stream" is created, for the two stream interfaces.
As per Edgars request, this is designed to be more generic than AXI-stream,
so in the future we may see more clients of this interface beyond AXI stream.
This is based primarily on Paolos original refactoring of the interconnect.
Signed-off-by: Paolo Bonzini
Signed-off-by: Peter A.G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/petalogix_ml605_mmu.c | 24 +--
hw/stream.c | 23 ++
hw/stream.h | 31 +++
hw/xilinx.h | 22 +
hw/xilinx_axidma.c | 74 +
hw/xilinx_axidma.h | 39
hw/xilinx_axienet.c | 32 ---
8 files changed, 139 insertions(+), 107 deletions(-)
create mode 100644 hw/stream.c
create mode 100644 hw/stream.h
delete mode 100644 hw/xilinx_axidma.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 12cc141..3849643 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -65,6 +65,7 @@ hw-obj-$(CONFIG_XILINX) += xilinx_timer.o
hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+hw-obj-$(CONFIG_XILINX_AXI) += stream.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 6a7d0c0..dced648 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -39,7 +39,8 @@
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
-#include "xilinx_axidma.h"
+
+#include "stream.h"
#define LMB_BRAM_SIZE (128 * 1024)
#define FLASH_SIZE (32 * 1024 * 1024)
@@ -76,7 +77,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
-DeviceState *dev;
+DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
CPUMBState *env;
DriveInfo *dinfo;
@@ -125,15 +126,18 @@ petalogix_ml605_init(ram_addr_t ram_size,
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 100);
-/* axi ethernet and dma initialization. TODO: Dynamically connect them. */
-{
-static struct XilinxDMAConnection dmach;
+/* axi ethernet and dma initialization. */
+dma = qdev_create(NULL, "xlnx.axi-dma");
-xilinx_axiethernet_create(&dmach, &nd_table[0], 0x8278,
- irq[3], 0x1000, 0x1000);
-xilinx_axiethernetdma_create(&dmach, 0x8460,
- irq[1], irq[0], 100 * 100);
-}
+/* FIXME: attach to the sysbus instead */
+object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ "xilinx-dma", OBJECT(dma), NULL);
+
+eth0 = xilinx_axiethernet_create(&nd_table[0], STREAM_SLAVE(dma),
+ 0x8278, irq[3], 0x1000, 0x1000);
+
+xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
+ 0x8460, irq[1], irq[0], 100 * 100);
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
diff --git a/hw/stream.c b/hw/stream.c
new file mode 100644
index 000..be57e8b
--- /dev/null
+++ b/hw/stream.c
@@ -0,0 +1,23 @@
+#include "stream.h"
+
+void
+stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app)
+{
+StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+
+k->push(sink, buf, len, app);
+}
+
+static TypeInfo stream_slave_info = {
+.name = TYPE_STREAM_SLAVE,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(StreamSlaveClass),
+};
+
+
+static void stream_slave_register_types(void)
+{
+type_register_static(&stream_slave_info);
+}
+
+type_init(stream_slave_register_types)
diff --git a/hw/stream.h b/hw/stream.h
new file mode 100644
index 000..21123a9
--- /dev/null
+++ b/hw/stream.h
@@ -0,0 +1,31 @@
+#ifndef STREAM_H
+#define STREAM_H 1
+
+#include "qemu-common.h"
+#include "qemu/object.h"
+
+/* stream slave. Used until qdev provides a generic way. */
+#define TYPE_STREAM_SLAVE "stream-slave"
+
+#define STREAM_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE(obj) \
+ INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
+
+typedef struct StreamSlave {
+Object Parent;
+} StreamSlave;
+
+typedef struct StreamSlaveClass {
+InterfaceClass parent;
+
+void (*push)(StreamSlave *obj, unsigned char *buf, size_t len,
+
[Qemu-devel] [PULL 0/1] device_tree: load_device_tree(): Allow NULL sizep
The following changes since commit 3d1d9652978ac5a32a0beb4bdf6065ca39440d89: Bruce Rogers (1): handle device help before accelerator set up are available in the git repository at: git://developer.petalogix.com/public/qemu.git for-upstream/device-tree-null-size.next Peter A. G. Crosthwaite (1): device_tree: load_device_tree(): Allow NULL sizep device_tree.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-)
[Qemu-devel] [PATCH] device_tree: load_device_tree(): Allow NULL sizep
The sizep arg is populated with the size of the loaded device tree. Since this
is one of those informational "please populate" type arguments it should be
optional. Guarded writes to *sizep against NULL accordingly.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Alexander Graf
---
device_tree.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index d7a9b6b..641a48a 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -71,7 +71,9 @@ void *load_device_tree(const char *filename_path, int *sizep)
int ret;
void *fdt = NULL;
-*sizep = 0;
+if (sizep) {
+*sizep = 0;
+}
dt_size = get_image_size(filename_path);
if (dt_size < 0) {
printf("Unable to get size of device tree file '%s'\n",
@@ -104,7 +106,9 @@ void *load_device_tree(const char *filename_path, int
*sizep)
filename_path);
goto fail;
}
-*sizep = dt_size;
+if (sizep) {
+*sizep = dt_size;
+}
return fdt;
fail:
--
1.7.0.4
[Qemu-devel] [RFC v0] HACK: qom: object_property_set: abort on failure
Hi All. A couple of times now ive had debug issues due to silent failure of
object_property_set. This function silently fails if the requested property
does not exist for the target object. To trap this error I applied the patch
below to my tree, but I am assuming that this is not mergeable as is as im
guessing there are clients out there that are speculatively trying to set props.
Could someone confirm the expected policy here? is setting a non-existant
property supposed to be a no-op (as it currently is) or should it fail
gracefully?
Whats the best meachinism for creating a no_fail version of object_property_set,
for the 90% case where a non-existant property is an error in machine model
development?
Signed-off-by: Peter A. G. Crosthwaite
---
qom/object.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index a552be2..6e875a8 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -687,7 +687,7 @@ void object_property_set(Object *obj, Visitor *v, const
char *name,
{
ObjectProperty *prop = object_property_find(obj, name, errp);
if (prop == NULL) {
-return;
+abort();
}
if (!prop->set) {
--
1.7.0.4
[Qemu-devel] [PATCH] i2c: factor out VMSD to parent class
Hi All. PMM raised a query on a recent series of mine (the SSI series) about
handling VMSD for devices which define state at multiple levels of the QOM
heirachy. Rather than complicate the discussion over in my series im trying to
start the discussion with an existing subsystem - i2c. This patch is a first
attempt at trying to get the VMSD for generic I2C state factored out of the
individual devices and handled transparently by the super class (I2C_SLAVE).
I have applied the change to only the one I2C device (max7310). If we were going
to run with this, the change pattern would be applied to all I2C devices.
This patch is not a merge proposal it is RFC only.
Please review and let us know if this is flawed or not. What needs to be done to
get this multi-level VMSD going?
I will use whatever review I get to fix my SSI series as well as fix I2C.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/i2c.c |2 ++
hw/i2c.h |8
hw/max7310.c |1 -
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/hw/i2c.c b/hw/i2c.c
index 296bece..17e1633 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -207,6 +207,8 @@ static int i2c_slave_qdev_init(DeviceState *dev)
I2CSlave *s = I2C_SLAVE_FROM_QDEV(dev);
I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
+vmstate_register(NULL, 0, &vmstate_i2c_slave, s);
+
return sc->init(s);
}
diff --git a/hw/i2c.h b/hw/i2c.h
index 0f5682b..5b75ecc 100644
--- a/hw/i2c.h
+++ b/hw/i2c.h
@@ -81,12 +81,4 @@ void lm832x_key_event(DeviceState *dev, int key, int state);
extern const VMStateDescription vmstate_i2c_slave;
-#define VMSTATE_I2C_SLAVE(_field, _state) { \
-.name = (stringify(_field)), \
-.size = sizeof(I2CSlave), \
-.vmsd = &vmstate_i2c_slave,\
-.flags = VMS_STRUCT,\
-.offset = vmstate_offset_value(_state, _field, I2CSlave),\
-}
-
#endif
diff --git a/hw/max7310.c b/hw/max7310.c
index 1ed18ba..9375691 100644
--- a/hw/max7310.c
+++ b/hw/max7310.c
@@ -156,7 +156,6 @@ static const VMStateDescription vmstate_max7310 = {
VMSTATE_UINT8(polarity, MAX7310State),
VMSTATE_UINT8(status, MAX7310State),
VMSTATE_UINT8(command, MAX7310State),
-VMSTATE_I2C_SLAVE(i2c, MAX7310State),
VMSTATE_END_OF_LIST()
}
};
--
1.7.0.4
[Qemu-devel] [RFC PATCH v2 0/4]Zynq-7000 EPP platform model
This is an RFC for a suite of Device models and a machine model for the Xilinx Zynq-7000 Extensible Processing Platform: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm This is an ARM based platform featuring embedded SoC peripherals. This patch series includes a minimal set of device models and a a machine model capable of emulating zynq platforms booting linux. This first 3 patches in this series are device models for IP provided by cadence for the Zynq platform. The final patch is the initial revision of the zynq machine model. Most of this work was originally authored by Xilinx, as indicated by (c) notices in added files. --- changes from v1: formatting and style fixes updated for QOM removed former patch 3 (cadence WDT device model) - not required removed former patch 5 (dtb argument) - this is currently under discussion in other patch series' removed former patch 6 (initrd parameterisation) - not required for minimal boot Peter A. G. Crosthwaite (4): cadence_uart: initial version of device model cadence_ttc: initial version of device model cadence_gem: initial version of device model xilinx_zynq: machine model initial version MAINTAINERS |5 + Makefile.target |4 + hw/cadence_gem.c | 1229 ++ hw/cadence_ttc.c | 399 hw/cadence_uart.c| 561 +++ hw/xilinx_zynq.c | 178 hw/zynq_arm_sysctl.c | 526 + 7 files changed, 2902 insertions(+), 0 deletions(-) create mode 100644 hw/cadence_gem.c create mode 100644 hw/cadence_ttc.c create mode 100644 hw/cadence_uart.c create mode 100644 hw/xilinx_zynq.c create mode 100644 hw/zynq_arm_sysctl.c -- 1.7.3.2
[Qemu-devel] [RFC PATCH v2 1/4] cadence_uart: initial version of device model
Implemented cadence UART serial controller
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1:
converted register file to array
added vmsd state save/load support
removed read side effects from CISR register
Makefile.target |1 +
hw/cadence_uart.c | 561 +
2 files changed, 562 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_uart.c
diff --git a/Makefile.target b/Makefile.target
index 68481a3..620a91d 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -337,6 +337,7 @@ endif
obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
+obj-arm-y += cadence_uart.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
new file mode 100644
index 000..1a57519
--- /dev/null
+++ b/hw/cadence_uart.c
@@ -0,0 +1,561 @@
+/*
+ * Device model for Cadence UART
+ *
+ * Copyright (c) 2010 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written by Haibing Ma
+ *M.Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_UART_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define UART_INTR_RTRIG 0x0001
+#define UART_INTR_REMPTY0x0002
+#define UART_INTR_RFUL 0x0004
+#define UART_INTR_TEMPTY0x0008
+#define UART_INTR_TFUL 0x0010
+#define UART_INTR_ROVR 0x0020
+#define UART_INTR_FRAME 0x0040
+#define UART_INTR_PARE 0x0080
+#define UART_INTR_TIMEOUT 0x0100
+#define UART_INTR_DMSI 0x0200
+#define UART_INTR_TTRIG 0x0400
+#define UART_INTR_TNFUL 0x0800
+#define UART_INTR_TOVR 0x1000
+
+#define UART_CSR_RTRIG 0x0001
+#define UART_CSR_REMPTY 0x0002
+#define UART_CSR_RFUL 0x0004
+#define UART_CSR_TEMPTY 0x0008
+#define UART_CSR_TFUL 0x0010
+#define UART_CSR_ROVR 0x0020
+#define UART_CSR_FRAME 0x0040
+#define UART_CSR_PARE 0x0080
+#define UART_CSR_TIMEOUT0x0100
+#define UART_CSR_DMSI 0x0200
+#define UART_CSR_RACTIVE0x0400
+#define UART_CSR_TACTIVE0x0800
+#define UART_CSR_FDELT 0x1000
+#define UART_CSR_TTRIG 0x2000
+#define UART_CSR_TNFUL 0x4000
+
+#define UART_CR_STOPBRK 0x0100
+#define UART_CR_STARTBRK0x0080
+#define UART_CR_RST_TO 0x0040
+#define UART_CR_TX_DIS 0x0020
+#define UART_CR_TX_EN 0x0010
+#define UART_CR_RX_DIS 0x0008
+#define UART_CR_RX_EN 0x0004
+#define UART_CR_TXRST 0x0002
+#define UART_CR_RXRST 0x0001
+
+#define UART_MR_CLKS0x0001
+#define UART_MR_CHRL0x0006
+#define UART_MR_PAR 0x0038
+#define UART_MR_NBSTOP 0x00C0
+#define UART_MR_CHMODE 0x0300
+#define UART_MR_UCLKEN 0x0400
+#define UART_MR_IRMODE 0x0800
+
+#define UART_PARITY_ODD0x001
+#define UART_PARITY_EVEN 0x000
+#define UART_DATA_BITS_6 0x003
+#define UART_DATA_BITS_7 0x002
+#define UART_STOP_BITS_1 0x003
+#define UART_STOP_BITS_2 0x002
+#define RX_FIFO_SIZE 16
+#define TX_FIFO_SIZE 16
+#define UARK_INPUT_CLK 5000
+
+#define NORMAL_MODE0
+#define ECHO_MODE 1
+#define LOCAL_LOOPBACK 2
+#define REMOTE_LOOPBACK3
+
+#define R_CR (0x00/4)
+#define R_MR (0x04/4)
+#define R_IER (0x08/4)
+#define R_IDR (0x0C/4)
+#define R_IMR (0x10/4)
+#define R_CISR (0x14/4)
+#define R_BRGR (0x18/4)
+#define R_RTOR (0x1C/4)
+#define R_RTRIG(0x20/4)
+#define R_MCR (0x24/4)
+#define R_MSR (0x28/4)
+#define R_CSR (0x2C/4)
+#define R_TX_RX(0x30/4)
+#define R_BDIV (0x34/4)
+#define R_FDEL (0x38/4)
+#define R_PMIN (0x3C/4)
+#define R_PWID (0x40/4)
+#define R_TTRIG(0x44/4)
+
+#define R_MAX (R_TTRIG + 1)
+
+typedef struct {
+
[Qemu-devel] [RFC PATCH v2 2/4] cadence_ttc: initial version of device model
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 399 ++
2 files changed, 400 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_ttc.c
diff --git a/Makefile.target b/Makefile.target
index 620a91d..feefafa 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -338,6 +338,7 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o
arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
+obj-arm-y += cadence_ttc.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
new file mode 100644
index 000..5074e2c
--- /dev/null
+++ b/hw/cadence_ttc.c
@@ -0,0 +1,399 @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+#include "ptimer.h"
+
+#ifdef CADENCE_TTC_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define COUNTER_INTR_IV 0x0001
+#define COUNTER_INTR_M1 0x0002
+#define COUNTER_INTR_M2 0x0004
+#define COUNTER_INTR_M3 0x0008
+#define COUNTER_INTR_OV 0x0010
+#define COUNTER_INTR_EV 0x0020
+
+#define COUNTER_CTRL_DIS0x0001
+#define COUNTER_CTRL_INT0x0002
+#define COUNTER_CTRL_DEC0x0004
+#define COUNTER_CTRL_MATCH 0x0008
+#define COUNTER_CTRL_RST0x0010
+
+#define CLOCK_CTRL_PS_EN0x0001
+#define CLOCK_CTRL_PS_V 0x001e
+
+typedef struct {
+ptimer_state *timer;
+int freq;
+
+uint32_t reg_clock;
+uint32_t reg_count;
+uint16_t reg_value;
+uint16_t reg_interval;
+uint16_t reg_match[3];
+uint32_t reg_intr;
+uint32_t reg_intr_en;
+uint32_t reg_event_ctrl;
+uint32_t reg_event;
+
+uint32_t event_interval;
+int serviced;
+
+qemu_irq irq;
+} CadenceTimerState;
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+CadenceTimerState * timer[3];
+} cadence_ttc_state;
+
+static void cadence_timer_update(CadenceTimerState *s)
+{
+qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+}
+
+static CadenceTimerState *cadence_timer_from_addr(void *opaque,
+target_phys_addr_t offset)
+{
+unsigned int index;
+cadence_ttc_state *s = (cadence_ttc_state *)opaque;
+
+index = (offset >> 2) % 3;
+
+return s->timer[index];
+}
+
+static inline int is_between(int x, int a, int b)
+{
+if (a < b) {
+return x > a && x < b;
+}
+return x < a && x > b;
+}
+
+static void cadence_timer_run(CadenceTimerState *s)
+{
+int i;
+int32_t event_interval;
+int32_t interval = (s->reg_count & COUNTER_CTRL_INT) ?
+((int32_t)s->reg_interval + 1) : 0x1;
+int32_t next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1 : interval;
+
+for (i = 0; i < 3; ++i) {
+if (is_between((int)s->reg_match[i], (int)s->reg_value, next_value)) {
+next_value = s->reg_match[i];
+}
+}
+event_interval = next_value - (int32_t)s->reg_value;
+s->event_interval = (event_interval < 0) ? -event_interval :
event_interval;
+s->serviced = 0;
+
+ptimer_set_limit(s->timer, (uint64_t)s->event_interval, 1);
+ptimer_run(s->timer, 1);
+}
+
+static uint32_t cadence_counter_value(CadenceTimerState *s)
+{
+int i;
+int32_t interval = (s->reg_count & COUNTER_CTRL_INT) ?
+(int)(s->reg_interval + 1) : 0x1;
+
+int32_t r = s->event_interval - ptimer_get_count(s->timer);
+int32_t x = s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);
+int32_t x_mod = (x + interval) % interval;
+
+if (!s->serviced) {
+for
[Qemu-devel] [RFC PATCH v2 4/4] xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G. Crosthwaite
---
changes since v1:
Added gem init function
remowed WDT instantiation
Added maintainers information
removed dead sys_id and proc_id variables
MAINTAINERS |5 +
Makefile.target |1 +
hw/xilinx_zynq.c | 178 +
hw/zynq_arm_sysctl.c | 526 ++
4 files changed, 710 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_zynq.c
create mode 100644 hw/zynq_arm_sysctl.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..9246bfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
+Xilinx Zynq
+M: Peter Crosthwaite
+S: Maintained
+F: hw/xilinx_zynq.c
+
CRIS Machines
-
Axis Dev88
diff --git a/Makefile.target b/Makefile.target
index e02a56b..87a8662 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -340,6 +340,7 @@ obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
+obj-arm-y += xilinx_zynq.o zynq_arm_sysctl.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
new file mode 100644
index 000..36765fb
--- /dev/null
+++ b/hw/xilinx_zynq.c
@@ -0,0 +1,178 @@
+/*
+ * Xilinx Zynq Baseboard System emulation.
+ *
+ * Copyright (c) 2010 Xilinx.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwa...@petalogix.com)
+ * Copyright (c) 2012 Petalogix Pty Ltd.
+ * Written by Haibing Ma
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "exec-memory.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "flash.h"
+#include "blockdev.h"
+#include "loader.h"
+
+#define FLASH_SIZE (64 * 1024 * 1024)
+#define FLASH_SECTOR_SIZE (128 * 1024)
+
+#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+
+static struct arm_boot_info zynq_binfo = {};
+
+static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+qemu_check_nic_model(nd, "cadence_gem");
+dev = qdev_create(NULL, "cadence_gem");
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+s = sysbus_from_qdev(dev);
+sysbus_mmio_map(s, 0, base);
+sysbus_connect_irq(s, 0, irq);
+}
+
+static void zynq_init(ram_addr_t ram_size, const char *boot_device,
+const char *kernel_filename, const char
*kernel_cmdline,
+const char *initrd_filename, const char *cpu_model)
+{
+CPUState *env = NULL;
+MemoryRegion *address_space_mem = get_system_memory();
+MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
+MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
+DeviceState *dev;
+SysBusDevice *busdev;
+qemu_irq *irqp;
+qemu_irq pic[64];
+NICInfo *nd;
+int n;
+qemu_irq cpu_irq[4];
+
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
+
+for (n = 0; n < smp_cpus; n++) {
+env = cpu_init(cpu_model);
+if (!env) {
+fprintf(stderr, "Unable to find CPU definition\n");
+exit(1);
+}
+irqp = arm_pic_init_cpu(env);
+cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+}
+
+/* max 2GB ram */
+if (ram_size > 0x8000) {
+ram_size = 0x8000;
+}
+
+/* DDR remapped to address zero. */
+memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
+vmstate_register_ram_global(ext_ram);
+memory_region_add_subregion(address_space_mem, 0, ext_ram);
+
+/* 256K of on-chip memory */
+memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
+vmstate_register_ram_global(ocm_ram);
+memory_region_add_subregion(address_space_mem, 0xFFFC, ocm_ram);
+
+DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
+
+#ifndef ZYNQ_FLASH_INTEL
+/* AMD */
+pflash_cfi02_register(0xe200, NULL, "zynq.pflash", FLASH_SIZE,
+ dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
+ FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
+ 1, 0x0066, 0x0022, 0
[Qemu-devel] [RFC PATCH v2 3/4] cadence_gem: initial version of device model
Device model for cadence gem ethernet controller.
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
removed global init function
marked vmsd as unmigratable
cleaned up debug messages
Makefile.target |1 +
hw/cadence_gem.c | 1229 ++
2 files changed, 1230 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_gem.c
diff --git a/Makefile.target b/Makefile.target
index feefafa..e02a56b 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -339,6 +339,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o
pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
+obj-arm-y += cadence_gem.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
new file mode 100644
index 000..0dfa47d
--- /dev/null
+++ b/hw/cadence_gem.c
@@ -0,0 +1,1229 @@
+/*
+ * QEMU Xilinx GEM emulation
+ *
+ * Copyright (c) 2011 Xilinx, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include /* For crc32 */
+#include
+
+#include "sysbus.h"
+#include "net.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "net/checksum.h"
+
+#ifdef CADENCE_GEM_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define GEM_NWCTRL 0x /* Network Control reg */
+#define GEM_NWCFG 0x0004 /* Network Config reg */
+#define GEM_NWSTATUS0x0008 /* Network Status reg */
+#define GEM_USERIO 0x000C /* User IO reg */
+#define GEM_DMACFG 0x0010 /* DMA Control reg */
+#define GEM_TXSTATUS0x0014 /* TX Status reg */
+#define GEM_RXQBASE 0x0018 /* RX Q Base address reg */
+#define GEM_TXQBASE 0x001C /* TX Q Base address reg */
+#define GEM_RXSTATUS0x0020 /* RX Status reg */
+#define GEM_ISR 0x0024 /* Interrupt Status reg */
+#define GEM_IER 0x0028 /* Interrupt Enable reg */
+#define GEM_IDR 0x002C /* Interrupt Disable reg */
+#define GEM_IMR 0x0030 /* Interrupt Mask reg */
+#define GEM_PHYMNTNC0x0034 /* Phy Maintaince reg */
+#define GEM_RXPAUSE 0x0038 /* RX Pause Time reg */
+#define GEM_TXPAUSE 0x003C /* TX Pause Time reg */
+#define GEM_TXPARTIALSF 0x0040 /* TX Partial Store and Forward */
+#define GEM_RXPARTIALSF 0x0044 /* RX Partial Store and Forward */
+#define GEM_HASHLO 0x0080 /* Hash Low address reg */
+#define GEM_HASHHI 0x0084 /* Hash High address reg */
+#define GEM_SPADDR1LO 0x0088 /* Specific addr 1 low reg */
+#define GEM_SPADDR1HI 0x008C /* Specific addr 1 high reg */
+#define GEM_SPADDR2LO 0x0090 /* Specific addr 2 low reg */
+#define GEM_SPADDR2HI 0x0094 /* Specific addr 2 high reg */
+#define GEM_SPADDR3LO 0x0098 /* Specific addr 3 low reg */
+#define GEM_SPADDR3HI 0x009C /* Specific addr 3 high reg */
+#define GEM_SPADDR4LO 0x00A0 /* Specific addr 4 low reg */
+#define GEM_SPADDR4HI 0x00A4 /* Specific addr 4 high reg */
+#define GEM_TIDMATCH1 0x00A8 /* Type ID1 Match reg */
+#define GEM_TIDMATCH2 0x00AC /* Type ID2 Match reg */
+#define GEM_TIDMATCH3 0x00B0 /* Type ID3 Match reg */
+#define GEM_TIDMATCH4 0x00B4 /* Type ID4 Match reg */
+#define GEM_WOLAN 0x00B8 /* Wake on LAN reg */
+#define GEM_IPGSTRETCH 0x00BC /* IPG Stretch reg */
+#define GEM_SVLAN 0x00C0 /* Stacked VLAN reg */
+#define GEM_MODID 0x00FC /* Module ID reg */
+#define GEM_OCTTXLO 0x0100 /* Octects transmitted Low reg */
+#define
[Qemu-devel] [RFC PATCH] arm boot: added QOM device definition
From: "Peter A. G. Crosthwaite"
Create a QOM device for bootstrapping linux on arm. Wraps the existing
arm_boot code and calls arm_load_kernel() at device init. Allows booting
of linux without -kernel -initrd -append arguments. The main drawback is
the boardid now has to be specified as there is no API for querying the
machine model for that. The code also assumes it is booting on first_cpu.
Added an automatic detection for the machine ram size so that ram size can
be detected by the bootloader without needing to get the value from either
the command line or machine model
Signed-off-by: Peter A. G. Crosthwaite
---
Makefile.objs|1 +
hw/arm-misc.h| 10
hw/arm_boot.c| 59 ++
hw/versatilepb.c | 14 +++-
4 files changed, 73 insertions(+), 11 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index ec35320..c397aa7 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -189,6 +189,7 @@ user-obj-y += $(trace-obj-y)
hw-obj-y =
hw-obj-y += vl.o loader.o
+hw-obj-y += image-loader.o
hw-obj-$(CONFIG_VIRTIO) += virtio-console.o
hw-obj-y += usb-libhw.o
hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index 5e5204b..754d8bd 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -25,10 +25,10 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
/* arm_boot.c */
struct arm_boot_info {
-int ram_size;
-const char *kernel_filename;
-const char *kernel_cmdline;
-const char *initrd_filename;
+uint32_t ram_size;
+char *kernel_filename;
+char *kernel_cmdline;
+char *initrd_filename;
target_phys_addr_t loader_start;
/* multicore boards that use the default secondary core boot functions
* need to put the address of the secondary boot code, the boot reg,
@@ -39,7 +39,7 @@ struct arm_boot_info {
target_phys_addr_t smp_bootreg_addr;
target_phys_addr_t smp_priv_base;
int nb_cpus;
-int board_id;
+uint32_t board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
/* multicore boards that use the default secondary core boot functions
* can ignore these two function calls. If the default functions won't
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 5f163fd..1f028f4 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -12,6 +12,9 @@
#include "sysemu.h"
#include "loader.h"
#include "elf.h"
+#include "qdev.h"
+#include "exec-memory.h"
+
#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x0001
@@ -245,6 +248,20 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info
*info)
target_phys_addr_t entry;
int big_endian;
+if (!env) {
+env = first_cpu;
+}
+
+if (!info->ram_size) {
+MemoryRegion *sysmem = get_system_memory();
+MemoryRegion *ram = memory_region_find(sysmem, 0, 4).mr;
+if (!ram) {
+fprintf(stderr, "Ram size not specified and autodetect failed\n");
+exit(1);
+}
+info->ram_size = memory_region_size(ram);
+}
+
/* Load the kernel. */
if (!info->kernel_filename) {
fprintf(stderr, "Kernel image must be specified\n");
@@ -321,3 +338,45 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info
*info)
qemu_register_reset(do_cpu_reset, env);
}
}
+
+struct ArmBoot {
+DeviceState qdev;
+struct arm_boot_info info;
+};
+
+static int arm_boot_init(DeviceState *dev)
+{
+struct ArmBoot *s = (struct ArmBoot *)dev;
+arm_load_kernel(NULL, &s->info);
+return 0;
+}
+
+static Property arm_boot_properties [] = {
+DEFINE_PROP_UINT32("boardid", struct ArmBoot, info.board_id, 0),
+DEFINE_PROP_STRING("initrd", struct ArmBoot, info.initrd_filename),
+DEFINE_PROP_STRING("kernel", struct ArmBoot, info.kernel_filename),
+DEFINE_PROP_STRING("cmdline", struct ArmBoot, info.kernel_cmdline),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void arm_boot_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->init = arm_boot_init;
+dc->props = arm_boot_properties;
+}
+
+static TypeInfo arm_boot_info_ = {
+.name = "arm_linux_loader",
+.parent= TYPE_DEVICE,
+.class_init= arm_boot_class_init,
+.instance_size = sizeof(struct ArmBoot),
+};
+
+static void arm_boot_register(void)
+{
+type_register_static(&arm_boot_info_);
+}
+
+device_init(arm_boot_register)
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 6e28e78..e42d845 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -313,12 +313,14 @@ static void versatile_init(ram_addr_t ram_size,
/* 0x101f3000 UART2. */
/* 0x101f4000 SSPI. */
-versatile_binfo.ram_size = ram_size;
-
[Qemu-devel] [PATCH v3 0/4] Zynq-7000 EPP platform model
This is a suite of Device models and a machine model for the Xilinx Zynq-7000 Extensible Processing Platform: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm This is an ARM based platform featuring embedded SoC peripherals. This patch series includes a minimal set of device models and a a machine model capable of emulating zynq platforms booting linux. This first 3 patches in this series are device models for IP provided by cadence for the Zynq platform. The final patch is the initial revision of the zynq machine model. Most of this work was originally authored by Xilinx, as indicated by (c) notices in added files. Tree is available from: git://developer.petalogix.com/private/peterc/qemu.git --- changed from v2: fixed timer prescision issue (2/4) fixed compile warnings in zynq_arm_sysctl (4/4) changes from v1: formatting and style fixes updated for QOM removed former patch 3 (cadence WDT device model) - not required removed former patch 5 (dtb argument) - this is currently under discussion in other patch series' removed former patch 6 (initrd parameterisation) - not required for minimal boot Peter A. G. Crosthwaite (4): cadence_uart: initial version of device model cadence_ttc: initial version of device model cadence_gem: initial version of device model xilinx_zynq: machine model initial version MAINTAINERS |5 + Makefile.target |4 + hw/cadence_gem.c | 1229 ++ hw/cadence_ttc.c | 435 ++ hw/cadence_uart.c| 561 +++ hw/xilinx_zynq.c | 178 hw/zynq_arm_sysctl.c | 526 + 7 files changed, 2938 insertions(+), 0 deletions(-) create mode 100644 hw/cadence_gem.c create mode 100644 hw/cadence_ttc.c create mode 100644 hw/cadence_uart.c create mode 100644 hw/xilinx_zynq.c create mode 100644 hw/zynq_arm_sysctl.c -- 1.7.3.2
[Qemu-devel] [PATCH v3 1/4] cadence_uart: initial version of device model
Implemented cadence UART serial controller
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1:
converted register file to array
added vmsd state save/load support
removed read side effects from CISR register
Makefile.target |1 +
hw/cadence_uart.c | 561 +
2 files changed, 562 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_uart.c
diff --git a/Makefile.target b/Makefile.target
index 29fde6e..411a4bf 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -343,6 +343,7 @@ endif
obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
+obj-arm-y += cadence_uart.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
new file mode 100644
index 000..1a57519
--- /dev/null
+++ b/hw/cadence_uart.c
@@ -0,0 +1,561 @@
+/*
+ * Device model for Cadence UART
+ *
+ * Copyright (c) 2010 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written by Haibing Ma
+ *M.Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_UART_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define UART_INTR_RTRIG 0x0001
+#define UART_INTR_REMPTY0x0002
+#define UART_INTR_RFUL 0x0004
+#define UART_INTR_TEMPTY0x0008
+#define UART_INTR_TFUL 0x0010
+#define UART_INTR_ROVR 0x0020
+#define UART_INTR_FRAME 0x0040
+#define UART_INTR_PARE 0x0080
+#define UART_INTR_TIMEOUT 0x0100
+#define UART_INTR_DMSI 0x0200
+#define UART_INTR_TTRIG 0x0400
+#define UART_INTR_TNFUL 0x0800
+#define UART_INTR_TOVR 0x1000
+
+#define UART_CSR_RTRIG 0x0001
+#define UART_CSR_REMPTY 0x0002
+#define UART_CSR_RFUL 0x0004
+#define UART_CSR_TEMPTY 0x0008
+#define UART_CSR_TFUL 0x0010
+#define UART_CSR_ROVR 0x0020
+#define UART_CSR_FRAME 0x0040
+#define UART_CSR_PARE 0x0080
+#define UART_CSR_TIMEOUT0x0100
+#define UART_CSR_DMSI 0x0200
+#define UART_CSR_RACTIVE0x0400
+#define UART_CSR_TACTIVE0x0800
+#define UART_CSR_FDELT 0x1000
+#define UART_CSR_TTRIG 0x2000
+#define UART_CSR_TNFUL 0x4000
+
+#define UART_CR_STOPBRK 0x0100
+#define UART_CR_STARTBRK0x0080
+#define UART_CR_RST_TO 0x0040
+#define UART_CR_TX_DIS 0x0020
+#define UART_CR_TX_EN 0x0010
+#define UART_CR_RX_DIS 0x0008
+#define UART_CR_RX_EN 0x0004
+#define UART_CR_TXRST 0x0002
+#define UART_CR_RXRST 0x0001
+
+#define UART_MR_CLKS0x0001
+#define UART_MR_CHRL0x0006
+#define UART_MR_PAR 0x0038
+#define UART_MR_NBSTOP 0x00C0
+#define UART_MR_CHMODE 0x0300
+#define UART_MR_UCLKEN 0x0400
+#define UART_MR_IRMODE 0x0800
+
+#define UART_PARITY_ODD0x001
+#define UART_PARITY_EVEN 0x000
+#define UART_DATA_BITS_6 0x003
+#define UART_DATA_BITS_7 0x002
+#define UART_STOP_BITS_1 0x003
+#define UART_STOP_BITS_2 0x002
+#define RX_FIFO_SIZE 16
+#define TX_FIFO_SIZE 16
+#define UARK_INPUT_CLK 5000
+
+#define NORMAL_MODE0
+#define ECHO_MODE 1
+#define LOCAL_LOOPBACK 2
+#define REMOTE_LOOPBACK3
+
+#define R_CR (0x00/4)
+#define R_MR (0x04/4)
+#define R_IER (0x08/4)
+#define R_IDR (0x0C/4)
+#define R_IMR (0x10/4)
+#define R_CISR (0x14/4)
+#define R_BRGR (0x18/4)
+#define R_RTOR (0x1C/4)
+#define R_RTRIG(0x20/4)
+#define R_MCR (0x24/4)
+#define R_MSR (0x28/4)
+#define R_CSR (0x2C/4)
+#define R_TX_RX(0x30/4)
+#define R_BDIV (0x34/4)
+#define R_FDEL (0x38/4)
+#define R_PMIN (0x3C/4)
+#define R_PWID (0x40/4)
+#define R_TTRIG(0x44/4)
+
+#define R_MAX (R_TTRIG + 1)
+
+typedef struct {
+
[Qemu-devel] [PATCH v3 2/4] cadence_ttc: initial version of device model
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changed from v2
changed ptimer to QEMUTimer (Fixed skew/drift issue in timer delays)
changes from v1
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 435 ++
2 files changed, 436 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_ttc.c
diff --git a/Makefile.target b/Makefile.target
index 411a4bf..1e8afe6 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -344,6 +344,7 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o
arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
+obj-arm-y += cadence_ttc.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
new file mode 100644
index 000..1f0ca42
--- /dev/null
+++ b/hw/cadence_ttc.c
@@ -0,0 +1,435 @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_TTC_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define COUNTER_INTR_IV 0x0001
+#define COUNTER_INTR_M1 0x0002
+#define COUNTER_INTR_M2 0x0004
+#define COUNTER_INTR_M3 0x0008
+#define COUNTER_INTR_OV 0x0010
+#define COUNTER_INTR_EV 0x0020
+
+#define COUNTER_CTRL_DIS0x0001
+#define COUNTER_CTRL_INT0x0002
+#define COUNTER_CTRL_DEC0x0004
+#define COUNTER_CTRL_MATCH 0x0008
+#define COUNTER_CTRL_RST0x0010
+
+#define CLOCK_CTRL_PS_EN0x0001
+#define CLOCK_CTRL_PS_V 0x001e
+
+typedef struct {
+QEMUTimer *timer;
+int freq;
+
+uint32_t reg_clock;
+uint32_t reg_count;
+uint32_t reg_value;
+uint16_t reg_interval;
+uint16_t reg_match[3];
+uint32_t reg_intr;
+uint32_t reg_intr_en;
+uint32_t reg_event_ctrl;
+uint32_t reg_event;
+
+uint64_t cpu_time;
+unsigned int cpu_time_valid;
+
+qemu_irq irq;
+} CadenceTimerState;
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+CadenceTimerState * timer[3];
+} cadence_ttc_state;
+
+static void cadence_timer_update(CadenceTimerState *s)
+{
+qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+}
+
+static CadenceTimerState *cadence_timer_from_addr(void *opaque,
+target_phys_addr_t offset)
+{
+unsigned int index;
+cadence_ttc_state *s = (cadence_ttc_state *)opaque;
+
+index = (offset >> 2) % 3;
+
+return s->timer[index];
+}
+
+static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t
timer_steps)
+{
+/* timer_steps has max value of 0x1. double check it
+ * (or overflow can happen below) */
+assert(timer_steps <= 1ULL << 32);
+
+uint64_t r = timer_steps * 10ULL;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
+} else {
+r >>= 16;
+}
+r /= (uint64_t)s->freq;
+return r;
+}
+
+static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
+{
+uint64_t to_divide = 10ULL;
+
+uint64_t r = ns;
+ /* for very large intervals (> 8s) do some division first to stop
+ * overflow (costs some prescision) */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r <<= 16;
+/* keep early-dividing as needed */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r *= (uint64_t)s->freq;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
+}
+
+r /= to_divide;
+return r;
+}
+
+static inline int
[Qemu-devel] [PATCH v3 3/4] cadence_gem: initial version of device model
Device model for cadence gem ethernet controller.
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1:
removed global init function
marked vmsd as unmigratable
cleaned up debug messages
Makefile.target |1 +
hw/cadence_gem.c | 1229 ++
2 files changed, 1230 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_gem.c
diff --git a/Makefile.target b/Makefile.target
index 1e8afe6..84b559c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -345,6 +345,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o
pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
+obj-arm-y += cadence_gem.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
new file mode 100644
index 000..0dfa47d
--- /dev/null
+++ b/hw/cadence_gem.c
@@ -0,0 +1,1229 @@
+/*
+ * QEMU Xilinx GEM emulation
+ *
+ * Copyright (c) 2011 Xilinx, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include /* For crc32 */
+#include
+
+#include "sysbus.h"
+#include "net.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "net/checksum.h"
+
+#ifdef CADENCE_GEM_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define GEM_NWCTRL 0x /* Network Control reg */
+#define GEM_NWCFG 0x0004 /* Network Config reg */
+#define GEM_NWSTATUS0x0008 /* Network Status reg */
+#define GEM_USERIO 0x000C /* User IO reg */
+#define GEM_DMACFG 0x0010 /* DMA Control reg */
+#define GEM_TXSTATUS0x0014 /* TX Status reg */
+#define GEM_RXQBASE 0x0018 /* RX Q Base address reg */
+#define GEM_TXQBASE 0x001C /* TX Q Base address reg */
+#define GEM_RXSTATUS0x0020 /* RX Status reg */
+#define GEM_ISR 0x0024 /* Interrupt Status reg */
+#define GEM_IER 0x0028 /* Interrupt Enable reg */
+#define GEM_IDR 0x002C /* Interrupt Disable reg */
+#define GEM_IMR 0x0030 /* Interrupt Mask reg */
+#define GEM_PHYMNTNC0x0034 /* Phy Maintaince reg */
+#define GEM_RXPAUSE 0x0038 /* RX Pause Time reg */
+#define GEM_TXPAUSE 0x003C /* TX Pause Time reg */
+#define GEM_TXPARTIALSF 0x0040 /* TX Partial Store and Forward */
+#define GEM_RXPARTIALSF 0x0044 /* RX Partial Store and Forward */
+#define GEM_HASHLO 0x0080 /* Hash Low address reg */
+#define GEM_HASHHI 0x0084 /* Hash High address reg */
+#define GEM_SPADDR1LO 0x0088 /* Specific addr 1 low reg */
+#define GEM_SPADDR1HI 0x008C /* Specific addr 1 high reg */
+#define GEM_SPADDR2LO 0x0090 /* Specific addr 2 low reg */
+#define GEM_SPADDR2HI 0x0094 /* Specific addr 2 high reg */
+#define GEM_SPADDR3LO 0x0098 /* Specific addr 3 low reg */
+#define GEM_SPADDR3HI 0x009C /* Specific addr 3 high reg */
+#define GEM_SPADDR4LO 0x00A0 /* Specific addr 4 low reg */
+#define GEM_SPADDR4HI 0x00A4 /* Specific addr 4 high reg */
+#define GEM_TIDMATCH1 0x00A8 /* Type ID1 Match reg */
+#define GEM_TIDMATCH2 0x00AC /* Type ID2 Match reg */
+#define GEM_TIDMATCH3 0x00B0 /* Type ID3 Match reg */
+#define GEM_TIDMATCH4 0x00B4 /* Type ID4 Match reg */
+#define GEM_WOLAN 0x00B8 /* Wake on LAN reg */
+#define GEM_IPGSTRETCH 0x00BC /* IPG Stretch reg */
+#define GEM_SVLAN 0x00C0 /* Stacked VLAN reg */
+#define GEM_MODID 0x00FC /* Module ID reg */
+#define GEM_OCTTXLO 0x0100 /* Octects transmitted Low reg */
[Qemu-devel] [PATCH v3 4/4] xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G. Crosthwaite
---
changes since v2:
removed 2 compile warnings from zynq_arm_sysctl.c
changes since v1:
Added gem init function
remowed WDT instantiation
Added maintainers information
removed dead sys_id and proc_id variables
MAINTAINERS |5 +
Makefile.target |1 +
hw/xilinx_zynq.c | 178 +
hw/zynq_arm_sysctl.c | 526 ++
4 files changed, 710 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_zynq.c
create mode 100644 hw/zynq_arm_sysctl.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..9246bfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
+Xilinx Zynq
+M: Peter Crosthwaite
+S: Maintained
+F: hw/xilinx_zynq.c
+
CRIS Machines
-
Axis Dev88
diff --git a/Makefile.target b/Makefile.target
index 84b559c..40fd1b2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -346,6 +346,7 @@ obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
+obj-arm-y += xilinx_zynq.o zynq_arm_sysctl.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
new file mode 100644
index 000..36765fb
--- /dev/null
+++ b/hw/xilinx_zynq.c
@@ -0,0 +1,178 @@
+/*
+ * Xilinx Zynq Baseboard System emulation.
+ *
+ * Copyright (c) 2010 Xilinx.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwa...@petalogix.com)
+ * Copyright (c) 2012 Petalogix Pty Ltd.
+ * Written by Haibing Ma
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "exec-memory.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "flash.h"
+#include "blockdev.h"
+#include "loader.h"
+
+#define FLASH_SIZE (64 * 1024 * 1024)
+#define FLASH_SECTOR_SIZE (128 * 1024)
+
+#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+
+static struct arm_boot_info zynq_binfo = {};
+
+static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+qemu_check_nic_model(nd, "cadence_gem");
+dev = qdev_create(NULL, "cadence_gem");
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+s = sysbus_from_qdev(dev);
+sysbus_mmio_map(s, 0, base);
+sysbus_connect_irq(s, 0, irq);
+}
+
+static void zynq_init(ram_addr_t ram_size, const char *boot_device,
+const char *kernel_filename, const char
*kernel_cmdline,
+const char *initrd_filename, const char *cpu_model)
+{
+CPUState *env = NULL;
+MemoryRegion *address_space_mem = get_system_memory();
+MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
+MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
+DeviceState *dev;
+SysBusDevice *busdev;
+qemu_irq *irqp;
+qemu_irq pic[64];
+NICInfo *nd;
+int n;
+qemu_irq cpu_irq[4];
+
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
+
+for (n = 0; n < smp_cpus; n++) {
+env = cpu_init(cpu_model);
+if (!env) {
+fprintf(stderr, "Unable to find CPU definition\n");
+exit(1);
+}
+irqp = arm_pic_init_cpu(env);
+cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+}
+
+/* max 2GB ram */
+if (ram_size > 0x8000) {
+ram_size = 0x8000;
+}
+
+/* DDR remapped to address zero. */
+memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
+vmstate_register_ram_global(ext_ram);
+memory_region_add_subregion(address_space_mem, 0, ext_ram);
+
+/* 256K of on-chip memory */
+memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
+vmstate_register_ram_global(ocm_ram);
+memory_region_add_subregion(address_space_mem, 0xFFFC, ocm_ram);
+
+DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
+
+#ifndef ZYNQ_FLASH_INTEL
+/* AMD */
+pflash_cfi02_register(0xe200, NULL, "zynq.pflash", FLASH_SIZE,
+ dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
+ FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
+
[Qemu-devel] [PATCH v4 0/4] Zynq-7000 EPP platform model
This is a suite of Device models and a machine model for the Xilinx Zynq-7000 Extensible Processing Platform: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm This is an ARM based platform featuring embedded SoC peripherals. This patch series includes a minimal set of device models and a a machine model capable of emulating zynq platforms booting linux. This first 3 patches in this series are device models for IP provided by cadence for the Zynq platform. The final patch is the initial revision of the zynq machine model. Most of this work was originally authored by Xilinx, as indicated by (c) notices in added files. Tree is available from: git://developer.petalogix.com/private/peterc/qemu.git branch: zynq-initial.4 --- changed from v3: fixed timer race condition issue (2/4) changed from v2: fixed timer prescision issue (2/4) fixed compile warnings in zynq_arm_sysctl (4/4) changes from v1: formatting and style fixes updated for QOM removed former patch 3 (cadence WDT device model) - not required removed former patch 5 (dtb argument) - this is currently under discussion in other patch series' removed former patch 6 (initrd parameterisation) - not required for minimal boot Peter A. G. Crosthwaite (4): cadence_uart: initial version of device model cadence_ttc: initial version of device model cadence_gem: initial version of device model xilinx_zynq: machine model initial version MAINTAINERS |5 + Makefile.target |4 + hw/cadence_gem.c | 1229 ++ hw/cadence_ttc.c | 441 ++ hw/cadence_uart.c| 561 +++ hw/xilinx_zynq.c | 178 hw/zynq_arm_sysctl.c | 526 + 7 files changed, 2944 insertions(+), 0 deletions(-) create mode 100644 hw/cadence_gem.c create mode 100644 hw/cadence_ttc.c create mode 100644 hw/cadence_uart.c create mode 100644 hw/xilinx_zynq.c create mode 100644 hw/zynq_arm_sysctl.c -- 1.7.3.2
[Qemu-devel] [PATCH v4 1/4] cadence_uart: initial version of device model
Implemented cadence UART serial controller
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1:
converted register file to array
added vmsd state save/load support
removed read side effects from CISR register
Makefile.target |1 +
hw/cadence_uart.c | 561 +
2 files changed, 562 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_uart.c
diff --git a/Makefile.target b/Makefile.target
index 29fde6e..411a4bf 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -343,6 +343,7 @@ endif
obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
+obj-arm-y += cadence_uart.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
new file mode 100644
index 000..1a57519
--- /dev/null
+++ b/hw/cadence_uart.c
@@ -0,0 +1,561 @@
+/*
+ * Device model for Cadence UART
+ *
+ * Copyright (c) 2010 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written by Haibing Ma
+ *M.Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_UART_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define UART_INTR_RTRIG 0x0001
+#define UART_INTR_REMPTY0x0002
+#define UART_INTR_RFUL 0x0004
+#define UART_INTR_TEMPTY0x0008
+#define UART_INTR_TFUL 0x0010
+#define UART_INTR_ROVR 0x0020
+#define UART_INTR_FRAME 0x0040
+#define UART_INTR_PARE 0x0080
+#define UART_INTR_TIMEOUT 0x0100
+#define UART_INTR_DMSI 0x0200
+#define UART_INTR_TTRIG 0x0400
+#define UART_INTR_TNFUL 0x0800
+#define UART_INTR_TOVR 0x1000
+
+#define UART_CSR_RTRIG 0x0001
+#define UART_CSR_REMPTY 0x0002
+#define UART_CSR_RFUL 0x0004
+#define UART_CSR_TEMPTY 0x0008
+#define UART_CSR_TFUL 0x0010
+#define UART_CSR_ROVR 0x0020
+#define UART_CSR_FRAME 0x0040
+#define UART_CSR_PARE 0x0080
+#define UART_CSR_TIMEOUT0x0100
+#define UART_CSR_DMSI 0x0200
+#define UART_CSR_RACTIVE0x0400
+#define UART_CSR_TACTIVE0x0800
+#define UART_CSR_FDELT 0x1000
+#define UART_CSR_TTRIG 0x2000
+#define UART_CSR_TNFUL 0x4000
+
+#define UART_CR_STOPBRK 0x0100
+#define UART_CR_STARTBRK0x0080
+#define UART_CR_RST_TO 0x0040
+#define UART_CR_TX_DIS 0x0020
+#define UART_CR_TX_EN 0x0010
+#define UART_CR_RX_DIS 0x0008
+#define UART_CR_RX_EN 0x0004
+#define UART_CR_TXRST 0x0002
+#define UART_CR_RXRST 0x0001
+
+#define UART_MR_CLKS0x0001
+#define UART_MR_CHRL0x0006
+#define UART_MR_PAR 0x0038
+#define UART_MR_NBSTOP 0x00C0
+#define UART_MR_CHMODE 0x0300
+#define UART_MR_UCLKEN 0x0400
+#define UART_MR_IRMODE 0x0800
+
+#define UART_PARITY_ODD0x001
+#define UART_PARITY_EVEN 0x000
+#define UART_DATA_BITS_6 0x003
+#define UART_DATA_BITS_7 0x002
+#define UART_STOP_BITS_1 0x003
+#define UART_STOP_BITS_2 0x002
+#define RX_FIFO_SIZE 16
+#define TX_FIFO_SIZE 16
+#define UARK_INPUT_CLK 5000
+
+#define NORMAL_MODE0
+#define ECHO_MODE 1
+#define LOCAL_LOOPBACK 2
+#define REMOTE_LOOPBACK3
+
+#define R_CR (0x00/4)
+#define R_MR (0x04/4)
+#define R_IER (0x08/4)
+#define R_IDR (0x0C/4)
+#define R_IMR (0x10/4)
+#define R_CISR (0x14/4)
+#define R_BRGR (0x18/4)
+#define R_RTOR (0x1C/4)
+#define R_RTRIG(0x20/4)
+#define R_MCR (0x24/4)
+#define R_MSR (0x28/4)
+#define R_CSR (0x2C/4)
+#define R_TX_RX(0x30/4)
+#define R_BDIV (0x34/4)
+#define R_FDEL (0x38/4)
+#define R_PMIN (0x3C/4)
+#define R_PWID (0x40/4)
+#define R_TTRIG(0x44/4)
+
+#define R_MAX (R_TTRIG + 1)
+
+typedef struct {
+
[Qemu-devel] [PATCH v4 2/4] cadence_ttc: initial version of device model
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changed from v3:
Fixed race condition where timer could miss match events on wrap around
changed from v2:
changed ptimer to QEMUTimer (Fixed skew/drift issue in timer delays)
changes from v1:
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 441 ++
2 files changed, 442 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_ttc.c
diff --git a/Makefile.target b/Makefile.target
index 411a4bf..1e8afe6 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -344,6 +344,7 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o
arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
+obj-arm-y += cadence_ttc.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
new file mode 100644
index 000..01c6984
--- /dev/null
+++ b/hw/cadence_ttc.c
@@ -0,0 +1,441 @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_TTC_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define COUNTER_INTR_IV 0x0001
+#define COUNTER_INTR_M1 0x0002
+#define COUNTER_INTR_M2 0x0004
+#define COUNTER_INTR_M3 0x0008
+#define COUNTER_INTR_OV 0x0010
+#define COUNTER_INTR_EV 0x0020
+
+#define COUNTER_CTRL_DIS0x0001
+#define COUNTER_CTRL_INT0x0002
+#define COUNTER_CTRL_DEC0x0004
+#define COUNTER_CTRL_MATCH 0x0008
+#define COUNTER_CTRL_RST0x0010
+
+#define CLOCK_CTRL_PS_EN0x0001
+#define CLOCK_CTRL_PS_V 0x001e
+
+typedef struct {
+QEMUTimer *timer;
+int freq;
+
+uint32_t reg_clock;
+uint32_t reg_count;
+uint32_t reg_value;
+uint16_t reg_interval;
+uint16_t reg_match[3];
+uint32_t reg_intr;
+uint32_t reg_intr_en;
+uint32_t reg_event_ctrl;
+uint32_t reg_event;
+
+uint64_t cpu_time;
+unsigned int cpu_time_valid;
+
+qemu_irq irq;
+} CadenceTimerState;
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+CadenceTimerState * timer[3];
+} cadence_ttc_state;
+
+static void cadence_timer_update(CadenceTimerState *s)
+{
+qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+}
+
+static CadenceTimerState *cadence_timer_from_addr(void *opaque,
+target_phys_addr_t offset)
+{
+unsigned int index;
+cadence_ttc_state *s = (cadence_ttc_state *)opaque;
+
+index = (offset >> 2) % 3;
+
+return s->timer[index];
+}
+
+static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t
timer_steps)
+{
+/* timer_steps has max value of 0x1. double check it
+ * (or overflow can happen below) */
+assert(timer_steps <= 1ULL << 32);
+
+uint64_t r = timer_steps * 10ULL;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
+} else {
+r >>= 16;
+}
+r /= (uint64_t)s->freq;
+return r;
+}
+
+static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
+{
+uint64_t to_divide = 10ULL;
+
+uint64_t r = ns;
+ /* for very large intervals (> 8s) do some division first to stop
+ * overflow (costs some prescision) */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r <<= 16;
+/* keep early-dividing as needed */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r *= (uint64_t)s->freq;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >>
[Qemu-devel] [PATCH v4 4/4] xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G. Crosthwaite
---
changes since v2:
removed 2 compile warnings from zynq_arm_sysctl.c
changes since v1:
Added gem init function
remowed WDT instantiation
Added maintainers information
removed dead sys_id and proc_id variables
MAINTAINERS |5 +
Makefile.target |1 +
hw/xilinx_zynq.c | 178 +
hw/zynq_arm_sysctl.c | 526 ++
4 files changed, 710 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_zynq.c
create mode 100644 hw/zynq_arm_sysctl.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..9246bfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
+Xilinx Zynq
+M: Peter Crosthwaite
+S: Maintained
+F: hw/xilinx_zynq.c
+
CRIS Machines
-
Axis Dev88
diff --git a/Makefile.target b/Makefile.target
index 84b559c..40fd1b2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -346,6 +346,7 @@ obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
+obj-arm-y += xilinx_zynq.o zynq_arm_sysctl.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
new file mode 100644
index 000..36765fb
--- /dev/null
+++ b/hw/xilinx_zynq.c
@@ -0,0 +1,178 @@
+/*
+ * Xilinx Zynq Baseboard System emulation.
+ *
+ * Copyright (c) 2010 Xilinx.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwa...@petalogix.com)
+ * Copyright (c) 2012 Petalogix Pty Ltd.
+ * Written by Haibing Ma
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "exec-memory.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "flash.h"
+#include "blockdev.h"
+#include "loader.h"
+
+#define FLASH_SIZE (64 * 1024 * 1024)
+#define FLASH_SECTOR_SIZE (128 * 1024)
+
+#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+
+static struct arm_boot_info zynq_binfo = {};
+
+static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+qemu_check_nic_model(nd, "cadence_gem");
+dev = qdev_create(NULL, "cadence_gem");
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+s = sysbus_from_qdev(dev);
+sysbus_mmio_map(s, 0, base);
+sysbus_connect_irq(s, 0, irq);
+}
+
+static void zynq_init(ram_addr_t ram_size, const char *boot_device,
+const char *kernel_filename, const char
*kernel_cmdline,
+const char *initrd_filename, const char *cpu_model)
+{
+CPUState *env = NULL;
+MemoryRegion *address_space_mem = get_system_memory();
+MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
+MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
+DeviceState *dev;
+SysBusDevice *busdev;
+qemu_irq *irqp;
+qemu_irq pic[64];
+NICInfo *nd;
+int n;
+qemu_irq cpu_irq[4];
+
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
+
+for (n = 0; n < smp_cpus; n++) {
+env = cpu_init(cpu_model);
+if (!env) {
+fprintf(stderr, "Unable to find CPU definition\n");
+exit(1);
+}
+irqp = arm_pic_init_cpu(env);
+cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+}
+
+/* max 2GB ram */
+if (ram_size > 0x8000) {
+ram_size = 0x8000;
+}
+
+/* DDR remapped to address zero. */
+memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
+vmstate_register_ram_global(ext_ram);
+memory_region_add_subregion(address_space_mem, 0, ext_ram);
+
+/* 256K of on-chip memory */
+memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
+vmstate_register_ram_global(ocm_ram);
+memory_region_add_subregion(address_space_mem, 0xFFFC, ocm_ram);
+
+DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
+
+#ifndef ZYNQ_FLASH_INTEL
+/* AMD */
+pflash_cfi02_register(0xe200, NULL, "zynq.pflash", FLASH_SIZE,
+ dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
+ FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
+
[Qemu-devel] [PATCH v4 3/4] cadence_gem: initial version of device model
Device model for cadence gem ethernet controller.
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1:
removed global init function
marked vmsd as unmigratable
cleaned up debug messages
Makefile.target |1 +
hw/cadence_gem.c | 1229 ++
2 files changed, 1230 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_gem.c
diff --git a/Makefile.target b/Makefile.target
index 1e8afe6..84b559c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -345,6 +345,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o
pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
+obj-arm-y += cadence_gem.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
new file mode 100644
index 000..0dfa47d
--- /dev/null
+++ b/hw/cadence_gem.c
@@ -0,0 +1,1229 @@
+/*
+ * QEMU Xilinx GEM emulation
+ *
+ * Copyright (c) 2011 Xilinx, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include /* For crc32 */
+#include
+
+#include "sysbus.h"
+#include "net.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "net/checksum.h"
+
+#ifdef CADENCE_GEM_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define GEM_NWCTRL 0x /* Network Control reg */
+#define GEM_NWCFG 0x0004 /* Network Config reg */
+#define GEM_NWSTATUS0x0008 /* Network Status reg */
+#define GEM_USERIO 0x000C /* User IO reg */
+#define GEM_DMACFG 0x0010 /* DMA Control reg */
+#define GEM_TXSTATUS0x0014 /* TX Status reg */
+#define GEM_RXQBASE 0x0018 /* RX Q Base address reg */
+#define GEM_TXQBASE 0x001C /* TX Q Base address reg */
+#define GEM_RXSTATUS0x0020 /* RX Status reg */
+#define GEM_ISR 0x0024 /* Interrupt Status reg */
+#define GEM_IER 0x0028 /* Interrupt Enable reg */
+#define GEM_IDR 0x002C /* Interrupt Disable reg */
+#define GEM_IMR 0x0030 /* Interrupt Mask reg */
+#define GEM_PHYMNTNC0x0034 /* Phy Maintaince reg */
+#define GEM_RXPAUSE 0x0038 /* RX Pause Time reg */
+#define GEM_TXPAUSE 0x003C /* TX Pause Time reg */
+#define GEM_TXPARTIALSF 0x0040 /* TX Partial Store and Forward */
+#define GEM_RXPARTIALSF 0x0044 /* RX Partial Store and Forward */
+#define GEM_HASHLO 0x0080 /* Hash Low address reg */
+#define GEM_HASHHI 0x0084 /* Hash High address reg */
+#define GEM_SPADDR1LO 0x0088 /* Specific addr 1 low reg */
+#define GEM_SPADDR1HI 0x008C /* Specific addr 1 high reg */
+#define GEM_SPADDR2LO 0x0090 /* Specific addr 2 low reg */
+#define GEM_SPADDR2HI 0x0094 /* Specific addr 2 high reg */
+#define GEM_SPADDR3LO 0x0098 /* Specific addr 3 low reg */
+#define GEM_SPADDR3HI 0x009C /* Specific addr 3 high reg */
+#define GEM_SPADDR4LO 0x00A0 /* Specific addr 4 low reg */
+#define GEM_SPADDR4HI 0x00A4 /* Specific addr 4 high reg */
+#define GEM_TIDMATCH1 0x00A8 /* Type ID1 Match reg */
+#define GEM_TIDMATCH2 0x00AC /* Type ID2 Match reg */
+#define GEM_TIDMATCH3 0x00B0 /* Type ID3 Match reg */
+#define GEM_TIDMATCH4 0x00B4 /* Type ID4 Match reg */
+#define GEM_WOLAN 0x00B8 /* Wake on LAN reg */
+#define GEM_IPGSTRETCH 0x00BC /* IPG Stretch reg */
+#define GEM_SVLAN 0x00C0 /* Stacked VLAN reg */
+#define GEM_MODID 0x00FC /* Module ID reg */
+#define GEM_OCTTXLO 0x0100 /* Octects transmitted Low reg */
[Qemu-devel] [PATCH v5 0/4] Zynq-7000 EPP platform model
This is a suite of Device models and a machine model for the Xilinx Zynq-7000 Extensible Processing Platform: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm This is an ARM based platform featuring embedded SoC peripherals. This patch series includes a minimal set of device models and a a machine model capable of emulating zynq platforms booting linux. This first 3 patches in this series are device models for IP provided by cadence for the Zynq platform. The final patch is the initial revision of the zynq machine model. Most of this work was originally authored by Xilinx, as indicated by (c) notices in added files. Tree is available from: git://developer.petalogix.com/private/peterc/qemu.git branch: zynq-initial.5 --- changed from v4: fixed FSF addess (1/4) (2/4) (4/4) changed device_init -> type_init (all) changed from v3: fixed timer race condition issue (2/4) changed from v2: fixed timer prescision issue (2/4) fixed compile warnings in zynq_arm_sysctl (4/4) changes from v1: formatting and style fixes updated for QOM removed former patch 3 (cadence WDT device model) - not required removed former patch 5 (dtb argument) - this is currently under discussion in other patch series' removed former patch 6 (initrd parameterisation) - not required for minimal boot Peter A. G. Crosthwaite (4): cadence_uart: initial version of device model cadence_ttc: initial version of device model cadence_gem: initial version of device model xilinx_zynq: machine model initial version MAINTAINERS |5 + Makefile.target |4 + hw/cadence_gem.c | 1229 ++ hw/cadence_ttc.c | 439 ++ hw/cadence_uart.c| 559 +++ hw/xilinx_zynq.c | 176 +++ hw/zynq_arm_sysctl.c | 532 ++ 7 files changed, 2944 insertions(+), 0 deletions(-) create mode 100644 hw/cadence_gem.c create mode 100644 hw/cadence_ttc.c create mode 100644 hw/cadence_uart.c create mode 100644 hw/xilinx_zynq.c create mode 100644 hw/zynq_arm_sysctl.c -- 1.7.3.2
[Qemu-devel] [PATCH v5 1/4] cadence_uart: initial version of device model
Implemented cadence UART serial controller
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changed from v4:
fixed FSF addess
changed device_init -> type_init
changes from v1:
converted register file to array
added vmsd state save/load support
removed read side effects from CISR register
Makefile.target |1 +
hw/cadence_uart.c | 559 +
2 files changed, 560 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_uart.c
diff --git a/Makefile.target b/Makefile.target
index 29fde6e..411a4bf 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -343,6 +343,7 @@ endif
obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
+obj-arm-y += cadence_uart.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
new file mode 100644
index 000..a7e461f
--- /dev/null
+++ b/hw/cadence_uart.c
@@ -0,0 +1,559 @@
+/*
+ * Device model for Cadence UART
+ *
+ * Copyright (c) 2010 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written by Haibing Ma
+ *M.Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_UART_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define UART_INTR_RTRIG 0x0001
+#define UART_INTR_REMPTY0x0002
+#define UART_INTR_RFUL 0x0004
+#define UART_INTR_TEMPTY0x0008
+#define UART_INTR_TFUL 0x0010
+#define UART_INTR_ROVR 0x0020
+#define UART_INTR_FRAME 0x0040
+#define UART_INTR_PARE 0x0080
+#define UART_INTR_TIMEOUT 0x0100
+#define UART_INTR_DMSI 0x0200
+#define UART_INTR_TTRIG 0x0400
+#define UART_INTR_TNFUL 0x0800
+#define UART_INTR_TOVR 0x1000
+
+#define UART_CSR_RTRIG 0x0001
+#define UART_CSR_REMPTY 0x0002
+#define UART_CSR_RFUL 0x0004
+#define UART_CSR_TEMPTY 0x0008
+#define UART_CSR_TFUL 0x0010
+#define UART_CSR_ROVR 0x0020
+#define UART_CSR_FRAME 0x0040
+#define UART_CSR_PARE 0x0080
+#define UART_CSR_TIMEOUT0x0100
+#define UART_CSR_DMSI 0x0200
+#define UART_CSR_RACTIVE0x0400
+#define UART_CSR_TACTIVE0x0800
+#define UART_CSR_FDELT 0x1000
+#define UART_CSR_TTRIG 0x2000
+#define UART_CSR_TNFUL 0x4000
+
+#define UART_CR_STOPBRK 0x0100
+#define UART_CR_STARTBRK0x0080
+#define UART_CR_RST_TO 0x0040
+#define UART_CR_TX_DIS 0x0020
+#define UART_CR_TX_EN 0x0010
+#define UART_CR_RX_DIS 0x0008
+#define UART_CR_RX_EN 0x0004
+#define UART_CR_TXRST 0x0002
+#define UART_CR_RXRST 0x0001
+
+#define UART_MR_CLKS0x0001
+#define UART_MR_CHRL0x0006
+#define UART_MR_PAR 0x0038
+#define UART_MR_NBSTOP 0x00C0
+#define UART_MR_CHMODE 0x0300
+#define UART_MR_UCLKEN 0x0400
+#define UART_MR_IRMODE 0x0800
+
+#define UART_PARITY_ODD0x001
+#define UART_PARITY_EVEN 0x000
+#define UART_DATA_BITS_6 0x003
+#define UART_DATA_BITS_7 0x002
+#define UART_STOP_BITS_1 0x003
+#define UART_STOP_BITS_2 0x002
+#define RX_FIFO_SIZE 16
+#define TX_FIFO_SIZE 16
+#define UARK_INPUT_CLK 5000
+
+#define NORMAL_MODE0
+#define ECHO_MODE 1
+#define LOCAL_LOOPBACK 2
+#define REMOTE_LOOPBACK3
+
+#define R_CR (0x00/4)
+#define R_MR (0x04/4)
+#define R_IER (0x08/4)
+#define R_IDR (0x0C/4)
+#define R_IMR (0x10/4)
+#define R_CISR (0x14/4)
+#define R_BRGR (0x18/4)
+#define R_RTOR (0x1C/4)
+#define R_RTRIG(0x20/4)
+#define R_MCR (0x24/4)
+#define R_MSR (0x28/4)
+#define R_CSR (0x2C/4)
+#define R_TX_RX(0x30/4)
+#define R_BDIV (0x34/4)
+#define R_FDEL (0x38/4)
+#define R_PMIN (0x3C/4)
+#define R_PWID (0x40/4)
+#define R_TTRIG(0x44/4)
+
+#define R_MAX (R_TTRIG
[Qemu-devel] [PATCH v5 2/4] cadence_ttc: initial version of device model
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changed from v4:
fixed FSF addess
changed device_init -> type_init
changed from v3:
Fixed race condition where timer could miss match events on wrap around
changed from v2:
changed ptimer to QEMUTimer (Fixed skew/drift issue in timer delays)
changes from v1:
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 439 ++
2 files changed, 440 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_ttc.c
diff --git a/Makefile.target b/Makefile.target
index 411a4bf..1e8afe6 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -344,6 +344,7 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o
arm_timer.o
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
+obj-arm-y += cadence_ttc.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
new file mode 100644
index 000..14c3ba7
--- /dev/null
+++ b/hw/cadence_ttc.c
@@ -0,0 +1,439 @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+
+#ifdef CADENCE_TTC_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define COUNTER_INTR_IV 0x0001
+#define COUNTER_INTR_M1 0x0002
+#define COUNTER_INTR_M2 0x0004
+#define COUNTER_INTR_M3 0x0008
+#define COUNTER_INTR_OV 0x0010
+#define COUNTER_INTR_EV 0x0020
+
+#define COUNTER_CTRL_DIS0x0001
+#define COUNTER_CTRL_INT0x0002
+#define COUNTER_CTRL_DEC0x0004
+#define COUNTER_CTRL_MATCH 0x0008
+#define COUNTER_CTRL_RST0x0010
+
+#define CLOCK_CTRL_PS_EN0x0001
+#define CLOCK_CTRL_PS_V 0x001e
+
+typedef struct {
+QEMUTimer *timer;
+int freq;
+
+uint32_t reg_clock;
+uint32_t reg_count;
+uint32_t reg_value;
+uint16_t reg_interval;
+uint16_t reg_match[3];
+uint32_t reg_intr;
+uint32_t reg_intr_en;
+uint32_t reg_event_ctrl;
+uint32_t reg_event;
+
+uint64_t cpu_time;
+unsigned int cpu_time_valid;
+
+qemu_irq irq;
+} CadenceTimerState;
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+CadenceTimerState * timer[3];
+} cadence_ttc_state;
+
+static void cadence_timer_update(CadenceTimerState *s)
+{
+qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+}
+
+static CadenceTimerState *cadence_timer_from_addr(void *opaque,
+target_phys_addr_t offset)
+{
+unsigned int index;
+cadence_ttc_state *s = (cadence_ttc_state *)opaque;
+
+index = (offset >> 2) % 3;
+
+return s->timer[index];
+}
+
+static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t
timer_steps)
+{
+/* timer_steps has max value of 0x1. double check it
+ * (or overflow can happen below) */
+assert(timer_steps <= 1ULL << 32);
+
+uint64_t r = timer_steps * 10ULL;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
+} else {
+r >>= 16;
+}
+r /= (uint64_t)s->freq;
+return r;
+}
+
+static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
+{
+uint64_t to_divide = 10ULL;
+
+uint64_t r = ns;
+ /* for very large intervals (> 8s) do some division first to stop
+ * overflow (costs some prescision) */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r <<= 16;
+/* keep early-dividing as needed */
+while (r >= 8ULL << 30 && to_divide > 1) {
+r /= 1000;
+to_divide /= 1000;
+}
+r *= (uint64_t)s->freq;
+if (s->reg_clock & CLOCK_CTRL_PS_EN) {
+r /= 1 << (((s->reg_clock & CLOCK_C
[Qemu-devel] [PATCH v5 3/4] cadence_gem: initial version of device model
Device model for cadence gem ethernet controller.
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changed from v4:
changed device_init -> type_init
changes from v1:
removed global init function
marked vmsd as unmigratable
cleaned up debug messages
Makefile.target |1 +
hw/cadence_gem.c | 1229 ++
2 files changed, 1230 insertions(+), 0 deletions(-)
create mode 100644 hw/cadence_gem.c
diff --git a/Makefile.target b/Makefile.target
index 1e8afe6..84b559c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -345,6 +345,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o
pl110.o pl181.o pl190.o
obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
+obj-arm-y += cadence_gem.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
new file mode 100644
index 000..bce9ada
--- /dev/null
+++ b/hw/cadence_gem.c
@@ -0,0 +1,1229 @@
+/*
+ * QEMU Xilinx GEM emulation
+ *
+ * Copyright (c) 2011 Xilinx, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include /* For crc32 */
+#include
+
+#include "sysbus.h"
+#include "net.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "net/checksum.h"
+
+#ifdef CADENCE_GEM_ERR_DEBUG
+#define qemu_debug(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+fflush(stderr); \
+} while (0);
+#else
+#define qemu_debug(...)
+#endif
+
+#define GEM_NWCTRL 0x /* Network Control reg */
+#define GEM_NWCFG 0x0004 /* Network Config reg */
+#define GEM_NWSTATUS0x0008 /* Network Status reg */
+#define GEM_USERIO 0x000C /* User IO reg */
+#define GEM_DMACFG 0x0010 /* DMA Control reg */
+#define GEM_TXSTATUS0x0014 /* TX Status reg */
+#define GEM_RXQBASE 0x0018 /* RX Q Base address reg */
+#define GEM_TXQBASE 0x001C /* TX Q Base address reg */
+#define GEM_RXSTATUS0x0020 /* RX Status reg */
+#define GEM_ISR 0x0024 /* Interrupt Status reg */
+#define GEM_IER 0x0028 /* Interrupt Enable reg */
+#define GEM_IDR 0x002C /* Interrupt Disable reg */
+#define GEM_IMR 0x0030 /* Interrupt Mask reg */
+#define GEM_PHYMNTNC0x0034 /* Phy Maintaince reg */
+#define GEM_RXPAUSE 0x0038 /* RX Pause Time reg */
+#define GEM_TXPAUSE 0x003C /* TX Pause Time reg */
+#define GEM_TXPARTIALSF 0x0040 /* TX Partial Store and Forward */
+#define GEM_RXPARTIALSF 0x0044 /* RX Partial Store and Forward */
+#define GEM_HASHLO 0x0080 /* Hash Low address reg */
+#define GEM_HASHHI 0x0084 /* Hash High address reg */
+#define GEM_SPADDR1LO 0x0088 /* Specific addr 1 low reg */
+#define GEM_SPADDR1HI 0x008C /* Specific addr 1 high reg */
+#define GEM_SPADDR2LO 0x0090 /* Specific addr 2 low reg */
+#define GEM_SPADDR2HI 0x0094 /* Specific addr 2 high reg */
+#define GEM_SPADDR3LO 0x0098 /* Specific addr 3 low reg */
+#define GEM_SPADDR3HI 0x009C /* Specific addr 3 high reg */
+#define GEM_SPADDR4LO 0x00A0 /* Specific addr 4 low reg */
+#define GEM_SPADDR4HI 0x00A4 /* Specific addr 4 high reg */
+#define GEM_TIDMATCH1 0x00A8 /* Type ID1 Match reg */
+#define GEM_TIDMATCH2 0x00AC /* Type ID2 Match reg */
+#define GEM_TIDMATCH3 0x00B0 /* Type ID3 Match reg */
+#define GEM_TIDMATCH4 0x00B4 /* Type ID4 Match reg */
+#define GEM_WOLAN 0x00B8 /* Wake on LAN reg */
+#define GEM_IPGSTRETCH 0x00BC /* IPG Stretch reg */
+#define GEM_SVLAN 0x00C0 /* Stacked VLAN reg */
+#define GEM_MODID 0x00FC /* Module ID reg */
+#define GEM_OCTTXLO
[Qemu-devel] [PATCH v5 4/4] xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4:
fixed FSF addess
changed device_init -> type_init
changes since v2:
removed 2 compile warnings from zynq_arm_sysctl.c
changes since v1:
Added gem init function
remowed WDT instantiation
Added maintainers information
removed dead sys_id and proc_id variables
MAINTAINERS |5 +
Makefile.target |1 +
hw/xilinx_zynq.c | 176 +
hw/zynq_arm_sysctl.c | 532 ++
4 files changed, 714 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_zynq.c
create mode 100644 hw/zynq_arm_sysctl.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..9246bfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
+Xilinx Zynq
+M: Peter Crosthwaite
+S: Maintained
+F: hw/xilinx_zynq.c
+
CRIS Machines
-
Axis Dev88
diff --git a/Makefile.target b/Makefile.target
index 84b559c..40fd1b2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -346,6 +346,7 @@ obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
+obj-arm-y += xilinx_zynq.o zynq_arm_sysctl.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += arm_l2x0.o
obj-arm-y += arm_mptimer.o
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
new file mode 100644
index 000..8c456d3
--- /dev/null
+++ b/hw/xilinx_zynq.c
@@ -0,0 +1,176 @@
+/*
+ * Xilinx Zynq Baseboard System emulation.
+ *
+ * Copyright (c) 2010 Xilinx.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwa...@petalogix.com)
+ * Copyright (c) 2012 Petalogix Pty Ltd.
+ * Written by Haibing Ma
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "exec-memory.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "flash.h"
+#include "blockdev.h"
+#include "loader.h"
+
+#define FLASH_SIZE (64 * 1024 * 1024)
+#define FLASH_SECTOR_SIZE (128 * 1024)
+
+#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+
+static struct arm_boot_info zynq_binfo = {};
+
+static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+qemu_check_nic_model(nd, "cadence_gem");
+dev = qdev_create(NULL, "cadence_gem");
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+s = sysbus_from_qdev(dev);
+sysbus_mmio_map(s, 0, base);
+sysbus_connect_irq(s, 0, irq);
+}
+
+static void zynq_init(ram_addr_t ram_size, const char *boot_device,
+const char *kernel_filename, const char
*kernel_cmdline,
+const char *initrd_filename, const char *cpu_model)
+{
+CPUState *env = NULL;
+MemoryRegion *address_space_mem = get_system_memory();
+MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
+MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
+DeviceState *dev;
+SysBusDevice *busdev;
+qemu_irq *irqp;
+qemu_irq pic[64];
+NICInfo *nd;
+int n;
+qemu_irq cpu_irq[4];
+
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
+
+for (n = 0; n < smp_cpus; n++) {
+env = cpu_init(cpu_model);
+if (!env) {
+fprintf(stderr, "Unable to find CPU definition\n");
+exit(1);
+}
+irqp = arm_pic_init_cpu(env);
+cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+}
+
+/* max 2GB ram */
+if (ram_size > 0x8000) {
+ram_size = 0x8000;
+}
+
+/* DDR remapped to address zero. */
+memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
+vmstate_register_ram_global(ext_ram);
+memory_region_add_subregion(address_space_mem, 0, ext_ram);
+
+/* 256K of on-chip memory */
+memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
+vmstate_register_ram_global(ocm_ram);
+memory_region_add_subregion(address_space_mem, 0xFFFC, ocm_ram);
+
+DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
+
+#ifndef ZYNQ_FLASH_INTEL
+/* AMD */
+pflash_cfi02_register(0xe200, NULL, "zynq.pflash", FLASH_SIZE,
+ dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
+
[Qemu-devel] [PATCH v4 0/2] Xilinx Zynq PL330 support
These patches add support for the Primcell PL330 DMA controller and add it to the Xilinx Zynq machine model. Patch 1 is the device model. Patch 2 is the machine model update. The Device model was originally contributed by Kirill Batuzov / Samsung, as indicated by the (C) notice in hw/pl330.c. changed since v3: rebased against Makefile refactor changed since v2: addressed reviewer comments from Igor mitsyanko and Peter Maydell (1/2) Peter A. G. Crosthwaite (2): pl330: initial version xilinx_zynq: added pl330 to machine model hw/arm/Makefile.objs |1 + hw/pl330.c | 1411 ++ hw/xilinx_zynq.c | 18 + 3 files changed, 1430 insertions(+), 0 deletions(-) create mode 100644 hw/pl330.c -- 1.7.3.2
[Qemu-devel] [PATCH v4 2/2] xilinx_zynq: added pl330 to machine model
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx_zynq.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 7e6c273..c20a896 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -61,6 +61,9 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
NICInfo *nd;
int n;
qemu_irq cpu_irq;
+int dma_irqs[8] = {
+46, 47, 48, 49, 72, 73, 74, 75
+};
if (!cpu_model) {
cpu_model = "cortex-a9";
@@ -130,6 +133,21 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
}
}
+dev = qdev_create(NULL, "pl330");
+qdev_prop_set_uint32(dev, "cfg0", 0x001e3071); /* CR0 */
+qdev_prop_set_uint32(dev, "cfg1", 0x0074); /* CR1 ... */
+qdev_prop_set_uint32(dev, "cfg2", 0x);
+qdev_prop_set_uint32(dev, "cfg3", 0x);
+qdev_prop_set_uint32(dev, "cfg4", 0x); /* ... CR4 */
+qdev_prop_set_uint32(dev, "cfg5", 0x07ff7f73); /* CRD */
+qdev_init_nofail(dev);
+busdev = sysbus_from_qdev(dev);
+sysbus_mmio_map(busdev, 0, 0xF8003000);
+sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
+for (n = 0; n < 8; ++n) { /* event irqs */
+sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
+}
+
zynq_binfo.ram_size = ram_size;
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
--
1.7.3.2
[Qemu-devel] [PATCH v4 1/2] pl330: initial version
Device model for Primecell PL330 dma controller.
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: Kirill Batuzov
---
changed from v3:
rebased against Makefile refactor
changed from v2 (in order of diff appearance):
GPL version changed to v2 or later
Register and field names changed to match TRM
id field corrected
PL330ChanState enum corrected
target_phys_addr_t usages removed
identifier camel casing and underscoring fixed
data fifo reworked (uses head ptr and a occupancy count rather than head & tail
ptrs)
pl330_insn_from_queue->pl330_queue_remove_insn
Numerous typos in comments corrected as per review
g_malloc0(sizeof(a) * b) -> g_new
pl330_fifo_inc: changed to accept PL330Fifo struct as argument (rather than
buf_size)
pl330_fifo_push/get: rollback on overflow mechanism replaced with pre-check
pl330_queue_find_insn: fixed ugly if statement whitespace (PMM review)
pl330_dmaaddh: fixed arugment reversal
pl330_dmaaddh: asserted on !manager
"ns": change to be and behave like a boolean globally
pl330_dmald: force num=1 when PL330_SINGLE
pl330_dma_kill: put in correct alphabet order
pl330_dmarmb/wmb:implemented
pl330_exec_insn: asserted insn->size not too big
pl330_exec_insn: enabled stall mechanism outside exec state (needed for rmb/wmb)
pl330_debug_exec: assert fault type on a fault
pl330_iomem_write: removed aligmnent assertion
pl330_iomem_write: corrected ev_status and irq_status logic
pl330_iomem_read_imp: fixed some incorrect bitfield positions (PMM review)
pl330_reset: stopped timer
pl330_init: removed redundant reset
changed from v1:
GPLv2 license
some code formatting fixes
hw/arm/Makefile.objs |1 +
hw/pl330.c | 1411 ++
2 files changed, 1412 insertions(+), 0 deletions(-)
create mode 100644 hw/pl330.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a0ff6a6..b28e5b7 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -7,6 +7,7 @@ obj-y += cadence_ttc.o
obj-y += cadence_gem.o
obj-y += xilinx_zynq.o zynq_slcr.o
obj-y += arm_gic.o
+obj-y += pl330.o
obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
diff --git a/hw/pl330.c b/hw/pl330.c
new file mode 100644
index 000..bc6bc35
--- /dev/null
+++ b/hw/pl330.c
@@ -0,0 +1,1411 @@
+/*
+ * ARM PrimeCell PL330 DMA Controller
+ *
+ * Copyright (c) 2009 Samsung Electronics.
+ * Contributed by Kirill Batuzov
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 or later.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+
+#ifdef PL330_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+#define PL330_CHAN_NUM 8
+#define PL330_PERIPH_NUM32
+#define PL330_MAX_BURST_LEN 128
+#define PL330_INSN_MAXSIZE 6
+
+#define PL330_FIFO_OK 0
+#define PL330_FIFO_STALL1
+#define PL330_FIFO_ERR (-1)
+
+#define PL330_FAULT_UNDEF_INSTR (1 << 0)
+#define PL330_FAULT_OPERAND_INVALID (1 << 1)
+#define PL330_FAULT_DMAGO_ERR (1 << 4)
+#define PL330_FAULT_EVENT_ERR (1 << 5)
+#define PL330_FAULT_CH_PERIPH_ERR (1 << 6)
+#define PL330_FAULT_CH_RDWR_ERR (1 << 7)
+#define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12)
+#define PL330_FAULT_FIFOEMPTY_ERR (1 << 13)
+#define PL330_FAULT_INSTR_FETCH_ERR (1 << 16)
+#define PL330_FAULT_DATA_WRITE_ERR (1 << 17)
+#define PL330_FAULT_DATA_READ_ERR (1 << 18)
+#define PL330_FAULT_DBG_INSTR (1 << 30)
+#define PL330_FAULT_LOCKUP_ERR (1 << 31)
+
+#define PL330_UNTAGGED 0xff
+
+#define PL330_SINGLE0x0
+#define PL330_BURST 0x1
+
+#define PL330_WATCHDOG_LIMIT1024
+
+/* IOMEM mapped registers */
+#define PL330_REG_DSR 0x000
+#define PL330_REG_DPC 0x004
+#define PL330_REG_INTEN 0x020
+#define PL330_REG_INT_EVENT_RIS 0x024
+#define PL330_REG_INTMIS0x028
+#define PL330_REG_INTCLR0x02C
+#define PL330_REG_FSRD 0x030
+#define PL330_REG_FSRC 0x034
+#define PL330_REG_FTRD
[Qemu-devel] [PATCH] arm_gic: Send dbg msgs to stderr not stdout
Signed-off-by: Peter A. G. Crosthwaite
---
hw/arm_gic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 72298b4..c78d58e 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -35,7 +35,7 @@
#ifdef DEBUG_GIC
#define DPRINTF(fmt, ...) \
-do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
+do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#endif
--
1.7.3.2
[Qemu-devel] [PATCH v2 0/2] These two patches add some flexibilities to the arm bootloader.
Set up the the bootloader so that if -dtb is specified, then the Linux bootflow is assumed. Conditionalised dtb command line update on there being a -append argument. Means you can use a dtb with a command line already present and boot without QEMU nuking your command line. The patches are independent. A block on patch one whould not block patch 2 and vice versa. Sent as one series for reviewer convenience. changed since v1: replaced old patch one (used to be cmd line arg for linux - now is just dtb implies linux) tweaked implementation of patch 2 Peter A. G. Crosthwaite (2): arm_boot: Assume Linux boot flow when -dtb given arm_boot: Conditionalised DTB command line update hw/arm_boot.c | 15 +++ 1 files changed, 11 insertions(+), 4 deletions(-) -- 1.7.3.2
[Qemu-devel] [PATCH v2 1/2] arm_boot: Assume Linux boot flow when -dtb given
If the user boots with a -dtb assume the Linux boot flow, even when handling an
elf.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/arm_boot.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 7447f5c..f0fa23c 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -360,6 +360,11 @@ void arm_load_kernel(CPUARMState *env, struct
arm_boot_info *info)
exit(1);
}
info->entry = entry;
+
+if (info->dtb_filename) {
+is_linux = 1;
+}
+
if (is_linux) {
if (info->initrd_filename) {
initrd_size = load_image_targphys(info->initrd_filename,
--
1.7.3.2
[Qemu-devel] [PATCH v2 2/2] arm_boot: Conditionalised DTB command line update
The DTB command line should only be overwritten if the user provides a command
line with -apend. Otherwise whatever command line was in the DTB should stay
unchanged.
Signed-off-by: Peter A. G. Crosthwaite
---
changed since v1:
checked cmd line string in binfo rather than machine opt
hw/arm_boot.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index f0fa23c..1b110ca 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -240,10 +240,12 @@ static int load_dtb(target_phys_addr_t addr, const struct
arm_boot_info *binfo)
fprintf(stderr, "couldn't set /memory/reg\n");
}
-rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
- binfo->kernel_cmdline);
-if (rc < 0) {
-fprintf(stderr, "couldn't set /chosen/bootargs\n");
+if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
+rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
+ binfo->kernel_cmdline);
+if (rc < 0) {
+fprintf(stderr, "couldn't set /chosen/bootargs\n");
+}
}
if (binfo->initrd_size) {
--
1.7.3.2
[Qemu-devel] [PATCH] cadence_gem: Avoid stack-writing buffer-overrun
From: Jim Meyering
Use sizeof(rxbuf)-size (not sizeof(rxbuf-size)) as the number
of bytes to clear. The latter would always clear 4 or 8
bytes, possibly writing beyond the end of that stack buffer.
Alternatively, depending on the value of the "size" parameter,
it could fail to initialize the end of "rxbuf".
Spotted by coverity.
Signed-off-by: Jim Meyering
Signed-off-by: Peter A. G. Crosthwaite
---
hw/cadence_gem.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index e2140ae..dbde392 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -664,7 +664,7 @@ static ssize_t gem_receive(VLANClientState *nc, const
uint8_t *buf, size_t size)
*/
memcpy(rxbuf, buf, size);
-memset(rxbuf + size, 0, sizeof(rxbuf - size));
+memset(rxbuf + size, 0, sizeof(rxbuf) - size);
rxbuf_ptr = rxbuf;
crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
if (size < 60) {
--
1.7.3.2
[Qemu-devel] [PATCH v1] device_tree: load_device_tree(): Allow NULL sizep
The sizep arg is populated with the size of the loaded device tree. Since this
is one of those informational "please populate" type arguments it should be
optional. Guarded writes to *sizep against NULL accordingly.
Signed-off-by: Peter A. G. Crosthwaite
---
device_tree.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index 86a694c..0ed0256 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -32,7 +32,9 @@ void *load_device_tree(const char *filename_path, int *sizep)
int ret;
void *fdt = NULL;
-*sizep = 0;
+if (sizep) {
+*sizep = 0;
+}
dt_size = get_image_size(filename_path);
if (dt_size < 0) {
printf("Unable to get size of device tree file '%s'\n",
@@ -65,7 +67,9 @@ void *load_device_tree(const char *filename_path, int *sizep)
filename_path);
goto fail;
}
-*sizep = dt_size;
+if (sizep) {
+*sizep = dt_size;
+}
return fdt;
fail:
--
1.7.3.2
[Qemu-devel] [RFC] block: Removed coroutine ownership assumption
The block layer assumes that it is the only user of coroutines -
The qemu_in_coroutine() is used to determine if a function is in one of the
block layers coroutines, which is flawed. I.E. If a client (e.g. a device or
a machine model) of the block layer uses couroutine itself, the block layer
will identify the callers coroutines as its own, and may falsely yield the
calling coroutine (instead of creating its own to yield).
AFAICT, there are no conflicts in the QEMU master here yet, but its kind of an
issue, as anyone who comes along and used coroutines and the block layer
together is going to run into some very obscure and hard to debug race
conditions.
Signed-off-by: Peter A. G. Crosthwaite
---
block.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/block.c b/block.c
index 0acdcac..b50af15 100644
--- a/block.c
+++ b/block.c
@@ -380,7 +380,7 @@ int bdrv_create(BlockDriver *drv, const char* filename,
return -ENOTSUP;
}
-if (qemu_in_coroutine()) {
+if (0) {
/* Fast-path if already in coroutine context */
bdrv_create_co_entry(&cco);
} else {
@@ -1590,7 +1590,7 @@ static int bdrv_rw_co(BlockDriverState *bs, int64_t
sector_num, uint8_t *buf,
bdrv_io_limits_disable(bs);
}
-if (qemu_in_coroutine()) {
+if (0) {
/* Fast-path if already in coroutine context */
bdrv_rw_co_entry(&rwco);
} else {
@@ -3813,7 +3813,7 @@ int bdrv_flush(BlockDriverState *bs)
.ret = NOT_DONE,
};
-if (qemu_in_coroutine()) {
+if (0) {
/* Fast-path if already in coroutine context */
bdrv_flush_co_entry(&rwco);
} else {
@@ -3874,7 +3874,7 @@ int bdrv_discard(BlockDriverState *bs, int64_t
sector_num, int nb_sectors)
.ret = NOT_DONE,
};
-if (qemu_in_coroutine()) {
+if (0) {
/* Fast-path if already in coroutine context */
bdrv_discard_co_entry(&rwco);
} else {
--
1.7.3.2
[Qemu-devel] [PATCH v2 0/3] Microblaze and Device Tree Maintainerships
Set some missing maintainer ships. Patch 1 is the Petalogix ML605 machine model (me). Patch 2 is the Xilinx EDK device suite (me + Edgar). Patch 3 is the device tree subsystem (me + Alex). Changed since v1: Added Alexs ack for p3. Peter A. G. Crosthwaite (3): MAINTAINERS: Add Petalogix ml605 machine model MAINTAINERS: Added Xilinx EDK devices MAINTAINERS: Added device tree MAINTAINERS | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) -- 1.7.3.2
[Qemu-devel] [PATCH v2 1/3] MAINTAINERS: Add Petalogix ml605 machine model
Signed-off-by: Peter A. G. Crosthwaite --- MAINTAINERS |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b45f075..d544a9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -311,6 +311,11 @@ M: Edgar E. Iglesias S: Maintained F: hw/petalogix_s3adsp1800.c +petalogix_ml605 +M: Peter Crosthwaite +S: Maintained +F: hw/petalogix_ml605_mmu.c + MIPS Machines - Jazz -- 1.7.3.2
[Qemu-devel] [PATCH v2 3/3] MAINTAINERS: Added device tree
Agreed between myself and Alex: http://lists.nongnu.org/archive/html/qemu-devel/2012-06/msg03561.html Signed-off-by: Peter A. G. Crosthwaite Acked-by: Alexander Graf --- MAINTAINERS |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index e19f491..2a514fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -511,6 +511,12 @@ M: Anthony Liguori S: Maintained F: qemu-char.c +Device Tree +M: Peter Crosthwaite +M: Alexander Graf +S: Maintained +F: device-tree.[ch] + GDB stub M: qemu-devel@nongnu.org S: Odd Fixes -- 1.7.3.2
[Qemu-devel] [PATCH v2 2/3] MAINTAINERS: Added Xilinx EDK devices
Signed-off-by: Peter A. G. Crosthwaite --- MAINTAINERS | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d544a9c..e19f491 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -482,6 +482,17 @@ S: Supported F: hw/virtio-serial* F: hw/virtio-console* +Xilinx EDK +M: Peter Crosthwaite +M: Edgar E. Iglesias +S: Maintained +F: hw/xilinx_axi* +F: hw/xilinx_uartlite.c +F: hw/xilinx_intc.c +F: hw/xilinx_ethlite.c +F: hw/xilinx_timer.c +F: hw/xilinx.h + Subsystems -- Audio -- 1.7.3.2
[Qemu-devel] [PULL] Standard SD host controller model
target-ppc: Fix 2nd parameter for tcg_gen_shri_tl (2012-06-24 22:52:11 +0200) are available in the git repository at: git://developer.petalogix.com/public/qemu.git third-party/igor-sdhci.next Igor Mitsyanko (2): hw: introduce standard SD host controller exynos4210: Added SD host controller model Peter A. G. Crosthwaite (2): vl.c: allow for repeated -sd arguments xilinx_zynq: Added SD controllers default-configs/arm-softmmu.mak |1 + hw/Makefile.objs|1 + hw/arm/Makefile.objs|1 + hw/exynos4210.c | 20 + hw/exynos4210_sdhci.c | 438 + hw/sdhci.c | 1306 +++ hw/sdhci.h | 310 + hw/xilinx_zynq.c| 12 + vl.c|2 +- 9 files changed, 2090 insertions(+), 1 deletions(-) create mode 100644 hw/exynos4210_sdhci.c create mode 100644 hw/sdhci.c create mode 100644 hw/sdhci.h
[Qemu-devel] [PATCH v1] xilinx_timer: Removed comma in device name
Fixes an error in a61e4b07a30c062260d2d01771773f14820d1eb7
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx.h |2 +-
hw/xilinx_timer.c |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 7df21eb..c4d9d19 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -20,7 +20,7 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq,
int oto, int freq)
{
DeviceState *dev;
-dev = qdev_create(NULL, "xlnx,xps-timer");
+dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", oto);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_init_nofail(dev);
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index b562bd0..053ba02 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -217,7 +217,7 @@ static int xilinx_timer_init(SysBusDevice *dev)
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
-memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx,xps-timer",
+memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
sysbus_init_mmio(dev, &t->mmio);
return 0;
@@ -239,7 +239,7 @@ static void xilinx_timer_class_init(ObjectClass *klass,
void *data)
}
static TypeInfo xilinx_timer_info = {
-.name = "xlnx,xps-timer",
+.name = "xlnx.xps-timer",
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct timerblock),
.class_init= xilinx_timer_class_init,
--
1.7.3.2
[Qemu-devel] [PATCH v2 0/2] QOMify AXI stream for Xilinx AXI ethernet/DMA
Next revision of the series for AXI-stream, rebased on anthonys refactoring of the Interface system. Anthonys patch is already on the mailing list, but I have included it form completeness. P2 is all the actual axi-stream device land device-land stuff. Changed since V1: Rebased Anthonys patch (P1) (Heavy conflict with final phase qom-next merge) Rolled Interface + link bug patch (formerly P3) into P1 Anthony Liguori (1): qom: Reimplement Interfaces Peter A. G. Crosthwaite (1): xilinx_axi*: Re-implemented interconnect hw/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 24 +++-- hw/stream.c | 23 + hw/stream.h | 31 +++ hw/xilinx.h | 22 ++--- hw/xilinx_axidma.c | 74 +--- hw/xilinx_axidma.h | 39 hw/xilinx_axienet.c | 32 --- include/qemu/object.h| 46 ++ qom/object.c | 220 ++ 10 files changed, 255 insertions(+), 257 deletions(-) create mode 100644 hw/stream.c create mode 100644 hw/stream.h delete mode 100644 hw/xilinx_axidma.h -- 1.7.3.2
[Qemu-devel] [PATCH v3 1/2] qom: Reimplement Interfaces
From: Anthony Liguori
The current implementation of Interfaces is poorly designed. Each interface
that an object implements ends up being an object that's tracked by the
implementing object. There's all sorts of gymnastics to deal with casting
between these objects.
But an interface shouldn't be associated with an Object. Interfaces are global
to a class. This patch moves all Interface knowledge to ObjectClass eliminating
the relationship between Object and Interfaces.
Interfaces are now abstract (as they should be) but this is okay. Interfaces
essentially act as additional parents for the classes and are treated as such.
With this new implementation, we should fully support derived interfaces
including reimplementing an inherited interface.
PC: Rebased against qom-next merge Jun-2012.
PC: Removed replication of cast logic for interfaces, i.e. there is only
one cast function - object_dynamic_cast() (and object_dynamic_cast_assert())
Signed-off-by: Anthony Liguori
Signed-off-by: Peter A. G. Crosthwaite
---
include/qemu/object.h | 46 +++
qom/object.c | 220 +++--
2 files changed, 116 insertions(+), 150 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index 8b17776..cc75fee 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -239,6 +239,7 @@ struct ObjectClass
{
/*< private >*/
Type type;
+GSList *interfaces;
};
/**
@@ -260,7 +261,6 @@ struct Object
{
/*< private >*/
ObjectClass *class;
-GSList *interfaces;
QTAILQ_HEAD(, ObjectProperty) properties;
uint32_t ref;
Object *parent;
@@ -387,6 +387,16 @@ struct TypeInfo
OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name)
/**
+ * InterfaceInfo:
+ * @type: The name of the interface.
+ *
+ * The information associated with an interface.
+ */
+struct InterfaceInfo {
+const char *type;
+};
+
+/**
* InterfaceClass:
* @parent_class: the base class
*
@@ -396,26 +406,30 @@ struct TypeInfo
struct InterfaceClass
{
ObjectClass parent_class;
+/*< private >*/
+ObjectClass *concrete_class;
};
+#define TYPE_INTERFACE "interface"
+
/**
- * InterfaceInfo:
- * @type: The name of the interface.
- * @interface_initfn: This method is called during class initialization and is
- * used to initialize an interface associated with a class. This function
- * should initialize any default virtual functions for a class and/or
override
- * virtual functions in a parent class.
- *
- * The information associated with an interface.
+ * INTERFACE_CLASS:
+ * @klass: class to cast from
+ * Returns: An #InterfaceClass or raise an error if cast is invalid
*/
-struct InterfaceInfo
-{
-const char *type;
+#define INTERFACE_CLASS(klass) \
+OBJECT_CLASS_CHECK(InterfaceClass, klass, TYPE_INTERFACE)
-void (*interface_initfn)(ObjectClass *class, void *data);
-};
-
-#define TYPE_INTERFACE "interface"
+/**
+ * INTERFACE_CHECK:
+ * @interface: the type to return
+ * @obj: the object to convert to an interface
+ * @name: the interface type name
+ *
+ * Returns: @obj casted to @interface if cast is valid, otherwise raise error.
+ */
+#define INTERFACE_CHECK(interface, obj, name) \
+((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name)))
/**
* object_new:
diff --git a/qom/object.c b/qom/object.c
index 00bb3b0..a552be2 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -31,9 +31,7 @@ typedef struct TypeImpl TypeImpl;
struct InterfaceImpl
{
-const char *parent;
-void (*interface_initfn)(ObjectClass *class, void *data);
-TypeImpl *type;
+const char *typename;
};
struct TypeImpl
@@ -64,14 +62,6 @@ struct TypeImpl
InterfaceImpl interfaces[MAX_INTERFACES];
};
-typedef struct Interface
-{
-Object parent;
-Object *obj;
-} Interface;
-
-#define INTERFACE(obj) OBJECT_CHECK(Interface, obj, TYPE_INTERFACE)
-
static Type type_interface;
static GHashTable *type_table_get(void)
@@ -98,6 +88,7 @@ static TypeImpl *type_table_lookup(const char *name)
static TypeImpl *type_register_internal(const TypeInfo *info)
{
TypeImpl *ti = g_malloc0(sizeof(*ti));
+int i;
g_assert(info->name != NULL);
@@ -122,15 +113,10 @@ static TypeImpl *type_register_internal(const TypeInfo
*info)
ti->abstract = info->abstract;
-if (info->interfaces) {
-int i;
-
-for (i = 0; info->interfaces[i].type; i++) {
-ti->interfaces[i].parent = info->interfaces[i].type;
-ti->interfaces[i].interface_initfn =
info->interfaces[i].interface_initfn;
-ti->num_interfaces++;
-}
+for (i = 0; info->interfaces && info->interfaces[i].type; i++) {
+ti->interfaces[i].typename = g_strdup(info->interfaces[i].type);
}
+ti->num_interfaces = i;
type_table_add(ti);
[Qemu-devel] [PATCH v3 2/2] xilinx_axi*: Re-implemented interconnect
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
controllers. A QOM interface "stream" is created, for the two stream interfaces.
As per Edgars request, this is designed to be more generic than AXI-stream,
so in the future we may see more clients of this interface beyond AXI stream.
This is based primarily on Paolos original refactoring of the interconnect.
Signed-off-by: Paolo Bonzini
Signed-off-by: Peter A.G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/petalogix_ml605_mmu.c | 24 +--
hw/stream.c | 23 ++
hw/stream.h | 31 +++
hw/xilinx.h | 22 +
hw/xilinx_axidma.c | 74 +
hw/xilinx_axidma.h | 39
hw/xilinx_axienet.c | 32 ---
8 files changed, 139 insertions(+), 107 deletions(-)
create mode 100644 hw/stream.c
create mode 100644 hw/stream.h
delete mode 100644 hw/xilinx_axidma.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 3d77259..5e2f5be 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -65,6 +65,7 @@ hw-obj-$(CONFIG_XILINX) += xilinx_timer.o
hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+hw-obj-$(CONFIG_XILINX_AXI) += stream.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 6a7d0c0..dced648 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -39,7 +39,8 @@
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
-#include "xilinx_axidma.h"
+
+#include "stream.h"
#define LMB_BRAM_SIZE (128 * 1024)
#define FLASH_SIZE (32 * 1024 * 1024)
@@ -76,7 +77,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
-DeviceState *dev;
+DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
CPUMBState *env;
DriveInfo *dinfo;
@@ -125,15 +126,18 @@ petalogix_ml605_init(ram_addr_t ram_size,
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 100);
-/* axi ethernet and dma initialization. TODO: Dynamically connect them. */
-{
-static struct XilinxDMAConnection dmach;
+/* axi ethernet and dma initialization. */
+dma = qdev_create(NULL, "xlnx.axi-dma");
-xilinx_axiethernet_create(&dmach, &nd_table[0], 0x8278,
- irq[3], 0x1000, 0x1000);
-xilinx_axiethernetdma_create(&dmach, 0x8460,
- irq[1], irq[0], 100 * 100);
-}
+/* FIXME: attach to the sysbus instead */
+object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ "xilinx-dma", OBJECT(dma), NULL);
+
+eth0 = xilinx_axiethernet_create(&nd_table[0], STREAM_SLAVE(dma),
+ 0x8278, irq[3], 0x1000, 0x1000);
+
+xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
+ 0x8460, irq[1], irq[0], 100 * 100);
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
diff --git a/hw/stream.c b/hw/stream.c
new file mode 100644
index 000..001e2bd
--- /dev/null
+++ b/hw/stream.c
@@ -0,0 +1,23 @@
+#include "stream.h"
+
+void
+axi_stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app)
+{
+StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+
+k->push(sink, buf, len, app);
+}
+
+static TypeInfo axi_stream_slave_info = {
+.name = TYPE_STREAM_SLAVE,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(StreamSlaveClass),
+};
+
+
+static void axi_stream_slave_register_types(void)
+{
+type_register_static(&axi_stream_slave_info);
+}
+
+type_init(axi_stream_slave_register_types)
diff --git a/hw/stream.h b/hw/stream.h
new file mode 100644
index 000..b7f3b3e
--- /dev/null
+++ b/hw/stream.h
@@ -0,0 +1,31 @@
+#ifndef STREAM_H
+#define STREAM_H 1
+
+#include "qemu-common.h"
+#include "qemu/object.h"
+
+/* AXI stream slave. Used until qdev provides a generic way. */
+#define TYPE_STREAM_SLAVE "stream-slave"
+
+#define STREAM_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
+#define STREAM_SLAVE(obj) \
+ INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
+
+typedef struct StreamSlave {
+Object Parent;
+} StreamSlave;
+
+typedef struct StreamSlaveClass {
+InterfaceClass parent;
+
+void (*push)(StreamSlave *obj, unsigned char *buf, size_t
[Qemu-devel] [PATCH v5 0/4] Standard SD host controller model
[Original cover by Igor] First patch introduces standard SD host controller model. This is accumulated version of my previous patch I sent a while ago and a recent SDHCI patch by Peter A. G. Crosthwaite. Second patch introduces Exynos4210-specific SDHCI built on top of standard SDHCI model. [New] Third patch changes the -sd command line argument to be repeatable, to support multiple SD controllers in one system. Fourth patch adds 2x SDHCI controllers to the Xilinx Zynq machine This revision is typo fixes and rebasing only. Changelog: Changed from v4: Igors changes re PMM review (P1/2) Typo in commit msg (P3) removed redundant braces in P4 Changed from v3: Rebased for new Makefile system Fixed include guard in sdhci.h Typos in commit messages Changed from v2: corrected typo errors in ADMA1 support added patches 3-4 v1->v2 PATCH1: add support for ADMA1 (I havn't tested it though). fixed s->prnsts <-> s->pwrcon typo (thanks to Peter, strange that it even worked before). PATCH2: change header prefix from "target-arm" to "exynos4210". Peter A. G. Crosthwaite (2): vl.c: allow for repeated -sd arguments xilinx_zynq: Added SD controllers default-configs/arm-softmmu.mak |1 + hw/Makefile.objs|1 + hw/arm/Makefile.objs|1 + hw/exynos4210.c | 20 + hw/exynos4210_sdhci.c | 443 + hw/sdhci.c | 1313 +++ hw/sdhci.h | 310 + hw/xilinx_zynq.c| 10 + vl.c|2 +- 9 files changed, 2100 insertions(+), 1 deletions(-) create mode 100644 hw/exynos4210_sdhci.c create mode 100644 hw/sdhci.c create mode 100644 hw/sdhci.h -- 1.7.3.2
[Qemu-devel] [PATCH v5 2/4] exynos4210: Added SD host controller model
From: Igor Mitsyanko
Custom Exynos4210 SD/MMC host controller, based on SD association standard host
controller ver. 2.00.
Signed-off-by: Igor Mitsyanko
---
changed from v4 (Igor):
set irq on SLOTINT status instead of interrupt registers status; instead;
conditional in exynos4210_sdhci_can_issue_command() made more readable and
documented;
add a comment to exynos4210_sdhci_writefn()'s SDHC_CLKCON case statement;
do not override superclass property in exynos4210.sdhci class, set properties
to required value in realize function
changed from v3:
rebased for new Makefile system
fixed commit msg typo (Andreas review)
hw/arm/Makefile.objs |1 +
hw/exynos4210.c | 20 +++
hw/exynos4210_sdhci.c | 443 +
3 files changed, 464 insertions(+), 0 deletions(-)
create mode 100644 hw/exynos4210_sdhci.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 88ff47d..c3afb6e 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -11,6 +11,7 @@ obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o
a9mpcore.o
obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
obj-y += exynos4210_pmu.o exynos4210_mct.o exynos4210_fimd.o
+obj-y += exynos4210_sdhci.o
obj-y += arm_l2x0.o
obj-y += arm_mptimer.o a15mpcore.o
obj-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
diff --git a/hw/exynos4210.c b/hw/exynos4210.c
index 9c20b3f..1a2e3d9 100644
--- a/hw/exynos4210.c
+++ b/hw/exynos4210.c
@@ -56,6 +56,12 @@
#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x1044
#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
+/* SD/MMC host controllers SFR base addresses */
+#define EXYNOS4210_SDHC0_BASE_ADDR 0x1251
+#define EXYNOS4210_SDHC1_BASE_ADDR 0x1252
+#define EXYNOS4210_SDHC2_BASE_ADDR 0x1253
+#define EXYNOS4210_SDHC3_BASE_ADDR 0x1254
+
/* PMU SFR base address */
#define EXYNOS4210_PMU_BASE_ADDR0x1002
@@ -292,6 +298,20 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP,
3)]);
+/*** SD/MMC host controllers ***/
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC0_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 0)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC1_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 1)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC2_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 2)]);
+
+sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC3_BASE_ADDR,
+s->irq_table[exynos4210_get_irq(29, 3)]);
+
/*** Display controller (FIMD) ***/
sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
s->irq_table[exynos4210_get_irq(11, 0)],
diff --git a/hw/exynos4210_sdhci.c b/hw/exynos4210_sdhci.c
new file mode 100644
index 000..4e87c0c
--- /dev/null
+++ b/hw/exynos4210_sdhci.c
@@ -0,0 +1,443 @@
+/*
+ * Samsung Exynos4210 SD/MMC host controller model
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Mitsyanko Igor
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see
[Qemu-devel] [PATCH v5 3/4] vl.c: allow for repeated -sd arguments
Allows for repeating of -sd arguments in the same way as -pflash and -mtdblock. Signed-off-by: Peter A. G. Crosthwaite Acked-by: Igor Mitsyanko --- changed from v4: fixed (another) commit msg typo changed from v3: fixed commit msg typo vl.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/vl.c b/vl.c index 1329c30..fe1f33b 100644 --- a/vl.c +++ b/vl.c @@ -2431,7 +2431,7 @@ int main(int argc, char **argv, char **envp) drive_add(IF_MTD, -1, optarg, MTD_OPTS); break; case QEMU_OPTION_sd: -drive_add(IF_SD, 0, optarg, SD_OPTS); +drive_add(IF_SD, -1, optarg, SD_OPTS); break; case QEMU_OPTION_pflash: drive_add(IF_PFLASH, -1, optarg, PFLASH_OPTS); -- 1.7.3.2
[Qemu-devel] [PATCH v5 4/4] xilinx_zynq: Added SD controllers
The Xilinx Zynq device has two SDHCI controllers. Added to the machine model. Signed-off-by: Peter A. G. Crosthwaite --- changed from v4: removed redundant braces changed from v3: fixed indentation tweaked commit msg hw/xilinx_zynq.c | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..a7feabe 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -130,6 +130,16 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, } } +dev = qdev_create(NULL, "sdhci"); +qdev_init_nofail(dev); +sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xE010); +sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[56-IRQ_OFFSET]); + +dev = qdev_create(NULL, "sdhci"); +qdev_init_nofail(dev); +sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xE0101000); +sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[79-IRQ_OFFSET]); + zynq_binfo.ram_size = ram_size; zynq_binfo.kernel_filename = kernel_filename; zynq_binfo.kernel_cmdline = kernel_cmdline; -- 1.7.3.2
[Qemu-devel] [PATCH v7 00/13] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller
This series reworks the SSI bus framework for SPI and add some new SPI controllers and devices: Patches 1-4 reworks SSI to add chip-select support to SPI devices and allow for multiple SPI devices attached to the same bus. Patches 5-6 fix the SPI setup in the stellaris machine model. Patch 7 is a general FIFO helper API used by the upcomming patches. Patch 8 is a device model for the m25p80 SPI flash family. Patches 9 & 11 are the Xilinx SPI flash controller devices Patches 10 & 12 add SPI controllers to the ML605 and Zynq machine models. Patch 13 is Maintainerships. CHANGELOG: changed from v6: Address Blue Swirl Review (P8, P11) changed from v5: VMSD version bump various line-by-line review fixes removed trivial patch (formerly P8) collapsed former P2-3 into one patch for bisectability changed from v4 (Major changes): Completely reworked SPI refactor. Please re-review from scratch. Added Zynq SPI flash. Factored out FIFO functionality from SPI flash controller. changed from v3: addressed reviewer comments from P Maydell and S Hajnoczi added patch 5 (re Paul Brooks request) changed from v2: folded former SPI bus functionality into existing SSI infrastructure (suggested - Paul Brook) (all patches) made m25p80 use async io (suggested - Stefan Hajnoczi) (2/4) instantiated two spi flashes instead of one in ml605 ref design (4/4) changed from v1: minor sylistic changes (1/4) converted spi api to modified txrx style (1-3/4) heavily refactored m25p80 model (2/4) Peter A. G. Crosthwaite (13): ssi: Support for multiple attached devices ssi: Implemented CS behaviour ssi: Added create_slave_no_init() qdev: allow multiple qdev_init_gpio_in() calls hw/stellaris: Removed gpio_out init array. stellaris: Removed SSI mux hw: Added generic FIFO API. m25p80: Initial implementation of SPI flash device xilinx_spi: Initial impl. of Xilinx SPI controller petalogix-ml605: added SPI controller with n25q128 xilinx_spips: Xilinx Zynq SPI cntrlr device model xilinx_zynq: Added SPI controllers + flashes MAINTAINERS: Added maintainerships for SSI MAINTAINERS |8 + default-configs/arm-softmmu.mak |1 + default-configs/microblaze-softmmu.mak |2 + default-configs/microblazeel-softmmu.mak |2 + hw/Makefile.objs |2 + hw/ads7846.c |7 +- hw/arm/Makefile.objs |1 + hw/fifo.c| 78 hw/fifo.h| 47 +++ hw/irq.c | 17 +- hw/irq.h | 11 +- hw/m25p80.c | 573 ++ hw/max111x.c |7 +- hw/microblaze/Makefile.objs |1 + hw/petalogix_ml605_mmu.c | 27 ++ hw/qdev.c|6 +- hw/spitz.c |8 +- hw/ssd0323.c |7 + hw/ssi-sd.c |7 + hw/ssi.c | 76 - hw/ssi.h | 38 ++ hw/stellaris.c | 111 ++- hw/xilinx_spi.c | 390 hw/xilinx_spips.c| 352 ++ hw/xilinx_zynq.c | 34 ++ hw/z2.c |7 +- 26 files changed, 1698 insertions(+), 122 deletions(-) create mode 100644 hw/fifo.c create mode 100644 hw/fifo.h create mode 100644 hw/m25p80.c create mode 100644 hw/xilinx_spi.c create mode 100644 hw/xilinx_spips.c
[Qemu-devel] [PATCH v7 01/13] ssi: Support for multiple attached devices
Removed assertion that only one device is attached to the SSI bus.
When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is active, and if not returning 0. The returned data is the logical or of
all responses from the (mulitple) devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssi.c | 24 +---
1 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/ssi.c b/hw/ssi.c
index e5f14a0..35d0a04 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -2,6 +2,8 @@
* QEMU Synchronous Serial Interface support
*
* Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
* Written by Paul Brook
*
* This code is licensed under the GNU GPL v2.
@@ -29,14 +31,6 @@ static int ssi_slave_init(DeviceState *dev)
{
SSISlave *s = SSI_SLAVE(dev);
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
-SSIBus *bus;
-BusChild *kid;
-
-bus = FROM_QBUS(SSIBus, qdev_get_parent_bus(dev));
-kid = QTAILQ_FIRST(&bus->qbus.children);
-if (kid->child != dev || QTAILQ_NEXT(kid, sibling) != NULL) {
-hw_error("Too many devices on SSI bus");
-}
return ssc->init(s);
}
@@ -74,16 +68,16 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char
*name)
uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
{
BusChild *kid;
-SSISlave *slave;
SSISlaveClass *ssc;
+uint32_t r = 0;
-kid = QTAILQ_FIRST(&bus->qbus.children);
-if (!kid) {
-return 0;
+QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+SSISlave *slave = SSI_SLAVE(kid->child);
+ssc = SSI_SLAVE_GET_CLASS(slave);
+r |= ssc->transfer(slave, val);
}
-slave = SSI_SLAVE(kid->child);
-ssc = SSI_SLAVE_GET_CLASS(slave);
-return ssc->transfer(slave, val);
+
+return r;
}
static void ssi_slave_register_types(void)
--
1.7.0.4
[Qemu-devel] [PATCH v7 02/13] ssi: Implemented CS behaviour
Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: Peter A. G. Crosthwaite
---
Changed since v5:
Addressed PMM review.
Collapsed into one patch for bisectability (this used to be two patches)
hw/ads7846.c |7 ---
hw/max111x.c |7 ---
hw/spitz.c |8 +---
hw/ssd0323.c |6 ++
hw/ssi-sd.c|6 ++
hw/ssi.c | 49 -
hw/ssi.h | 37 +
hw/stellaris.c |7 ---
hw/z2.c|7 ---
9 files changed, 118 insertions(+), 16 deletions(-)
diff --git a/hw/ads7846.c b/hw/ads7846.c
index 41c7f10..2ea9e55 100644
--- a/hw/ads7846.c
+++ b/hw/ads7846.c
@@ -119,11 +119,12 @@ static int ads7856_post_load(void *opaque, int version_id)
static const VMStateDescription vmstate_ads7846 = {
.name = "ads7846",
-.version_id = 0,
-.minimum_version_id = 0,
-.minimum_version_id_old = 0,
+.version_id = 1,
+.minimum_version_id = 1,
+.minimum_version_id_old = 1,
.post_load = ads7856_post_load,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, ADS7846State),
VMSTATE_INT32_ARRAY(input, ADS7846State, 8),
VMSTATE_INT32(noise, ADS7846State),
VMSTATE_INT32(cycle, ADS7846State),
diff --git a/hw/max111x.c b/hw/max111x.c
index 706d89f..67640f1 100644
--- a/hw/max111x.c
+++ b/hw/max111x.c
@@ -99,10 +99,11 @@ static uint32_t max111x_transfer(SSISlave *dev, uint32_t
value)
static const VMStateDescription vmstate_max111x = {
.name = "max111x",
-.version_id = 0,
-.minimum_version_id = 0,
-.minimum_version_id_old = 0,
+.version_id = 1,
+.minimum_version_id = 1,
+.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
+VMSTATE_SSI_SLAVE(ssidev, MAX111xState),
VMSTATE_UINT8(tb1, MAX111xState),
VMSTATE_UINT8(rb2, MAX111xState),
VMSTATE_UINT8(rb3, MAX111xState),
diff --git a/hw/spitz.c b/hw/spitz.c
index 20e7835..24346dc 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -1083,10 +1083,11 @@ static TypeInfo spitz_keyboard_info = {
static const VMStateDescription vmstate_corgi_ssp_regs = {
.name = "corgi-ssp",
-.version_id = 1,
-.minimum_version_id = 1,
-.minimum_version_id_old = 1,
+.version_id = 2,
+.minimum_version_id = 2,
+.minimum_version_id_old = 2,
.fields = (VMStateField []) {
+VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
VMSTATE_END_OF_LIST(),
}
@@ -1115,6 +1116,7 @@ static const VMStateDescription vmstate_spitz_lcdtg_regs
= {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
+VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
VMSTATE_UINT32(bl_power, SpitzLCDTG),
VMSTATE_END_OF_LIST(),
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index b101c51..5d05a35 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -279,6 +279,7 @@ static void ssd0323_cd(void *opaque, int n, int level)
static void ssd0323_save(QEMUFile *f, void *opaque)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
@@ -296,10 +297,13 @@ static void ssd0323_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->remap);
qemu_put_be32(f, s->mode);
qemu_put_buffer(f, s->framebuffer, sizeof(s->framebuffer));
+
+qemu_put_be32(f, ss->cs);
}
static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
@@ -321,6 +325,8 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int
version_id)
s->mode = qemu_get_be32(f);
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
+ss->cs = qemu_get_be32(f);
+
return 0;
}
diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c
index b519bdb..cbbc645 100644
--- a/hw/ssi-sd.c
+++ b/hw/ssi-sd.c
@@ -197,6 +197,7 @@ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
static void ssi_sd_save(QEMUFile *f, void *opaque)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
@@ -209,10 +210,13 @@ static void ssi_sd_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->arglen);
qemu_put_be32(f, s->response_pos);
qemu_put_be32(f, s->stopping);
+
+qemu_put_be32(f, ss->cs);
}
static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id)
{
+SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
@@ -229,6 +233,8 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int
[Qemu-devel] [PATCH v7 03/13] ssi: Added create_slave_no_init()
Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a chance to set properties.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssi.c |9 +++--
hw/ssi.h |1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/ssi.c b/hw/ssi.c
index 2e4f2fe..c47419d 100644
--- a/hw/ssi.c
+++ b/hw/ssi.c
@@ -86,10 +86,15 @@ static TypeInfo ssi_slave_info = {
.abstract = true,
};
+DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name)
+{
+return qdev_create(&bus->qbus, name);
+}
+
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
{
-DeviceState *dev;
-dev = qdev_create(&bus->qbus, name);
+DeviceState *dev = ssi_create_slave_no_init(bus, name);
+
qdev_init_nofail(dev);
return dev;
}
diff --git a/hw/ssi.h b/hw/ssi.h
index 65b159d..2bde9f5 100644
--- a/hw/ssi.h
+++ b/hw/ssi.h
@@ -76,6 +76,7 @@ extern const VMStateDescription vmstate_ssi_slave;
}
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
+DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name);
/* Master interface. */
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
--
1.7.0.4
[Qemu-devel] [PATCH v7 06/13] stellaris: Removed SSI mux
Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |1 +
hw/ssi-sd.c|1 +
hw/stellaris.c | 98 ++--
3 files changed, 19 insertions(+), 81 deletions(-)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index 5d05a35..9c42d64 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -354,6 +354,7 @@ static void ssd0323_class_init(ObjectClass *klass, void
*data)
k->init = ssd0323_init;
k->transfer = ssd0323_transfer;
+k->cs_polarity = SSI_CS_HIGH;
}
static TypeInfo ssd0323_info = {
diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c
index cbbc645..c5505ee 100644
--- a/hw/ssi-sd.c
+++ b/hw/ssi-sd.c
@@ -256,6 +256,7 @@ static void ssi_sd_class_init(ObjectClass *klass, void
*data)
k->init = ssi_sd_init;
k->transfer = ssi_sd_transfer;
+k->cs_polarity = SSI_CS_LOW;
}
static TypeInfo ssi_sd_info = {
diff --git a/hw/stellaris.c b/hw/stellaris.c
index a7b68f4..acb297b 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1154,58 +1154,6 @@ static int stellaris_adc_init(SysBusDevice *dev)
return 0;
}
-/* Some boards have both an OLED controller and SD card connected to
- the same SSI port, with the SD card chip select connected to a
- GPIO pin. Technically the OLED chip select is connected to the SSI
- Fss pin. We do not bother emulating that as both devices should
- never be selected simultaneously, and our OLED controller ignores stray
- 0xff commands that occur when deselecting the SD card. */
-
-typedef struct {
-SSISlave ssidev;
-qemu_irq irq;
-int current_dev;
-SSIBus *bus[2];
-} stellaris_ssi_bus_state;
-
-static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
-{
-stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
-
-s->current_dev = level;
-}
-
-static uint32_t stellaris_ssi_bus_transfer(SSISlave *dev, uint32_t val)
-{
-stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
-
-return ssi_transfer(s->bus[s->current_dev], val);
-}
-
-static const VMStateDescription vmstate_stellaris_ssi_bus = {
-.name = "stellaris_ssi_bus",
-.version_id = 2,
-.minimum_version_id = 2,
-.minimum_version_id_old = 2,
-.fields = (VMStateField[]) {
-VMSTATE_SSI_SLAVE(ssidev, stellaris_ssi_bus_state),
-VMSTATE_INT32(current_dev, stellaris_ssi_bus_state),
-VMSTATE_END_OF_LIST()
-}
-};
-
-static int stellaris_ssi_bus_init(SSISlave *dev)
-{
-stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
-
-s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
-s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
-qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
-
-vmstate_register(&dev->qdev, -1, &vmstate_stellaris_ssi_bus, s);
-return 0;
-}
-
/* Board init. */
static stellaris_board_info stellaris_boards[] = {
{ "LM3S811EVB",
@@ -1306,29 +1254,33 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
if (board->dc2 & (1 << 4)) {
dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
if (board->peripherals & BP_OLED_SSI) {
-DeviceState *mux;
void *bus;
-qemu_irq select_pin;
+/* Some boards have both an OLED controller and SD card connected
to
+ * the same SSI port, with the SD card chip select connected to a
+ * GPIO pin. Technically the OLED chip select is connected to the
+ * SSI Fss pin. We do not bother emulating that as both devices
+ * should never be selected simultaneously, and our OLED controller
+ * ignores stray 0xff commands that occur when deselecting the SD
+ * card.
+ */
bus = qdev_get_child_bus(dev, "ssi");
-mux = ssi_create_slave(bus, "evb6965-ssi");
-select_pin = qdev_get_gpio_in(mux, 0);
+
+dev = ssi_create_slave(bus, "ssi-sd");
if (gpio_dev[GPIO_D]) {
-qdev_connect_gpio_out(gpio_dev[GPIO_D], 0, select_pin);
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0,
+qdev_get_gpio_in(dev, 0));
}
-bus = qdev_get_child_bus(mux, "ssi0");
-ssi_create_slave(bus, "ssi-sd");
-
-bus = qdev_get_child_bus(mux, "ssi1");
dev = ssi_create_slave(bus, "ssd0323");
+if (gpio_dev[GPIO_D]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0,
+qdev_get_gpio_in(dev, 0));
+}
if (gpio_dev[GPIO_C]) {
qdev_connec
[Qemu-devel] [PATCH v7 09/13] xilinx_spi: Initial impl. of Xilinx SPI controller
Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4 (Near total rewrite):
removed timer delay. This was innacturate anyways removed for simlicity.
updated for new SSI interface.
factored out txrx fifos using fifo.h
changed from v3:
typedef'd struct XilinxSPI
changed unsigned int -> uin32_t
removed unused vars (c_fifo_exist and cmd_ongoing)
txfifo_reset removed duplicate s->regs[R_SPISR] &= ~SR_TX_FULL (PMM review)
reset: changed to Device Class style reset
reset: stope the ptimer (pmm review)
xlx_spi_update_irq: dont -> don't (PMM review)
init: set irq_line to 1 (force refresh on vmsd load)
init: dropped call to reset
implemetned vmsd
changed from v2:
converted spi api to ssi api
changed from v1:
converted spi api to modified txrx style
hw/microblaze/Makefile.objs |1 +
hw/xilinx_spi.c | 390 +++
2 files changed, 391 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_spi.c
diff --git a/hw/microblaze/Makefile.objs b/hw/microblaze/Makefile.objs
index 274d2c5..3028e65 100644
--- a/hw/microblaze/Makefile.objs
+++ b/hw/microblaze/Makefile.objs
@@ -1,6 +1,7 @@
obj-y = petalogix_s3adsp1800_mmu.o
obj-y += petalogix_ml605_mmu.o
obj-y += microblaze_boot.o
+obj-y += xilinx_spi.o
obj-y += microblaze_pic_cpu.o
obj-y += xilinx_ethlite.o
diff --git a/hw/xilinx_spi.c b/hw/xilinx_spi.c
new file mode 100644
index 000..933858f
--- /dev/null
+++ b/hw/xilinx_spi.c
@@ -0,0 +1,390 @@
+/*
+ * QEMU model of the Xilinx SPI Controller
+ *
+ * Copyright (C) 2010 Edgar E. Iglesias.
+ * Copyright (C) 2012 Peter A. G. Crosthwaite
+ * Copyright (C) 2012 PetaLogix
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu.h"
+#include "qemu-log.h"
+#include "fifo.h"
+
+#include "ssi.h"
+
+#ifdef XILINX_SPI_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+#define R_DGIER (0x1c / 4)
+#define R_DGIER_IE (1 << 31)
+
+#define R_IPISR (0x20 / 4)
+#define IRQ_DRR_NOT_EMPTY(1 << (31 - 23))
+#define IRQ_DRR_OVERRUN (1 << (31 - 26))
+#define IRQ_DRR_FULL (1 << (31 - 27))
+#define IRQ_TX_FF_HALF_EMPTY (1 << 6)
+#define IRQ_DTR_UNDERRUN (1 << 3)
+#define IRQ_DTR_EMPTY(1 << (31 - 29))
+
+#define R_IPIER (0x28 / 4)
+#define R_SRR (0x40 / 4)
+#define R_SPICR (0x60 / 4)
+#define R_SPICR_TXFF_RST (1 << 5)
+#define R_SPICR_RXFF_RST (1 << 6)
+#define R_SPICR_MTI (1 << 8)
+
+#define R_SPISR (0x64 / 4)
+#define SR_TX_FULL(1 << 3)
+#define SR_TX_EMPTY (1 << 2)
+#define SR_RX_FULL(1 << 1)
+#define SR_RX_EMPTY (1 << 0)
+
+#define R_SPIDTR(0x68 / 4)
+#define R_SPIDRR(0x6C / 4)
+#define R_SPISSR(0x70 / 4)
+#define R_TX_FF_OCY (0x74 / 4)
+#define R_RX_FF_OCY (0x78 / 4)
+#define R_MAX (0x7C / 4)
+
+#define FIFO_CAPACITY 256
+
+typedef struct XilinxSPI {
+SysBusDevice busdev;
+MemoryRegion mmio;
+
+qemu_irq irq;
+int irqline;
+
+uint8_t num_cs;
+qemu_irq *cs_lines;
+
+SSIBus *spi;
+
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+
+uint32_t regs[R_MAX];
+} XilinxSPI;
+
+static void txfifo_reset(XilinxSPI *s)
+{
+fifo8_reset(&s->tx_fifo);
+
+s->regs[R_SPISR] &= ~SR_TX_FULL;
+s->regs[R_SPISR] |= SR_TX_EMPTY;
+}
+
+static void rxfifo_reset(XilinxSPI *s)
+{
+fifo8_reset(&s->rx_fifo);
+
+s->regs[R_SPISR] |= SR_RX_EMPTY;
+s->regs[R_SPISR] &= ~SR_RX_FULL;
+}
+
+static void xlx_spi_update_cs(XilinxSPI *s)
+{
+ int i;
+
+for (i = 0; i < s->num_cs; ++i
[Qemu-devel] [PATCH v7 12/13] xilinx_zynq: Added SPI controllers + flashes
Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx_zynq.c | 34 ++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 7e6c273..e273711 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -24,6 +24,9 @@
#include "flash.h"
#include "blockdev.h"
#include "loader.h"
+#include "ssi.h"
+
+#define NUM_SPI_FLASHES 2
#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)
@@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq
irq)
sysbus_connect_irq(s, 0, irq);
}
+static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *busdev;
+SSIBus *spi;
+int i;
+
+dev = qdev_create(NULL, "xilinx,spips");
+qdev_init_nofail(dev);
+busdev = sysbus_from_qdev(dev);
+sysbus_mmio_map(busdev, 0, base_addr);
+sysbus_connect_irq(busdev, 0, irq);
+
+spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
+
+for (i = 0; i < NUM_SPI_FLASHES; ++i) {
+qemu_irq cs_line;
+
+dev = ssi_create_slave_no_init(spi, "m25p80");
+qdev_prop_set_string(dev, "partname", (char *)"n25q128");
+qdev_init_nofail(dev);
+
+cs_line = qdev_get_gpio_in(dev, 0);
+sysbus_connect_irq(busdev, i+1, cs_line);
+}
+
+}
+
static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char
*kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
pic[n] = qdev_get_gpio_in(dev, n);
}
+zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]);
+zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]);
+
sysbus_create_simple("cadence_uart", 0xE000, pic[59-IRQ_OFFSET]);
sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
--
1.7.0.4
[Qemu-devel] [PATCH v7 11/13] xilinx_spips: Xilinx Zynq SPI cntrlr device model
Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: Peter A. G. Crosthwaite
---
Changed from v6:
Addressed Blue Swirl review
s/interupt/interrupt
s/defintion/definition
constified TypeInfo
hw/arm/Makefile.objs |1 +
hw/xilinx_spips.c| 352 ++
2 files changed, 353 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_spips.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2b39fb3..6d049e7 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -1,6 +1,7 @@
obj-y = integratorcp.o versatilepb.o arm_pic.o
obj-y += arm_boot.o
obj-y += xilinx_zynq.o zynq_slcr.o
+obj-y += xilinx_spips.o
obj-y += arm_gic.o arm_gic_common.o
obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
new file mode 100644
index 000..f6cf255
--- /dev/null
+++ b/hw/xilinx_spips.c
@@ -0,0 +1,352 @@
+/*
+ * QEMU model of the Xilinx Zynq SPI controller
+ *
+ * Copyright (c) 2012 Peter A. G. Crosthwaite
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu.h"
+#include "ptimer.h"
+#include "qemu-log.h"
+#include "fifo.h"
+#include "ssi.h"
+
+#ifdef XILINX_SPIPS_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+/* config register */
+#define R_CONFIG(0x00 / 4)
+#define MODEFAIL_GEN_EN (1 << 17)
+#define MAN_START_COM (1 << 16)
+#define MAN_START_EN(1 << 15)
+#define MANUAL_CS (1 << 14)
+#define CS (0xF << 10)
+#define CS_SHIFT(10)
+#define PERI_SEL(1 << 9)
+#define REF_CLK (1 << 8)
+#define FIFO_WIDTH (3 << 6)
+#define BAUD_RATE_DIV (7 << 3)
+#define CLK_PH (1 << 2)
+#define CLK_POL (1 << 1)
+#define MODE_SEL(1 << 1)
+
+/* interrupt mechanism */
+#define R_INTR_STATUS (0x04 / 4)
+#define R_INTR_EN (0x08 / 4)
+#define R_INTR_DIS (0x0C / 4)
+#define R_INTR_MASK (0x10 / 4)
+#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
+#define IXR_RX_FIFO_FULL(1 << 5)
+#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
+#define IXR_TX_FIFO_FULL(1 << 3)
+#define IXR_TX_FIFO_NOT_FULL(1 << 2)
+#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
+#define IXR_RX_FIFO_OVERFLOW(1 << 0)
+#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
+
+#define R_EN(0x14 / 4)
+#define R_DELAY (0x18 / 4)
+#define R_TX_DATA (0x1C / 4)
+#define R_RX_DATA (0x20 / 4)
+#define R_SLAVE_IDLE_COUNT (0x24 / 4)
+#define R_TX_THRES (0x28 / 4)
+#define R_RX_THRES (0x2C / 4)
+#define R_MOD_ID(0xFC / 4)
+
+#define R_MAX (R_MOD_ID+1)
+
+/* size of TXRX FIFOs */
+#define NUM_CS_LINES4
+#define RXFF_A 32
+#define TXFF_A 32
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq irq;
+int irqline;
+
+qemu_irq cs_lines[NUM_CS_LINES];
+SSIBus *spi;
+
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+
+uint32_t regs[R_MAX];
+} XilinxSPIPS;
+
+static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
+{
+int i;
+bool found = false;
+int field = s->regs[R_CONFIG] >> CS_SHIFT;
+
+for (i = 0; i < NUM_CS_LINES; i++) {
+if (~field & (1 << i) & !found) {
+found = true;
+DB_PRINT("selecting slave %d\n", i);
+qemu_set_irq(s->cs_lines[i],
[Qemu-devel] [PATCH v7 07/13] hw: Added generic FIFO API.
Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/fifo.c| 78 ++
hw/fifo.h| 47
3 files changed, 126 insertions(+), 0 deletions(-)
create mode 100644 hw/fifo.c
create mode 100644 hw/fifo.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 6dfebd2..dcb0bcd 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -15,6 +15,7 @@ hw-obj-$(CONFIG_ECC) += ecc.o
hw-obj-$(CONFIG_NAND) += nand.o
hw-obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o
hw-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
+hw-obj-y += fifo.o
hw-obj-$(CONFIG_M48T59) += m48t59.o
hw-obj-$(CONFIG_ESCC) += escc.o
diff --git a/hw/fifo.c b/hw/fifo.c
new file mode 100644
index 000..366dae4
--- /dev/null
+++ b/hw/fifo.c
@@ -0,0 +1,78 @@
+/*
+ * Generic FIFO component, implemented as a circular buffer.
+ *
+ * Copyright (c) 2012 Peter A. G. Crosthwaite
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "fifo.h"
+
+void fifo8_create(Fifo8 *fifo, uint32_t capacity)
+{
+fifo->data = g_new(uint8_t, capacity);
+fifo->capacity = capacity;
+fifo->head = 0;
+fifo->num = 0;
+}
+
+void fifo8_destroy(Fifo8 *fifo)
+{
+g_free(fifo->data);
+}
+
+void fifo8_push(Fifo8 *fifo, uint8_t data)
+{
+if (fifo->num == fifo->capacity) {
+abort();
+}
+fifo->data[(fifo->head + fifo->num) % fifo->capacity] = data;
+fifo->num++;
+}
+
+uint8_t fifo8_pop(Fifo8 *fifo)
+{
+uint8_t ret;
+
+if (fifo->num == 0) {
+abort();
+}
+ret = fifo->data[fifo->head++];
+fifo->head %= fifo->capacity;
+fifo->num--;
+return ret;
+}
+
+void fifo8_reset(Fifo8 *fifo)
+{
+fifo->num = 0;
+}
+
+bool fifo8_is_empty(Fifo8 *fifo)
+{
+return (fifo->num == 0);
+}
+
+bool fifo8_is_full(Fifo8 *fifo)
+{
+return (fifo->num == fifo->capacity);
+}
+
+const VMStateDescription vmstate_fifo8 = {
+.name = "SSISlave",
+.version_id = 1,
+.minimum_version_id = 1,
+.minimum_version_id_old = 1,
+.fields = (VMStateField[]) {
+VMSTATE_VBUFFER_UINT32(data, Fifo8, 1, NULL, 0, capacity),
+VMSTATE_UINT32(head, Fifo8),
+VMSTATE_UINT32(num, Fifo8),
+VMSTATE_END_OF_LIST()
+}
+};
diff --git a/hw/fifo.h b/hw/fifo.h
new file mode 100644
index 000..3fb09ff
--- /dev/null
+++ b/hw/fifo.h
@@ -0,0 +1,47 @@
+#ifndef FIFO_H
+#define FIFO_H
+
+#include "hw.h"
+
+typedef struct {
+/* All fields are private */
+uint8_t *data;
+uint32_t capacity;
+uint32_t head;
+uint32_t num;
+} Fifo8;
+
+/* create a fifo of the specified size */
+
+void fifo8_create(Fifo8 *, uint32_t);
+
+/* cleanup a fifo */
+
+void fifo8_destroy(Fifo8 *);
+
+/* push a data byte to the fifo. Behaviour is undefined if the fifo is full */
+
+void fifo8_push(Fifo8 *, uint8_t);
+
+/* pop a data byte from the fifo. Behviour is undefined if the fifo is empty */
+
+uint8_t fifo8_pop(Fifo8 *);
+
+/* reset (empty) the fifo */
+
+void fifo8_reset(Fifo8 *);
+
+bool fifo8_is_empty(Fifo8 *);
+bool fifo8_is_full(Fifo8 *);
+
+extern const VMStateDescription vmstate_fifo8;
+
+#define VMSTATE_FIFO8(_field, _state) { \
+.name = (stringify(_field)), \
+.size = sizeof(Fifo8), \
+.vmsd = &vmstate_fifo8,\
+.flags = VMS_STRUCT,\
+.offset = vmstate_offset_value(_state, _field, Fifo8), \
+}
+
+#endif /* FIFO_H */
--
1.7.0.4
[Qemu-devel] [PATCH v7 10/13] petalogix-ml605: added SPI controller with n25q128
Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: Peter A. G. Crosthwaite
---
Changed since v5:
Removed redundant (char*) cast with qdev_get_prop_string
hw/petalogix_ml605_mmu.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index dced648..78ebdb9 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -36,6 +36,7 @@
#include "blockdev.h"
#include "pc.h"
#include "exec-memory.h"
+#include "ssi.h"
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
@@ -47,6 +48,8 @@
#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
+#define NUM_SPI_FLASHES 2
+
#define MEMORY_BASEADDR 0x5000
#define FLASH_BASEADDR 0x8600
#define INTC_BASEADDR 0x8180
@@ -79,6 +82,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
+SysBusDevice *busdev;
CPUMBState *env;
DriveInfo *dinfo;
int i;
@@ -139,6 +143,29 @@ petalogix_ml605_init(ram_addr_t ram_size,
xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
0x8460, irq[1], irq[0], 100 * 100);
+{
+SSIBus *spi;
+
+dev = qdev_create(NULL, "xilinx,spi");
+qdev_prop_set_uint8(dev, "num-cs", NUM_SPI_FLASHES);
+qdev_init_nofail(dev);
+busdev = sysbus_from_qdev(dev);
+sysbus_mmio_map(busdev, 0, 0x40a0);
+sysbus_connect_irq(busdev, 0, irq[4]);
+
+spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
+
+for (i = 0; i < NUM_SPI_FLASHES; i++) {
+qemu_irq cs_line;
+
+dev = ssi_create_slave_no_init(spi, "m25p80");
+qdev_prop_set_string(dev, "partname", "n25q128");
+qdev_init_nofail(dev);
+cs_line = qdev_get_gpio_in(dev, 0);
+sysbus_connect_irq(busdev, i+1, cs_line);
+}
+}
+
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
--
1.7.0.4
[Qemu-devel] [PATCH v7 05/13] hw/stellaris: Removed gpio_out init array.
stellaris_init() defines arrays of qemu_irq to decides what each of the GPIO
pins are connected to. This is ok for inputs (as an input can only have one
source) but is flawed for outputs as an output can connect to any number of
sinks. Removed the gpio_out array completely and just replaced its setters with
direct calls to qdev_connect_gpio_out().
Signed-off-by: Peter A. G. Crosthwaite
---
hw/stellaris.c | 26 --
1 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 01050d1..a7b68f4 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1244,7 +1244,6 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
qemu_irq *pic;
DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8];
-qemu_irq gpio_out[7][8];
qemu_irq adc;
int sram_size;
int flash_size;
@@ -1284,8 +1283,9 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
pic[gpio_irq[i]]);
for (j = 0; j < 8; j++) {
gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
-gpio_out[i][j] = NULL;
}
+} else {
+gpio_dev[i] = NULL;
}
}
@@ -1308,20 +1308,27 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
if (board->peripherals & BP_OLED_SSI) {
DeviceState *mux;
void *bus;
+qemu_irq select_pin;
bus = qdev_get_child_bus(dev, "ssi");
mux = ssi_create_slave(bus, "evb6965-ssi");
-gpio_out[GPIO_D][0] = qdev_get_gpio_in(mux, 0);
+select_pin = qdev_get_gpio_in(mux, 0);
+if (gpio_dev[GPIO_D]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_D], 0, select_pin);
+}
bus = qdev_get_child_bus(mux, "ssi0");
ssi_create_slave(bus, "ssi-sd");
bus = qdev_get_child_bus(mux, "ssi1");
dev = ssi_create_slave(bus, "ssd0323");
-gpio_out[GPIO_C][7] = qdev_get_gpio_in(dev, 0);
+if (gpio_dev[GPIO_C]) {
+qdev_connect_gpio_out(gpio_dev[GPIO_C], 7,
+qdev_get_gpio_in(dev, 0));
+}
/* Make sure the select pin is high. */
-qemu_irq_raise(gpio_out[GPIO_D][0]);
+qemu_irq_raise(select_pin);
}
}
if (board->dc4 & (1 << 28)) {
@@ -1347,15 +1354,6 @@ static void stellaris_init(const char *kernel_filename,
const char *cpu_model,
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
}
-for (i = 0; i < 7; i++) {
-if (board->dc4 & (1 << i)) {
-for (j = 0; j < 8; j++) {
-if (gpio_out[i][j]) {
-qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
-}
-}
-}
-}
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
--
1.7.0.4
[Qemu-devel] [PATCH v7 13/13] MAINTAINERS: Added maintainerships for SSI
Added maintainership for SSI, M25P80 and the Xilinx SPI controllers. Signed-off-by: Peter A. G. Crosthwaite --- MAINTAINERS |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 61f8b45..0ebe247 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -268,6 +268,7 @@ S: Maintained F: hw/xilinx_zynq.c F: hw/zynq_slcr.c F: hw/cadence_* +F: hw/xilinx_spips.c CRIS Machines - @@ -469,6 +470,12 @@ M: Paul Brook S: Odd Fixes F: hw/lsi53c895a.c +SSI +M: Peter Crosthwaite +S: Maintained +F: hw/ssi.* +F: hw/m25p80.c + USB M: Gerd Hoffmann S: Maintained @@ -512,6 +519,7 @@ F: hw/xilinx_intc.c F: hw/xilinx_ethlite.c F: hw/xilinx_timer.c F: hw/xilinx.h +F: hw/xilinx_spi.c Subsystems -- -- 1.7.0.4
[Qemu-devel] [PATCH v7 08/13] m25p80: Initial implementation of SPI flash device
Added device model for m25p80 style SPI flash family.
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v6:
Addressed Blue Swirl review
Constified TypeInfo
Constified part_name string prop
Added missing break
s/assert(false)/abort()
changed from v4:
Added write-1 flag (EEPROM mode).
n25q128 table entry indentation fix.
updated for new SSI interface.
various debug messages cleaned up and added.
changed from v3:
changed licence to v2 or later (PMM review)
generalised device model - rather than being fixed to the fl064k, it can handle
a wide range of m25p80 devices
refactored erase commands (previously they were fl064k specific and used
spansions broken terminology)
typdef'd strcuts and enums
fixed some camel casing
added comment to explain why bdrv_sync_complete is a nop (PMM review)
removed hardcoded "512" for BDRV_SECTOR_SIZE
flash_sync_area: use bdrv_aio_writev instead of bdrv_write
flash_chip_erase/flash_block_erase32k/flash_sector_erase: consolidated to one
function
decode_new_cmd: fixed multi-statement lines (PMM review)
CHIP_ERASE->BULK_ERASE
init: drive_get -> drive_get_next (PMM review)
changed from v2:
updated for SSI slave interface
used async io (suggested - Stefan Hajnoczi)
changed from v1:
converted spi api to modified txrx style
factored out lots of common code and inlined overly short single call functions.
undated for txrx style spi interface
default-configs/arm-softmmu.mak |1 +
default-configs/microblaze-softmmu.mak |2 +
default-configs/microblazeel-softmmu.mak |2 +
hw/Makefile.objs |1 +
hw/m25p80.c | 573 ++
5 files changed, 579 insertions(+), 0 deletions(-)
create mode 100644 hw/m25p80.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f335a72..2f1a5c9 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -22,6 +22,7 @@ CONFIG_ADS7846=y
CONFIG_MAX111X=y
CONFIG_SSI=y
CONFIG_SSI_SD=y
+CONFIG_SSI_M25P80=y
CONFIG_LAN9118=y
CONFIG_SMC91C111=y
CONFIG_DS1338=y
diff --git a/default-configs/microblaze-softmmu.mak
b/default-configs/microblaze-softmmu.mak
index 64c9485..2f442e5 100644
--- a/default-configs/microblaze-softmmu.mak
+++ b/default-configs/microblaze-softmmu.mak
@@ -5,3 +5,5 @@ CONFIG_PFLASH_CFI01=y
CONFIG_SERIAL=y
CONFIG_XILINX=y
CONFIG_XILINX_AXI=y
+CONFIG_SSI=y
+CONFIG_SSI_M25P80=y
diff --git a/default-configs/microblazeel-softmmu.mak
b/default-configs/microblazeel-softmmu.mak
index a962276..af9a3cd 100644
--- a/default-configs/microblazeel-softmmu.mak
+++ b/default-configs/microblazeel-softmmu.mak
@@ -5,3 +5,5 @@ CONFIG_PFLASH_CFI01=y
CONFIG_SERIAL=y
CONFIG_XILINX=y
CONFIG_XILINX_AXI=y
+CONFIG_SSI=y
+CONFIG_SSI_M25P80=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index dcb0bcd..5524b5f 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -174,6 +174,7 @@ common-obj-y += scsi-disk.o cdrom.o hd-geometry.o
block-common.o
common-obj-y += scsi-generic.o scsi-bus.o
common-obj-y += hid.o
common-obj-$(CONFIG_SSI) += ssi.o
+common-obj-$(CONFIG_SSI_M25P80) += m25p80.o
common-obj-$(CONFIG_SSI_SD) += ssi-sd.o
common-obj-$(CONFIG_SD) += sd.o
common-obj-y += bt.o bt-l2cap.o bt-sdp.o bt-hci.o bt-hid.o
diff --git a/hw/m25p80.c b/hw/m25p80.c
new file mode 100644
index 000..024e635
--- /dev/null
+++ b/hw/m25p80.c
@@ -0,0 +1,573 @@
+/*
+ * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80
command
+ * set. Known devices table current as of Jun/2012 and taked from linux.
+ * See drivers/mtd/devices/m25p80.c.
+ *
+ * Copyright (C) 2011 Edgar E. Iglesias
+ * Copyright (C) 2012 Peter A. G. Crosthwaite
+ * Copyright (C) 2012 PetaLogix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) a later version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw.h"
+#include "blockdev.h"
+#include "ssi.h"
+#include "devices.h"
+
+#ifdef M25P80_ERR_DEBUG
+#define DB_PRINT(...) do { \
+fprintf(stderr, ": %s: ", __func__); \
+fprintf(stderr, ## __VA_ARGS__); \
+} while (0);
+#else
+#define DB_PRINT(...)
+#endif
+
+typedef struct FlashPartInfo {
+const char *part_name;
+/* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
+uint32_t jedec;
+/* extended jedec code */
+uint16_
[Qemu-devel] [PATCH v7 04/13] qdev: allow multiple qdev_init_gpio_in() calls
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy both
define GPIO functionality, as a single GPIO handler with an index selecter is
not possible.
Signed-off-by: Peter A. G. Crosthwaite
---
changed since v5:
moved implementation to irq.c as per PMM review
hw/irq.c | 17 ++---
hw/irq.h | 11 ++-
hw/qdev.c |6 +++---
3 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/hw/irq.c b/hw/irq.c
index d413a0b..cd17551 100644
--- a/hw/irq.c
+++ b/hw/irq.c
@@ -38,15 +38,20 @@ void qemu_set_irq(qemu_irq irq, int level)
irq->handler(irq->opaque, irq->n, level);
}
-qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
+qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
+void *opaque, int n)
{
qemu_irq *s;
struct IRQState *p;
int i;
-s = (qemu_irq *)g_malloc0(sizeof(qemu_irq) * n);
+if (!old) {
+n_old = 0;
+}
+s = old ? g_renew(qemu_irq, old, n + n_old) :
+(qemu_irq *)g_new0(qemu_irq, n);
p = (struct IRQState *)g_malloc0(sizeof(struct IRQState) * n);
-for (i = 0; i < n; i++) {
+for (i = n_old; i < n + n_old; i++) {
p->handler = handler;
p->opaque = opaque;
p->n = i;
@@ -56,6 +61,12 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void
*opaque, int n)
return s;
}
+qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
+{
+return qemu_extend_irqs(NULL, 0, handler, opaque, n);
+}
+
+
void qemu_free_irqs(qemu_irq *s)
{
g_free(s[0]);
diff --git a/hw/irq.h b/hw/irq.h
index 56c55f0..e640c10 100644
--- a/hw/irq.h
+++ b/hw/irq.h
@@ -23,8 +23,17 @@ static inline void qemu_irq_pulse(qemu_irq irq)
qemu_set_irq(irq, 0);
}
-/* Returns an array of N IRQs. */
+/* Returns an array of N IRQs. Each IRQ is assigned the argument handler and
+ * opaque data.
+ */
qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n);
+
+/* Extends an Array of IRQs. Old IRQs have their handlers and opaque data
+ * preserved. New IRQs are assigned the argument handler and opaque data.
+ */
+qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
+void *opaque, int n);
+
void qemu_free_irqs(qemu_irq *s);
/* Returns a new IRQ with opposite polarity. */
diff --git a/hw/qdev.c b/hw/qdev.c
index b5a52ac..eea9eae 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -291,9 +291,9 @@ BusState *qdev_get_parent_bus(DeviceState *dev)
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n)
{
-assert(dev->num_gpio_in == 0);
-dev->num_gpio_in = n;
-dev->gpio_in = qemu_allocate_irqs(handler, dev, n);
+dev->gpio_in = qemu_extend_irqs(dev->gpio_in, dev->num_gpio_in, handler,
+dev, n);
+dev->num_gpio_in += n;
}
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n)
--
1.7.0.4
[Qemu-devel] [PATCH v1 0/6] Microblaze Patches
Misc microblaze patches. Chris Wulff (1): xilinx_timer: Fix a compile error if debug enabled Peter A. G. Crosthwaite (5): xilinx_timer: Removed comma in device name xilinx_timer: Send dbg msgs to stderr not stdout xilinx_timer: Fixed "frequency" prop name xilinx.h: Error check when setting links xilinx: fix names of ethernet and dma links. hw/xilinx.h | 16 hw/xilinx_timer.c | 16 +--- 2 files changed, 21 insertions(+), 11 deletions(-)
[Qemu-devel] [PATCH v1 1/6] xilinx_timer: Removed comma in device name
Fixes an error in a61e4b07a30c062260d2d01771773f14820d1eb7
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx.h |2 +-
hw/xilinx_timer.c |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 556c5aa..df06a00 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -21,7 +21,7 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq,
int oto, int freq)
{
DeviceState *dev;
-dev = qdev_create(NULL, "xlnx,xps-timer");
+dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", oto);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_init_nofail(dev);
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index b562bd0..053ba02 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -217,7 +217,7 @@ static int xilinx_timer_init(SysBusDevice *dev)
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
-memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx,xps-timer",
+memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
sysbus_init_mmio(dev, &t->mmio);
return 0;
@@ -239,7 +239,7 @@ static void xilinx_timer_class_init(ObjectClass *klass,
void *data)
}
static TypeInfo xilinx_timer_info = {
-.name = "xlnx,xps-timer",
+.name = "xlnx.xps-timer",
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct timerblock),
.class_init= xilinx_timer_class_init,
--
1.7.0.4
[Qemu-devel] [PATCH v1 2/6] xilinx_timer: Send dbg msgs to stderr not stdout
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx_timer.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index 053ba02..c02e6ca 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -119,7 +119,7 @@ timer_read(void *opaque, target_phys_addr_t addr, unsigned
int size)
break;
}
-D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
+D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
return r;
}
@@ -127,7 +127,7 @@ static void timer_enable(struct xlx_timer *xt)
{
uint64_t count;
-D(printf("%s timer=%d down=%d\n", __func__,
+D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
ptimer_stop(xt->ptimer);
@@ -152,7 +152,7 @@ timer_write(void *opaque, target_phys_addr_t addr,
addr >>= 2;
timer = timer_from_addr(addr);
xt = &t->timers[timer];
-D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
+D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
__func__, addr * 4, value, timer, addr & 3));
/* Further decoding to address a specific timers reg. */
addr &= 3;
@@ -189,7 +189,7 @@ static void timer_hit(void *opaque)
{
struct xlx_timer *xt = opaque;
struct timerblock *t = xt->parent;
-D(printf("%s %d\n", __func__, timer));
+D(fprintf(stderr, "%s %d\n", __func__, timer));
xt->regs[R_TCSR] |= TCSR_TINT;
if (xt->regs[R_TCSR] & TCSR_ARHT)
--
1.7.0.4
[Qemu-devel] [PATCH v1 4/6] xilinx.h: Error check when setting links
Assert that the ethernet and dma controller are sucessfully linked to their
peers.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx.h | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 45a6bdc..4d29265 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -55,13 +55,16 @@ xilinx_axiethernet_create(NICInfo *nd, StreamSlave *peer,
int txmem, int rxmem)
{
DeviceState *dev;
+Error *errp = NULL;
+
qemu_check_nic_model(nd, "xlnx.axi-ethernet");
dev = qdev_create(NULL, "xlnx.axi-ethernet");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint32(dev, "rxmem", rxmem);
qdev_prop_set_uint32(dev, "txmem", txmem);
-object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", NULL);
+object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", &errp);
+assert_no_error(errp);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
@@ -74,8 +77,11 @@ xilinx_axiethernetdma_init(DeviceState *dev, StreamSlave
*peer,
target_phys_addr_t base, qemu_irq irq,
qemu_irq irq2, int freqhz)
{
+Error *errp = NULL;
+
qdev_prop_set_uint32(dev, "freqhz", freqhz);
-object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", NULL);
+object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", &errp);
+assert_no_error(errp);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
--
1.7.0.4
[Qemu-devel] [PATCH v1 5/6] xilinx: fix names of ethernet and dma links.
These names were incorrect. Fixed to match to actual link names Signed-off-by: Peter A. G. Crosthwaite --- hw/xilinx.h |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/xilinx.h b/hw/xilinx.h index 4d29265..6449bd4 100644 --- a/hw/xilinx.h +++ b/hw/xilinx.h @@ -63,7 +63,8 @@ xilinx_axiethernet_create(NICInfo *nd, StreamSlave *peer, qdev_set_nic_properties(dev, nd); qdev_prop_set_uint32(dev, "rxmem", rxmem); qdev_prop_set_uint32(dev, "txmem", txmem); -object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", &errp); +object_property_set_link(OBJECT(dev), OBJECT(peer), "axistream-connected", +&errp); assert_no_error(errp); qdev_init_nofail(dev); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); @@ -80,7 +81,8 @@ xilinx_axiethernetdma_init(DeviceState *dev, StreamSlave *peer, Error *errp = NULL; qdev_prop_set_uint32(dev, "freqhz", freqhz); -object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", &errp); +object_property_set_link(OBJECT(dev), OBJECT(peer), "axistream-connected", +&errp); assert_no_error(errp); qdev_init_nofail(dev); -- 1.7.0.4
[Qemu-devel] [PATCH v1 3/6] xilinx_timer: Fixed "frequency" prop name
The "frequency" qdev prop matches the "clock-frequency" property in Xilinx EDK.
Renamed "frequency" -> "clock-frequency" accordingly.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx.h |2 +-
hw/xilinx_timer.c |3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/xilinx.h b/hw/xilinx.h
index df06a00..45a6bdc 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -23,7 +23,7 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq,
int oto, int freq)
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", oto);
-qdev_prop_set_uint32(dev, "frequency", freq);
+qdev_prop_set_uint32(dev, "clock-frequency", freq);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index c02e6ca..9eb5ef7 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -224,7 +224,8 @@ static int xilinx_timer_init(SysBusDevice *dev)
}
static Property xilinx_timer_properties[] = {
-DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 62 *
100),
+DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
+62 * 100),
DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
1.7.0.4
[Qemu-devel] [RFC v0 00/10] Microblaze generic FDT framework
In response to Chris Wulff series which add FDT driver machine generation for microblaze, heres the current version of the system maintained out of tree at Xilinx. Looking to collaborate with Chris (or anyone else out there) on how we can converge our implementations. Major outstanding issues: -The Flash and Serial stuff is a bit of a hack as they arent there yet with QOM. I think Anthony has some stuff in a series to fix up serial which clear this series up a little bit. Ditto for PFlash, with outstanding QOM issues. -Need to rework the API to handle nodepaths a little cleaner. Peter A. G. Crosthwaite (10): device_tree: allow offsets for cell properties device_tree: return Error* from prop getters device_tree: allow property getters to inherit device_tree: get_prop(): memdup returned properties qemu-coroutine: Add simple work queue support device_tree: Extended interface for fdt_generic fdt_generic: First revision pflash_cfi01: Added fdt generic platform support microblaze_generic_fdt: first revision serial: added fdt generic platform support default-configs/microblaze-softmmu.mak |1 + default-configs/microblazeel-softmmu.mak |1 + device_tree.c| 199 +- device_tree.h| 38 +++- hw/arm_boot.c| 10 +- hw/fdt_generic.c | 215 +++ hw/fdt_generic.h | 92 +++ hw/fdt_generic_devices.c | 80 ++ hw/fdt_generic_devices.h |8 + hw/fdt_generic_util.c| 438 ++ hw/fdt_generic_util.h| 36 +++ hw/microblaze/Makefile.objs |5 + hw/microblaze_generic_fdt.c | 378 ++ qemu-coroutine-lock.c| 13 + qemu-coroutine.h |9 + 15 files changed, 1507 insertions(+), 16 deletions(-) create mode 100644 hw/fdt_generic.c create mode 100644 hw/fdt_generic.h create mode 100644 hw/fdt_generic_devices.c create mode 100644 hw/fdt_generic_devices.h create mode 100644 hw/fdt_generic_util.c create mode 100644 hw/fdt_generic_util.h create mode 100644 hw/microblaze_generic_fdt.c
