RE: [QEMU][master][PATCH v2 1/1] hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
Hi Shiva,
>-Original Message-
>From: Shiva sagar Myana
>Sent: Friday, May 31, 2024 1:56 PM
>To: Iglesias, Francisco ; jasow...@redhat.com;
>qemu-devel@nongnu.org; p...@cmp.felk.cvut.cz
>Cc: peter.mayd...@linaro.org; Boddu, Sai Pavan ;
>Myana, Shivasagar
>Subject: [QEMU][master][PATCH v2 1/1] hw/net/can/xlnx-versal-canfd: Fix
>sorting of the tx queue
>
>Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to
>become wrongly sorted when executing g_slist_sort. Fix this by always
>returning -1 or 1 from g_cmp_ids based on the ID comparison instead.
>Also, if two message IDs are the same, sort them by using their index and
>transmit the message at the lowest index first.
[Boddu, Sai Pavan]
Reviewed-by: Sai Pavan Boddu
FYI, this part of subject-line "[QEMU][master]" is not needed, as we target
only one branch here.
Regards,
Sai Pavan
>
>Signed-off-by: Shiva sagar Myana
>Reviewed-by: Francisco Iglesias
>---
>ChangeLog:
>v1->v2 : Subject line modified.
>
> hw/net/can/xlnx-versal-canfd.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
>index 47a14cfe63..5f083c21e9 100644
>--- a/hw/net/can/xlnx-versal-canfd.c
>+++ b/hw/net/can/xlnx-versal-canfd.c
>@@ -1312,7 +1312,10 @@ static gint g_cmp_ids(gconstpointer data1,
>gconstpointer data2)
> tx_ready_reg_info *tx_reg_1 = (tx_ready_reg_info *) data1;
> tx_ready_reg_info *tx_reg_2 = (tx_ready_reg_info *) data2;
>
>-return tx_reg_1->can_id - tx_reg_2->can_id;
>+if (tx_reg_1->can_id == tx_reg_2->can_id) {
>+return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1;
>+}
>+return (tx_reg_1->can_id < tx_reg_2->can_id) ? -1 : 1;
> }
>
> static void free_list(GSList *list)
>--
>2.37.6
RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
Hi Edgar,
From: Edgar E. Iglesias
Sent: Friday, June 14, 2024 4:38 PM
To: Boddu, Sai Pavan
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis
; Peter Maydell ; Iglesias,
Francisco
Subject: Re: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
On Thu, Jun 13, 2024 at 5:36 PM Sai Pavan Boddu
mailto:sai.pavan.bo...@amd.com>> wrote:
Read boot-mode value as machine property and propagate that to
SLCR.BOOT_MODE register.
Hi Sai,
Directly exposing the register field to the user to set on the command-line
probably makes usability a little too rough (user has to check the register
specs in the TRM to change boot-mode).
We could perhaps add friendly names that we internally map to the register
field values.
Another question, can we use the existing -boot command-line arg for this?
Something along the lines of what x86 PC does:
https://github.com/qemu/qemu/blob/master/hw/i386/pc.c#L395
I don't know if the framework allows for long names but something like the
following would be nice:
qemu -boot spi,ethernet,jtag,uart,etc
[Boddu, Sai Pavan] Ok it makes much sense, Otherwise I would add more details
in the description of the new property about the possible boot modes.
Would also be great to document a small example, perhaps in
https://github.com/qemu/qemu/tree/master/docs/system/arm
[Boddu, Sai Pavan] Sure.
Regards,
Sai Pavan
Best regards,
Edgar
Signed-off-by: Sai Pavan Boddu
mailto:sai.pavan.bo...@amd.com>>
---
hw/arm/xilinx_zynq.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 7f7a3d23fb..4dfa9184ac 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -38,6 +38,7 @@
#include "qom/object.h"
#include "exec/tswap.h"
#include "target/arm/cpu-qom.h"
+#include "qapi/visitor.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
@@ -90,6 +91,7 @@ struct ZynqMachineState {
MachineState parent;
Clock *ps_clk;
ARMCPU *cpu[ZYNQ_MAX_CPUS];
+uint8_t BootMode;
};
static void zynq_write_board_setup(ARMCPU *cpu,
@@ -176,6 +178,19 @@ static inline int zynq_init_spi_flashes(uint32_t
base_addr, qemu_irq irq,
return unit;
}
+static void zynq_set_boot_mode(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ZynqMachineState *m = ZYNQ_MACHINE(obj);
+uint8_t val;
+
+if (!visit_type_uint8(v, name, &val, errp)) {
+return;
+}
+m->BootMode = val;
+}
+
static void zynq_init(MachineState *machine)
{
ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
@@ -241,6 +256,7 @@ static void zynq_init(MachineState *machine)
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_new("xilinx-zynq_slcr");
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
+qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->BootMode);
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF800);
@@ -372,6 +388,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void
*data)
NULL
};
MachineClass *mc = MACHINE_CLASS(oc);
+ObjectProperty *prop;
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
mc->max_cpus = ZYNQ_MAX_CPUS;
@@ -379,6 +396,11 @@ static void zynq_machine_class_init(ObjectClass *oc, void
*data)
mc->ignore_memory_transaction_failures = true;
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "zynq.ext_ram";
+prop = object_class_property_add(oc, "boot-mode", "uint8_t", NULL,
+ zynq_set_boot_mode, NULL, NULL);
+object_class_property_set_description(oc, "boot-mode",
+ "Update SLCR.BOOT_MODE register");
+object_property_set_default_uint(prop, 1);
}
static const TypeInfo zynq_machine_type = {
--
2.34.1
RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
Hi Edgar,
From: Boddu, Sai Pavan
Sent: Friday, June 14, 2024 8:37 PM
To: Edgar E. Iglesias
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis
; Peter Maydell ; Iglesias,
Francisco
Subject: RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
Hi Edgar,
I examined -boot switch to configure boot mode.
It would become little complex to map zynq boot devices to below expected
mapping.
* a-b: floppy disk drives
* c-f: IDE disk drives
* g-m: machine implementation dependent drives
* n-p: network devices
With above options, we may need to use “g-m” flags for our boot modes, which
becomes a little confusing.
So in order to make it user friendly, I would convert the proposed boot-mode
property to accept strings like “jtag/qspi/sd”.
Regards,
Sai Pavan
From: Edgar E. Iglesias
mailto:edgar.igles...@gmail.com>>
Sent: Friday, June 14, 2024 4:38 PM
To: Boddu, Sai Pavan mailto:sai.pavan.bo...@amd.com>>
Cc: qemu-...@nongnu.org<mailto:qemu-...@nongnu.org>;
qemu-devel@nongnu.org<mailto:qemu-devel@nongnu.org>; Alistair Francis
mailto:alist...@alistair23.me>>; Peter Maydell
mailto:peter.mayd...@linaro.org>>; Iglesias,
Francisco mailto:francisco.igles...@amd.com>>
Subject: Re: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
On Thu, Jun 13, 2024 at 5:36 PM Sai Pavan Boddu
mailto:sai.pavan.bo...@amd.com>> wrote:
Read boot-mode value as machine property and propagate that to
SLCR.BOOT_MODE register.
Hi Sai,
Directly exposing the register field to the user to set on the command-line
probably makes usability a little too rough (user has to check the register
specs in the TRM to change boot-mode).
We could perhaps add friendly names that we internally map to the register
field values.
Another question, can we use the existing -boot command-line arg for this?
Something along the lines of what x86 PC does:
https://github.com/qemu/qemu/blob/master/hw/i386/pc.c#L395
I don't know if the framework allows for long names but something like the
following would be nice:
qemu -boot spi,ethernet,jtag,uart,etc
[Boddu, Sai Pavan] Ok it makes much sense, Otherwise I would add more details
in the description of the new property about the possible boot modes.
Would also be great to document a small example, perhaps in
https://github.com/qemu/qemu/tree/master/docs/system/arm
[Boddu, Sai Pavan] Sure.
Regards,
Sai Pavan
Best regards,
Edgar
Signed-off-by: Sai Pavan Boddu
mailto:sai.pavan.bo...@amd.com>>
---
hw/arm/xilinx_zynq.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 7f7a3d23fb..4dfa9184ac 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -38,6 +38,7 @@
#include "qom/object.h"
#include "exec/tswap.h"
#include "target/arm/cpu-qom.h"
+#include "qapi/visitor.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
@@ -90,6 +91,7 @@ struct ZynqMachineState {
MachineState parent;
Clock *ps_clk;
ARMCPU *cpu[ZYNQ_MAX_CPUS];
+uint8_t BootMode;
};
static void zynq_write_board_setup(ARMCPU *cpu,
@@ -176,6 +178,19 @@ static inline int zynq_init_spi_flashes(uint32_t
base_addr, qemu_irq irq,
return unit;
}
+static void zynq_set_boot_mode(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ZynqMachineState *m = ZYNQ_MACHINE(obj);
+uint8_t val;
+
+if (!visit_type_uint8(v, name, &val, errp)) {
+return;
+}
+m->BootMode = val;
+}
+
static void zynq_init(MachineState *machine)
{
ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
@@ -241,6 +256,7 @@ static void zynq_init(MachineState *machine)
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_new("xilinx-zynq_slcr");
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
+qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->BootMode);
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF800);
@@ -372,6 +388,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void
*data)
NULL
};
MachineClass *mc = MACHINE_CLASS(oc);
+ObjectProperty *prop;
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
mc->max_cpus = ZYNQ_MAX_CPUS;
@@ -379,6 +396,11 @@ static void zynq_machine_class_init(ObjectClass *oc, void
*data)
mc->ignore_memory_transaction_failures = true;
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "zynq.ext_ram";
+prop = object_class_property_add(oc, "boot-mode", "uint8
RE: [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
Hi
Looks good.
Reviewed-by: sai.pavan.bo...@amd.com
Regards,
Sai Pavan
>-Original Message-
>From: Francisco Iglesias
>Sent: Monday, July 10, 2023 7:33 PM
>To: qemu-devel@nongnu.org
>Cc: frasse.igles...@gmail.com; alist...@alistair23.me;
>edgar.igles...@gmail.com; peter.mayd...@linaro.org; Konrad, Frederic
>; Boddu, Sai Pavan
>; Ho, Tong ; Garhwal,
>Vikram
>Subject: [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
>
>Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting CFI
>data packets between the Xilinx Configuration Frame Unit models (CFU_APB,
>CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG) and the
>Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
>emulating bitstream programming and readback).
>
>Signed-off-by: Francisco Iglesias
>---
> MAINTAINERS | 6
> hw/misc/meson.build | 1 +
> hw/misc/xlnx-cfi-if.c | 34
> include/hw/misc/xlnx-cfi-if.h | 59 +++
> 4 files changed, 100 insertions(+)
> create mode 100644 hw/misc/xlnx-cfi-if.c create mode 100644
>include/hw/misc/xlnx-cfi-if.h
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index 1817cfc62f..3ba115bb9b 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -1036,6 +1036,12 @@ S: Maintained
> F: hw/ssi/xlnx-versal-ospi.c
> F: include/hw/ssi/xlnx-versal-ospi.h
>
>+Xilinx Versal CFI
>+M: Francisco Iglesias
>+S: Maintained
>+F: hw/misc/xlnx-cfi-if.c
>+F: include/hw/misc/xlnx-cfi-if.h
>+
> STM32F100
> M: Alexandre Iooss
> L: qemu-...@nongnu.org
>diff --git a/hw/misc/meson.build b/hw/misc/meson.build index
>05877f61cc..9971b1e4db 100644
>--- a/hw/misc/meson.build
>+++ b/hw/misc/meson.build
>@@ -96,6 +96,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true:
>files('xlnx-versal-crl.c'))
> system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
> 'xlnx-versal-xramc.c',
> 'xlnx-versal-pmc-iou-slcr.c',
>+ 'xlnx-cfi-if.c',
> ))
> system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true:
>files('stm32f2xx_syscfg.c'))
> system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true:
>files('stm32f4xx_syscfg.c')) diff --git a/hw/misc/xlnx-cfi-if.c
>b/hw/misc/xlnx-cfi-
>if.c new file mode 100644 index 00..c45f05c4aa
>--- /dev/null
>+++ b/hw/misc/xlnx-cfi-if.c
>@@ -0,0 +1,34 @@
>+/*
>+ * Xilinx CFI interface
>+ *
>+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
>+ *
>+ * Written by Francisco Iglesias
>+ *
>+ * SPDX-License-Identifier: GPL-2.0-or-later */ #include
>+"qemu/osdep.h"
>+#include "hw/misc/xlnx-cfi-if.h"
>+
>+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt) {
>+XlnxCfiIfClass *xcic = XLNX_CFI_IF_GET_CLASS(cfi_if);
>+
>+if (xcic->cfi_transfer_packet) {
>+xcic->cfi_transfer_packet(cfi_if, pkt);
>+}
>+}
>+
>+static const TypeInfo xlnx_cfi_if_info = {
>+.name = TYPE_XLNX_CFI_IF,
>+.parent= TYPE_INTERFACE,
>+.class_size = sizeof(XlnxCfiIfClass), };
>+
>+static void xlnx_cfi_if_register_types(void) {
>+type_register_static(&xlnx_cfi_if_info);
>+}
>+
>+type_init(xlnx_cfi_if_register_types)
>+
>diff --git a/include/hw/misc/xlnx-cfi-if.h b/include/hw/misc/xlnx-cfi-if.h new
>file
>mode 100644 index 00..f9bd12292d
>--- /dev/null
>+++ b/include/hw/misc/xlnx-cfi-if.h
>@@ -0,0 +1,59 @@
>+/*
>+ * Xilinx CFI interface
>+ *
>+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
>+ *
>+ * Written by Francisco Iglesias
>+ *
>+ * SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef XLNX_CFI_IF_H
>+#define XLNX_CFI_IF_H 1
>+
>+#include "qemu/help-texts.h"
>+#include "hw/hw.h"
>+#include "qom/object.h"
>+
>+#define TYPE_XLNX_CFI_IF "xlnx-cfi-if"
>+typedef struct XlnxCfiIfClass XlnxCfiIfClass;
>+DECLARE_CLASS_CHECKERS(XlnxCfiIfClass, XLNX_CFI_IF, TYPE_XLNX_CFI_IF)
>+
>+#define XLNX_CFI_IF(obj) \
>+ INTERFACE_CHECK(XlnxCfiIf, (obj), TYPE_XLNX_CFI_IF)
>+
>+typedef enum {
>+PACKET_TYPE_CFU = 0x52,
>+PACKET_TYPE_CFRAME = 0xA1,
>+} xlnx_cfi_packet_type;
>+
>+typedef enum {
>+CFRAME_FAR = 1,
>+CFRAME_SFR = 2,
>+CFRAME_FDRI = 4,
>+CFRAME_CMD = 6,
>+} xlnx_cfi_reg_addr;
>+
>+typedef struct XlnxCfiPacket {
>+uint8_t reg_addr;
>+uint32_t data[4];
>+} XlnxCfiPacket;
>+
>+typedef struct XlnxCfiIf {
>+Object Parent;
>+} XlnxCfiIf;
>+
>+typedef struct XlnxCfiIfClass {
>+InterfaceClass parent;
>+
>+void (*cfi_transfer_packet)(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
>+} XlnxCfiIfClass;
>+
>+/**
>+ * Transfer a XlnxCfiPacket.
>+ *
>+ * @cfi_if: the object implementing this interface
>+ * @XlnxCfiPacket: a pointer to the XlnxCfiPacket to transfer */ void
>+xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
>+
>+#endif /* XLNX_CFI_IF_H */
>--
>2.34.1
RE: [PATCH 1/1] xlnx-versal-ospi: disable reentrancy detection for iomem_dac
Hi Peter,
>-Original Message-
>From: Peter Maydell
>Sent: Tuesday, December 12, 2023 10:12 PM
>To: Boddu, Sai Pavan
>Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; qemu-
>bl...@nongnu.org; Alistair Francis ; Edgar E. Iglesias
>; Kevin Wolf ; Francisco
>Iglesias ; saipavanbo...@gmail.com
>Subject: Re: [PATCH 1/1] xlnx-versal-ospi: disable reentrancy detection for
>iomem_dac
>
>On Tue, 5 Dec 2023 at 10:08, Sai Pavan Boddu
>wrote:
>>
>> The OSPI DMA reads flash data through the OSPI linear address space
>> (the iomem_dac region), because of this the reentrancy guard
>> introduced in commit a2e1753b ("memory: prevent dma-reentracy issues")
>> is disabled for the memory region.
>>
>> Signed-off-by: Sai Pavan Boddu
>> ---
>> hw/ssi/xlnx-versal-ospi.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c
>> index 1a61679c2f..5123e7dde7 100644
>> --- a/hw/ssi/xlnx-versal-ospi.c
>> +++ b/hw/ssi/xlnx-versal-ospi.c
>> @@ -1772,6 +1772,7 @@ static void xlnx_versal_ospi_init(Object *obj)
>> memory_region_init_io(&s->iomem_dac, obj, &ospi_dac_ops, s,
>>TYPE_XILINX_VERSAL_OSPI "-dac", 0x2000);
>> sysbus_init_mmio(sbd, &s->iomem_dac);
>> +s->iomem_dac.disable_reentrancy_guard = true;
>
>Where we set this flag we should have a comment explaining why we need to
>do it, please.
[Boddu, Sai Pavan] Sure, I will send a V2 on this.
Regards,
Sai pavan
>
>PS: for a single patch you don't need to use a separate cover letter; cover
>letters
>are only needed for multi-patch series.
>
>thanks
>-- PMM
RE: [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions
Reviewed-by: sai.pavan.bo...@amd.com
Regards,
Sai Pavan
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register
>definitions
>
>Replace register defines with the REG32 macro from registerfields.h in the
>Cadence GEM device.
>
>Signed-off-by: Luc Michel
>---
> hw/net/cadence_gem.c | 527 +--
> 1 file changed, 261 insertions(+), 266 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>f445d8bb5e..0e5744ecd7 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -26,10 +26,11 @@
> #include /* For crc32 */
>
> #include "hw/irq.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/qdev-properties.h"
>+#include "hw/registerfields.h"
> #include "migration/vmstate.h"
> #include "qapi/error.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "sysemu/dma.h"
>@@ -42,151 +43,146 @@
> qemu_log(": %s: ", __func__); \
> qemu_log(__VA_ARGS__); \
> } \
> } while (0)
>
>-#define GEM_NWCTRL(0x / 4) /* Network Control reg */
>-#define GEM_NWCFG (0x0004 / 4) /* Network Config reg */
>-#define GEM_NWSTATUS (0x0008 / 4) /* Network Status reg */
>-#define GEM_USERIO(0x000C / 4) /* User IO reg */
>-#define GEM_DMACFG(0x0010 / 4) /* DMA Control reg */
>-#define GEM_TXSTATUS (0x0014 / 4) /* TX Status reg */
>-#define GEM_RXQBASE (0x0018 / 4) /* RX Q Base address reg */
>-#define GEM_TXQBASE (0x001C / 4) /* TX Q Base address reg */
>-#define GEM_RXSTATUS (0x0020 / 4) /* RX Status reg */
>-#define GEM_ISR (0x0024 / 4) /* Interrupt Status reg */
>-#define GEM_IER (0x0028 / 4) /* Interrupt Enable reg */
>-#define GEM_IDR (0x002C / 4) /* Interrupt Disable reg */
>-#define GEM_IMR (0x0030 / 4) /* Interrupt Mask reg */
>-#define GEM_PHYMNTNC (0x0034 / 4) /* Phy Maintenance reg */
>-#define GEM_RXPAUSE (0x0038 / 4) /* RX Pause Time reg */
>-#define GEM_TXPAUSE (0x003C / 4) /* TX Pause Time reg */
>-#define GEM_TXPARTIALSF (0x0040 / 4) /* TX Partial Store and Forward
>*/
>-#define GEM_RXPARTIALSF (0x0044 / 4) /* RX Partial Store and Forward
>*/
>-#define GEM_JUMBO_MAX_LEN (0x0048 / 4) /* Max Jumbo Frame Size
>*/
>-#define GEM_HASHLO(0x0080 / 4) /* Hash Low address reg */
>-#define GEM_HASHHI(0x0084 / 4) /* Hash High address reg */
>-#define GEM_SPADDR1LO (0x0088 / 4) /* Specific addr 1 low reg */
>-#define GEM_SPADDR1HI (0x008C / 4) /* Specific addr 1 high reg */
>-#define GEM_SPADDR2LO (0x0090 / 4) /* Specific addr 2 low reg */
>-#define GEM_SPADDR2HI (0x0094 / 4) /* Specific addr 2 high reg */
>-#define GEM_SPADDR3LO (0x0098 / 4) /* Specific addr 3 low reg */
>-#define GEM_SPADDR3HI (0x009C / 4) /* Specific addr 3 high reg */
>-#define GEM_SPADDR4LO (0x00A0 / 4) /* Specific addr 4 low reg */
>-#define GEM_SPADDR4HI (0x00A4 / 4) /* Specific addr 4 high reg */
>-#define GEM_TIDMATCH1 (0x00A8 / 4) /* Type ID1 Match reg */
>-#define GEM_TIDMATCH2 (0x00AC / 4) /* Type ID2 Match reg */
>-#define GEM_TIDMATCH3 (0x00B0 / 4) /* Type ID3 Match reg */
>-#define GEM_TIDMATCH4 (0x00B4 / 4) /* Type ID4 Match reg */
>-#define GEM_WOLAN (0x00B8 / 4) /* Wake on LAN reg */
>-#define GEM_IPGSTRETCH(0x00BC / 4) /* IPG Stretch reg */
>-#define GEM_SVLAN (0x00C0 / 4) /* Stacked VLAN reg */
>-#define GEM_MODID (0x00FC / 4) /* Module ID reg */
>-#define GEM_OCTTXLO (0x0100 / 4) /* Octets transmitted Low reg */
>-#define GEM_OCTTXHI (0x0104 / 4) /* Octets transmitted High reg */
>-#define GEM_TXCNT (0x0108 / 4) /* Error-free Frames transmitted
>*/
>-#define GEM_TXBCNT(0x010C / 4) /* Error-free Broadcast Frames */
>-#define GEM_TXMCNT(0x0110 / 4) /* Error-free Multicast Frame */
>-#define GEM_TXPAUSECNT(0x0114 / 4) /* Pause Frames Transmitted
>*/
>-#define GEM_TX64CNT (0x0118 / 4) /* Error-free 64 TX */
>-#define GEM_TX65CNT (0x011C / 4) /* Error-free 65-127 TX */
>-#define GEM_TX128CNT (0x0120
RE: [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
>
>Describe screening registers fields using the FIELD macros.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 92 ++--
> 1 file changed, 47 insertions(+), 45 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>0e5744ecd7..f01c81de97 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -168,39 +168,42 @@ REG32(INT_Q7_ENABLE, 0x618)
>
> REG32(INT_Q1_DISABLE, 0x620)
> REG32(INT_Q7_DISABLE, 0x638)
>
> REG32(SCREENING_TYPE1_REG0, 0x500)
>-
>-#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
>-#define GEM_ST1R_DSTC_ENABLE(1 << 28)
>-#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
>-#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 -
>GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
>-#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
>-#define GEM_ST1R_DSTC_MATCH_WIDTH (11 -
>GEM_ST1R_DSTC_MATCH_SHIFT + 1)
>-#define GEM_ST1R_QUEUE_SHIFT(0)
>-#define GEM_ST1R_QUEUE_WIDTH(3 - GEM_ST1R_QUEUE_SHIFT + 1)
>+FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
>+FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8)
>+FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16)
>+FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1)
>+FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1)
>+FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1)
>
> REG32(SCREENING_TYPE2_REG0, 0x540)
>-
>-#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
>-#define GEM_ST2R_COMPARE_A_SHIFT(13)
>-#define GEM_ST2R_COMPARE_WIDTH (17 -
>GEM_ST2R_COMPARE_A_SHIFT + 1)
>-#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
>-#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) -#define
>GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 -
>GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
>-+ 1)
>-#define GEM_ST2R_QUEUE_SHIFT(0)
>-#define GEM_ST2R_QUEUE_WIDTH(3 - GEM_ST2R_QUEUE_SHIFT + 1)
>+FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
>+FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3)
>+FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1)
>+FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3)
>+FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5)
>+FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1)
>+FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1)
>
> REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
>+
> REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
>+FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
>+FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16)
>
>-#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) -#define
>GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 -
>GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
>-#define GEM_T2CW1_OFFSET_VALUE_SHIFT(0)
>-#define GEM_T2CW1_OFFSET_VALUE_WIDTH(6 -
>GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
>+REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>+FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
>+FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
>+FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
>+FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
> #define GEM_NWCTRL_TXSTART 0x0200 /* Transmit Enable */
> #define GEM_NWCTRL_TXENA 0x0008 /* Transmit Enable */
> #define GEM_NWCTRL_RXENA 0x0004 /* Receive Enable */
>@@ -753,45 +756,43 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
> matched = false;
> mismatched = false;
>
> /* Screening is based on UDP Port */
>-if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
>+if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) {
> uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
>-if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
>- GEM_ST1R_UDP_PORT_MATCH_W
RE: [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL
>register fields
>
>Use the FIELD macro to describe the NWCTRL register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 53 +---
>
> 1 file changed, 40 insertions(+), 13 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>f01c81de97..2864f0940e 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -44,10 +44,42 @@
> qemu_log(__VA_ARGS__); \
> } \
> } while (0)
>
> REG32(NWCTRL, 0x0) /* Network Control reg */
>+FIELD(NWCTRL, LOOPBACK , 0, 1)
>+FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1)
>+FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1)
>+FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1)
>+FIELD(NWCTRL, MAN_PORT_EN , 4, 1)
>+FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1)
>+FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1)
>+FIELD(NWCTRL, STATS_WRITE_EN, 7, 1)
>+FIELD(NWCTRL, BACK_PRESSURE, 8, 1)
>+FIELD(NWCTRL, TRANSMIT_START , 9, 1)
>+FIELD(NWCTRL, TRANSMIT_HALT, 10, 1)
>+FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1)
>+FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1)
>+FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1)
>+FIELD(NWCTRL, STATS_READ_SNAP, 14, 1)
>+FIELD(NWCTRL, STORE_RX_TS, 15, 1)
>+FIELD(NWCTRL, PFC_ENABLE, 16, 1)
>+FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1)
>+FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1)
>+FIELD(NWCTRL, TX_LPI_EN, 19, 1)
>+FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1)
>+FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1)
>+FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1)
>+FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1)
>+FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1)
>+FIELD(NWCTRL, PFC_CTRL , 25, 1)
>+FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1)
>+FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1)
>+FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
>+FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
>+FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
>+
> REG32(NWCFG, 0x4) /* Network Config reg */ REG32(NWSTATUS, 0x8) /*
>Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ REG32(DMACFG,
>0x10) /* DMA Control reg */ REG32(TXSTATUS, 0x14) /* TX Status reg */ @@ -
>202,15 +234,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
>-#define GEM_NWCTRL_TXSTART 0x0200 /* Transmit Enable */
>-#define GEM_NWCTRL_TXENA 0x0008 /* Transmit Enable */
>-#define GEM_NWCTRL_RXENA 0x0004 /* Receive Enable */
>-#define GEM_NWCTRL_LOCALLOOP 0x0002 /* Local Loopback */
>-
> #define GEM_NWCFG_STRIP_FCS0x0002 /* Strip FCS field */
> #define GEM_NWCFG_LERR_DISC0x0001 /* Discard RX frames with len
>err */
> #define GEM_NWCFG_BUFF_OFST_M 0xC000 /* Receive buffer offset
>mask */
> #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
> #define GEM_NWCFG_RCV_1538 0x0100 /* Receive 1538 bytes frame
>*/
>@@ -558,11 +585,11 @@ static bool gem_can_receive(NetClientState *nc)
> int i;
>
> s = qemu_get_nic_opaque(nc);
>
> /* Do nothing if receive is not enabled. */
>-if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
>+if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) {
> if (s->can_rx_state != 1) {
> s->can_rx_state = 1;
> DB_PRINT("can't receive - no enable\n");
> }
> return false;
>@@ -1171,11 +1198,11 @@ static void gem_transmit(CadenceGEMState *s)
> uint8_t *p;
> unsignedtotal_bytes;
> int q = 0;
>
> /* Do nothing if transmit is not enabled. */
>-if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
>+if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
> return;
> }
>
> DB_PRINT("\n");
>
>@@ -1196,11 +1223,11 @@ static void gem_transmit(CadenceGEMState *s)
>sizeof(uint32_t) * gem_get_desc_len(s, false));
> /* Handle all descriptors owned by hardware */
> while (tx_desc_get_used(desc) == 0) {
>
> /* Do n
RE: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG
>register fields
>
>Use de FIELD macro to describe the NWCFG register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 60 ---
>-
> 1 file changed, 39 insertions(+), 21 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>2864f0940e..09f570b6fb 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -77,10 +77,39 @@ REG32(NWCTRL, 0x0) /* Network Control reg */
> FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
> FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
> FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
>
> REG32(NWCFG, 0x4) /* Network Config reg */
>+FIELD(NWCFG, SPEED, 0, 1)
>+FIELD(NWCFG, FULL_DUPLEX, 1, 1)
>+FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1)
>+FIELD(NWCFG, JUMBO_FRAMES, 3, 1)
>+FIELD(NWCFG, PROMISC, 4, 1)
>+FIELD(NWCFG, NO_BROADCAST, 5, 1)
>+FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1)
>+FIELD(NWCFG, UNICAST_HASH_EN, 7, 1)
>+FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1)
>+FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1)
>+FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1)
>+FIELD(NWCFG, PCS_SELECT, 11, 1)
>+FIELD(NWCFG, RETRY_TEST, 12, 1)
>+FIELD(NWCFG, PAUSE_ENABLE, 13, 1)
>+FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2)
>+FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1)
>+FIELD(NWCFG, FCS_REMOVE, 17, 1)
>+FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3)
>+FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2)
>+FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1)
>+FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1)
>+FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1)
>+FIELD(NWCFG, IGNORE_RX_FCS, 26, 1)
>+FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1)
>+FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1)
>+FIELD(NWCFG, NSP_ACCEPT, 29, 1)
>+FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
>+FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
>+
> REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /*
>User IO reg */ REG32(DMACFG, 0x10) /* DMA Control reg */
>REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q
>Base address reg */ @@ -234,21 +263,10 @@
>REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
>-#define GEM_NWCFG_STRIP_FCS0x0002 /* Strip FCS field */
>-#define GEM_NWCFG_LERR_DISC0x0001 /* Discard RX frames with len
>err */
>-#define GEM_NWCFG_BUFF_OFST_M 0xC000 /* Receive buffer offset
>mask */
>-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
>-#define GEM_NWCFG_RCV_1538 0x0100 /* Receive 1538 bytes frame
>*/
>-#define GEM_NWCFG_UCAST_HASH 0x0080 /* accept unicast if hash
>match */
>-#define GEM_NWCFG_MCAST_HASH 0x0040 /* accept multicast if hash
>match */
>-#define GEM_NWCFG_BCAST_REJ0x0020 /* Reject broadcast packets
>*/
>-#define GEM_NWCFG_PROMISC 0x0010 /* Accept all packets */
>-#define GEM_NWCFG_JUMBO_FRAME 0x0008 /* Jumbo Frames enable
>*/
>-
> #define GEM_DMACFG_ADDR_64B(1U << 30)
> #define GEM_DMACFG_TX_BD_EXT (1U << 29)
> #define GEM_DMACFG_RX_BD_EXT (1U << 28)
> #define GEM_DMACFG_RBUFSZ_M0x00FF /* DMA RX Buffer Size mask
>*/
> #define GEM_DMACFG_RBUFSZ_S16 /* DMA RX Buffer Size shift */
>@@ -480,21 +498,22 @@ static inline void rx_desc_set_sar(uint32_t *desc, int
>sar_idx) static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF,
>0xFF,
>0xFF };
>
> static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) {
> uint32_t size;
>-if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
>+if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) {
> size = s->regs[R_JUMBO_MAX_LEN];
> if (size > s->jumbo_max_len) {
> size = s->jumbo_max_len;
> qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg
>cannot be"
> " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> }
> } else if (tx) {
> size = 1518;
> } else {
>-size
RE: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG
>register fields
>
>Use de FIELD macro to describe the DMACFG register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 48 ---
>-
> 1 file changed, 31 insertions(+), 17 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>09f570b6fb..5c386adff2 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -108,11 +108,31 @@ REG32(NWCFG, 0x4) /* Network Config reg */
> FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
> FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
>
> REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /*
>User IO reg */
>+
> REG32(DMACFG, 0x10) /* DMA Control reg */
>+FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1)
>+FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1)
>+FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1)
>+FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1)
>+FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1)
>+FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1)
>+FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1)
>+FIELD(DMACFG, RX_BUF_SIZE, 16, 8)
>+FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1)
>+FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1)
>+FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1)
>+FIELD(DMACFG, TX_PBUF_SIZE, 10, 1)
>+FIELD(DMACFG, RX_PBUF_SIZE, 8, 2)
>+FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1)
>+FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1)
>+FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
>+FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
>+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>+
> REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q
>Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
>REG32(RXSTATUS, 0x20) /* RX Status reg */ REG32(ISR, 0x24) /* Interrupt
>Status reg */ @@ -263,17 +283,10 @@ REG32(TYPE2_COMPARE_0_WORD_1,
>0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
>-#define GEM_DMACFG_ADDR_64B(1U << 30)
>-#define GEM_DMACFG_TX_BD_EXT (1U << 29)
>-#define GEM_DMACFG_RX_BD_EXT (1U << 28)
>-#define GEM_DMACFG_RBUFSZ_M0x00FF /* DMA RX Buffer Size mask
>*/
>-#define GEM_DMACFG_RBUFSZ_S16 /* DMA RX Buffer Size shift */
>-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>-#define GEM_DMACFG_TXCSUM_OFFL 0x0800 /* Transmit checksum
>offload */
>
> #define GEM_TXSTATUS_TXCMPL0x0020 /* Transmit Complete */
> #define GEM_TXSTATUS_USED 0x0001 /* sw owned descriptor
>encountered */
>
> #define GEM_RXSTATUS_FRMRCVD 0x0002 /* Frame received */
>@@ -367,11 +380,11 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>
> static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0];
>
>-if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
>@@ -412,25 +425,25 @@ static inline void print_gem_tx_desc(uint32_t *desc,
>uint8_t queue)
>
> static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0] & ~0x3UL;
>
>-if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
> static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) {
> int ret = 2;
>
>-if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret += 2;
> }
>-if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
>- : GEM_DMACFG_TX_BD_EXT)) {
>+if (s->regs[R_DMACFG] & (rx_n_tx ?
>R_DMACFG_RX_BD_EXT_MODE_EN_MASK
>+ :
>+ R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) {
> ret += 2;
> }
>
> assert(ret <= D
RE: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe
>[TX|RX]STATUS register fields
>
>Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 34 +-
> 1 file changed, 25 insertions(+), 9 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>5c386adff2..0acee1d544 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -130,13 +130,34 @@ REG32(DMACFG, 0x10) /* DMA Control reg */
> FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
> FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
> #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>
> REG32(TXSTATUS, 0x14) /* TX Status reg */
>+FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
>+FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
>+FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
>+FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
>+FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
>+FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
>+FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
>+FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
>+FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
>+FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
>+FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
>+FIELD(TXSTATUS, COLLISION, 1, 1)
>+FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
>+
> REG32(RXQBASE, 0x18) /* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /*
>TX Q Base address reg */ REG32(RXSTATUS, 0x20) /* RX Status reg */
>+FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
>+FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
>+FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
>+FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
>+FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
>+FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>+
> REG32(ISR, 0x24) /* Interrupt Status reg */ REG32(IER, 0x28) /* Interrupt
>Enable reg */ REG32(IDR, 0x2c) /* Interrupt Disable reg */ REG32(IMR, 0x30)
>/* Interrupt Mask reg */ REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>@@ -284,15 +305,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
>
>-#define GEM_TXSTATUS_TXCMPL0x0020 /* Transmit Complete */
>-#define GEM_TXSTATUS_USED 0x0001 /* sw owned descriptor
>encountered */
>-
>-#define GEM_RXSTATUS_FRMRCVD 0x0002 /* Frame received */
>-#define GEM_RXSTATUS_NOBUF 0x0001 /* Buffer unavailable */
>
> /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> #define GEM_INT_TXCMPL0x0080 /* Transmit Complete */
> #define GEM_INT_AMBA_ERR 0x0040
> #define GEM_INT_TXUSED 0x0008
>@@ -985,11 +1001,11 @@ static void gem_get_rx_desc(CadenceGEMState *s,
>int q)
>sizeof(uint32_t) * gem_get_desc_len(s, true));
>
> /* Descriptor owned by software ? */
> if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
> DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
>-s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
>+s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
> gem_set_isr(s, q, GEM_INT_RXUSED);
> /* Handle interrupt consequences */
> gem_update_int_status(s);
> }
> }
>@@ -1162,11 +1178,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
> }
>
> /* Count it */
> gem_receive_updatestats(s, buf, size);
>
>-s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
>+s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
> gem_set_isr(s, q, GEM_INT_RXCMPL);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
>@@ -1313,11 +1329,11 @@ static void gem_transmit(CadenceGEMState *s)
> s->tx_desc_addr[q] = packet_desc_addr +
> 4 * gem_get_desc_len(s, false);
> }
> DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
>-s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
>+s->regs[R_TXSTATUS] |=
>+ R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
> gem_set_isr(s, q, GEM_INT_TXCMPL);
>
> /* Handle interr
RE: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ
>register fields
>
>Use de FIELD macro to describe the IRQ related register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 51 +---
>
> 1 file changed, 39 insertions(+), 12 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>0acee1d544..6d084a3b31 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -155,13 +155,46 @@ REG32(RXSTATUS, 0x20) /* RX Status reg */
> FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
> FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
> FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>
> REG32(ISR, 0x24) /* Interrupt Status reg */
>+FIELD(ISR, TX_LOCKUP, 31, 1)
>+FIELD(ISR, RX_LOCKUP, 30, 1)
>+FIELD(ISR, TSU_TIMER, 29, 1)
>+FIELD(ISR, WOL, 28, 1)
>+FIELD(ISR, RECV_LPI, 27, 1)
>+FIELD(ISR, TSU_SEC_INCR, 26, 1)
>+FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
>+FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
>+FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
>+FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
>+FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
>+FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
>+FIELD(ISR, PTP_SYNC_RECV, 19, 1)
>+FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
>+FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
>+FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
>+FIELD(ISR, EXT_IRQ, 15, 1)
>+FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
>+FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
>+FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
>+FIELD(ISR, RESP_NOT_OK, 11, 1)
>+FIELD(ISR, RECV_OVERRUN, 10, 1)
>+FIELD(ISR, LINK_CHANGE, 9, 1)
>+FIELD(ISR, USXGMII_INT, 8, 1)
>+FIELD(ISR, XMIT_COMPLETE, 7, 1)
>+FIELD(ISR, AMBA_ERROR, 6, 1)
>+FIELD(ISR, RETRY_EXCEEDED, 5, 1)
>+FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
>+FIELD(ISR, TX_USED, 3, 1)
>+FIELD(ISR, RX_USED, 2, 1)
>+FIELD(ISR, RECV_COMPLETE, 1, 1)
>+FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
> REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt
>Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */
>+
> REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ REG32(RXPAUSE, 0x38)
>/* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
>REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
>REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ @@ -306,16
>+339,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*/
>
>
>-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
>-#define GEM_INT_TXCMPL0x0080 /* Transmit Complete */
>-#define GEM_INT_AMBA_ERR 0x0040
>-#define GEM_INT_TXUSED 0x0008
>-#define GEM_INT_RXUSED 0x0004
>-#define GEM_INT_RXCMPL0x0002
>
> #define GEM_PHYMNTNC_OP_R 0x2000 /* read operation */
> #define GEM_PHYMNTNC_OP_W 0x1000 /* write operation */
> #define GEM_PHYMNTNC_ADDR 0x0F80 /* Address bits */
> #define GEM_PHYMNTNC_ADDR_SHFT 23
>@@ -1002,11 +1029,11 @@ static void gem_get_rx_desc(CadenceGEMState
>*s, int q)
>
> /* Descriptor owned by software ? */
> if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
> DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
> s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
>-gem_set_isr(s, q, GEM_INT_RXUSED);
>+gem_set_isr(s, q, R_ISR_RX_USED_MASK);
> /* Handle interrupt consequences */
> gem_update_int_status(s);
> }
> }
>
>@@ -1102,11 +1129,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
> /* Find which queue we are targeting */
> q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
>
> if (size > gem_get_max_buf_len(s, false)) {
> qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
>-gem_set_isr(s, q, GEM_INT_AMBA_ERR);
>+gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
> return -1;
> }
>
> while (bytes_to_copy) {
> hwaddr desc_addr;
>@@ -1179,11 +1206,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
> /* Count it */
> gem_receive
RE: [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe
>PHYMNTNC register fields
>
>Use the FIELD macro to describe the PHYMNTNC register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 27 ++-
> 1 file changed, 14 insertions(+), 13 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>955a8da134..4c5fe10316 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -192,10 +192,18 @@ REG32(ISR, 0x24) /* Interrupt Status reg */
>REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt
>Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */
>
> REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>+FIELD(PHYMNTNC, DATA, 0, 16)
>+FIELD(PHYMNTNC, REG_ADDR, 18, 5)
>+FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
>+FIELD(PHYMNTNC, OP, 28, 2)
>+FIELD(PHYMNTNC, ST, 30, 2)
>+#define MDIO_OP_READ0x3
>+#define MDIO_OP_WRITE 0x2
>+
> REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX
>Pause Time reg */ REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward
>*/ REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
>REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ @@ -340,17
>+348,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>
> /*/
>
>
>
>-#define GEM_PHYMNTNC_OP_R 0x2000 /* read operation */
>-#define GEM_PHYMNTNC_OP_W 0x1000 /* write operation */
>-#define GEM_PHYMNTNC_ADDR 0x0F80 /* Address bits */
>-#define GEM_PHYMNTNC_ADDR_SHFT 23
>-#define GEM_PHYMNTNC_REG 0x007C /* register bits */
>-#define GEM_PHYMNTNC_REG_SHIFT 18
>-
> /* Marvell PHY definitions */
> #define BOARD_PHY_ADDRESS0 /* PHY address we will emulate a device at
>*/
>
> #define PHY_REG_CONTROL 0
> #define PHY_REG_STATUS 1
>@@ -1539,16 +1540,16 @@ static uint64_t gem_read(void *opaque, hwaddr
>offset, unsigned size)
> case R_ISR:
> DB_PRINT("lowering irqs on ISR read\n");
> /* The interrupts get updated at the end of the function. */
> break;
> case R_PHYMNTNC:
>-if (retval & GEM_PHYMNTNC_OP_R) {
>+if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
> uint32_t phy_addr, reg_num;
>
>-phy_addr = (retval & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
>+phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
> if (phy_addr == s->phy_addr) {
>-reg_num = (retval & GEM_PHYMNTNC_REG) >>
>GEM_PHYMNTNC_REG_SHIFT;
>+reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
> retval &= 0x;
> retval |= gem_phy_read(s, reg_num);
> } else {
> retval |= 0x; /* No device at this address */
> }
>@@ -1662,16 +1663,16 @@ static void gem_write(void *opaque, hwaddr
>offset, uint64_t val,
> case R_SPADDR3HI:
> case R_SPADDR4HI:
> s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
> break;
> case R_PHYMNTNC:
>-if (val & GEM_PHYMNTNC_OP_W) {
>+if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
> uint32_t phy_addr, reg_num;
>
>-phy_addr = (val & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
>+phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
> if (phy_addr == s->phy_addr) {
>-reg_num = (val & GEM_PHYMNTNC_REG) >>
>GEM_PHYMNTNC_REG_SHIFT;
>+reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
> gem_phy_write(s, reg_num, val);
> }
> }
> break;
> }
>--
>2.39.2
RE: [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write
>only
>
>The MDIO access is done only on a write to the PHYMNTNC register. A
>subsequent read is used to retrieve the result but does not trigger an MDIO
>access by itself.
>
>Refactor the PHY access logic to perform all accesses (MDIO reads and
>writes) at PHYMNTNC write time.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 56 ++--
> 1 file changed, 33 insertions(+), 23 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>4c5fe10316..21146f4242 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1519,10 +1519,42 @@ static void gem_phy_write(CadenceGEMState *s,
>unsigned reg_num, uint16_t val)
> break;
> }
> s->phy_regs[reg_num] = val;
> }
>
>+static void gem_handle_phy_access(CadenceGEMState *s) {
>+uint32_t val = s->regs[R_PHYMNTNC];
>+uint32_t phy_addr, reg_num;
>+
>+phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
>+
>+if (phy_addr != s->phy_addr) {
>+/* no phy at this address */
>+if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
>+s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0x);
>+}
>+return;
>+}
>+
>+reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
>+
>+switch (FIELD_EX32(val, PHYMNTNC, OP)) {
>+case MDIO_OP_READ:
>+s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
>+ gem_phy_read(s, reg_num));
>+break;
>+
>+case MDIO_OP_WRITE:
>+gem_phy_write(s, reg_num, val);
>+break;
>+
>+default:
>+break; /* only clause 22 operations are supported */
>+}
>+}
>+
> /*
> * gem_read32:
> * Read a GEM register.
> */
> static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) @@ -
>1539,24 +1571,10 @@ static uint64_t gem_read(void *opaque, hwaddr
>offset, unsigned size)
> switch (offset) {
> case R_ISR:
> DB_PRINT("lowering irqs on ISR read\n");
> /* The interrupts get updated at the end of the function. */
> break;
>-case R_PHYMNTNC:
>-if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
>-uint32_t phy_addr, reg_num;
>-
>-phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
>-if (phy_addr == s->phy_addr) {
>-reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
>-retval &= 0x;
>-retval |= gem_phy_read(s, reg_num);
>-} else {
>-retval |= 0x; /* No device at this address */
>-}
>-}
>-break;
> }
>
> /* Squash read to clear bits */
> s->regs[offset] &= ~(s->regs_rtc[offset]);
>
>@@ -1663,19 +1681,11 @@ static void gem_write(void *opaque, hwaddr
>offset, uint64_t val,
> case R_SPADDR3HI:
> case R_SPADDR4HI:
> s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
> break;
> case R_PHYMNTNC:
>-if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
>-uint32_t phy_addr, reg_num;
>-
>-phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
>-if (phy_addr == s->phy_addr) {
>-reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
>-gem_phy_write(s, reg_num, val);
>-}
>-}
>+gem_handle_phy_access(s);
> break;
> }
>
> DB_PRINT("newval: 0x%08x\n", s->regs[offset]); }
>--
>2.39.2
RE: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc ; qemu-...@nongnu.org; Edgar E .
>Iglesias ; Alistair Francis ;
>Peter Maydell ; Jason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for
>CRC
>
>The CRC was stored in an unsigned variable in gem_receive. Change it for a
>uint32_t to ensure we have the correct variable size here.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
>---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>21146f4242..d52530bae4 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1103,11 +1103,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
> /* Strip of FCS field ? (usually yes) */
> if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
> rxbuf_ptr = (void *)buf;
> } else {
>-unsigned crc_val;
>+uint32_t crc_val;
>
> if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
> size = MAX_FRAME_SIZE - sizeof(crc_val);
> }
> bytes_to_copy = size;
>--
>2.39.2
RE: [PATCH] hw/riscv: Add Microblaze V 32bit virt board
Hi Daniel, Thanks for the review, I will send a V2 addressing the comments. Regards, Sai Pavan >-Original Message- >From: Daniel Henrique Barboza >Sent: Wednesday, October 16, 2024 1:28 AM >To: Boddu, Sai Pavan ; qemu-devel@nongnu.org; >qemu-ri...@nongnu.org >Cc: Paolo Bonzini ; Palmer Dabbelt >; Alistair Francis ; Bin Meng >; Weiwei Li ; Liu Zhiwei >; Simek, Michal >Subject: Re: [PATCH] hw/riscv: Add Microblaze V 32bit virt board > >Hi, > > >The doc file included in the patch will break the build: > >/home/danielhb/work/qemu/docs/system/riscv/microblaze-v-virt.rst:document isn't >included in any toctree > >You'll need this extra change: > > >$ git diff >diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index >ba195f1518..6161f01d21 100644 >--- a/docs/system/target-riscv.rst >+++ b/docs/system/target-riscv.rst >@@ -70,6 +70,7 @@ undocumented; you can get a complete list by running > riscv/shakti-c > riscv/sifive_u > riscv/virt >+ riscv/microblaze-v-virt > > RISC-V CPU firmware > > >More comments below: > >On 10/15/24 10:39 AM, Sai Pavan Boddu wrote: >> Add a basic board with interrupt controller (intc), timer, serial >> (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000 >> (configured via command line eg. -m 2g). >> This is basic configuration which matches HW generated out of AMD >> Vivado (design tools). But initial configuration is going beyond what >> it is configured by default because validation should be done on other >> configurations too. That's why wire also additional uart16500, axi >> ethernet(with axi dma). >> GPIOs, i2c and qspi is also listed for completeness. >> >> IRQ map is: (addr) >> 0 - timer (0x41c0) >> 1 - uartlite (0x4060) >> 2 - i2c (0x4080) >> 3 - qspi (0x44a0) >> 4 - uart16550 (0x44a1) >> 5 - emaclite (0x40e0) >> 6 - timer2 (0x41c1) >> 7 - axi emac (0x40c0) >> 8 - axi dma (0x41e0) >> 9 - axi dma >> 10 - gpio (0x4000) >> 11 - gpio2 (0x4001) >> 12 - gpio3 (0x4002) >> >> Signed-off-by: Sai Pavan Boddu >> Signed-off-by: Michal Simek >> --- >> MAINTAINERS | 6 + >> docs/system/riscv/microblaze-v-virt.rst | 39 + >> hw/riscv/microblaze-v-virt.c| 182 >> hw/riscv/Kconfig| 8 ++ >> hw/riscv/meson.build| 1 + >> 5 files changed, 236 insertions(+) >> create mode 100644 docs/system/riscv/microblaze-v-virt.rst >> create mode 100644 hw/riscv/microblaze-v-virt.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS index d7a11fe6017..b104b6d0f7f >> 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -1274,6 +1274,12 @@ M: Edgar E. Iglesias >> S: Maintained >> F: hw/microblaze/petalogix_ml605_mmu.c >> >> +amd-microblaze-v-virt >> +M: Sai Pavan Boddu >> +S: Maintained >> +F: hw/riscv/microblaze-v-virt.c >> +F: docs/system/riscv/microblaze-v-virt.rst >> + >> MIPS Machines >> - >> Overall MIPS Machines >> diff --git a/docs/system/riscv/microblaze-v-virt.rst >> b/docs/system/riscv/microblaze-v-virt.rst >> new file mode 100644 >> index 000..42cac9ac475 >> --- /dev/null >> +++ b/docs/system/riscv/microblaze-v-virt.rst >> @@ -0,0 +1,39 @@ >> +microblaze-v virt board (``amd-microblaze-v-virt``) >> +=== >> +The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD >adaptive SoCs and FPGAs. >> +The MicroBlaze V processor is based on a 32-bit RISC-V instruction set >architecture (ISA). >> + >> +More details here: >> +https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaz >> +e-V-Architecture >> + >> +The microblaze-v virt board in QEMU is a virtual board with following >> +supported devices >> + >> +Implemented CPU cores: >> + >> +1 RISCV32 core >> + >> +Implemented devices: >> + >> +- timer >> +- uartlite >> +- uart16550 >> +- emaclite >> +- timer2 >> +- axi emac >> +- axi dma >> + >> +Running >> +""""""" >> +Running U-boot >> + >> +.. code-block:: bash >> + >> + >> + $ qemu-system-riscv32 -M amd-microblaze-v-virt \ >> + -display none \ >> + -device loader,addr=0x8000
RE: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board
Hi Alistair, Thanks for the review, I will send a v3 as follow-up. Regards, Sai Pavan >-Original Message- >From: Alistair Francis >Sent: Thursday, October 31, 2024 10:01 AM >To: Philippe Mathieu-Daudé >Cc: Simek, Michal ; Boddu, Sai Pavan >; qemu-devel@nongnu.org; qemu-ri...@nongnu.org; >Paolo Bonzini ; Palmer Dabbelt ; >Alistair Francis ; Bin Meng ; >Weiwei Li ; Daniel Henrique Barboza >; Liu Zhiwei >Subject: Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board > >On Thu, Oct 31, 2024 at 2:06 PM Philippe Mathieu-Daudé >wrote: >> >> Hi Michal, >> >> On 30/10/24 02:53, Michal Simek wrote: >> > Hi Alistair, >> > >> > On 10/30/24 03:54, Alistair Francis wrote: >> >> On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu >> >> wrote: >> > >> >>> diff --git a/hw/riscv/microblaze-v-virt.c >> >>> b/hw/riscv/microblaze-v-virt.c new file mode 100644 index >> >>> 000..6603e6d6b06 >> >>> --- /dev/null >> >>> +++ b/hw/riscv/microblaze-v-virt.c >> >>> @@ -0,0 +1,181 @@ >> >>> +/* >> >>> + * QEMU model of Microblaze V (32bit version) >> >> Is there a 64-bit model planned? >> >> >>> + * >> >>> + * based on hw/microblaze/petalogix_ml605_mmu.c >> >> >> >> Just a question, are you sure the virt board should be based on the >> >> petalogix_ml605_mmu? >> > >> > It is definitely based on ml605 and it is fair to say it and keep >> > origin copyrights around. >> > >> >> This will be the reference Microblaze V implementation in QEMU, and >> >> the petalogix_ml605_mmu might be a bit old now. It also uses a lot >> >> of the Microblaze architecture components (like the interrupt >> >> controller) compared to the RISC-V architecture components which >> >> might cause issues for you in the future. >> >> >> >> Just something to keep in mind >> > >> > And the reason is that it is really design like that in design tool >> > (Vivado). >> > There is no risc-v specific interrupt controller use but origin axi >> > intc used in origin Microblaze designs. Timer is the same story. >> > >> > ml605 board and it's chip is old but IPs which are used are still >> > supported and used in new designs. > >Fine with me, just wanted to check. > >It's probably worth stating all of this in the board's documentation, just to >be clear that >it's an abstract board. > >> > >> > And regarding using virt in name. We can create design like it is >> > described but it is not going to work on standard evaluation boards >> > without extra fmc cards for example. >> > It means word virt is just description that it is not really target >> > any specific board. Definitely name can change and suggestions are welcome. >> >> What about 'generic'? > >Yeah, I think we should avoid virt. generic seems better. Or something like >"example" >or "base". Names are hard > >Alistair
RE: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board
Thanks Phil, I will send a v3 for follow-up. Regards, Sai Pavan >-Original Message- >From: Philippe Mathieu-Daudé >Sent: Thursday, October 31, 2024 9:30 PM >To: Simek, Michal ; Alistair Francis >; Boddu, Sai Pavan >Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Paolo Bonzini >; Palmer Dabbelt ; Alistair Francis >; Bin Meng ; Weiwei Li >; Daniel Henrique Barboza ; >Liu Zhiwei >Subject: Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board > >On 31/10/24 05:43, Michal Simek wrote: >> Hi, >> >> On 10/31/24 05:06, Philippe Mathieu-Daudé wrote: >>> Hi Michal, >>> >>> On 30/10/24 02:53, Michal Simek wrote: >>>> Hi Alistair, >>>> >>>> On 10/30/24 03:54, Alistair Francis wrote: >>>>> On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu >>>>> wrote: >>>> >>>>>> diff --git a/hw/riscv/microblaze-v-virt.c >>>>>> b/hw/riscv/microblaze-v-virt.c new file mode 100644 index >>>>>> 000..6603e6d6b06 >>>>>> --- /dev/null >>>>>> +++ b/hw/riscv/microblaze-v-virt.c >>>>>> @@ -0,0 +1,181 @@ >>>>>> +/* >>>>>> + * QEMU model of Microblaze V (32bit version) >>> >>> Is there a 64-bit model planned? >> >> This guide is talking about 64bit too >> https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide > >Same board, different core (synthesized with C_DATA_SIZE = 64). > >> It means answer is yes. And pretty much this generic model with the >> same layout should be possible to use with generic 64bit version too. >> >> I expect that means that default_cpu_type should be TYPE_RISCV_CPU_BASE. >> and Kconfig should be extended >> + depends on RISCV32 || RISCV64 >> >> Also some small updates in documentation to cover it. >> >> Is there something else what should be updated? > >No issue, I was just checking. > >Regards, > >Phil.
OOO for first half
Hi, I would be out of office first half, will connect online post lunch. Regards, Sai Pavan
RE: [PATCH v3] hw/riscv: Add Microblaze V generic board
Hi Alistair, Thanks for Review. I will address below comments in V4. Regards, Sai Pavan >-Original Message- >From: Alistair Francis >Sent: Monday, November 18, 2024 11:37 AM >To: Boddu, Sai Pavan >Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Paolo Bonzini >; Palmer Dabbelt ; Bin Meng >; Weiwei Li ; Daniel Henrique >Barboza ; Liu Zhiwei >; Simek, Michal ; Philippe >Mathieu-Daudé ; Iglesias, Francisco > >Subject: Re: [PATCH v3] hw/riscv: Add Microblaze V generic board > >On Tue, Nov 5, 2024 at 3:43 AM Sai Pavan Boddu >wrote: >> >> Add a basic board with interrupt controller (intc), timer, serial >> (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000 >> (configured via command line eg. -m 2g). >> This is basic configuration which matches HW generated out of AMD >> Vivado (design tools). But initial configuration is going beyond what >> it is configured by default because validation should be done on other >> configurations too. That's why wire also additional uart16500, axi >> ethernet(with axi dma). >> GPIOs, i2c and qspi is also listed for completeness. >> >> IRQ map is: (addr) >> 0 - timer (0x41c0) >> 1 - uartlite (0x4060) >> 2 - i2c (0x4080) >> 3 - qspi (0x44a0) >> 4 - uart16550 (0x44a1) >> 5 - emaclite (0x40e0) >> 6 - timer2 (0x41c1) >> 7 - axi emac (0x40c0) >> 8 - axi dma (0x41e0) >> 9 - axi dma >> 10 - gpio (0x4000) >> 11 - gpio2 (0x4001) >> 12 - gpio3 (0x4002) >> >> Signed-off-by: Sai Pavan Boddu >> Signed-off-by: Michal Simek >> Reviewed-by: Francisco Iglesias >> --- >> Changes for V2: >> Make changes to support -cpu switch >> Remove setting of default board >> Include doc to toctree >> Remove setting of 'imac' extensions as they are available by >> default. >> Chages for V3: >> Replace virt with generic >> Update doc with supported riscv extensions >> Change base CPU to TYPE_RISCV_CPU_BASE >> >> >> MAINTAINERS| 6 + >> docs/system/riscv/microblaze-v-generic.rst | 45 + >> docs/system/target-riscv.rst | 1 + >> hw/riscv/microblaze-v-generic.c| 182 + >> hw/riscv/Kconfig | 8 + >> hw/riscv/meson.build | 1 + >> 6 files changed, 243 insertions(+) >> create mode 100644 docs/system/riscv/microblaze-v-generic.rst >> create mode 100644 hw/riscv/microblaze-v-generic.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS index 03741d41e58..9830a46d819 >> 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -1290,6 +1290,12 @@ M: Edgar E. Iglesias >> S: Maintained >> F: hw/microblaze/petalogix_ml605_mmu.c >> >> +AMD Microblaze-V Generic Board >> +M: Sai Pavan Boddu >> +S: Maintained >> +F: hw/riscv/microblaze-v-generic.c >> +F: docs/system/riscv/microblaze-v-generic.rst > >This should be with the other RISC-V machines > >> + >> MIPS Machines >> - >> Overall MIPS Machines >> diff --git a/docs/system/riscv/microblaze-v-generic.rst >> b/docs/system/riscv/microblaze-v-generic.rst >> new file mode 100644 >> index 000..71e9e655f66 >> --- /dev/null >> +++ b/docs/system/riscv/microblaze-v-generic.rst >> @@ -0,0 +1,45 @@ >> +Microblaze-V generic board (``amd-microblaze-v-generic``) >> += >> +The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD >adaptive SoCs and FPGAs. >> +The MicroBlaze V processor is based on a 32-bit / 64-bit RISC-V >> +instruction set architecture (ISA) and its fully hardware compatible with >> the >classic MicroBlaze processor. > >I'm not sure "fully hardware compatible" is the right thing to say here as >it's a different >ISA. > >Maybe just say that it works with the existing Microblaze IP > >> + >> +More details here: >> +https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaz >> +e-V-Architecture >> + >> +The microblaze-v generic board in QEMU has following supported >> +devices > >The supported devices should probably be listed here > >> + >> +Implemented CPU cores: >> + >> +1 RISCV core >> +* RV32I base integer instruction set > >Maybe just say RV32I/RV64I and drop the configurable part later on > >> +* "Zicsr"
RE: [PATCH 01/48] hw/net/cadence_gem: fix register mask initialization
[AMD Official Use Only - AMD Internal Distribution Only]
>-Original Message-
>From: Luc Michel
>Sent: Wednesday, July 16, 2025 3:24 PM
>To: qemu-devel@nongnu.org; qemu-...@nongnu.org
>Cc: Michel, Luc ; Peter Maydell
>; Iglesias, Francisco ;
>Iglesias, Edgar ; Philippe Mathieu-Daudé
>; Alistair Francis ; Konrad,
>Frederic
>; Boddu, Sai Pavan ;
>Jason Wang
>Subject: [PATCH 01/48] hw/net/cadence_gem: fix register mask initialization
>
>The gem_init_register_masks function was called at init time but it relies on
>the num-
>priority-queues property. Call it at realize time instead.
>
>Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt
>registers")
>Signed-off-by: Luc Michel
Reviewed-by: Sai Pavan Boddu
>---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>50025d5a6f2..deb 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1754,10 +1754,11 @@ static void gem_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < s->num_priority_queues; ++i) {
> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
> }
>
>+gem_init_register_masks(s);
> qemu_macaddr_default_if_unset(&s->conf.macaddr);
>
> s->nic = qemu_new_nic(&net_gem_info, &s->conf,
> object_get_typename(OBJECT(dev)), dev->id,
> &dev->mem_reentrancy_guard, s); @@ -1774,11
> +1775,10 @@
>static void gem_init(Object *obj)
> CadenceGEMState *s = CADENCE_GEM(obj);
> DeviceState *dev = DEVICE(obj);
>
> DB_PRINT("\n");
>
>-gem_init_register_masks(s);
> memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
> "enet", sizeof(s->regs));
>
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); }
>--
>2.50.0
